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Ошибка # 152

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-__CPAchecker_initialize()
{
20 typedef unsigned char __u8;
23 typedef unsigned short __u16;
25 typedef int __s32;
26 typedef unsigned int __u32;
30 typedef unsigned long long __u64;
15 typedef signed char s8;
16 typedef unsigned char u8;
19 typedef unsigned short u16;
21 typedef int s32;
22 typedef unsigned int u32;
24 typedef long long s64;
25 typedef unsigned long long u64;
14 typedef long __kernel_long_t;
15 typedef unsigned long __kernel_ulong_t;
27 typedef int __kernel_pid_t;
48 typedef unsigned int __kernel_uid32_t;
49 typedef unsigned int __kernel_gid32_t;
71 typedef __kernel_ulong_t __kernel_size_t;
72 typedef __kernel_long_t __kernel_ssize_t;
87 typedef long long __kernel_loff_t;
88 typedef __kernel_long_t __kernel_time_t;
89 typedef __kernel_long_t __kernel_clock_t;
90 typedef int __kernel_timer_t;
91 typedef int __kernel_clockid_t;
33 typedef __u16 __be16;
35 typedef __u32 __be32;
40 typedef __u32 __wsum;
255 struct kernel_symbol { unsigned long value; const char *name; } ;
33 struct module ;
12 typedef __u32 __kernel_dev_t;
15 typedef __kernel_dev_t dev_t;
18 typedef unsigned short umode_t;
21 typedef __kernel_pid_t pid_t;
26 typedef __kernel_clockid_t clockid_t;
29 typedef _Bool bool;
31 typedef __kernel_uid32_t uid_t;
32 typedef __kernel_gid32_t gid_t;
45 typedef __kernel_loff_t loff_t;
54 typedef __kernel_size_t size_t;
59 typedef __kernel_ssize_t ssize_t;
69 typedef __kernel_time_t time_t;
102 typedef __s32 int32_t;
106 typedef __u8 uint8_t;
108 typedef __u32 uint32_t;
111 typedef __u64 uint64_t;
133 typedef unsigned long sector_t;
134 typedef unsigned long blkcnt_t;
152 typedef u64 dma_addr_t;
157 typedef unsigned int gfp_t;
158 typedef unsigned int fmode_t;
159 typedef unsigned int oom_flags_t;
162 typedef u64 phys_addr_t;
167 typedef phys_addr_t resource_size_t;
173 typedef unsigned long irq_hw_number_t;
177 struct __anonstruct_atomic_t_6 { int counter; } ;
177 typedef struct __anonstruct_atomic_t_6 atomic_t;
182 struct __anonstruct_atomic64_t_7 { long counter; } ;
182 typedef struct __anonstruct_atomic64_t_7 atomic64_t;
183 struct list_head { struct list_head *next; struct list_head *prev; } ;
188 struct hlist_node ;
188 struct hlist_head { struct hlist_node *first; } ;
192 struct hlist_node { struct hlist_node *next; struct hlist_node **pprev; } ;
203 struct callback_head { struct callback_head *next; void (*func)(struct callback_head *); } ;
72 struct pt_regs { unsigned long r15; unsigned long r14; unsigned long r13; unsigned long r12; unsigned long bp; unsigned long bx; unsigned long r11; unsigned long r10; unsigned long r9; unsigned long r8; unsigned long ax; unsigned long cx; unsigned long dx; unsigned long si; unsigned long di; unsigned long orig_ax; unsigned long ip; unsigned long cs; unsigned long flags; unsigned long sp; unsigned long ss; } ;
66 struct __anonstruct____missing_field_name_9 { unsigned int a; unsigned int b; } ;
66 struct __anonstruct____missing_field_name_10 { u16 limit0; u16 base0; unsigned char base1; unsigned char type; unsigned char s; unsigned char dpl; unsigned char p; unsigned char limit; unsigned char avl; unsigned char l; unsigned char d; unsigned char g; unsigned char base2; } ;
66 union __anonunion____missing_field_name_8 { struct __anonstruct____missing_field_name_9 __annonCompField4; struct __anonstruct____missing_field_name_10 __annonCompField5; } ;
66 struct desc_struct { union __anonunion____missing_field_name_8 __annonCompField6; } ;
12 typedef unsigned long pteval_t;
13 typedef unsigned long pmdval_t;
15 typedef unsigned long pgdval_t;
16 typedef unsigned long pgprotval_t;
18 struct __anonstruct_pte_t_11 { pteval_t pte; } ;
18 typedef struct __anonstruct_pte_t_11 pte_t;
20 struct pgprot { pgprotval_t pgprot; } ;
221 typedef struct pgprot pgprot_t;
223 struct __anonstruct_pgd_t_12 { pgdval_t pgd; } ;
223 typedef struct __anonstruct_pgd_t_12 pgd_t;
262 struct __anonstruct_pmd_t_14 { pmdval_t pmd; } ;
262 typedef struct __anonstruct_pmd_t_14 pmd_t;
390 struct page ;
390 typedef struct page *pgtable_t;
401 struct file ;
414 struct seq_file ;
452 struct thread_struct ;
454 struct mm_struct ;
455 struct task_struct ;
456 struct cpumask ;
20 struct qspinlock { atomic_t val; } ;
33 typedef struct qspinlock arch_spinlock_t;
34 struct qrwlock { atomic_t cnts; arch_spinlock_t wait_lock; } ;
14 typedef struct qrwlock arch_rwlock_t;
131 typedef void (*ctor_fn_t)();
48 struct device ;
54 struct net_device ;
420 struct file_operations ;
432 struct completion ;
27 union __anonunion___u_16 { struct list_head *__val; char __c[1U]; } ;
200 union __anonunion___u_20 { struct list_head *__val; char __c[1U]; } ;
555 struct bug_entry { int bug_addr_disp; int file_disp; unsigned short line; unsigned short flags; } ;
102 struct timespec ;
103 struct compat_timespec ;
104 struct __anonstruct_futex_32 { u32 *uaddr; u32 val; u32 flags; u32 bitset; u64 time; u32 *uaddr2; } ;
104 struct __anonstruct_nanosleep_33 { clockid_t clockid; struct timespec *rmtp; struct compat_timespec *compat_rmtp; u64 expires; } ;
104 struct pollfd ;
104 struct __anonstruct_poll_34 { struct pollfd *ufds; int nfds; int has_timeout; unsigned long tv_sec; unsigned long tv_nsec; } ;
104 union __anonunion____missing_field_name_31 { struct __anonstruct_futex_32 futex; struct __anonstruct_nanosleep_33 nanosleep; struct __anonstruct_poll_34 poll; } ;
104 struct restart_block { long int (*fn)(struct restart_block *); union __anonunion____missing_field_name_31 __annonCompField7; } ;
27 struct math_emu_info { long ___orig_eip; struct pt_regs *regs; } ;
328 struct cpumask { unsigned long bits[128U]; } ;
15 typedef struct cpumask cpumask_t;
656 typedef struct cpumask *cpumask_var_t;
23 typedef atomic64_t atomic_long_t;
82 struct static_key { atomic_t enabled; } ;
264 struct tracepoint_func { void *func; void *data; int prio; } ;
18 struct tracepoint { const char *name; struct static_key key; void (*regfunc)(); void (*unregfunc)(); struct tracepoint_func *funcs; } ;
260 struct fregs_state { u32 cwd; u32 swd; u32 twd; u32 fip; u32 fcs; u32 foo; u32 fos; u32 st_space[20U]; u32 status; } ;
26 struct __anonstruct____missing_field_name_59 { u64 rip; u64 rdp; } ;
26 struct __anonstruct____missing_field_name_60 { u32 fip; u32 fcs; u32 foo; u32 fos; } ;
26 union __anonunion____missing_field_name_58 { struct __anonstruct____missing_field_name_59 __annonCompField13; struct __anonstruct____missing_field_name_60 __annonCompField14; } ;
26 union __anonunion____missing_field_name_61 { u32 padding1[12U]; u32 sw_reserved[12U]; } ;
26 struct fxregs_state { u16 cwd; u16 swd; u16 twd; u16 fop; union __anonunion____missing_field_name_58 __annonCompField15; u32 mxcsr; u32 mxcsr_mask; u32 st_space[32U]; u32 xmm_space[64U]; u32 padding[12U]; union __anonunion____missing_field_name_61 __annonCompField16; } ;
66 struct swregs_state { u32 cwd; u32 swd; u32 twd; u32 fip; u32 fcs; u32 foo; u32 fos; u32 st_space[20U]; u8 ftop; u8 changed; u8 lookahead; u8 no_update; u8 rm; u8 alimit; struct math_emu_info *info; u32 entry_eip; } ;
214 struct xstate_header { u64 xfeatures; u64 xcomp_bv; u64 reserved[6U]; } ;
220 struct xregs_state { struct fxregs_state i387; struct xstate_header header; u8 extended_state_area[0U]; } ;
235 union fpregs_state { struct fregs_state fsave; struct fxregs_state fxsave; struct swregs_state soft; struct xregs_state xsave; u8 __padding[4096U]; } ;
252 struct fpu { unsigned int last_cpu; unsigned char fpstate_active; unsigned char fpregs_active; unsigned char counter; union fpregs_state state; } ;
170 struct seq_operations ;
369 struct perf_event ;
370 struct thread_struct { struct desc_struct tls_array[3U]; unsigned long sp0; unsigned long sp; unsigned short es; unsigned short ds; unsigned short fsindex; unsigned short gsindex; unsigned long fs; unsigned long gs; struct perf_event *ptrace_bps[4U]; unsigned long debugreg6; unsigned long ptrace_dr7; unsigned long cr2; unsigned long trap_nr; unsigned long error_code; unsigned long *io_bitmap_ptr; unsigned long iopl; unsigned int io_bitmap_max; struct fpu fpu; } ;
488 struct __anonstruct_mm_segment_t_73 { unsigned long seg; } ;
488 typedef struct __anonstruct_mm_segment_t_73 mm_segment_t;
842 struct thread_info { struct task_struct *task; __u32 flags; __u32 status; __u32 cpu; mm_segment_t addr_limit; unsigned char sig_on_uaccess_error; unsigned char uaccess_err; } ;
33 struct lockdep_map ;
55 struct stack_trace { unsigned int nr_entries; unsigned int max_entries; unsigned long *entries; int skip; } ;
28 struct lockdep_subclass_key { char __one_byte; } ;
53 struct lock_class_key { struct lockdep_subclass_key subkeys[8U]; } ;
59 struct lock_class { struct list_head hash_entry; struct list_head lock_entry; struct lockdep_subclass_key *key; unsigned int subclass; unsigned int dep_gen_id; unsigned long usage_mask; struct stack_trace usage_traces[13U]; struct list_head locks_after; struct list_head locks_before; unsigned int version; unsigned long ops; const char *name; int name_version; unsigned long contention_point[4U]; unsigned long contending_point[4U]; } ;
144 struct lockdep_map { struct lock_class_key *key; struct lock_class *class_cache[2U]; const char *name; int cpu; unsigned long ip; } ;
205 struct held_lock { u64 prev_chain_key; unsigned long acquire_ip; struct lockdep_map *instance; struct lockdep_map *nest_lock; u64 waittime_stamp; u64 holdtime_stamp; unsigned short class_idx; unsigned char irq_context; unsigned char trylock; unsigned char read; unsigned char check; unsigned char hardirqs_off; unsigned short references; unsigned int pin_count; } ;
546 struct raw_spinlock { arch_spinlock_t raw_lock; unsigned int magic; unsigned int owner_cpu; void *owner; struct lockdep_map dep_map; } ;
32 typedef struct raw_spinlock raw_spinlock_t;
33 struct __anonstruct____missing_field_name_75 { u8 __padding[24U]; struct lockdep_map dep_map; } ;
33 union __anonunion____missing_field_name_74 { struct raw_spinlock rlock; struct __anonstruct____missing_field_name_75 __annonCompField19; } ;
33 struct spinlock { union __anonunion____missing_field_name_74 __annonCompField20; } ;
76 typedef struct spinlock spinlock_t;
23 struct __anonstruct_rwlock_t_76 { arch_rwlock_t raw_lock; unsigned int magic; unsigned int owner_cpu; void *owner; struct lockdep_map dep_map; } ;
23 typedef struct __anonstruct_rwlock_t_76 rwlock_t;
416 struct seqcount { unsigned int sequence; struct lockdep_map dep_map; } ;
52 typedef struct seqcount seqcount_t;
404 struct __anonstruct_seqlock_t_89 { struct seqcount seqcount; spinlock_t lock; } ;
404 typedef struct __anonstruct_seqlock_t_89 seqlock_t;
598 struct timespec { __kernel_time_t tv_sec; long tv_nsec; } ;
83 struct user_namespace ;
22 struct __anonstruct_kuid_t_90 { uid_t val; } ;
22 typedef struct __anonstruct_kuid_t_90 kuid_t;
27 struct __anonstruct_kgid_t_91 { gid_t val; } ;
27 typedef struct __anonstruct_kgid_t_91 kgid_t;
139 struct kstat { u64 ino; dev_t dev; umode_t mode; unsigned int nlink; kuid_t uid; kgid_t gid; dev_t rdev; loff_t size; struct timespec atime; struct timespec mtime; struct timespec ctime; unsigned long blksize; unsigned long long blocks; } ;
36 struct vm_area_struct ;
12 struct __wait_queue ;
12 typedef struct __wait_queue wait_queue_t;
15 struct __wait_queue { unsigned int flags; void *private; int (*func)(wait_queue_t *, unsigned int, int, void *); struct list_head task_list; } ;
38 struct __wait_queue_head { spinlock_t lock; struct list_head task_list; } ;
43 typedef struct __wait_queue_head wait_queue_head_t;
95 struct __anonstruct_nodemask_t_92 { unsigned long bits[16U]; } ;
95 typedef struct __anonstruct_nodemask_t_92 nodemask_t;
13 struct optimistic_spin_queue { atomic_t tail; } ;
39 struct mutex { atomic_t count; spinlock_t wait_lock; struct list_head wait_list; struct task_struct *owner; void *magic; struct lockdep_map dep_map; } ;
67 struct mutex_waiter { struct list_head list; struct task_struct *task; void *magic; } ;
177 struct rw_semaphore ;
178 struct rw_semaphore { long count; struct list_head wait_list; raw_spinlock_t wait_lock; struct optimistic_spin_queue osq; struct task_struct *owner; struct lockdep_map dep_map; } ;
172 struct completion { unsigned int done; wait_queue_head_t wait; } ;
446 union ktime { s64 tv64; } ;
41 typedef union ktime ktime_t;
335 struct notifier_block ;
1148 struct timer_list { struct hlist_node entry; unsigned long expires; void (*function)(unsigned long); unsigned long data; u32 flags; int slack; int start_pid; void *start_site; char start_comm[16U]; struct lockdep_map lockdep_map; } ;
238 struct hrtimer ;
239 enum hrtimer_restart ;
240 struct rb_node { unsigned long __rb_parent_color; struct rb_node *rb_right; struct rb_node *rb_left; } ;
41 struct rb_root { struct rb_node *rb_node; } ;
837 struct ctl_table ;
838 struct nsproxy ;
839 struct ctl_table_root ;
840 struct ctl_table_header ;
841 struct ctl_dir ;
37 typedef int proc_handler(struct ctl_table *, int, void *, size_t *, loff_t *);
57 struct ctl_table_poll { atomic_t event; wait_queue_head_t wait; } ;
96 struct ctl_table { const char *procname; void *data; int maxlen; umode_t mode; struct ctl_table *child; proc_handler *proc_handler; struct ctl_table_poll *poll; void *extra1; void *extra2; } ;
117 struct ctl_node { struct rb_node node; struct ctl_table_header *header; } ;
122 struct __anonstruct____missing_field_name_96 { struct ctl_table *ctl_table; int used; int count; int nreg; } ;
122 union __anonunion____missing_field_name_95 { struct __anonstruct____missing_field_name_96 __annonCompField21; struct callback_head rcu; } ;
122 struct ctl_table_set ;
122 struct ctl_table_header { union __anonunion____missing_field_name_95 __annonCompField22; struct completion *unregistering; struct ctl_table *ctl_table_arg; struct ctl_table_root *root; struct ctl_table_set *set; struct ctl_dir *parent; struct ctl_node *node; } ;
143 struct ctl_dir { struct ctl_table_header header; struct rb_root root; } ;
149 struct ctl_table_set { int (*is_seen)(struct ctl_table_set *); struct ctl_dir dir; } ;
154 struct ctl_table_root { struct ctl_table_set default_set; struct ctl_table_set * (*lookup)(struct ctl_table_root *, struct nsproxy *); int (*permissions)(struct ctl_table_header *, struct ctl_table *); } ;
259 struct workqueue_struct ;
260 struct work_struct ;
54 struct work_struct { atomic_long_t data; struct list_head entry; void (*func)(struct work_struct *); struct lockdep_map lockdep_map; } ;
107 struct delayed_work { struct work_struct work; struct timer_list timer; struct workqueue_struct *wq; int cpu; } ;
51 struct notifier_block { int (*notifier_call)(struct notifier_block *, unsigned long, void *); struct notifier_block *next; int priority; } ;
215 struct resource ;
64 struct resource { resource_size_t start; resource_size_t end; const char *name; unsigned long flags; struct resource *parent; struct resource *sibling; struct resource *child; } ;
169 struct pci_dev ;
58 struct pm_message { int event; } ;
64 typedef struct pm_message pm_message_t;
65 struct dev_pm_ops { int (*prepare)(struct device *); void (*complete)(struct device *); int (*suspend)(struct device *); int (*resume)(struct device *); int (*freeze)(struct device *); int (*thaw)(struct device *); int (*poweroff)(struct device *); int (*restore)(struct device *); int (*suspend_late)(struct device *); int (*resume_early)(struct device *); int (*freeze_late)(struct device *); int (*thaw_early)(struct device *); int (*poweroff_late)(struct device *); int (*restore_early)(struct device *); int (*suspend_noirq)(struct device *); int (*resume_noirq)(struct device *); int (*freeze_noirq)(struct device *); int (*thaw_noirq)(struct device *); int (*poweroff_noirq)(struct device *); int (*restore_noirq)(struct device *); int (*runtime_suspend)(struct device *); int (*runtime_resume)(struct device *); int (*runtime_idle)(struct device *); } ;
320 enum rpm_status { RPM_ACTIVE = 0, RPM_RESUMING = 1, RPM_SUSPENDED = 2, RPM_SUSPENDING = 3 } ;
327 enum rpm_request { RPM_REQ_NONE = 0, RPM_REQ_IDLE = 1, RPM_REQ_SUSPEND = 2, RPM_REQ_AUTOSUSPEND = 3, RPM_REQ_RESUME = 4 } ;
335 struct wakeup_source ;
336 struct wake_irq ;
337 struct pm_domain_data ;
338 struct pm_subsys_data { spinlock_t lock; unsigned int refcount; struct list_head clock_list; struct pm_domain_data *domain_data; } ;
556 struct dev_pm_qos ;
556 struct dev_pm_info { pm_message_t power_state; unsigned char can_wakeup; unsigned char async_suspend; bool is_prepared; bool is_suspended; bool is_noirq_suspended; bool is_late_suspended; bool ignore_children; bool early_init; bool direct_complete; spinlock_t lock; struct list_head entry; struct completion completion; struct wakeup_source *wakeup; bool wakeup_path; bool syscore; bool no_pm_callbacks; struct timer_list suspend_timer; unsigned long timer_expires; struct work_struct work; wait_queue_head_t wait_queue; struct wake_irq *wakeirq; atomic_t usage_count; atomic_t child_count; unsigned char disable_depth; unsigned char idle_notification; unsigned char request_pending; unsigned char deferred_resume; unsigned char run_wake; unsigned char runtime_auto; unsigned char no_callbacks; unsigned char irq_safe; unsigned char use_autosuspend; unsigned char timer_autosuspends; unsigned char memalloc_noio; enum rpm_request request; enum rpm_status runtime_status; int runtime_error; int autosuspend_delay; unsigned long last_busy; unsigned long active_jiffies; unsigned long suspended_jiffies; unsigned long accounting_timestamp; struct pm_subsys_data *subsys_data; void (*set_latency_tolerance)(struct device *, s32 ); struct dev_pm_qos *qos; } ;
616 struct dev_pm_domain { struct dev_pm_ops ops; void (*detach)(struct device *, bool ); int (*activate)(struct device *); void (*sync)(struct device *); void (*dismiss)(struct device *); } ;
133 struct pci_bus ;
25 struct ldt_struct ;
25 struct __anonstruct_mm_context_t_161 { struct ldt_struct *ldt; unsigned short ia32_compat; struct mutex lock; void *vdso; atomic_t perf_rdpmc_allowed; } ;
25 typedef struct __anonstruct_mm_context_t_161 mm_context_t;
22 struct bio_vec ;
1211 struct llist_node ;
1211 struct llist_head { struct llist_node *first; } ;
64 struct llist_node { struct llist_node *next; } ;
37 struct cred ;
19 struct inode ;
58 struct arch_uprobe_task { unsigned long saved_scratch_register; unsigned int saved_trap_nr; unsigned int saved_tf; } ;
66 enum uprobe_task_state { UTASK_RUNNING = 0, UTASK_SSTEP = 1, UTASK_SSTEP_ACK = 2, UTASK_SSTEP_TRAPPED = 3 } ;
73 struct __anonstruct____missing_field_name_197 { struct arch_uprobe_task autask; unsigned long vaddr; } ;
73 struct __anonstruct____missing_field_name_198 { struct callback_head dup_xol_work; unsigned long dup_xol_addr; } ;
73 union __anonunion____missing_field_name_196 { struct __anonstruct____missing_field_name_197 __annonCompField35; struct __anonstruct____missing_field_name_198 __annonCompField36; } ;
73 struct uprobe ;
73 struct return_instance ;
73 struct uprobe_task { enum uprobe_task_state state; union __anonunion____missing_field_name_196 __annonCompField37; struct uprobe *active_uprobe; unsigned long xol_vaddr; struct return_instance *return_instances; unsigned int depth; } ;
94 struct return_instance { struct uprobe *uprobe; unsigned long func; unsigned long stack; unsigned long orig_ret_vaddr; bool chained; struct return_instance *next; } ;
110 struct xol_area ;
111 struct uprobes_state { struct xol_area *xol_area; } ;
150 struct address_space ;
151 struct mem_cgroup ;
152 union __anonunion____missing_field_name_199 { struct address_space *mapping; void *s_mem; atomic_t compound_mapcount; } ;
152 union __anonunion____missing_field_name_201 { unsigned long index; void *freelist; } ;
152 struct __anonstruct____missing_field_name_205 { unsigned short inuse; unsigned short objects; unsigned char frozen; } ;
152 union __anonunion____missing_field_name_204 { atomic_t _mapcount; struct __anonstruct____missing_field_name_205 __annonCompField40; int units; } ;
152 struct __anonstruct____missing_field_name_203 { union __anonunion____missing_field_name_204 __annonCompField41; atomic_t _count; } ;
152 union __anonunion____missing_field_name_202 { unsigned long counters; struct __anonstruct____missing_field_name_203 __annonCompField42; unsigned int active; } ;
152 struct __anonstruct____missing_field_name_200 { union __anonunion____missing_field_name_201 __annonCompField39; union __anonunion____missing_field_name_202 __annonCompField43; } ;
152 struct dev_pagemap ;
152 struct __anonstruct____missing_field_name_207 { struct page *next; int pages; int pobjects; } ;
152 struct __anonstruct____missing_field_name_208 { unsigned long compound_head; unsigned int compound_dtor; unsigned int compound_order; } ;
152 struct __anonstruct____missing_field_name_209 { unsigned long __pad; pgtable_t pmd_huge_pte; } ;
152 union __anonunion____missing_field_name_206 { struct list_head lru; struct dev_pagemap *pgmap; struct __anonstruct____missing_field_name_207 __annonCompField45; struct callback_head callback_head; struct __anonstruct____missing_field_name_208 __annonCompField46; struct __anonstruct____missing_field_name_209 __annonCompField47; } ;
152 struct kmem_cache ;
152 union __anonunion____missing_field_name_210 { unsigned long private; spinlock_t *ptl; struct kmem_cache *slab_cache; } ;
152 struct page { unsigned long flags; union __anonunion____missing_field_name_199 __annonCompField38; struct __anonstruct____missing_field_name_200 __annonCompField44; union __anonunion____missing_field_name_206 __annonCompField48; union __anonunion____missing_field_name_210 __annonCompField49; struct mem_cgroup *mem_cgroup; } ;
191 struct page_frag { struct page *page; __u32 offset; __u32 size; } ;
276 struct userfaultfd_ctx ;
276 struct vm_userfaultfd_ctx { struct userfaultfd_ctx *ctx; } ;
283 struct __anonstruct_shared_211 { struct rb_node rb; unsigned long rb_subtree_last; } ;
283 struct anon_vma ;
283 struct vm_operations_struct ;
283 struct mempolicy ;
283 struct vm_area_struct { unsigned long vm_start; unsigned long vm_end; struct vm_area_struct *vm_next; struct vm_area_struct *vm_prev; struct rb_node vm_rb; unsigned long rb_subtree_gap; struct mm_struct *vm_mm; pgprot_t vm_page_prot; unsigned long vm_flags; struct __anonstruct_shared_211 shared; struct list_head anon_vma_chain; struct anon_vma *anon_vma; const struct vm_operations_struct *vm_ops; unsigned long vm_pgoff; struct file *vm_file; void *vm_private_data; struct mempolicy *vm_policy; struct vm_userfaultfd_ctx vm_userfaultfd_ctx; } ;
356 struct core_thread { struct task_struct *task; struct core_thread *next; } ;
361 struct core_state { atomic_t nr_threads; struct core_thread dumper; struct completion startup; } ;
375 struct task_rss_stat { int events; int count[4U]; } ;
383 struct mm_rss_stat { atomic_long_t count[4U]; } ;
388 struct kioctx_table ;
389 struct linux_binfmt ;
389 struct mmu_notifier_mm ;
389 struct mm_struct { struct vm_area_struct *mmap; struct rb_root mm_rb; u32 vmacache_seqnum; unsigned long int (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); unsigned long mmap_base; unsigned long mmap_legacy_base; unsigned long task_size; unsigned long highest_vm_end; pgd_t *pgd; atomic_t mm_users; atomic_t mm_count; atomic_long_t nr_ptes; atomic_long_t nr_pmds; int map_count; spinlock_t page_table_lock; struct rw_semaphore mmap_sem; struct list_head mmlist; unsigned long hiwater_rss; unsigned long hiwater_vm; unsigned long total_vm; unsigned long locked_vm; unsigned long pinned_vm; unsigned long data_vm; unsigned long exec_vm; unsigned long stack_vm; unsigned long def_flags; unsigned long start_code; unsigned long end_code; unsigned long start_data; unsigned long end_data; unsigned long start_brk; unsigned long brk; unsigned long start_stack; unsigned long arg_start; unsigned long arg_end; unsigned long env_start; unsigned long env_end; unsigned long saved_auxv[46U]; struct mm_rss_stat rss_stat; struct linux_binfmt *binfmt; cpumask_var_t cpu_vm_mask_var; mm_context_t context; unsigned long flags; struct core_state *core_state; spinlock_t ioctx_lock; struct kioctx_table *ioctx_table; struct task_struct *owner; struct file *exe_file; struct mmu_notifier_mm *mmu_notifier_mm; struct cpumask cpumask_allocation; unsigned long numa_next_scan; unsigned long numa_scan_offset; int numa_scan_seq; bool tlb_flush_pending; struct uprobes_state uprobes_state; void *bd_addr; atomic_long_t hugetlb_usage; } ;
15 typedef __u64 Elf64_Addr;
16 typedef __u16 Elf64_Half;
20 typedef __u32 Elf64_Word;
21 typedef __u64 Elf64_Xword;
190 struct elf64_sym { Elf64_Word st_name; unsigned char st_info; unsigned char st_other; Elf64_Half st_shndx; Elf64_Addr st_value; Elf64_Xword st_size; } ;
198 typedef struct elf64_sym Elf64_Sym;
53 union __anonunion____missing_field_name_216 { unsigned long bitmap[4U]; struct callback_head callback_head; } ;
53 struct idr_layer { int prefix; int layer; struct idr_layer *ary[256U]; int count; union __anonunion____missing_field_name_216 __annonCompField50; } ;
41 struct idr { struct idr_layer *hint; struct idr_layer *top; int layers; int cur; spinlock_t lock; int id_free_cnt; struct idr_layer *id_free; } ;
124 struct ida_bitmap { long nr_busy; unsigned long bitmap[15U]; } ;
167 struct ida { struct idr idr; struct ida_bitmap *free_bitmap; } ;
199 struct dentry ;
200 struct iattr ;
201 struct super_block ;
202 struct file_system_type ;
203 struct kernfs_open_node ;
204 struct kernfs_iattrs ;
227 struct kernfs_root ;
227 struct kernfs_elem_dir { unsigned long subdirs; struct rb_root children; struct kernfs_root *root; } ;
85 struct kernfs_node ;
85 struct kernfs_elem_symlink { struct kernfs_node *target_kn; } ;
89 struct kernfs_ops ;
89 struct kernfs_elem_attr { const struct kernfs_ops *ops; struct kernfs_open_node *open; loff_t size; struct kernfs_node *notify_next; } ;
96 union __anonunion____missing_field_name_221 { struct kernfs_elem_dir dir; struct kernfs_elem_symlink symlink; struct kernfs_elem_attr attr; } ;
96 struct kernfs_node { atomic_t count; atomic_t active; struct lockdep_map dep_map; struct kernfs_node *parent; const char *name; struct rb_node rb; const void *ns; unsigned int hash; union __anonunion____missing_field_name_221 __annonCompField51; void *priv; unsigned short flags; umode_t mode; unsigned int ino; struct kernfs_iattrs *iattr; } ;
138 struct kernfs_syscall_ops { int (*remount_fs)(struct kernfs_root *, int *, char *); int (*show_options)(struct seq_file *, struct kernfs_root *); int (*mkdir)(struct kernfs_node *, const char *, umode_t ); int (*rmdir)(struct kernfs_node *); int (*rename)(struct kernfs_node *, struct kernfs_node *, const char *); } ;
155 struct kernfs_root { struct kernfs_node *kn; unsigned int flags; struct ida ino_ida; struct kernfs_syscall_ops *syscall_ops; struct list_head supers; wait_queue_head_t deactivate_waitq; } ;
171 struct kernfs_open_file { struct kernfs_node *kn; struct file *file; void *priv; struct mutex mutex; int event; struct list_head list; char *prealloc_buf; size_t atomic_write_len; bool mmapped; const struct vm_operations_struct *vm_ops; } ;
188 struct kernfs_ops { int (*seq_show)(struct seq_file *, void *); void * (*seq_start)(struct seq_file *, loff_t *); void * (*seq_next)(struct seq_file *, void *, loff_t *); void (*seq_stop)(struct seq_file *, void *); ssize_t (*read)(struct kernfs_open_file *, char *, size_t , loff_t ); size_t atomic_write_len; bool prealloc; ssize_t (*write)(struct kernfs_open_file *, char *, size_t , loff_t ); int (*mmap)(struct kernfs_open_file *, struct vm_area_struct *); struct lock_class_key lockdep_key; } ;
493 struct sock ;
494 struct kobject ;
495 enum kobj_ns_type { KOBJ_NS_TYPE_NONE = 0, KOBJ_NS_TYPE_NET = 1, KOBJ_NS_TYPES = 2 } ;
501 struct kobj_ns_type_operations { enum kobj_ns_type type; bool (*current_may_mount)(); void * (*grab_current_ns)(); const void * (*netlink_ns)(struct sock *); const void * (*initial_ns)(); void (*drop_ns)(void *); } ;
59 struct bin_attribute ;
60 struct attribute { const char *name; umode_t mode; bool ignore_lockdep; struct lock_class_key *key; struct lock_class_key skey; } ;
37 struct attribute_group { const char *name; umode_t (*is_visible)(struct kobject *, struct attribute *, int); umode_t (*is_bin_visible)(struct kobject *, struct bin_attribute *, int); struct attribute **attrs; struct bin_attribute **bin_attrs; } ;
92 struct bin_attribute { struct attribute attr; size_t size; void *private; ssize_t (*read)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t , size_t ); ssize_t (*write)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t , size_t ); int (*mmap)(struct file *, struct kobject *, struct bin_attribute *, struct vm_area_struct *); } ;
165 struct sysfs_ops { ssize_t (*show)(struct kobject *, struct attribute *, char *); ssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t ); } ;
530 struct kref { atomic_t refcount; } ;
52 struct kset ;
52 struct kobj_type ;
52 struct kobject { const char *name; struct list_head entry; struct kobject *parent; struct kset *kset; struct kobj_type *ktype; struct kernfs_node *sd; struct kref kref; struct delayed_work release; unsigned char state_initialized; unsigned char state_in_sysfs; unsigned char state_add_uevent_sent; unsigned char state_remove_uevent_sent; unsigned char uevent_suppress; } ;
115 struct kobj_type { void (*release)(struct kobject *); const struct sysfs_ops *sysfs_ops; struct attribute **default_attrs; const struct kobj_ns_type_operations * (*child_ns_type)(struct kobject *); const void * (*namespace)(struct kobject *); } ;
123 struct kobj_uevent_env { char *argv[3U]; char *envp[32U]; int envp_idx; char buf[2048U]; int buflen; } ;
131 struct kset_uevent_ops { const int (*filter)(struct kset *, struct kobject *); const const char * (*name)(struct kset *, struct kobject *); const int (*uevent)(struct kset *, struct kobject *, struct kobj_uevent_env *); } ;
148 struct kset { struct list_head list; spinlock_t list_lock; struct kobject kobj; const struct kset_uevent_ops *uevent_ops; } ;
223 struct kernel_param ;
228 struct kernel_param_ops { unsigned int flags; int (*set)(const char *, const struct kernel_param *); int (*get)(char *, const struct kernel_param *); void (*free)(void *); } ;
62 struct kparam_string ;
62 struct kparam_array ;
62 union __anonunion____missing_field_name_224 { void *arg; const struct kparam_string *str; const struct kparam_array *arr; } ;
62 struct kernel_param { const char *name; struct module *mod; const struct kernel_param_ops *ops; const u16 perm; s8 level; u8 flags; union __anonunion____missing_field_name_224 __annonCompField52; } ;
83 struct kparam_string { unsigned int maxlen; char *string; } ;
89 struct kparam_array { unsigned int max; unsigned int elemsize; unsigned int *num; const struct kernel_param_ops *ops; void *elem; } ;
470 struct latch_tree_node { struct rb_node node[2U]; } ;
211 struct mod_arch_specific { } ;
38 struct module_param_attrs ;
38 struct module_kobject { struct kobject kobj; struct module *mod; struct kobject *drivers_dir; struct module_param_attrs *mp; struct completion *kobj_completion; } ;
48 struct module_attribute { struct attribute attr; ssize_t (*show)(struct module_attribute *, struct module_kobject *, char *); ssize_t (*store)(struct module_attribute *, struct module_kobject *, const char *, size_t ); void (*setup)(struct module *, const char *); int (*test)(struct module *); void (*free)(struct module *); } ;
74 struct exception_table_entry ;
290 enum module_state { MODULE_STATE_LIVE = 0, MODULE_STATE_COMING = 1, MODULE_STATE_GOING = 2, MODULE_STATE_UNFORMED = 3 } ;
297 struct mod_tree_node { struct module *mod; struct latch_tree_node node; } ;
304 struct module_layout { void *base; unsigned int size; unsigned int text_size; unsigned int ro_size; struct mod_tree_node mtn; } ;
318 struct module_sect_attrs ;
318 struct module_notes_attrs ;
318 struct trace_event_call ;
318 struct trace_enum_map ;
318 struct module { enum module_state state; struct list_head list; char name[56U]; struct module_kobject mkobj; struct module_attribute *modinfo_attrs; const char *version; const char *srcversion; struct kobject *holders_dir; const struct kernel_symbol *syms; const unsigned long *crcs; unsigned int num_syms; struct mutex param_lock; struct kernel_param *kp; unsigned int num_kp; unsigned int num_gpl_syms; const struct kernel_symbol *gpl_syms; const unsigned long *gpl_crcs; const struct kernel_symbol *unused_syms; const unsigned long *unused_crcs; unsigned int num_unused_syms; unsigned int num_unused_gpl_syms; const struct kernel_symbol *unused_gpl_syms; const unsigned long *unused_gpl_crcs; bool sig_ok; bool async_probe_requested; const struct kernel_symbol *gpl_future_syms; const unsigned long *gpl_future_crcs; unsigned int num_gpl_future_syms; unsigned int num_exentries; struct exception_table_entry *extable; int (*init)(); struct module_layout core_layout; struct module_layout init_layout; struct mod_arch_specific arch; unsigned int taints; unsigned int num_bugs; struct list_head bug_list; struct bug_entry *bug_table; Elf64_Sym *symtab; Elf64_Sym *core_symtab; unsigned int num_symtab; unsigned int core_num_syms; char *strtab; char *core_strtab; struct module_sect_attrs *sect_attrs; struct module_notes_attrs *notes_attrs; char *args; void *percpu; unsigned int percpu_size; unsigned int num_tracepoints; const struct tracepoint **tracepoints_ptrs; unsigned int num_trace_bprintk_fmt; const char **trace_bprintk_fmt_start; struct trace_event_call **trace_events; unsigned int num_trace_events; struct trace_enum_map **trace_enums; unsigned int num_trace_enums; bool klp_alive; struct list_head source_list; struct list_head target_list; void (*exit)(); atomic_t refcnt; ctor_fn_t (**ctors)(); unsigned int num_ctors; } ;
24 struct __anonstruct_sigset_t_231 { unsigned long sig[1U]; } ;
24 typedef struct __anonstruct_sigset_t_231 sigset_t;
25 struct siginfo ;
17 typedef void __signalfn_t(int);
18 typedef __signalfn_t *__sighandler_t;
20 typedef void __restorefn_t();
21 typedef __restorefn_t *__sigrestore_t;
34 union sigval { int sival_int; void *sival_ptr; } ;
10 typedef union sigval sigval_t;
11 struct __anonstruct__kill_233 { __kernel_pid_t _pid; __kernel_uid32_t _uid; } ;
11 struct __anonstruct__timer_234 { __kernel_timer_t _tid; int _overrun; char _pad[0U]; sigval_t _sigval; int _sys_private; } ;
11 struct __anonstruct__rt_235 { __kernel_pid_t _pid; __kernel_uid32_t _uid; sigval_t _sigval; } ;
11 struct __anonstruct__sigchld_236 { __kernel_pid_t _pid; __kernel_uid32_t _uid; int _status; __kernel_clock_t _utime; __kernel_clock_t _stime; } ;
11 struct __anonstruct__addr_bnd_238 { void *_lower; void *_upper; } ;
11 struct __anonstruct__sigfault_237 { void *_addr; short _addr_lsb; struct __anonstruct__addr_bnd_238 _addr_bnd; } ;
11 struct __anonstruct__sigpoll_239 { long _band; int _fd; } ;
11 struct __anonstruct__sigsys_240 { void *_call_addr; int _syscall; unsigned int _arch; } ;
11 union __anonunion__sifields_232 { int _pad[28U]; struct __anonstruct__kill_233 _kill; struct __anonstruct__timer_234 _timer; struct __anonstruct__rt_235 _rt; struct __anonstruct__sigchld_236 _sigchld; struct __anonstruct__sigfault_237 _sigfault; struct __anonstruct__sigpoll_239 _sigpoll; struct __anonstruct__sigsys_240 _sigsys; } ;
11 struct siginfo { int si_signo; int si_errno; int si_code; union __anonunion__sifields_232 _sifields; } ;
113 typedef struct siginfo siginfo_t;
12 struct user_struct ;
22 struct sigpending { struct list_head list; sigset_t signal; } ;
242 struct sigaction { __sighandler_t sa_handler; unsigned long sa_flags; __sigrestore_t sa_restorer; sigset_t sa_mask; } ;
256 struct k_sigaction { struct sigaction sa; } ;
22 struct kernel_cap_struct { __u32 cap[2U]; } ;
25 typedef struct kernel_cap_struct kernel_cap_t;
84 struct plist_node { int prio; struct list_head prio_list; struct list_head node_list; } ;
4 typedef unsigned long cputime_t;
25 struct sem_undo_list ;
25 struct sysv_sem { struct sem_undo_list *undo_list; } ;
26 struct sysv_shm { struct list_head shm_clist; } ;
57 enum pid_type { PIDTYPE_PID = 0, PIDTYPE_PGID = 1, PIDTYPE_SID = 2, PIDTYPE_MAX = 3 } ;
64 struct pid_namespace ;
64 struct upid { int nr; struct pid_namespace *ns; struct hlist_node pid_chain; } ;
56 struct pid { atomic_t count; unsigned int level; struct hlist_head tasks[3U]; struct callback_head rcu; struct upid numbers[1U]; } ;
68 struct pid_link { struct hlist_node node; struct pid *pid; } ;
174 struct percpu_counter { raw_spinlock_t lock; s64 count; struct list_head list; s32 *counters; } ;
53 struct seccomp_filter ;
54 struct seccomp { int mode; struct seccomp_filter *filter; } ;
40 struct rt_mutex_waiter ;
41 struct rlimit { __kernel_ulong_t rlim_cur; __kernel_ulong_t rlim_max; } ;
11 struct timerqueue_node { struct rb_node node; ktime_t expires; } ;
12 struct timerqueue_head { struct rb_root head; struct timerqueue_node *next; } ;
50 struct hrtimer_clock_base ;
51 struct hrtimer_cpu_base ;
60 enum hrtimer_restart { HRTIMER_NORESTART = 0, HRTIMER_RESTART = 1 } ;
65 struct hrtimer { struct timerqueue_node node; ktime_t _softexpires; enum hrtimer_restart (*function)(struct hrtimer *); struct hrtimer_clock_base *base; unsigned long state; int start_pid; void *start_site; char start_comm[16U]; } ;
123 struct hrtimer_clock_base { struct hrtimer_cpu_base *cpu_base; int index; clockid_t clockid; struct timerqueue_head active; ktime_t (*get_time)(); ktime_t offset; } ;
156 struct hrtimer_cpu_base { raw_spinlock_t lock; seqcount_t seq; struct hrtimer *running; unsigned int cpu; unsigned int active_bases; unsigned int clock_was_set_seq; bool migration_enabled; bool nohz_active; unsigned char in_hrtirq; unsigned char hres_active; unsigned char hang_detected; ktime_t expires_next; struct hrtimer *next_timer; unsigned int nr_events; unsigned int nr_retries; unsigned int nr_hangs; unsigned int max_hang_time; struct hrtimer_clock_base clock_base[4U]; } ;
466 struct task_io_accounting { u64 rchar; u64 wchar; u64 syscr; u64 syscw; u64 read_bytes; u64 write_bytes; u64 cancelled_write_bytes; } ;
45 struct latency_record { unsigned long backtrace[12U]; unsigned int count; unsigned long time; unsigned long max; } ;
39 struct assoc_array_ptr ;
39 struct assoc_array { struct assoc_array_ptr *root; unsigned long nr_leaves_on_tree; } ;
31 typedef int32_t key_serial_t;
34 typedef uint32_t key_perm_t;
35 struct key ;
36 struct signal_struct ;
37 struct key_type ;
41 struct keyring_index_key { struct key_type *type; const char *description; size_t desc_len; } ;
91 union key_payload { void *rcu_data0; void *data[4U]; } ;
128 union __anonunion____missing_field_name_260 { struct list_head graveyard_link; struct rb_node serial_node; } ;
128 struct key_user ;
128 union __anonunion____missing_field_name_261 { time_t expiry; time_t revoked_at; } ;
128 struct __anonstruct____missing_field_name_263 { struct key_type *type; char *description; } ;
128 union __anonunion____missing_field_name_262 { struct keyring_index_key index_key; struct __anonstruct____missing_field_name_263 __annonCompField55; } ;
128 struct __anonstruct____missing_field_name_265 { struct list_head name_link; struct assoc_array keys; } ;
128 union __anonunion____missing_field_name_264 { union key_payload payload; struct __anonstruct____missing_field_name_265 __annonCompField57; int reject_error; } ;
128 struct key { atomic_t usage; key_serial_t serial; union __anonunion____missing_field_name_260 __annonCompField53; struct rw_semaphore sem; struct key_user *user; void *security; union __anonunion____missing_field_name_261 __annonCompField54; time_t last_used_at; kuid_t uid; kgid_t gid; key_perm_t perm; unsigned short quotalen; unsigned short datalen; unsigned long flags; union __anonunion____missing_field_name_262 __annonCompField56; union __anonunion____missing_field_name_264 __annonCompField58; } ;
354 struct audit_context ;
27 struct group_info { atomic_t usage; int ngroups; int nblocks; kgid_t small_block[32U]; kgid_t *blocks[0U]; } ;
90 struct cred { atomic_t usage; atomic_t subscribers; void *put_addr; unsigned int magic; kuid_t uid; kgid_t gid; kuid_t suid; kgid_t sgid; kuid_t euid; kgid_t egid; kuid_t fsuid; kgid_t fsgid; unsigned int securebits; kernel_cap_t cap_inheritable; kernel_cap_t cap_permitted; kernel_cap_t cap_effective; kernel_cap_t cap_bset; kernel_cap_t cap_ambient; unsigned char jit_keyring; struct key *session_keyring; struct key *process_keyring; struct key *thread_keyring; struct key *request_key_auth; void *security; struct user_struct *user; struct user_namespace *user_ns; struct group_info *group_info; struct callback_head rcu; } ;
377 struct percpu_ref ;
55 typedef void percpu_ref_func_t(struct percpu_ref *);
68 struct percpu_ref { atomic_long_t count; unsigned long percpu_count_ptr; percpu_ref_func_t *release; percpu_ref_func_t *confirm_switch; bool force_atomic; struct callback_head rcu; } ;
327 enum rcu_sync_type { RCU_SYNC = 0, RCU_SCHED_SYNC = 1, RCU_BH_SYNC = 2 } ;
333 struct rcu_sync { int gp_state; int gp_count; wait_queue_head_t gp_wait; int cb_state; struct callback_head cb_head; enum rcu_sync_type gp_type; } ;
65 struct percpu_rw_semaphore { struct rcu_sync rss; unsigned int *fast_read_ctr; struct rw_semaphore rw_sem; atomic_t slow_read_ctr; wait_queue_head_t write_waitq; } ;
54 struct cgroup ;
55 struct cgroup_root ;
56 struct cgroup_subsys ;
57 struct cgroup_taskset ;
100 struct cgroup_file { struct kernfs_node *kn; } ;
89 struct cgroup_subsys_state { struct cgroup *cgroup; struct cgroup_subsys *ss; struct percpu_ref refcnt; struct cgroup_subsys_state *parent; struct list_head sibling; struct list_head children; int id; unsigned int flags; u64 serial_nr; struct callback_head callback_head; struct work_struct destroy_work; } ;
134 struct css_set { atomic_t refcount; struct hlist_node hlist; struct list_head tasks; struct list_head mg_tasks; struct list_head cgrp_links; struct cgroup *dfl_cgrp; struct cgroup_subsys_state *subsys[13U]; struct list_head mg_preload_node; struct list_head mg_node; struct cgroup *mg_src_cgrp; struct css_set *mg_dst_cset; struct list_head e_cset_node[13U]; struct list_head task_iters; struct callback_head callback_head; } ;
210 struct cgroup { struct cgroup_subsys_state self; unsigned long flags; int id; int level; int populated_cnt; struct kernfs_node *kn; struct cgroup_file procs_file; struct cgroup_file events_file; unsigned int subtree_control; unsigned int child_subsys_mask; struct cgroup_subsys_state *subsys[13U]; struct cgroup_root *root; struct list_head cset_links; struct list_head e_csets[13U]; struct list_head pidlists; struct mutex pidlist_mutex; wait_queue_head_t offline_waitq; struct work_struct release_agent_work; int ancestor_ids[]; } ;
294 struct cgroup_root { struct kernfs_root *kf_root; unsigned int subsys_mask; int hierarchy_id; struct cgroup cgrp; int cgrp_ancestor_id_storage; atomic_t nr_cgrps; struct list_head root_list; unsigned int flags; struct idr cgroup_idr; char release_agent_path[4096U]; char name[64U]; } ;
333 struct cftype { char name[64U]; unsigned long private; size_t max_write_len; unsigned int flags; unsigned int file_offset; struct cgroup_subsys *ss; struct list_head node; struct kernfs_ops *kf_ops; u64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *); s64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *); int (*seq_show)(struct seq_file *, void *); void * (*seq_start)(struct seq_file *, loff_t *); void * (*seq_next)(struct seq_file *, void *, loff_t *); void (*seq_stop)(struct seq_file *, void *); int (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64 ); int (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64 ); ssize_t (*write)(struct kernfs_open_file *, char *, size_t , loff_t ); struct lock_class_key lockdep_key; } ;
418 struct cgroup_subsys { struct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *); int (*css_online)(struct cgroup_subsys_state *); void (*css_offline)(struct cgroup_subsys_state *); void (*css_released)(struct cgroup_subsys_state *); void (*css_free)(struct cgroup_subsys_state *); void (*css_reset)(struct cgroup_subsys_state *); void (*css_e_css_changed)(struct cgroup_subsys_state *); int (*can_attach)(struct cgroup_taskset *); void (*cancel_attach)(struct cgroup_taskset *); void (*attach)(struct cgroup_taskset *); int (*can_fork)(struct task_struct *); void (*cancel_fork)(struct task_struct *); void (*fork)(struct task_struct *); void (*exit)(struct task_struct *); void (*free)(struct task_struct *); void (*bind)(struct cgroup_subsys_state *); int early_init; bool broken_hierarchy; bool warned_broken_hierarchy; int id; const char *name; const char *legacy_name; struct cgroup_root *root; struct idr css_idr; struct list_head cfts; struct cftype *dfl_cftypes; struct cftype *legacy_cftypes; unsigned int depends_on; } ;
128 struct futex_pi_state ;
129 struct robust_list_head ;
130 struct bio_list ;
131 struct fs_struct ;
132 struct perf_event_context ;
133 struct blk_plug ;
135 struct nameidata ;
188 struct cfs_rq ;
189 struct task_group ;
482 struct sighand_struct { atomic_t count; struct k_sigaction action[64U]; spinlock_t siglock; wait_queue_head_t signalfd_wqh; } ;
523 struct pacct_struct { int ac_flag; long ac_exitcode; unsigned long ac_mem; cputime_t ac_utime; cputime_t ac_stime; unsigned long ac_minflt; unsigned long ac_majflt; } ;
531 struct cpu_itimer { cputime_t expires; cputime_t incr; u32 error; u32 incr_error; } ;
538 struct prev_cputime { cputime_t utime; cputime_t stime; raw_spinlock_t lock; } ;
563 struct task_cputime { cputime_t utime; cputime_t stime; unsigned long long sum_exec_runtime; } ;
579 struct task_cputime_atomic { atomic64_t utime; atomic64_t stime; atomic64_t sum_exec_runtime; } ;
601 struct thread_group_cputimer { struct task_cputime_atomic cputime_atomic; bool running; bool checking_timer; } ;
646 struct autogroup ;
647 struct tty_struct ;
647 struct taskstats ;
647 struct tty_audit_buf ;
647 struct signal_struct { atomic_t sigcnt; atomic_t live; int nr_threads; struct list_head thread_head; wait_queue_head_t wait_chldexit; struct task_struct *curr_target; struct sigpending shared_pending; int group_exit_code; int notify_count; struct task_struct *group_exit_task; int group_stop_count; unsigned int flags; unsigned char is_child_subreaper; unsigned char has_child_subreaper; int posix_timer_id; struct list_head posix_timers; struct hrtimer real_timer; struct pid *leader_pid; ktime_t it_real_incr; struct cpu_itimer it[2U]; struct thread_group_cputimer cputimer; struct task_cputime cputime_expires; struct list_head cpu_timers[3U]; struct pid *tty_old_pgrp; int leader; struct tty_struct *tty; struct autogroup *autogroup; seqlock_t stats_lock; cputime_t utime; cputime_t stime; cputime_t cutime; cputime_t cstime; cputime_t gtime; cputime_t cgtime; struct prev_cputime prev_cputime; unsigned long nvcsw; unsigned long nivcsw; unsigned long cnvcsw; unsigned long cnivcsw; unsigned long min_flt; unsigned long maj_flt; unsigned long cmin_flt; unsigned long cmaj_flt; unsigned long inblock; unsigned long oublock; unsigned long cinblock; unsigned long coublock; unsigned long maxrss; unsigned long cmaxrss; struct task_io_accounting ioac; unsigned long long sum_sched_runtime; struct rlimit rlim[16U]; struct pacct_struct pacct; struct taskstats *stats; unsigned int audit_tty; unsigned int audit_tty_log_passwd; struct tty_audit_buf *tty_audit_buf; oom_flags_t oom_flags; short oom_score_adj; short oom_score_adj_min; struct mutex cred_guard_mutex; } ;
814 struct user_struct { atomic_t __count; atomic_t processes; atomic_t sigpending; atomic_t inotify_watches; atomic_t inotify_devs; atomic_t fanotify_listeners; atomic_long_t epoll_watches; unsigned long mq_bytes; unsigned long locked_shm; unsigned long unix_inflight; atomic_long_t pipe_bufs; struct key *uid_keyring; struct key *session_keyring; struct hlist_node uidhash_node; kuid_t uid; atomic_long_t locked_vm; } ;
859 struct backing_dev_info ;
860 struct reclaim_state ;
861 struct sched_info { unsigned long pcount; unsigned long long run_delay; unsigned long long last_arrival; unsigned long long last_queued; } ;
875 struct task_delay_info { spinlock_t lock; unsigned int flags; u64 blkio_start; u64 blkio_delay; u64 swapin_delay; u32 blkio_count; u32 swapin_count; u64 freepages_start; u64 freepages_delay; u32 freepages_count; } ;
923 struct wake_q_node { struct wake_q_node *next; } ;
1150 struct io_context ;
1184 struct pipe_inode_info ;
1185 struct uts_namespace ;
1186 struct load_weight { unsigned long weight; u32 inv_weight; } ;
1193 struct sched_avg { u64 last_update_time; u64 load_sum; u32 util_sum; u32 period_contrib; unsigned long load_avg; unsigned long util_avg; } ;
1213 struct sched_statistics { u64 wait_start; u64 wait_max; u64 wait_count; u64 wait_sum; u64 iowait_count; u64 iowait_sum; u64 sleep_start; u64 sleep_max; s64 sum_sleep_runtime; u64 block_start; u64 block_max; u64 exec_max; u64 slice_max; u64 nr_migrations_cold; u64 nr_failed_migrations_affine; u64 nr_failed_migrations_running; u64 nr_failed_migrations_hot; u64 nr_forced_migrations; u64 nr_wakeups; u64 nr_wakeups_sync; u64 nr_wakeups_migrate; u64 nr_wakeups_local; u64 nr_wakeups_remote; u64 nr_wakeups_affine; u64 nr_wakeups_affine_attempts; u64 nr_wakeups_passive; u64 nr_wakeups_idle; } ;
1248 struct sched_entity { struct load_weight load; struct rb_node run_node; struct list_head group_node; unsigned int on_rq; u64 exec_start; u64 sum_exec_runtime; u64 vruntime; u64 prev_sum_exec_runtime; u64 nr_migrations; struct sched_statistics statistics; int depth; struct sched_entity *parent; struct cfs_rq *cfs_rq; struct cfs_rq *my_q; struct sched_avg avg; } ;
1285 struct rt_rq ;
1285 struct sched_rt_entity { struct list_head run_list; unsigned long timeout; unsigned long watchdog_stamp; unsigned int time_slice; struct sched_rt_entity *back; struct sched_rt_entity *parent; struct rt_rq *rt_rq; struct rt_rq *my_q; } ;
1301 struct sched_dl_entity { struct rb_node rb_node; u64 dl_runtime; u64 dl_deadline; u64 dl_period; u64 dl_bw; s64 runtime; u64 deadline; unsigned int flags; int dl_throttled; int dl_new; int dl_boosted; int dl_yielded; struct hrtimer dl_timer; } ;
1369 struct tlbflush_unmap_batch { struct cpumask cpumask; bool flush_required; bool writable; } ;
1388 struct sched_class ;
1388 struct files_struct ;
1388 struct compat_robust_list_head ;
1388 struct numa_group ;
1388 struct task_struct { volatile long state; void *stack; atomic_t usage; unsigned int flags; unsigned int ptrace; struct llist_node wake_entry; int on_cpu; unsigned int wakee_flips; unsigned long wakee_flip_decay_ts; struct task_struct *last_wakee; int wake_cpu; int on_rq; int prio; int static_prio; int normal_prio; unsigned int rt_priority; const struct sched_class *sched_class; struct sched_entity se; struct sched_rt_entity rt; struct task_group *sched_task_group; struct sched_dl_entity dl; struct hlist_head preempt_notifiers; unsigned int policy; int nr_cpus_allowed; cpumask_t cpus_allowed; unsigned long rcu_tasks_nvcsw; bool rcu_tasks_holdout; struct list_head rcu_tasks_holdout_list; int rcu_tasks_idle_cpu; struct sched_info sched_info; struct list_head tasks; struct plist_node pushable_tasks; struct rb_node pushable_dl_tasks; struct mm_struct *mm; struct mm_struct *active_mm; u32 vmacache_seqnum; struct vm_area_struct *vmacache[4U]; struct task_rss_stat rss_stat; int exit_state; int exit_code; int exit_signal; int pdeath_signal; unsigned long jobctl; unsigned int personality; unsigned char sched_reset_on_fork; unsigned char sched_contributes_to_load; unsigned char sched_migrated; unsigned char; unsigned char in_execve; unsigned char in_iowait; unsigned char memcg_may_oom; unsigned char memcg_kmem_skip_account; unsigned char brk_randomized; unsigned long atomic_flags; struct restart_block restart_block; pid_t pid; pid_t tgid; struct task_struct *real_parent; struct task_struct *parent; struct list_head children; struct list_head sibling; struct task_struct *group_leader; struct list_head ptraced; struct list_head ptrace_entry; struct pid_link pids[3U]; struct list_head thread_group; struct list_head thread_node; struct completion *vfork_done; int *set_child_tid; int *clear_child_tid; cputime_t utime; cputime_t stime; cputime_t utimescaled; cputime_t stimescaled; cputime_t gtime; struct prev_cputime prev_cputime; unsigned long nvcsw; unsigned long nivcsw; u64 start_time; u64 real_start_time; unsigned long min_flt; unsigned long maj_flt; struct task_cputime cputime_expires; struct list_head cpu_timers[3U]; const struct cred *real_cred; const struct cred *cred; char comm[16U]; struct nameidata *nameidata; struct sysv_sem sysvsem; struct sysv_shm sysvshm; unsigned long last_switch_count; struct fs_struct *fs; struct files_struct *files; struct nsproxy *nsproxy; struct signal_struct *signal; struct sighand_struct *sighand; sigset_t blocked; sigset_t real_blocked; sigset_t saved_sigmask; struct sigpending pending; unsigned long sas_ss_sp; size_t sas_ss_size; struct callback_head *task_works; struct audit_context *audit_context; kuid_t loginuid; unsigned int sessionid; struct seccomp seccomp; u32 parent_exec_id; u32 self_exec_id; spinlock_t alloc_lock; raw_spinlock_t pi_lock; struct wake_q_node wake_q; struct rb_root pi_waiters; struct rb_node *pi_waiters_leftmost; struct rt_mutex_waiter *pi_blocked_on; struct mutex_waiter *blocked_on; unsigned int irq_events; unsigned long hardirq_enable_ip; unsigned long hardirq_disable_ip; unsigned int hardirq_enable_event; unsigned int hardirq_disable_event; int hardirqs_enabled; int hardirq_context; unsigned long softirq_disable_ip; unsigned long softirq_enable_ip; unsigned int softirq_disable_event; unsigned int softirq_enable_event; int softirqs_enabled; int softirq_context; u64 curr_chain_key; int lockdep_depth; unsigned int lockdep_recursion; struct held_lock held_locks[48U]; gfp_t lockdep_reclaim_gfp; unsigned int in_ubsan; void *journal_info; struct bio_list *bio_list; struct blk_plug *plug; struct reclaim_state *reclaim_state; struct backing_dev_info *backing_dev_info; struct io_context *io_context; unsigned long ptrace_message; siginfo_t *last_siginfo; struct task_io_accounting ioac; u64 acct_rss_mem1; u64 acct_vm_mem1; cputime_t acct_timexpd; nodemask_t mems_allowed; seqcount_t mems_allowed_seq; int cpuset_mem_spread_rotor; int cpuset_slab_spread_rotor; struct css_set *cgroups; struct list_head cg_list; struct robust_list_head *robust_list; struct compat_robust_list_head *compat_robust_list; struct list_head pi_state_list; struct futex_pi_state *pi_state_cache; struct perf_event_context *perf_event_ctxp[2U]; struct mutex perf_event_mutex; struct list_head perf_event_list; struct mempolicy *mempolicy; short il_next; short pref_node_fork; int numa_scan_seq; unsigned int numa_scan_period; unsigned int numa_scan_period_max; int numa_preferred_nid; unsigned long numa_migrate_retry; u64 node_stamp; u64 last_task_numa_placement; u64 last_sum_exec_runtime; struct callback_head numa_work; struct list_head numa_entry; struct numa_group *numa_group; unsigned long *numa_faults; unsigned long total_numa_faults; unsigned long numa_faults_locality[3U]; unsigned long numa_pages_migrated; struct tlbflush_unmap_batch tlb_ubc; struct callback_head rcu; struct pipe_inode_info *splice_pipe; struct page_frag task_frag; struct task_delay_info *delays; int make_it_fail; int nr_dirtied; int nr_dirtied_pause; unsigned long dirty_paused_when; int latency_record_count; struct latency_record latency_record[32U]; unsigned long timer_slack_ns; unsigned long default_timer_slack_ns; unsigned int kasan_depth; unsigned long trace; unsigned long trace_recursion; struct mem_cgroup *memcg_in_oom; gfp_t memcg_oom_gfp_mask; int memcg_oom_order; unsigned int memcg_nr_pages_over_high; struct uprobe_task *utask; unsigned int sequential_io; unsigned int sequential_io_avg; unsigned long task_state_change; int pagefault_disabled; struct thread_struct thread; } ;
3209 enum irqreturn { IRQ_NONE = 0, IRQ_HANDLED = 1, IRQ_WAKE_THREAD = 2 } ;
16 typedef enum irqreturn irqreturn_t;
8 struct irq_desc ;
135 struct irq_data ;
30 struct msi_msg ;
31 enum irqchip_irq_state ;
63 struct msi_desc ;
64 struct irq_domain ;
65 struct irq_common_data { unsigned int state_use_accessors; unsigned int node; void *handler_data; struct msi_desc *msi_desc; cpumask_var_t affinity; } ;
148 struct irq_chip ;
148 struct irq_data { u32 mask; unsigned int irq; unsigned long hwirq; struct irq_common_data *common; struct irq_chip *chip; struct irq_domain *domain; struct irq_data *parent_data; void *chip_data; } ;
306 struct irq_chip { const char *name; unsigned int (*irq_startup)(struct irq_data *); void (*irq_shutdown)(struct irq_data *); void (*irq_enable)(struct irq_data *); void (*irq_disable)(struct irq_data *); void (*irq_ack)(struct irq_data *); void (*irq_mask)(struct irq_data *); void (*irq_mask_ack)(struct irq_data *); void (*irq_unmask)(struct irq_data *); void (*irq_eoi)(struct irq_data *); int (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool ); int (*irq_retrigger)(struct irq_data *); int (*irq_set_type)(struct irq_data *, unsigned int); int (*irq_set_wake)(struct irq_data *, unsigned int); void (*irq_bus_lock)(struct irq_data *); void (*irq_bus_sync_unlock)(struct irq_data *); void (*irq_cpu_online)(struct irq_data *); void (*irq_cpu_offline)(struct irq_data *); void (*irq_suspend)(struct irq_data *); void (*irq_resume)(struct irq_data *); void (*irq_pm_shutdown)(struct irq_data *); void (*irq_calc_mask)(struct irq_data *); void (*irq_print_chip)(struct irq_data *, struct seq_file *); int (*irq_request_resources)(struct irq_data *); void (*irq_release_resources)(struct irq_data *); void (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *); void (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *); int (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state , bool *); int (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state , bool ); int (*irq_set_vcpu_affinity)(struct irq_data *, void *); unsigned long flags; } ;
400 struct irq_affinity_notify ;
401 struct proc_dir_entry ;
402 struct irqaction ;
402 struct irq_desc { struct irq_common_data irq_common_data; struct irq_data irq_data; unsigned int *kstat_irqs; void (*handle_irq)(struct irq_desc *); struct irqaction *action; unsigned int status_use_accessors; unsigned int core_internal_state__do_not_mess_with_it; unsigned int depth; unsigned int wake_depth; unsigned int irq_count; unsigned long last_unhandled; unsigned int irqs_unhandled; atomic_t threads_handled; int threads_handled_last; raw_spinlock_t lock; struct cpumask *percpu_enabled; const struct cpumask *affinity_hint; struct irq_affinity_notify *affinity_notify; cpumask_var_t pending_mask; unsigned long threads_oneshot; atomic_t threads_active; wait_queue_head_t wait_for_threads; unsigned int nr_actions; unsigned int no_suspend_depth; unsigned int cond_suspend_depth; unsigned int force_resume_depth; struct proc_dir_entry *dir; struct callback_head rcu; int parent_irq; struct module *owner; const char *name; } ;
62 struct exception_table_entry { int insn; int fixup; } ;
710 struct irq_chip_regs { unsigned long enable; unsigned long disable; unsigned long mask; unsigned long ack; unsigned long eoi; unsigned long type; unsigned long polarity; } ;
749 struct irq_chip_type { struct irq_chip chip; struct irq_chip_regs regs; void (*handler)(struct irq_desc *); u32 type; u32 mask_cache_priv; u32 *mask_cache; } ;
771 struct irq_chip_generic { raw_spinlock_t lock; void *reg_base; u32 (*reg_readl)(void *); void (*reg_writel)(u32 , void *); void (*suspend)(struct irq_chip_generic *); void (*resume)(struct irq_chip_generic *); unsigned int irq_base; unsigned int irq_cnt; u32 mask_cache; u32 type_cache; u32 polarity_cache; u32 wake_enabled; u32 wake_active; unsigned int num_ct; void *private; unsigned long installed; unsigned long unused; struct irq_domain *domain; struct list_head list; struct irq_chip_type chip_types[0U]; } ;
827 enum irq_gc_flags { IRQ_GC_INIT_MASK_CACHE = 1, IRQ_GC_INIT_NESTED_LOCK = 2, IRQ_GC_MASK_CACHE_PER_TYPE = 4, IRQ_GC_NO_MASK = 8, IRQ_GC_BE_IO = 16 } ;
835 struct irq_domain_chip_generic { unsigned int irqs_per_chip; unsigned int num_chips; unsigned int irq_flags_to_clear; unsigned int irq_flags_to_set; enum irq_gc_flags gc_flags; struct irq_chip_generic *gc[0U]; } ;
93 struct irqaction { irqreturn_t (*handler)(int, void *); void *dev_id; void *percpu_dev_id; struct irqaction *next; irqreturn_t (*thread_fn)(int, void *); struct task_struct *thread; struct irqaction *secondary; unsigned int irq; unsigned int flags; unsigned long thread_flags; unsigned long thread_mask; const char *name; struct proc_dir_entry *dir; } ;
204 struct irq_affinity_notify { unsigned int irq; struct kref kref; struct work_struct work; void (*notify)(struct irq_affinity_notify *, const cpumask_t *); void (*release)(struct kref *); } ;
366 enum irqchip_irq_state { IRQCHIP_STATE_PENDING = 0, IRQCHIP_STATE_ACTIVE = 1, IRQCHIP_STATE_MASKED = 2, IRQCHIP_STATE_LINE_LEVEL = 3 } ;
468 struct tasklet_struct { struct tasklet_struct *next; unsigned long state; atomic_t count; void (*func)(unsigned long); unsigned long data; } ;
13 typedef unsigned long kernel_ulong_t;
14 struct pci_device_id { __u32 vendor; __u32 device; __u32 subvendor; __u32 subdevice; __u32 class; __u32 class_mask; kernel_ulong_t driver_data; } ;
186 struct acpi_device_id { __u8 id[9U]; kernel_ulong_t driver_data; __u32 cls; __u32 cls_msk; } ;
229 struct of_device_id { char name[32U]; char type[32U]; char compatible[128U]; const void *data; } ;
659 struct klist_node ;
37 struct klist_node { void *n_klist; struct list_head n_node; struct kref n_ref; } ;
68 struct path ;
69 struct seq_file { char *buf; size_t size; size_t from; size_t count; size_t pad_until; loff_t index; loff_t read_pos; u64 version; struct mutex lock; const struct seq_operations *op; int poll_event; struct user_namespace *user_ns; void *private; } ;
35 struct seq_operations { void * (*start)(struct seq_file *, loff_t *); void (*stop)(struct seq_file *, void *); void * (*next)(struct seq_file *, void *, loff_t *); int (*show)(struct seq_file *, void *); } ;
227 struct pinctrl ;
228 struct pinctrl_state ;
194 struct dev_pin_info { struct pinctrl *p; struct pinctrl_state *default_state; struct pinctrl_state *init_state; struct pinctrl_state *sleep_state; struct pinctrl_state *idle_state; } ;
48 struct dma_map_ops ;
48 struct dev_archdata { struct dma_map_ops *dma_ops; void *iommu; } ;
24 struct device_private ;
25 struct device_driver ;
26 struct driver_private ;
27 struct class ;
28 struct subsys_private ;
29 struct bus_type ;
30 struct device_node ;
31 struct fwnode_handle ;
32 struct iommu_ops ;
33 struct iommu_group ;
61 struct device_attribute ;
61 struct bus_type { const char *name; const char *dev_name; struct device *dev_root; struct device_attribute *dev_attrs; const struct attribute_group **bus_groups; const struct attribute_group **dev_groups; const struct attribute_group **drv_groups; int (*match)(struct device *, struct device_driver *); int (*uevent)(struct device *, struct kobj_uevent_env *); int (*probe)(struct device *); int (*remove)(struct device *); void (*shutdown)(struct device *); int (*online)(struct device *); int (*offline)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); const struct dev_pm_ops *pm; const struct iommu_ops *iommu_ops; struct subsys_private *p; struct lock_class_key lock_key; } ;
139 struct device_type ;
198 enum probe_type { PROBE_DEFAULT_STRATEGY = 0, PROBE_PREFER_ASYNCHRONOUS = 1, PROBE_FORCE_SYNCHRONOUS = 2 } ;
204 struct device_driver { const char *name; struct bus_type *bus; struct module *owner; const char *mod_name; bool suppress_bind_attrs; enum probe_type probe_type; const struct of_device_id *of_match_table; const struct acpi_device_id *acpi_match_table; int (*probe)(struct device *); int (*remove)(struct device *); void (*shutdown)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); const struct attribute_group **groups; const struct dev_pm_ops *pm; struct driver_private *p; } ;
354 struct class_attribute ;
354 struct class { const char *name; struct module *owner; struct class_attribute *class_attrs; const struct attribute_group **dev_groups; struct kobject *dev_kobj; int (*dev_uevent)(struct device *, struct kobj_uevent_env *); char * (*devnode)(struct device *, umode_t *); void (*class_release)(struct class *); void (*dev_release)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); const struct kobj_ns_type_operations *ns_type; const void * (*namespace)(struct device *); const struct dev_pm_ops *pm; struct subsys_private *p; } ;
447 struct class_attribute { struct attribute attr; ssize_t (*show)(struct class *, struct class_attribute *, char *); ssize_t (*store)(struct class *, struct class_attribute *, const char *, size_t ); } ;
515 struct device_type { const char *name; const struct attribute_group **groups; int (*uevent)(struct device *, struct kobj_uevent_env *); char * (*devnode)(struct device *, umode_t *, kuid_t *, kgid_t *); void (*release)(struct device *); const struct dev_pm_ops *pm; } ;
543 struct device_attribute { struct attribute attr; ssize_t (*show)(struct device *, struct device_attribute *, char *); ssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t ); } ;
684 struct device_dma_parameters { unsigned int max_segment_size; unsigned long segment_boundary_mask; } ;
693 struct dma_coherent_mem ;
693 struct cma ;
693 struct device { struct device *parent; struct device_private *p; struct kobject kobj; const char *init_name; const struct device_type *type; struct mutex mutex; struct bus_type *bus; struct device_driver *driver; void *platform_data; void *driver_data; struct dev_pm_info power; struct dev_pm_domain *pm_domain; struct irq_domain *msi_domain; struct dev_pin_info *pins; struct list_head msi_list; int numa_node; u64 *dma_mask; u64 coherent_dma_mask; unsigned long dma_pfn_offset; struct device_dma_parameters *dma_parms; struct list_head dma_pools; struct dma_coherent_mem *dma_mem; struct cma *cma_area; struct dev_archdata archdata; struct device_node *of_node; struct fwnode_handle *fwnode; dev_t devt; u32 id; spinlock_t devres_lock; struct list_head devres_head; struct klist_node knode_class; struct class *class; const struct attribute_group **groups; void (*release)(struct device *); struct iommu_group *iommu_group; bool offline_disabled; bool offline; } ;
847 struct wakeup_source { const char *name; struct list_head entry; spinlock_t lock; struct wake_irq *wakeirq; struct timer_list timer; unsigned long timer_expires; ktime_t total_time; ktime_t max_time; ktime_t last_time; ktime_t start_prevent_time; ktime_t prevent_sleep_time; unsigned long event_count; unsigned long active_count; unsigned long relax_count; unsigned long expire_count; unsigned long wakeup_count; bool active; bool autosleep_enabled; } ;
70 struct hotplug_slot ;
70 struct pci_slot { struct pci_bus *bus; struct list_head list; struct hotplug_slot *hotplug; unsigned char number; struct kobject kobj; } ;
110 typedef int pci_power_t;
137 typedef unsigned int pci_channel_state_t;
138 enum pci_channel_state { pci_channel_io_normal = 1, pci_channel_io_frozen = 2, pci_channel_io_perm_failure = 3 } ;
163 typedef unsigned short pci_dev_flags_t;
192 typedef unsigned short pci_bus_flags_t;
249 struct pcie_link_state ;
250 struct pci_vpd ;
251 struct pci_sriov ;
253 struct pci_driver ;
253 union __anonunion____missing_field_name_302 { struct pci_sriov *sriov; struct pci_dev *physfn; } ;
253 struct pci_dev { struct list_head bus_list; struct pci_bus *bus; struct pci_bus *subordinate; void *sysdata; struct proc_dir_entry *procent; struct pci_slot *slot; unsigned int devfn; unsigned short vendor; unsigned short device; unsigned short subsystem_vendor; unsigned short subsystem_device; unsigned int class; u8 revision; u8 hdr_type; u8 pcie_cap; u8 msi_cap; u8 msix_cap; unsigned char pcie_mpss; u8 rom_base_reg; u8 pin; u16 pcie_flags_reg; u8 dma_alias_devfn; struct pci_driver *driver; u64 dma_mask; struct device_dma_parameters dma_parms; pci_power_t current_state; u8 pm_cap; unsigned char pme_support; unsigned char pme_interrupt; unsigned char pme_poll; unsigned char d1_support; unsigned char d2_support; unsigned char no_d1d2; unsigned char no_d3cold; unsigned char d3cold_allowed; unsigned char mmio_always_on; unsigned char wakeup_prepared; unsigned char runtime_d3cold; unsigned char ignore_hotplug; unsigned int d3_delay; unsigned int d3cold_delay; struct pcie_link_state *link_state; pci_channel_state_t error_state; struct device dev; int cfg_size; unsigned int irq; struct resource resource[17U]; bool match_driver; unsigned char transparent; unsigned char multifunction; unsigned char is_added; unsigned char is_busmaster; unsigned char no_msi; unsigned char no_64bit_msi; unsigned char block_cfg_access; unsigned char broken_parity_status; unsigned char irq_reroute_variant; unsigned char msi_enabled; unsigned char msix_enabled; unsigned char ari_enabled; unsigned char ats_enabled; unsigned char is_managed; unsigned char needs_freset; unsigned char state_saved; unsigned char is_physfn; unsigned char is_virtfn; unsigned char reset_fn; unsigned char is_hotplug_bridge; unsigned char __aer_firmware_first_valid; unsigned char __aer_firmware_first; unsigned char broken_intx_masking; unsigned char io_window_1k; unsigned char irq_managed; unsigned char has_secondary_link; pci_dev_flags_t dev_flags; atomic_t enable_cnt; u32 saved_config_space[16U]; struct hlist_head saved_cap_space; struct bin_attribute *rom_attr; int rom_attr_enabled; struct bin_attribute *res_attr[17U]; struct bin_attribute *res_attr_wc[17U]; const struct attribute_group **msi_irq_groups; struct pci_vpd *vpd; union __anonunion____missing_field_name_302 __annonCompField72; u16 ats_cap; u8 ats_stu; atomic_t ats_ref_cnt; phys_addr_t rom; size_t romlen; char *driver_override; } ;
453 struct pci_ops ;
453 struct msi_controller ;
453 struct pci_bus { struct list_head node; struct pci_bus *parent; struct list_head children; struct list_head devices; struct pci_dev *self; struct list_head slots; struct resource *resource[4U]; struct list_head resources; struct resource busn_res; struct pci_ops *ops; struct msi_controller *msi; void *sysdata; struct proc_dir_entry *procdir; unsigned char number; unsigned char primary; unsigned char max_bus_speed; unsigned char cur_bus_speed; char name[48U]; unsigned short bridge_ctl; pci_bus_flags_t bus_flags; struct device *bridge; struct device dev; struct bin_attribute *legacy_io; struct bin_attribute *legacy_mem; unsigned char is_added; } ;
577 struct pci_ops { void * (*map_bus)(struct pci_bus *, unsigned int, int); int (*read)(struct pci_bus *, unsigned int, int, int, u32 *); int (*write)(struct pci_bus *, unsigned int, int, int, u32 ); } ;
605 struct pci_dynids { spinlock_t lock; struct list_head list; } ;
619 typedef unsigned int pci_ers_result_t;
629 struct pci_error_handlers { pci_ers_result_t (*error_detected)(struct pci_dev *, enum pci_channel_state ); pci_ers_result_t (*mmio_enabled)(struct pci_dev *); pci_ers_result_t (*link_reset)(struct pci_dev *); pci_ers_result_t (*slot_reset)(struct pci_dev *); void (*reset_notify)(struct pci_dev *, bool ); void (*resume)(struct pci_dev *); } ;
662 struct pci_driver { struct list_head node; const char *name; const struct pci_device_id *id_table; int (*probe)(struct pci_dev *, const struct pci_device_id *); void (*remove)(struct pci_dev *); int (*suspend)(struct pci_dev *, pm_message_t ); int (*suspend_late)(struct pci_dev *, pm_message_t ); int (*resume_early)(struct pci_dev *); int (*resume)(struct pci_dev *); void (*shutdown)(struct pci_dev *); int (*sriov_configure)(struct pci_dev *, int); const struct pci_error_handlers *err_handler; struct device_driver driver; struct pci_dynids dynids; } ;
93 struct shrink_control { gfp_t gfp_mask; unsigned long nr_to_scan; int nid; struct mem_cgroup *memcg; } ;
27 struct shrinker { unsigned long int (*count_objects)(struct shrinker *, struct shrink_control *); unsigned long int (*scan_objects)(struct shrinker *, struct shrink_control *); int seeks; long batch; unsigned long flags; struct list_head list; atomic_long_t *nr_deferred; } ;
68 struct file_ra_state ;
69 struct writeback_control ;
70 struct bdi_writeback ;
226 struct vm_fault { unsigned int flags; gfp_t gfp_mask; unsigned long pgoff; void *virtual_address; struct page *cow_page; struct page *page; unsigned long max_pgoff; pte_t *pte; } ;
262 struct vm_operations_struct { void (*open)(struct vm_area_struct *); void (*close)(struct vm_area_struct *); int (*mremap)(struct vm_area_struct *); int (*fault)(struct vm_area_struct *, struct vm_fault *); int (*pmd_fault)(struct vm_area_struct *, unsigned long, pmd_t *, unsigned int); void (*map_pages)(struct vm_area_struct *, struct vm_fault *); int (*page_mkwrite)(struct vm_area_struct *, struct vm_fault *); int (*pfn_mkwrite)(struct vm_area_struct *, struct vm_fault *); int (*access)(struct vm_area_struct *, unsigned long, void *, int, int); const char * (*name)(struct vm_area_struct *); int (*set_policy)(struct vm_area_struct *, struct mempolicy *); struct mempolicy * (*get_policy)(struct vm_area_struct *, unsigned long); struct page * (*find_special_page)(struct vm_area_struct *, unsigned long); } ;
1285 struct kvec ;
2365 struct scatterlist { unsigned long sg_magic; unsigned long page_link; unsigned int offset; unsigned int length; dma_addr_t dma_address; unsigned int dma_length; } ;
21 struct sg_table { struct scatterlist *sgl; unsigned int nents; unsigned int orig_nents; } ;
34 struct dma_attrs { unsigned long flags[1U]; } ;
89 enum dma_data_direction { DMA_BIDIRECTIONAL = 0, DMA_TO_DEVICE = 1, DMA_FROM_DEVICE = 2, DMA_NONE = 3 } ;
158 struct dma_map_ops { void * (*alloc)(struct device *, size_t , dma_addr_t *, gfp_t , struct dma_attrs *); void (*free)(struct device *, size_t , void *, dma_addr_t , struct dma_attrs *); int (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t , size_t , struct dma_attrs *); int (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t , size_t , struct dma_attrs *); dma_addr_t (*map_page)(struct device *, struct page *, unsigned long, size_t , enum dma_data_direction , struct dma_attrs *); void (*unmap_page)(struct device *, dma_addr_t , size_t , enum dma_data_direction , struct dma_attrs *); int (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction , struct dma_attrs *); void (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction , struct dma_attrs *); void (*sync_single_for_cpu)(struct device *, dma_addr_t , size_t , enum dma_data_direction ); void (*sync_single_for_device)(struct device *, dma_addr_t , size_t , enum dma_data_direction ); void (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction ); void (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction ); int (*mapping_error)(struct device *, dma_addr_t ); int (*dma_supported)(struct device *, u64 ); int (*set_dma_mask)(struct device *, u64 ); int is_phys; } ;
81 struct hlist_bl_node ;
81 struct hlist_bl_head { struct hlist_bl_node *first; } ;
36 struct hlist_bl_node { struct hlist_bl_node *next; struct hlist_bl_node **pprev; } ;
114 struct __anonstruct____missing_field_name_320 { spinlock_t lock; int count; } ;
114 union __anonunion____missing_field_name_319 { struct __anonstruct____missing_field_name_320 __annonCompField73; } ;
114 struct lockref { union __anonunion____missing_field_name_319 __annonCompField74; } ;
50 struct vfsmount ;
51 struct __anonstruct____missing_field_name_322 { u32 hash; u32 len; } ;
51 union __anonunion____missing_field_name_321 { struct __anonstruct____missing_field_name_322 __annonCompField75; u64 hash_len; } ;
51 struct qstr { union __anonunion____missing_field_name_321 __annonCompField76; const unsigned char *name; } ;
90 struct dentry_operations ;
90 union __anonunion_d_u_323 { struct hlist_node d_alias; struct callback_head d_rcu; } ;
90 struct dentry { unsigned int d_flags; seqcount_t d_seq; struct hlist_bl_node d_hash; struct dentry *d_parent; struct qstr d_name; struct inode *d_inode; unsigned char d_iname[32U]; struct lockref d_lockref; const struct dentry_operations *d_op; struct super_block *d_sb; unsigned long d_time; void *d_fsdata; struct list_head d_lru; struct list_head d_child; struct list_head d_subdirs; union __anonunion_d_u_323 d_u; } ;
142 struct dentry_operations { int (*d_revalidate)(struct dentry *, unsigned int); int (*d_weak_revalidate)(struct dentry *, unsigned int); int (*d_hash)(const struct dentry *, struct qstr *); int (*d_compare)(const struct dentry *, const struct dentry *, unsigned int, const char *, const struct qstr *); int (*d_delete)(const struct dentry *); void (*d_release)(struct dentry *); void (*d_prune)(struct dentry *); void (*d_iput)(struct dentry *, struct inode *); char * (*d_dname)(struct dentry *, char *, int); struct vfsmount * (*d_automount)(struct path *); int (*d_manage)(struct dentry *, bool ); struct inode * (*d_select_inode)(struct dentry *, unsigned int); } ;
586 struct path { struct vfsmount *mnt; struct dentry *dentry; } ;
27 struct list_lru_one { struct list_head list; long nr_items; } ;
32 struct list_lru_memcg { struct list_lru_one *lru[0U]; } ;
37 struct list_lru_node { spinlock_t lock; struct list_lru_one lru; struct list_lru_memcg *memcg_lrus; } ;
47 struct list_lru { struct list_lru_node *node; struct list_head list; } ;
67 struct __anonstruct____missing_field_name_327 { struct radix_tree_node *parent; void *private_data; } ;
67 union __anonunion____missing_field_name_326 { struct __anonstruct____missing_field_name_327 __annonCompField77; struct callback_head callback_head; } ;
67 struct radix_tree_node { unsigned int path; unsigned int count; union __anonunion____missing_field_name_326 __annonCompField78; struct list_head private_list; void *slots[64U]; unsigned long tags[3U][1U]; } ;
114 struct radix_tree_root { unsigned int height; gfp_t gfp_mask; struct radix_tree_node *rnode; } ;
45 struct fiemap_extent { __u64 fe_logical; __u64 fe_physical; __u64 fe_length; __u64 fe_reserved64[2U]; __u32 fe_flags; __u32 fe_reserved[3U]; } ;
38 enum migrate_mode { MIGRATE_ASYNC = 0, MIGRATE_SYNC_LIGHT = 1, MIGRATE_SYNC = 2 } ;
47 struct block_device ;
19 struct bio_vec { struct page *bv_page; unsigned int bv_len; unsigned int bv_offset; } ;
268 struct delayed_call { void (*fn)(void *); void *arg; } ;
162 struct export_operations ;
164 struct iovec ;
165 struct kiocb ;
166 struct poll_table_struct ;
167 struct kstatfs ;
168 struct swap_info_struct ;
169 struct iov_iter ;
76 struct iattr { unsigned int ia_valid; umode_t ia_mode; kuid_t ia_uid; kgid_t ia_gid; loff_t ia_size; struct timespec ia_atime; struct timespec ia_mtime; struct timespec ia_ctime; struct file *ia_file; } ;
212 struct dquot ;
19 typedef __kernel_uid32_t projid_t;
23 struct __anonstruct_kprojid_t_333 { projid_t val; } ;
23 typedef struct __anonstruct_kprojid_t_333 kprojid_t;
166 enum quota_type { USRQUOTA = 0, GRPQUOTA = 1, PRJQUOTA = 2 } ;
66 typedef long long qsize_t;
67 union __anonunion____missing_field_name_334 { kuid_t uid; kgid_t gid; kprojid_t projid; } ;
67 struct kqid { union __anonunion____missing_field_name_334 __annonCompField80; enum quota_type type; } ;
184 struct mem_dqblk { qsize_t dqb_bhardlimit; qsize_t dqb_bsoftlimit; qsize_t dqb_curspace; qsize_t dqb_rsvspace; qsize_t dqb_ihardlimit; qsize_t dqb_isoftlimit; qsize_t dqb_curinodes; time_t dqb_btime; time_t dqb_itime; } ;
206 struct quota_format_type ;
207 struct mem_dqinfo { struct quota_format_type *dqi_format; int dqi_fmt_id; struct list_head dqi_dirty_list; unsigned long dqi_flags; unsigned int dqi_bgrace; unsigned int dqi_igrace; qsize_t dqi_max_spc_limit; qsize_t dqi_max_ino_limit; void *dqi_priv; } ;
272 struct dquot { struct hlist_node dq_hash; struct list_head dq_inuse; struct list_head dq_free; struct list_head dq_dirty; struct mutex dq_lock; atomic_t dq_count; wait_queue_head_t dq_wait_unused; struct super_block *dq_sb; struct kqid dq_id; loff_t dq_off; unsigned long dq_flags; struct mem_dqblk dq_dqb; } ;
299 struct quota_format_ops { int (*check_quota_file)(struct super_block *, int); int (*read_file_info)(struct super_block *, int); int (*write_file_info)(struct super_block *, int); int (*free_file_info)(struct super_block *, int); int (*read_dqblk)(struct dquot *); int (*commit_dqblk)(struct dquot *); int (*release_dqblk)(struct dquot *); } ;
310 struct dquot_operations { int (*write_dquot)(struct dquot *); struct dquot * (*alloc_dquot)(struct super_block *, int); void (*destroy_dquot)(struct dquot *); int (*acquire_dquot)(struct dquot *); int (*release_dquot)(struct dquot *); int (*mark_dirty)(struct dquot *); int (*write_info)(struct super_block *, int); qsize_t * (*get_reserved_space)(struct inode *); int (*get_projid)(struct inode *, kprojid_t *); } ;
325 struct qc_dqblk { int d_fieldmask; u64 d_spc_hardlimit; u64 d_spc_softlimit; u64 d_ino_hardlimit; u64 d_ino_softlimit; u64 d_space; u64 d_ino_count; s64 d_ino_timer; s64 d_spc_timer; int d_ino_warns; int d_spc_warns; u64 d_rt_spc_hardlimit; u64 d_rt_spc_softlimit; u64 d_rt_space; s64 d_rt_spc_timer; int d_rt_spc_warns; } ;
348 struct qc_type_state { unsigned int flags; unsigned int spc_timelimit; unsigned int ino_timelimit; unsigned int rt_spc_timelimit; unsigned int spc_warnlimit; unsigned int ino_warnlimit; unsigned int rt_spc_warnlimit; unsigned long long ino; blkcnt_t blocks; blkcnt_t nextents; } ;
394 struct qc_state { unsigned int s_incoredqs; struct qc_type_state s_state[3U]; } ;
405 struct qc_info { int i_fieldmask; unsigned int i_flags; unsigned int i_spc_timelimit; unsigned int i_ino_timelimit; unsigned int i_rt_spc_timelimit; unsigned int i_spc_warnlimit; unsigned int i_ino_warnlimit; unsigned int i_rt_spc_warnlimit; } ;
418 struct quotactl_ops { int (*quota_on)(struct super_block *, int, int, struct path *); int (*quota_off)(struct super_block *, int); int (*quota_enable)(struct super_block *, unsigned int); int (*quota_disable)(struct super_block *, unsigned int); int (*quota_sync)(struct super_block *, int); int (*set_info)(struct super_block *, int, struct qc_info *); int (*get_dqblk)(struct super_block *, struct kqid , struct qc_dqblk *); int (*set_dqblk)(struct super_block *, struct kqid , struct qc_dqblk *); int (*get_state)(struct super_block *, struct qc_state *); int (*rm_xquota)(struct super_block *, unsigned int); } ;
432 struct quota_format_type { int qf_fmt_id; const struct quota_format_ops *qf_ops; struct module *qf_owner; struct quota_format_type *qf_next; } ;
496 struct quota_info { unsigned int flags; struct mutex dqio_mutex; struct mutex dqonoff_mutex; struct inode *files[3U]; struct mem_dqinfo info[3U]; const struct quota_format_ops *ops[3U]; } ;
526 struct kiocb { struct file *ki_filp; loff_t ki_pos; void (*ki_complete)(struct kiocb *, long, long); void *private; int ki_flags; } ;
367 struct address_space_operations { int (*writepage)(struct page *, struct writeback_control *); int (*readpage)(struct file *, struct page *); int (*writepages)(struct address_space *, struct writeback_control *); int (*set_page_dirty)(struct page *); int (*readpages)(struct file *, struct address_space *, struct list_head *, unsigned int); int (*write_begin)(struct file *, struct address_space *, loff_t , unsigned int, unsigned int, struct page **, void **); int (*write_end)(struct file *, struct address_space *, loff_t , unsigned int, unsigned int, struct page *, void *); sector_t (*bmap)(struct address_space *, sector_t ); void (*invalidatepage)(struct page *, unsigned int, unsigned int); int (*releasepage)(struct page *, gfp_t ); void (*freepage)(struct page *); ssize_t (*direct_IO)(struct kiocb *, struct iov_iter *, loff_t ); int (*migratepage)(struct address_space *, struct page *, struct page *, enum migrate_mode ); int (*launder_page)(struct page *); int (*is_partially_uptodate)(struct page *, unsigned long, unsigned long); void (*is_dirty_writeback)(struct page *, bool *, bool *); int (*error_remove_page)(struct address_space *, struct page *); int (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *); void (*swap_deactivate)(struct file *); } ;
424 struct address_space { struct inode *host; struct radix_tree_root page_tree; spinlock_t tree_lock; atomic_t i_mmap_writable; struct rb_root i_mmap; struct rw_semaphore i_mmap_rwsem; unsigned long nrpages; unsigned long nrexceptional; unsigned long writeback_index; const struct address_space_operations *a_ops; unsigned long flags; spinlock_t private_lock; struct list_head private_list; void *private_data; } ;
445 struct request_queue ;
446 struct hd_struct ;
446 struct gendisk ;
446 struct block_device { dev_t bd_dev; int bd_openers; struct inode *bd_inode; struct super_block *bd_super; struct mutex bd_mutex; struct list_head bd_inodes; void *bd_claiming; void *bd_holder; int bd_holders; bool bd_write_holder; struct list_head bd_holder_disks; struct block_device *bd_contains; unsigned int bd_block_size; struct hd_struct *bd_part; unsigned int bd_part_count; int bd_invalidated; struct gendisk *bd_disk; struct request_queue *bd_queue; struct list_head bd_list; unsigned long bd_private; int bd_fsfreeze_count; struct mutex bd_fsfreeze_mutex; int bd_map_count; } ;
565 struct posix_acl ;
566 struct inode_operations ;
566 union __anonunion____missing_field_name_339 { const unsigned int i_nlink; unsigned int __i_nlink; } ;
566 union __anonunion____missing_field_name_340 { struct hlist_head i_dentry; struct callback_head i_rcu; } ;
566 struct file_lock_context ;
566 struct cdev ;
566 union __anonunion____missing_field_name_341 { struct pipe_inode_info *i_pipe; struct block_device *i_bdev; struct cdev *i_cdev; char *i_link; } ;
566 struct inode { umode_t i_mode; unsigned short i_opflags; kuid_t i_uid; kgid_t i_gid; unsigned int i_flags; struct posix_acl *i_acl; struct posix_acl *i_default_acl; const struct inode_operations *i_op; struct super_block *i_sb; struct address_space *i_mapping; void *i_security; unsigned long i_ino; union __anonunion____missing_field_name_339 __annonCompField81; dev_t i_rdev; loff_t i_size; struct timespec i_atime; struct timespec i_mtime; struct timespec i_ctime; spinlock_t i_lock; unsigned short i_bytes; unsigned int i_blkbits; blkcnt_t i_blocks; unsigned long i_state; struct mutex i_mutex; unsigned long dirtied_when; unsigned long dirtied_time_when; struct hlist_node i_hash; struct list_head i_io_list; struct bdi_writeback *i_wb; int i_wb_frn_winner; u16 i_wb_frn_avg_time; u16 i_wb_frn_history; struct list_head i_lru; struct list_head i_sb_list; union __anonunion____missing_field_name_340 __annonCompField82; u64 i_version; atomic_t i_count; atomic_t i_dio_count; atomic_t i_writecount; atomic_t i_readcount; const struct file_operations *i_fop; struct file_lock_context *i_flctx; struct address_space i_data; struct list_head i_devices; union __anonunion____missing_field_name_341 __annonCompField83; __u32 i_generation; __u32 i_fsnotify_mask; struct hlist_head i_fsnotify_marks; void *i_private; } ;
837 struct fown_struct { rwlock_t lock; struct pid *pid; enum pid_type pid_type; kuid_t uid; kuid_t euid; int signum; } ;
845 struct file_ra_state { unsigned long start; unsigned int size; unsigned int async_size; unsigned int ra_pages; unsigned int mmap_miss; loff_t prev_pos; } ;
868 union __anonunion_f_u_342 { struct llist_node fu_llist; struct callback_head fu_rcuhead; } ;
868 struct file { union __anonunion_f_u_342 f_u; struct path f_path; struct inode *f_inode; const struct file_operations *f_op; spinlock_t f_lock; atomic_long_t f_count; unsigned int f_flags; fmode_t f_mode; struct mutex f_pos_lock; loff_t f_pos; struct fown_struct f_owner; const struct cred *f_cred; struct file_ra_state f_ra; u64 f_version; void *f_security; void *private_data; struct list_head f_ep_links; struct list_head f_tfile_llink; struct address_space *f_mapping; } ;
953 typedef void *fl_owner_t;
954 struct file_lock ;
955 struct file_lock_operations { void (*fl_copy_lock)(struct file_lock *, struct file_lock *); void (*fl_release_private)(struct file_lock *); } ;
961 struct lock_manager_operations { int (*lm_compare_owner)(struct file_lock *, struct file_lock *); unsigned long int (*lm_owner_key)(struct file_lock *); fl_owner_t (*lm_get_owner)(fl_owner_t ); void (*lm_put_owner)(fl_owner_t ); void (*lm_notify)(struct file_lock *); int (*lm_grant)(struct file_lock *, int); bool (*lm_break)(struct file_lock *); int (*lm_change)(struct file_lock *, int, struct list_head *); void (*lm_setup)(struct file_lock *, void **); } ;
982 struct net ;
988 struct nlm_lockowner ;
989 struct nfs_lock_info { u32 state; struct nlm_lockowner *owner; struct list_head list; } ;
14 struct nfs4_lock_state ;
15 struct nfs4_lock_info { struct nfs4_lock_state *owner; } ;
19 struct fasync_struct ;
19 struct __anonstruct_afs_344 { struct list_head link; int state; } ;
19 union __anonunion_fl_u_343 { struct nfs_lock_info nfs_fl; struct nfs4_lock_info nfs4_fl; struct __anonstruct_afs_344 afs; } ;
19 struct file_lock { struct file_lock *fl_next; struct list_head fl_list; struct hlist_node fl_link; struct list_head fl_block; fl_owner_t fl_owner; unsigned int fl_flags; unsigned char fl_type; unsigned int fl_pid; int fl_link_cpu; struct pid *fl_nspid; wait_queue_head_t fl_wait; struct file *fl_file; loff_t fl_start; loff_t fl_end; struct fasync_struct *fl_fasync; unsigned long fl_break_time; unsigned long fl_downgrade_time; const struct file_lock_operations *fl_ops; const struct lock_manager_operations *fl_lmops; union __anonunion_fl_u_343 fl_u; } ;
1041 struct file_lock_context { spinlock_t flc_lock; struct list_head flc_flock; struct list_head flc_posix; struct list_head flc_lease; } ;
1244 struct fasync_struct { spinlock_t fa_lock; int magic; int fa_fd; struct fasync_struct *fa_next; struct file *fa_file; struct callback_head fa_rcu; } ;
1279 struct sb_writers { int frozen; wait_queue_head_t wait_unfrozen; struct percpu_rw_semaphore rw_sem[3U]; } ;
1305 struct super_operations ;
1305 struct xattr_handler ;
1305 struct mtd_info ;
1305 struct super_block { struct list_head s_list; dev_t s_dev; unsigned char s_blocksize_bits; unsigned long s_blocksize; loff_t s_maxbytes; struct file_system_type *s_type; const struct super_operations *s_op; const struct dquot_operations *dq_op; const struct quotactl_ops *s_qcop; const struct export_operations *s_export_op; unsigned long s_flags; unsigned long s_iflags; unsigned long s_magic; struct dentry *s_root; struct rw_semaphore s_umount; int s_count; atomic_t s_active; void *s_security; const struct xattr_handler **s_xattr; struct hlist_bl_head s_anon; struct list_head s_mounts; struct block_device *s_bdev; struct backing_dev_info *s_bdi; struct mtd_info *s_mtd; struct hlist_node s_instances; unsigned int s_quota_types; struct quota_info s_dquot; struct sb_writers s_writers; char s_id[32U]; u8 s_uuid[16U]; void *s_fs_info; unsigned int s_max_links; fmode_t s_mode; u32 s_time_gran; struct mutex s_vfs_rename_mutex; char *s_subtype; char *s_options; const struct dentry_operations *s_d_op; int cleancache_poolid; struct shrinker s_shrink; atomic_long_t s_remove_count; int s_readonly_remount; struct workqueue_struct *s_dio_done_wq; struct hlist_head s_pins; struct list_lru s_dentry_lru; struct list_lru s_inode_lru; struct callback_head rcu; struct work_struct destroy_work; struct mutex s_sync_lock; int s_stack_depth; spinlock_t s_inode_list_lock; struct list_head s_inodes; } ;
1554 struct fiemap_extent_info { unsigned int fi_flags; unsigned int fi_extents_mapped; unsigned int fi_extents_max; struct fiemap_extent *fi_extents_start; } ;
1568 struct dir_context ;
1593 struct dir_context { int (*actor)(struct dir_context *, const char *, int, loff_t , u64 , unsigned int); loff_t pos; } ;
1600 struct file_operations { struct module *owner; loff_t (*llseek)(struct file *, loff_t , int); ssize_t (*read)(struct file *, char *, size_t , loff_t *); ssize_t (*write)(struct file *, const char *, size_t , loff_t *); ssize_t (*read_iter)(struct kiocb *, struct iov_iter *); ssize_t (*write_iter)(struct kiocb *, struct iov_iter *); int (*iterate)(struct file *, struct dir_context *); unsigned int (*poll)(struct file *, struct poll_table_struct *); long int (*unlocked_ioctl)(struct file *, unsigned int, unsigned long); long int (*compat_ioctl)(struct file *, unsigned int, unsigned long); int (*mmap)(struct file *, struct vm_area_struct *); int (*open)(struct inode *, struct file *); int (*flush)(struct file *, fl_owner_t ); int (*release)(struct inode *, struct file *); int (*fsync)(struct file *, loff_t , loff_t , int); int (*aio_fsync)(struct kiocb *, int); int (*fasync)(int, struct file *, int); int (*lock)(struct file *, int, struct file_lock *); ssize_t (*sendpage)(struct file *, struct page *, int, size_t , loff_t *, int); unsigned long int (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); int (*check_flags)(int); int (*flock)(struct file *, int, struct file_lock *); ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t , unsigned int); ssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t , unsigned int); int (*setlease)(struct file *, long, struct file_lock **, void **); long int (*fallocate)(struct file *, int, loff_t , loff_t ); void (*show_fdinfo)(struct seq_file *, struct file *); ssize_t (*copy_file_range)(struct file *, loff_t , struct file *, loff_t , size_t , unsigned int); int (*clone_file_range)(struct file *, loff_t , struct file *, loff_t , u64 ); ssize_t (*dedupe_file_range)(struct file *, u64 , u64 , struct file *, u64 ); } ;
1668 struct inode_operations { struct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int); const char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *); int (*permission)(struct inode *, int); struct posix_acl * (*get_acl)(struct inode *, int); int (*readlink)(struct dentry *, char *, int); int (*create)(struct inode *, struct dentry *, umode_t , bool ); int (*link)(struct dentry *, struct inode *, struct dentry *); int (*unlink)(struct inode *, struct dentry *); int (*symlink)(struct inode *, struct dentry *, const char *); int (*mkdir)(struct inode *, struct dentry *, umode_t ); int (*rmdir)(struct inode *, struct dentry *); int (*mknod)(struct inode *, struct dentry *, umode_t , dev_t ); int (*rename)(struct inode *, struct dentry *, struct inode *, struct dentry *); int (*rename2)(struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*setattr)(struct dentry *, struct iattr *); int (*getattr)(struct vfsmount *, struct dentry *, struct kstat *); int (*setxattr)(struct dentry *, const char *, const void *, size_t , int); ssize_t (*getxattr)(struct dentry *, const char *, void *, size_t ); ssize_t (*listxattr)(struct dentry *, char *, size_t ); int (*removexattr)(struct dentry *, const char *); int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 , u64 ); int (*update_time)(struct inode *, struct timespec *, int); int (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t , int *); int (*tmpfile)(struct inode *, struct dentry *, umode_t ); int (*set_acl)(struct inode *, struct posix_acl *, int); } ;
1723 struct super_operations { struct inode * (*alloc_inode)(struct super_block *); void (*destroy_inode)(struct inode *); void (*dirty_inode)(struct inode *, int); int (*write_inode)(struct inode *, struct writeback_control *); int (*drop_inode)(struct inode *); void (*evict_inode)(struct inode *); void (*put_super)(struct super_block *); int (*sync_fs)(struct super_block *, int); int (*freeze_super)(struct super_block *); int (*freeze_fs)(struct super_block *); int (*thaw_super)(struct super_block *); int (*unfreeze_fs)(struct super_block *); int (*statfs)(struct dentry *, struct kstatfs *); int (*remount_fs)(struct super_block *, int *, char *); void (*umount_begin)(struct super_block *); int (*show_options)(struct seq_file *, struct dentry *); int (*show_devname)(struct seq_file *, struct dentry *); int (*show_path)(struct seq_file *, struct dentry *); int (*show_stats)(struct seq_file *, struct dentry *); ssize_t (*quota_read)(struct super_block *, int, char *, size_t , loff_t ); ssize_t (*quota_write)(struct super_block *, int, const char *, size_t , loff_t ); struct dquot ** (*get_dquots)(struct inode *); int (*bdev_try_to_free_page)(struct super_block *, struct page *, gfp_t ); long int (*nr_cached_objects)(struct super_block *, struct shrink_control *); long int (*free_cached_objects)(struct super_block *, struct shrink_control *); } ;
1962 struct file_system_type { const char *name; int fs_flags; struct dentry * (*mount)(struct file_system_type *, int, const char *, void *); void (*kill_sb)(struct super_block *); struct module *owner; struct file_system_type *next; struct hlist_head fs_supers; struct lock_class_key s_lock_key; struct lock_class_key s_umount_key; struct lock_class_key s_vfs_rename_key; struct lock_class_key s_writers_key[3U]; struct lock_class_key i_lock_key; struct lock_class_key i_mutex_key; struct lock_class_key i_mutex_dir_key; } ;
6 typedef unsigned char cc_t;
7 typedef unsigned int speed_t;
8 typedef unsigned int tcflag_t;
30 struct ktermios { tcflag_t c_iflag; tcflag_t c_oflag; tcflag_t c_cflag; tcflag_t c_lflag; cc_t c_line; cc_t c_cc[19U]; speed_t c_ispeed; speed_t c_ospeed; } ;
41 struct winsize { unsigned short ws_row; unsigned short ws_col; unsigned short ws_xpixel; unsigned short ws_ypixel; } ;
93 struct termiox { __u16 x_hflag; __u16 x_cflag; __u16 x_rflag[5U]; __u16 x_sflag; } ;
16 struct cdev { struct kobject kobj; struct module *owner; const struct file_operations *ops; struct list_head list; dev_t dev; unsigned int count; } ;
32 struct tty_driver ;
33 struct serial_icounter_struct ;
34 struct tty_operations { struct tty_struct * (*lookup)(struct tty_driver *, struct inode *, int); int (*install)(struct tty_driver *, struct tty_struct *); void (*remove)(struct tty_driver *, struct tty_struct *); int (*open)(struct tty_struct *, struct file *); void (*close)(struct tty_struct *, struct file *); void (*shutdown)(struct tty_struct *); void (*cleanup)(struct tty_struct *); int (*write)(struct tty_struct *, const unsigned char *, int); int (*put_char)(struct tty_struct *, unsigned char); void (*flush_chars)(struct tty_struct *); int (*write_room)(struct tty_struct *); int (*chars_in_buffer)(struct tty_struct *); int (*ioctl)(struct tty_struct *, unsigned int, unsigned long); long int (*compat_ioctl)(struct tty_struct *, unsigned int, unsigned long); void (*set_termios)(struct tty_struct *, struct ktermios *); void (*throttle)(struct tty_struct *); void (*unthrottle)(struct tty_struct *); void (*stop)(struct tty_struct *); void (*start)(struct tty_struct *); void (*hangup)(struct tty_struct *); int (*break_ctl)(struct tty_struct *, int); void (*flush_buffer)(struct tty_struct *); void (*set_ldisc)(struct tty_struct *); void (*wait_until_sent)(struct tty_struct *, int); void (*send_xchar)(struct tty_struct *, char); int (*tiocmget)(struct tty_struct *); int (*tiocmset)(struct tty_struct *, unsigned int, unsigned int); int (*resize)(struct tty_struct *, struct winsize *); int (*set_termiox)(struct tty_struct *, struct termiox *); int (*get_icount)(struct tty_struct *, struct serial_icounter_struct *); int (*poll_init)(struct tty_driver *, int, char *); int (*poll_get_char)(struct tty_driver *, int); void (*poll_put_char)(struct tty_driver *, int, char); const struct file_operations *proc_fops; } ;
295 struct tty_port ;
295 struct tty_driver { int magic; struct kref kref; struct cdev **cdevs; struct module *owner; const char *driver_name; const char *name; int name_base; int major; int minor_start; unsigned int num; short type; short subtype; struct ktermios init_termios; unsigned long flags; struct proc_dir_entry *proc_entry; struct tty_driver *other; struct tty_struct **ttys; struct tty_port **ports; struct ktermios **termios; void *driver_state; const struct tty_operations *ops; struct list_head tty_drivers; } ;
362 struct ld_semaphore { long count; raw_spinlock_t wait_lock; unsigned int wait_readers; struct list_head read_wait; struct list_head write_wait; struct lockdep_map dep_map; } ;
170 struct tty_ldisc_ops { int magic; char *name; int num; int flags; int (*open)(struct tty_struct *); void (*close)(struct tty_struct *); void (*flush_buffer)(struct tty_struct *); ssize_t (*chars_in_buffer)(struct tty_struct *); ssize_t (*read)(struct tty_struct *, struct file *, unsigned char *, size_t ); ssize_t (*write)(struct tty_struct *, struct file *, const unsigned char *, size_t ); int (*ioctl)(struct tty_struct *, struct file *, unsigned int, unsigned long); long int (*compat_ioctl)(struct tty_struct *, struct file *, unsigned int, unsigned long); void (*set_termios)(struct tty_struct *, struct ktermios *); unsigned int (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *); int (*hangup)(struct tty_struct *); void (*receive_buf)(struct tty_struct *, const unsigned char *, char *, int); void (*write_wakeup)(struct tty_struct *); void (*dcd_change)(struct tty_struct *, unsigned int); void (*fasync)(struct tty_struct *, int); int (*receive_buf2)(struct tty_struct *, const unsigned char *, char *, int); struct module *owner; int refcount; } ;
220 struct tty_ldisc { struct tty_ldisc_ops *ops; struct tty_struct *tty; } ;
230 union __anonunion____missing_field_name_345 { struct tty_buffer *next; struct llist_node free; } ;
230 struct tty_buffer { union __anonunion____missing_field_name_345 __annonCompField84; int used; int size; int commit; int read; int flags; unsigned long data[0U]; } ;
82 struct tty_bufhead { struct tty_buffer *head; struct work_struct work; struct mutex lock; atomic_t priority; struct tty_buffer sentinel; struct llist_head free; atomic_t mem_used; int mem_limit; struct tty_buffer *tail; } ;
94 struct tty_port_operations { int (*carrier_raised)(struct tty_port *); void (*dtr_rts)(struct tty_port *, int); void (*shutdown)(struct tty_port *); int (*activate)(struct tty_port *, struct tty_struct *); void (*destruct)(struct tty_port *); } ;
220 struct tty_port { struct tty_bufhead buf; struct tty_struct *tty; struct tty_struct *itty; const struct tty_port_operations *ops; spinlock_t lock; int blocked_open; int count; wait_queue_head_t open_wait; wait_queue_head_t delta_msr_wait; unsigned long flags; unsigned char console; unsigned char low_latency; struct mutex mutex; struct mutex buf_mutex; unsigned char *xmit_buf; unsigned int close_delay; unsigned int closing_wait; int drain_delay; struct kref kref; } ;
244 struct tty_struct { int magic; struct kref kref; struct device *dev; struct tty_driver *driver; const struct tty_operations *ops; int index; struct ld_semaphore ldisc_sem; struct tty_ldisc *ldisc; struct mutex atomic_write_lock; struct mutex legacy_mutex; struct mutex throttle_mutex; struct rw_semaphore termios_rwsem; struct mutex winsize_mutex; spinlock_t ctrl_lock; spinlock_t flow_lock; struct ktermios termios; struct ktermios termios_locked; struct termiox *termiox; char name[64U]; struct pid *pgrp; struct pid *session; unsigned long flags; int count; struct winsize winsize; unsigned char stopped; unsigned char flow_stopped; unsigned long unused; int hw_stopped; unsigned char ctrl_status; unsigned char packet; unsigned long unused_ctrl; unsigned int receive_room; int flow_change; struct tty_struct *link; struct fasync_struct *fasync; int alt_speed; wait_queue_head_t write_wait; wait_queue_head_t read_wait; struct work_struct hangup_work; void *disc_data; void *driver_data; struct list_head tty_files; int closing; unsigned char *write_buf; int write_cnt; struct work_struct SAK_work; struct tty_port *port; } ;
96 struct serial_icounter_struct { int cts; int dsr; int rng; int dcd; int rx; int tx; int frame; int overrun; int parity; int brk; int buf_overrun; int reserved[9U]; } ;
25 struct mnt_namespace ;
26 struct ipc_namespace ;
27 struct nsproxy { atomic_t count; struct uts_namespace *uts_ns; struct ipc_namespace *ipc_ns; struct mnt_namespace *mnt_ns; struct pid_namespace *pid_ns_for_children; struct net *net_ns; } ;
84 struct proc_ns_operations ;
85 struct ns_common { atomic_long_t stashed; const struct proc_ns_operations *ops; unsigned int inum; } ;
11 struct pidmap { atomic_t nr_free; void *page; } ;
17 struct fs_pin ;
18 struct pid_namespace { struct kref kref; struct pidmap pidmap[128U]; struct callback_head rcu; int last_pid; unsigned int nr_hashed; struct task_struct *child_reaper; struct kmem_cache *pid_cachep; unsigned int level; struct pid_namespace *parent; struct vfsmount *proc_mnt; struct dentry *proc_self; struct dentry *proc_thread_self; struct fs_pin *bacct; struct user_namespace *user_ns; struct work_struct proc_work; kgid_t pid_gid; int hide_pid; int reboot; struct ns_common ns; } ;
56 struct iovec { void *iov_base; __kernel_size_t iov_len; } ;
21 struct kvec { void *iov_base; size_t iov_len; } ;
27 union __anonunion____missing_field_name_350 { const struct iovec *iov; const struct kvec *kvec; const struct bio_vec *bvec; } ;
27 struct iov_iter { int type; size_t iov_offset; size_t count; union __anonunion____missing_field_name_350 __annonCompField85; unsigned long nr_segs; } ;
1380 struct dql { unsigned int num_queued; unsigned int adj_limit; unsigned int last_obj_cnt; unsigned int limit; unsigned int num_completed; unsigned int prev_ovlimit; unsigned int prev_num_queued; unsigned int prev_last_obj_cnt; unsigned int lowest_slack; unsigned long slack_start_time; unsigned int max_limit; unsigned int min_limit; unsigned int slack_hold_time; } ;
11 typedef unsigned short __kernel_sa_family_t;
23 typedef __kernel_sa_family_t sa_family_t;
24 struct sockaddr { sa_family_t sa_family; char sa_data[14U]; } ;
43 struct __anonstruct_sync_serial_settings_352 { unsigned int clock_rate; unsigned int clock_type; unsigned short loopback; } ;
43 typedef struct __anonstruct_sync_serial_settings_352 sync_serial_settings;
50 struct __anonstruct_te1_settings_353 { unsigned int clock_rate; unsigned int clock_type; unsigned short loopback; unsigned int slot_map; } ;
50 typedef struct __anonstruct_te1_settings_353 te1_settings;
55 struct __anonstruct_raw_hdlc_proto_354 { unsigned short encoding; unsigned short parity; } ;
55 typedef struct __anonstruct_raw_hdlc_proto_354 raw_hdlc_proto;
65 struct __anonstruct_fr_proto_355 { unsigned int t391; unsigned int t392; unsigned int n391; unsigned int n392; unsigned int n393; unsigned short lmi; unsigned short dce; } ;
65 typedef struct __anonstruct_fr_proto_355 fr_proto;
69 struct __anonstruct_fr_proto_pvc_356 { unsigned int dlci; } ;
69 typedef struct __anonstruct_fr_proto_pvc_356 fr_proto_pvc;
74 struct __anonstruct_fr_proto_pvc_info_357 { unsigned int dlci; char master[16U]; } ;
74 typedef struct __anonstruct_fr_proto_pvc_info_357 fr_proto_pvc_info;
79 struct __anonstruct_cisco_proto_358 { unsigned int interval; unsigned int timeout; } ;
79 typedef struct __anonstruct_cisco_proto_358 cisco_proto;
117 struct ifmap { unsigned long mem_start; unsigned long mem_end; unsigned short base_addr; unsigned char irq; unsigned char dma; unsigned char port; } ;
177 union __anonunion_ifs_ifsu_359 { raw_hdlc_proto *raw_hdlc; cisco_proto *cisco; fr_proto *fr; fr_proto_pvc *fr_pvc; fr_proto_pvc_info *fr_pvc_info; sync_serial_settings *sync; te1_settings *te1; } ;
177 struct if_settings { unsigned int type; unsigned int size; union __anonunion_ifs_ifsu_359 ifs_ifsu; } ;
195 union __anonunion_ifr_ifrn_360 { char ifrn_name[16U]; } ;
195 union __anonunion_ifr_ifru_361 { struct sockaddr ifru_addr; struct sockaddr ifru_dstaddr; struct sockaddr ifru_broadaddr; struct sockaddr ifru_netmask; struct sockaddr ifru_hwaddr; short ifru_flags; int ifru_ivalue; int ifru_mtu; struct ifmap ifru_map; char ifru_slave[16U]; char ifru_newname[16U]; void *ifru_data; struct if_settings ifru_settings; } ;
195 struct ifreq { union __anonunion_ifr_ifrn_360 ifr_ifrn; union __anonunion_ifr_ifru_361 ifr_ifru; } ;
18 typedef s32 compat_time_t;
39 typedef s32 compat_long_t;
44 typedef u32 compat_uptr_t;
45 struct compat_timespec { compat_time_t tv_sec; s32 tv_nsec; } ;
276 struct compat_robust_list { compat_uptr_t next; } ;
280 struct compat_robust_list_head { struct compat_robust_list list; compat_long_t futex_offset; compat_uptr_t list_op_pending; } ;
161 struct in6_addr ;
140 struct sk_buff ;
15 typedef u64 netdev_features_t;
66 union __anonunion_in6_u_377 { __u8 u6_addr8[16U]; __be16 u6_addr16[8U]; __be32 u6_addr32[4U]; } ;
66 struct in6_addr { union __anonunion_in6_u_377 in6_u; } ;
46 struct ethhdr { unsigned char h_dest[6U]; unsigned char h_source[6U]; __be16 h_proto; } ;
186 struct pipe_buf_operations ;
186 struct pipe_buffer { struct page *page; unsigned int offset; unsigned int len; const struct pipe_buf_operations *ops; unsigned int flags; unsigned long private; } ;
27 struct pipe_inode_info { struct mutex mutex; wait_queue_head_t wait; unsigned int nrbufs; unsigned int curbuf; unsigned int buffers; unsigned int readers; unsigned int writers; unsigned int files; unsigned int waiting_writers; unsigned int r_counter; unsigned int w_counter; struct page *tmp_page; struct fasync_struct *fasync_readers; struct fasync_struct *fasync_writers; struct pipe_buffer *bufs; struct user_struct *user; } ;
63 struct pipe_buf_operations { int can_merge; int (*confirm)(struct pipe_inode_info *, struct pipe_buffer *); void (*release)(struct pipe_inode_info *, struct pipe_buffer *); int (*steal)(struct pipe_inode_info *, struct pipe_buffer *); void (*get)(struct pipe_inode_info *, struct pipe_buffer *); } ;
265 struct napi_struct ;
266 struct nf_conntrack { atomic_t use; } ;
253 union __anonunion____missing_field_name_387 { __be32 ipv4_daddr; struct in6_addr ipv6_daddr; char neigh_header[8U]; } ;
253 struct nf_bridge_info { atomic_t use; unsigned char orig_proto; unsigned char pkt_otherhost; unsigned char in_prerouting; unsigned char bridged_dnat; __u16 frag_max_size; struct net_device *physindev; struct net_device *physoutdev; union __anonunion____missing_field_name_387 __annonCompField89; } ;
277 struct sk_buff_head { struct sk_buff *next; struct sk_buff *prev; __u32 qlen; spinlock_t lock; } ;
491 typedef unsigned int sk_buff_data_t;
492 struct __anonstruct____missing_field_name_390 { u32 stamp_us; u32 stamp_jiffies; } ;
492 union __anonunion____missing_field_name_389 { u64 v64; struct __anonstruct____missing_field_name_390 __annonCompField90; } ;
492 struct skb_mstamp { union __anonunion____missing_field_name_389 __annonCompField91; } ;
555 union __anonunion____missing_field_name_393 { ktime_t tstamp; struct skb_mstamp skb_mstamp; } ;
555 struct __anonstruct____missing_field_name_392 { struct sk_buff *next; struct sk_buff *prev; union __anonunion____missing_field_name_393 __annonCompField92; } ;
555 union __anonunion____missing_field_name_391 { struct __anonstruct____missing_field_name_392 __annonCompField93; struct rb_node rbnode; } ;
555 struct sec_path ;
555 struct __anonstruct____missing_field_name_395 { __u16 csum_start; __u16 csum_offset; } ;
555 union __anonunion____missing_field_name_394 { __wsum csum; struct __anonstruct____missing_field_name_395 __annonCompField95; } ;
555 union __anonunion____missing_field_name_396 { unsigned int napi_id; unsigned int sender_cpu; } ;
555 union __anonunion____missing_field_name_397 { __u32 secmark; __u32 offload_fwd_mark; } ;
555 union __anonunion____missing_field_name_398 { __u32 mark; __u32 reserved_tailroom; } ;
555 union __anonunion____missing_field_name_399 { __be16 inner_protocol; __u8 inner_ipproto; } ;
555 struct sk_buff { union __anonunion____missing_field_name_391 __annonCompField94; struct sock *sk; struct net_device *dev; char cb[48U]; unsigned long _skb_refdst; void (*destructor)(struct sk_buff *); struct sec_path *sp; struct nf_conntrack *nfct; struct nf_bridge_info *nf_bridge; unsigned int len; unsigned int data_len; __u16 mac_len; __u16 hdr_len; __u16 queue_mapping; unsigned char cloned; unsigned char nohdr; unsigned char fclone; unsigned char peeked; unsigned char head_frag; unsigned char xmit_more; __u32 headers_start[0U]; __u8 __pkt_type_offset[0U]; unsigned char pkt_type; unsigned char pfmemalloc; unsigned char ignore_df; unsigned char nfctinfo; unsigned char nf_trace; unsigned char ip_summed; unsigned char ooo_okay; unsigned char l4_hash; unsigned char sw_hash; unsigned char wifi_acked_valid; unsigned char wifi_acked; unsigned char no_fcs; unsigned char encapsulation; unsigned char encap_hdr_csum; unsigned char csum_valid; unsigned char csum_complete_sw; unsigned char csum_level; unsigned char csum_bad; unsigned char ndisc_nodetype; unsigned char ipvs_property; unsigned char inner_protocol_type; unsigned char remcsum_offload; __u16 tc_index; __u16 tc_verd; union __anonunion____missing_field_name_394 __annonCompField96; __u32 priority; int skb_iif; __u32 hash; __be16 vlan_proto; __u16 vlan_tci; union __anonunion____missing_field_name_396 __annonCompField97; union __anonunion____missing_field_name_397 __annonCompField98; union __anonunion____missing_field_name_398 __annonCompField99; union __anonunion____missing_field_name_399 __annonCompField100; __u16 inner_transport_header; __u16 inner_network_header; __u16 inner_mac_header; __be16 protocol; __u16 transport_header; __u16 network_header; __u16 mac_header; __u32 headers_end[0U]; sk_buff_data_t tail; sk_buff_data_t end; unsigned char *head; unsigned char *data; unsigned int truesize; atomic_t users; } ;
822 struct dst_entry ;
34 struct ethtool_cmd { __u32 cmd; __u32 supported; __u32 advertising; __u16 speed; __u8 duplex; __u8 port; __u8 phy_address; __u8 transceiver; __u8 autoneg; __u8 mdio_support; __u32 maxtxpkt; __u32 maxrxpkt; __u16 speed_hi; __u8 eth_tp_mdix; __u8 eth_tp_mdix_ctrl; __u32 lp_advertising; __u32 reserved[2U]; } ;
125 struct ethtool_drvinfo { __u32 cmd; char driver[32U]; char version[32U]; char fw_version[32U]; char bus_info[32U]; char erom_version[32U]; char reserved2[12U]; __u32 n_priv_flags; __u32 n_stats; __u32 testinfo_len; __u32 eedump_len; __u32 regdump_len; } ;
189 struct ethtool_wolinfo { __u32 cmd; __u32 supported; __u32 wolopts; __u8 sopass[6U]; } ;
233 struct ethtool_tunable { __u32 cmd; __u32 id; __u32 type_id; __u32 len; void *data[0U]; } ;
245 struct ethtool_regs { __u32 cmd; __u32 version; __u32 len; __u8 data[0U]; } ;
267 struct ethtool_eeprom { __u32 cmd; __u32 magic; __u32 offset; __u32 len; __u8 data[0U]; } ;
293 struct ethtool_eee { __u32 cmd; __u32 supported; __u32 advertised; __u32 lp_advertised; __u32 eee_active; __u32 eee_enabled; __u32 tx_lpi_enabled; __u32 tx_lpi_timer; __u32 reserved[2U]; } ;
322 struct ethtool_modinfo { __u32 cmd; __u32 type; __u32 eeprom_len; __u32 reserved[8U]; } ;
339 struct ethtool_coalesce { __u32 cmd; __u32 rx_coalesce_usecs; __u32 rx_max_coalesced_frames; __u32 rx_coalesce_usecs_irq; __u32 rx_max_coalesced_frames_irq; __u32 tx_coalesce_usecs; __u32 tx_max_coalesced_frames; __u32 tx_coalesce_usecs_irq; __u32 tx_max_coalesced_frames_irq; __u32 stats_block_coalesce_usecs; __u32 use_adaptive_rx_coalesce; __u32 use_adaptive_tx_coalesce; __u32 pkt_rate_low; __u32 rx_coalesce_usecs_low; __u32 rx_max_coalesced_frames_low; __u32 tx_coalesce_usecs_low; __u32 tx_max_coalesced_frames_low; __u32 pkt_rate_high; __u32 rx_coalesce_usecs_high; __u32 rx_max_coalesced_frames_high; __u32 tx_coalesce_usecs_high; __u32 tx_max_coalesced_frames_high; __u32 rate_sample_interval; } ;
438 struct ethtool_ringparam { __u32 cmd; __u32 rx_max_pending; __u32 rx_mini_max_pending; __u32 rx_jumbo_max_pending; __u32 tx_max_pending; __u32 rx_pending; __u32 rx_mini_pending; __u32 rx_jumbo_pending; __u32 tx_pending; } ;
475 struct ethtool_channels { __u32 cmd; __u32 max_rx; __u32 max_tx; __u32 max_other; __u32 max_combined; __u32 rx_count; __u32 tx_count; __u32 other_count; __u32 combined_count; } ;
503 struct ethtool_pauseparam { __u32 cmd; __u32 autoneg; __u32 rx_pause; __u32 tx_pause; } ;
607 struct ethtool_test { __u32 cmd; __u32 flags; __u32 reserved; __u32 len; __u64 data[0U]; } ;
639 struct ethtool_stats { __u32 cmd; __u32 n_stats; __u64 data[0U]; } ;
681 struct ethtool_tcpip4_spec { __be32 ip4src; __be32 ip4dst; __be16 psrc; __be16 pdst; __u8 tos; } ;
714 struct ethtool_ah_espip4_spec { __be32 ip4src; __be32 ip4dst; __be32 spi; __u8 tos; } ;
730 struct ethtool_usrip4_spec { __be32 ip4src; __be32 ip4dst; __be32 l4_4_bytes; __u8 tos; __u8 ip_ver; __u8 proto; } ;
750 union ethtool_flow_union { struct ethtool_tcpip4_spec tcp_ip4_spec; struct ethtool_tcpip4_spec udp_ip4_spec; struct ethtool_tcpip4_spec sctp_ip4_spec; struct ethtool_ah_espip4_spec ah_ip4_spec; struct ethtool_ah_espip4_spec esp_ip4_spec; struct ethtool_usrip4_spec usr_ip4_spec; struct ethhdr ether_spec; __u8 hdata[52U]; } ;
761 struct ethtool_flow_ext { __u8 padding[2U]; unsigned char h_dest[6U]; __be16 vlan_etype; __be16 vlan_tci; __be32 data[2U]; } ;
780 struct ethtool_rx_flow_spec { __u32 flow_type; union ethtool_flow_union h_u; struct ethtool_flow_ext h_ext; union ethtool_flow_union m_u; struct ethtool_flow_ext m_ext; __u64 ring_cookie; __u32 location; } ;
830 struct ethtool_rxnfc { __u32 cmd; __u32 flow_type; __u64 data; struct ethtool_rx_flow_spec fs; __u32 rule_cnt; __u32 rule_locs[0U]; } ;
1001 struct ethtool_flash { __u32 cmd; __u32 region; char data[128U]; } ;
1009 struct ethtool_dump { __u32 cmd; __u32 version; __u32 flag; __u32 len; __u8 data[0U]; } ;
1085 struct ethtool_ts_info { __u32 cmd; __u32 so_timestamping; __s32 phc_index; __u32 tx_types; __u32 tx_reserved[3U]; __u32 rx_filters; __u32 rx_reserved[3U]; } ;
44 enum ethtool_phys_id_state { ETHTOOL_ID_INACTIVE = 0, ETHTOOL_ID_ACTIVE = 1, ETHTOOL_ID_ON = 2, ETHTOOL_ID_OFF = 3 } ;
99 struct ethtool_ops { int (*get_settings)(struct net_device *, struct ethtool_cmd *); int (*set_settings)(struct net_device *, struct ethtool_cmd *); void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *); int (*get_regs_len)(struct net_device *); void (*get_regs)(struct net_device *, struct ethtool_regs *, void *); void (*get_wol)(struct net_device *, struct ethtool_wolinfo *); int (*set_wol)(struct net_device *, struct ethtool_wolinfo *); u32 (*get_msglevel)(struct net_device *); void (*set_msglevel)(struct net_device *, u32 ); int (*nway_reset)(struct net_device *); u32 (*get_link)(struct net_device *); int (*get_eeprom_len)(struct net_device *); int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *); int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *); void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *); int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *); void (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *); int (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *); void (*self_test)(struct net_device *, struct ethtool_test *, u64 *); void (*get_strings)(struct net_device *, u32 , u8 *); int (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state ); void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *); int (*begin)(struct net_device *); void (*complete)(struct net_device *); u32 (*get_priv_flags)(struct net_device *); int (*set_priv_flags)(struct net_device *, u32 ); int (*get_sset_count)(struct net_device *, int); int (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *); int (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *); int (*flash_device)(struct net_device *, struct ethtool_flash *); int (*reset)(struct net_device *, u32 *); u32 (*get_rxfh_key_size)(struct net_device *); u32 (*get_rxfh_indir_size)(struct net_device *); int (*get_rxfh)(struct net_device *, u32 *, u8 *, u8 *); int (*set_rxfh)(struct net_device *, const u32 *, const u8 *, const u8 ); void (*get_channels)(struct net_device *, struct ethtool_channels *); int (*set_channels)(struct net_device *, struct ethtool_channels *); int (*get_dump_flag)(struct net_device *, struct ethtool_dump *); int (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *); int (*set_dump)(struct net_device *, struct ethtool_dump *); int (*get_ts_info)(struct net_device *, struct ethtool_ts_info *); int (*get_module_info)(struct net_device *, struct ethtool_modinfo *); int (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); int (*get_eee)(struct net_device *, struct ethtool_eee *); int (*set_eee)(struct net_device *, struct ethtool_eee *); int (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *); int (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *); } ;
282 struct prot_inuse ;
283 struct netns_core { struct ctl_table_header *sysctl_hdr; int sysctl_somaxconn; struct prot_inuse *inuse; } ;
38 struct u64_stats_sync { } ;
146 struct ipstats_mib { u64 mibs[36U]; struct u64_stats_sync syncp; } ;
61 struct icmp_mib { unsigned long mibs[28U]; } ;
67 struct icmpmsg_mib { atomic_long_t mibs[512U]; } ;
72 struct icmpv6_mib { unsigned long mibs[6U]; } ;
83 struct icmpv6msg_mib { atomic_long_t mibs[512U]; } ;
93 struct tcp_mib { unsigned long mibs[16U]; } ;
100 struct udp_mib { unsigned long mibs[9U]; } ;
106 struct linux_mib { unsigned long mibs[117U]; } ;
112 struct linux_xfrm_mib { unsigned long mibs[29U]; } ;
118 struct netns_mib { struct tcp_mib *tcp_statistics; struct ipstats_mib *ip_statistics; struct linux_mib *net_statistics; struct udp_mib *udp_statistics; struct udp_mib *udplite_statistics; struct icmp_mib *icmp_statistics; struct icmpmsg_mib *icmpmsg_statistics; struct proc_dir_entry *proc_net_devsnmp6; struct udp_mib *udp_stats_in6; struct udp_mib *udplite_stats_in6; struct ipstats_mib *ipv6_statistics; struct icmpv6_mib *icmpv6_statistics; struct icmpv6msg_mib *icmpv6msg_statistics; struct linux_xfrm_mib *xfrm_statistics; } ;
26 struct netns_unix { int sysctl_max_dgram_qlen; struct ctl_table_header *ctl; } ;
12 struct netns_packet { struct mutex sklist_lock; struct hlist_head sklist; } ;
14 struct netns_frags { struct percpu_counter mem; int timeout; int high_thresh; int low_thresh; } ;
186 struct ipv4_devconf ;
187 struct fib_rules_ops ;
188 struct fib_table ;
189 struct local_ports { seqlock_t lock; int range[2U]; bool warned; } ;
24 struct ping_group_range { seqlock_t lock; kgid_t range[2U]; } ;
29 struct inet_peer_base ;
29 struct xt_table ;
29 struct netns_ipv4 { struct ctl_table_header *forw_hdr; struct ctl_table_header *frags_hdr; struct ctl_table_header *ipv4_hdr; struct ctl_table_header *route_hdr; struct ctl_table_header *xfrm4_hdr; struct ipv4_devconf *devconf_all; struct ipv4_devconf *devconf_dflt; struct fib_rules_ops *rules_ops; bool fib_has_custom_rules; struct fib_table *fib_local; struct fib_table *fib_main; struct fib_table *fib_default; int fib_num_tclassid_users; struct hlist_head *fib_table_hash; bool fib_offload_disabled; struct sock *fibnl; struct sock **icmp_sk; struct sock *mc_autojoin_sk; struct inet_peer_base *peers; struct sock **tcp_sk; struct netns_frags frags; struct xt_table *iptable_filter; struct xt_table *iptable_mangle; struct xt_table *iptable_raw; struct xt_table *arptable_filter; struct xt_table *iptable_security; struct xt_table *nat_table; int sysctl_icmp_echo_ignore_all; int sysctl_icmp_echo_ignore_broadcasts; int sysctl_icmp_ignore_bogus_error_responses; int sysctl_icmp_ratelimit; int sysctl_icmp_ratemask; int sysctl_icmp_errors_use_inbound_ifaddr; struct local_ports ip_local_ports; int sysctl_tcp_ecn; int sysctl_tcp_ecn_fallback; int sysctl_ip_no_pmtu_disc; int sysctl_ip_fwd_use_pmtu; int sysctl_ip_nonlocal_bind; int sysctl_fwmark_reflect; int sysctl_tcp_fwmark_accept; int sysctl_tcp_l3mdev_accept; int sysctl_tcp_mtu_probing; int sysctl_tcp_base_mss; int sysctl_tcp_probe_threshold; u32 sysctl_tcp_probe_interval; int sysctl_tcp_keepalive_time; int sysctl_tcp_keepalive_probes; int sysctl_tcp_keepalive_intvl; struct ping_group_range ping_group_range; atomic_t dev_addr_genid; unsigned long *sysctl_local_reserved_ports; struct list_head mr_tables; struct fib_rules_ops *mr_rules_ops; atomic_t rt_genid; } ;
120 struct neighbour ;
120 struct dst_ops { unsigned short family; unsigned int gc_thresh; int (*gc)(struct dst_ops *); struct dst_entry * (*check)(struct dst_entry *, __u32 ); unsigned int (*default_advmss)(const struct dst_entry *); unsigned int (*mtu)(const struct dst_entry *); u32 * (*cow_metrics)(struct dst_entry *, unsigned long); void (*destroy)(struct dst_entry *); void (*ifdown)(struct dst_entry *, struct net_device *, int); struct dst_entry * (*negative_advice)(struct dst_entry *); void (*link_failure)(struct sk_buff *); void (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32 ); void (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *); int (*local_out)(struct net *, struct sock *, struct sk_buff *); struct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *); struct kmem_cache *kmem_cachep; struct percpu_counter pcpuc_entries; } ;
73 struct netns_sysctl_ipv6 { struct ctl_table_header *hdr; struct ctl_table_header *route_hdr; struct ctl_table_header *icmp_hdr; struct ctl_table_header *frags_hdr; struct ctl_table_header *xfrm6_hdr; int bindv6only; int flush_delay; int ip6_rt_max_size; int ip6_rt_gc_min_interval; int ip6_rt_gc_timeout; int ip6_rt_gc_interval; int ip6_rt_gc_elasticity; int ip6_rt_mtu_expires; int ip6_rt_min_advmss; int flowlabel_consistency; int auto_flowlabels; int icmpv6_time; int anycast_src_echo_reply; int ip_nonlocal_bind; int fwmark_reflect; int idgen_retries; int idgen_delay; int flowlabel_state_ranges; } ;
40 struct ipv6_devconf ;
40 struct rt6_info ;
40 struct rt6_statistics ;
40 struct fib6_table ;
40 struct netns_ipv6 { struct netns_sysctl_ipv6 sysctl; struct ipv6_devconf *devconf_all; struct ipv6_devconf *devconf_dflt; struct inet_peer_base *peers; struct netns_frags frags; struct xt_table *ip6table_filter; struct xt_table *ip6table_mangle; struct xt_table *ip6table_raw; struct xt_table *ip6table_security; struct xt_table *ip6table_nat; struct rt6_info *ip6_null_entry; struct rt6_statistics *rt6_stats; struct timer_list ip6_fib_timer; struct hlist_head *fib_table_hash; struct fib6_table *fib6_main_tbl; struct dst_ops ip6_dst_ops; unsigned int ip6_rt_gc_expire; unsigned long ip6_rt_last_gc; struct rt6_info *ip6_prohibit_entry; struct rt6_info *ip6_blk_hole_entry; struct fib6_table *fib6_local_tbl; struct fib_rules_ops *fib6_rules_ops; struct sock **icmp_sk; struct sock *ndisc_sk; struct sock *tcp_sk; struct sock *igmp_sk; struct sock *mc_autojoin_sk; struct list_head mr6_tables; struct fib_rules_ops *mr6_rules_ops; atomic_t dev_addr_genid; atomic_t fib6_sernum; } ;
86 struct netns_nf_frag { struct netns_sysctl_ipv6 sysctl; struct netns_frags frags; } ;
92 struct netns_sysctl_lowpan { struct ctl_table_header *frags_hdr; } ;
14 struct netns_ieee802154_lowpan { struct netns_sysctl_lowpan sysctl; struct netns_frags frags; } ;
20 struct sctp_mib ;
21 struct netns_sctp { struct sctp_mib *sctp_statistics; struct proc_dir_entry *proc_net_sctp; struct ctl_table_header *sysctl_header; struct sock *ctl_sock; struct list_head local_addr_list; struct list_head addr_waitq; struct timer_list addr_wq_timer; struct list_head auto_asconf_splist; spinlock_t addr_wq_lock; spinlock_t local_addr_lock; unsigned int rto_initial; unsigned int rto_min; unsigned int rto_max; int rto_alpha; int rto_beta; int max_burst; int cookie_preserve_enable; char *sctp_hmac_alg; unsigned int valid_cookie_life; unsigned int sack_timeout; unsigned int hb_interval; int max_retrans_association; int max_retrans_path; int max_retrans_init; int pf_retrans; int pf_enable; int sndbuf_policy; int rcvbuf_policy; int default_auto_asconf; int addip_enable; int addip_noauth; int prsctp_enable; int auth_enable; int scope_policy; int rwnd_upd_shift; unsigned long max_autoclose; } ;
141 struct netns_dccp { struct sock *v4_ctl_sk; struct sock *v6_ctl_sk; } ;
79 struct nf_logger ;
80 struct netns_nf { struct proc_dir_entry *proc_netfilter; const struct nf_logger *nf_loggers[13U]; struct ctl_table_header *nf_log_dir_header; struct list_head hooks[13U][8U]; } ;
19 struct ebt_table ;
20 struct netns_xt { struct list_head tables[13U]; bool notrack_deprecated_warning; bool clusterip_deprecated_warning; struct ebt_table *broute_table; struct ebt_table *frame_filter; struct ebt_table *frame_nat; } ;
19 struct hlist_nulls_node ;
19 struct hlist_nulls_head { struct hlist_nulls_node *first; } ;
23 struct hlist_nulls_node { struct hlist_nulls_node *next; struct hlist_nulls_node **pprev; } ;
32 struct nf_proto_net { struct ctl_table_header *ctl_table_header; struct ctl_table *ctl_table; struct ctl_table_header *ctl_compat_header; struct ctl_table *ctl_compat_table; unsigned int users; } ;
25 struct nf_generic_net { struct nf_proto_net pn; unsigned int timeout; } ;
30 struct nf_tcp_net { struct nf_proto_net pn; unsigned int timeouts[14U]; unsigned int tcp_loose; unsigned int tcp_be_liberal; unsigned int tcp_max_retrans; } ;
44 struct nf_udp_net { struct nf_proto_net pn; unsigned int timeouts[2U]; } ;
49 struct nf_icmp_net { struct nf_proto_net pn; unsigned int timeout; } ;
54 struct nf_ip_net { struct nf_generic_net generic; struct nf_tcp_net tcp; struct nf_udp_net udp; struct nf_icmp_net icmp; struct nf_icmp_net icmpv6; struct ctl_table_header *ctl_table_header; struct ctl_table *ctl_table; } ;
65 struct ct_pcpu { spinlock_t lock; struct hlist_nulls_head unconfirmed; struct hlist_nulls_head dying; } ;
72 struct ip_conntrack_stat ;
72 struct nf_ct_event_notifier ;
72 struct nf_exp_event_notifier ;
72 struct netns_ct { atomic_t count; unsigned int expect_count; struct delayed_work ecache_dwork; bool ecache_dwork_pending; struct ctl_table_header *sysctl_header; struct ctl_table_header *acct_sysctl_header; struct ctl_table_header *tstamp_sysctl_header; struct ctl_table_header *event_sysctl_header; struct ctl_table_header *helper_sysctl_header; char *slabname; unsigned int sysctl_log_invalid; int sysctl_events; int sysctl_acct; int sysctl_auto_assign_helper; bool auto_assign_helper_warned; int sysctl_tstamp; int sysctl_checksum; unsigned int htable_size; seqcount_t generation; struct kmem_cache *nf_conntrack_cachep; struct hlist_nulls_head *hash; struct hlist_head *expect_hash; struct ct_pcpu *pcpu_lists; struct ip_conntrack_stat *stat; struct nf_ct_event_notifier *nf_conntrack_event_cb; struct nf_exp_event_notifier *nf_expect_event_cb; struct nf_ip_net nf_ct_proto; unsigned int labels_used; u8 label_words; struct hlist_head *nat_bysource; unsigned int nat_htable_size; } ;
114 struct nft_af_info ;
115 struct netns_nftables { struct list_head af_info; struct list_head commit_list; struct nft_af_info *ipv4; struct nft_af_info *ipv6; struct nft_af_info *inet; struct nft_af_info *arp; struct nft_af_info *bridge; struct nft_af_info *netdev; unsigned int base_seq; u8 gencursor; } ;
508 struct flow_cache_percpu { struct hlist_head *hash_table; int hash_count; u32 hash_rnd; int hash_rnd_recalc; struct tasklet_struct flush_tasklet; } ;
16 struct flow_cache { u32 hash_shift; struct flow_cache_percpu *percpu; struct notifier_block hotcpu_notifier; int low_watermark; int high_watermark; struct timer_list rnd_timer; } ;
25 struct xfrm_policy_hash { struct hlist_head *table; unsigned int hmask; u8 dbits4; u8 sbits4; u8 dbits6; u8 sbits6; } ;
21 struct xfrm_policy_hthresh { struct work_struct work; seqlock_t lock; u8 lbits4; u8 rbits4; u8 lbits6; u8 rbits6; } ;
30 struct netns_xfrm { struct list_head state_all; struct hlist_head *state_bydst; struct hlist_head *state_bysrc; struct hlist_head *state_byspi; unsigned int state_hmask; unsigned int state_num; struct work_struct state_hash_work; struct hlist_head state_gc_list; struct work_struct state_gc_work; struct list_head policy_all; struct hlist_head *policy_byidx; unsigned int policy_idx_hmask; struct hlist_head policy_inexact[3U]; struct xfrm_policy_hash policy_bydst[3U]; unsigned int policy_count[6U]; struct work_struct policy_hash_work; struct xfrm_policy_hthresh policy_hthresh; struct sock *nlsk; struct sock *nlsk_stash; u32 sysctl_aevent_etime; u32 sysctl_aevent_rseqth; int sysctl_larval_drop; u32 sysctl_acq_expires; struct ctl_table_header *sysctl_hdr; struct dst_ops xfrm4_dst_ops; struct dst_ops xfrm6_dst_ops; spinlock_t xfrm_state_lock; rwlock_t xfrm_policy_lock; struct mutex xfrm_cfg_mutex; struct flow_cache flow_cache_global; atomic_t flow_cache_genid; struct list_head flow_cache_gc_list; spinlock_t flow_cache_gc_lock; struct work_struct flow_cache_gc_work; struct work_struct flow_cache_flush_work; struct mutex flow_flush_sem; } ;
88 struct mpls_route ;
89 struct netns_mpls { size_t platform_labels; struct mpls_route **platform_label; struct ctl_table_header *ctl; } ;
16 struct net_generic ;
17 struct netns_ipvs ;
18 struct net { atomic_t passive; atomic_t count; spinlock_t rules_mod_lock; atomic64_t cookie_gen; struct list_head list; struct list_head cleanup_list; struct list_head exit_list; struct user_namespace *user_ns; spinlock_t nsid_lock; struct idr netns_ids; struct ns_common ns; struct proc_dir_entry *proc_net; struct proc_dir_entry *proc_net_stat; struct ctl_table_set sysctls; struct sock *rtnl; struct sock *genl_sock; struct list_head dev_base_head; struct hlist_head *dev_name_head; struct hlist_head *dev_index_head; unsigned int dev_base_seq; int ifindex; unsigned int dev_unreg_count; struct list_head rules_ops; struct net_device *loopback_dev; struct netns_core core; struct netns_mib mib; struct netns_packet packet; struct netns_unix unx; struct netns_ipv4 ipv4; struct netns_ipv6 ipv6; struct netns_ieee802154_lowpan ieee802154_lowpan; struct netns_sctp sctp; struct netns_dccp dccp; struct netns_nf nf; struct netns_xt xt; struct netns_ct ct; struct netns_nftables nft; struct netns_nf_frag nf_frag; struct sock *nfnl; struct sock *nfnl_stash; struct list_head nfnl_acct_list; struct list_head nfct_timeout_list; struct sk_buff_head wext_nlevents; struct net_generic *gen; struct netns_xfrm xfrm; struct netns_ipvs *ipvs; struct netns_mpls mpls; struct sock *diag_nlsk; atomic_t fnhe_genid; } ;
247 struct __anonstruct_possible_net_t_407 { struct net *net; } ;
247 typedef struct __anonstruct_possible_net_t_407 possible_net_t;
382 enum fwnode_type { FWNODE_INVALID = 0, FWNODE_OF = 1, FWNODE_ACPI = 2, FWNODE_ACPI_DATA = 3, FWNODE_PDATA = 4, FWNODE_IRQCHIP = 5 } ;
391 struct fwnode_handle { enum fwnode_type type; struct fwnode_handle *secondary; } ;
32 typedef u32 phandle;
34 struct property { char *name; int length; void *value; struct property *next; unsigned long _flags; unsigned int unique_id; struct bin_attribute attr; } ;
44 struct device_node { const char *name; const char *type; phandle phandle; const char *full_name; struct fwnode_handle fwnode; struct property *properties; struct property *deadprops; struct device_node *parent; struct device_node *child; struct device_node *sibling; struct kobject kobj; unsigned long _flags; void *data; } ;
51 struct irq_fwspec { struct fwnode_handle *fwnode; int param_count; u32 param[16U]; } ;
63 enum irq_domain_bus_token { DOMAIN_BUS_ANY = 0, DOMAIN_BUS_PCI_MSI = 1, DOMAIN_BUS_PLATFORM_MSI = 2, DOMAIN_BUS_NEXUS = 3 } ;
70 struct irq_domain_ops { int (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token ); int (*map)(struct irq_domain *, unsigned int, irq_hw_number_t ); void (*unmap)(struct irq_domain *, unsigned int); int (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, unsigned long *, unsigned int *); int (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *); void (*free)(struct irq_domain *, unsigned int, unsigned int); void (*activate)(struct irq_domain *, struct irq_data *); void (*deactivate)(struct irq_domain *, struct irq_data *); int (*translate)(struct irq_domain *, struct irq_fwspec *, unsigned long *, unsigned int *); } ;
116 struct irq_domain { struct list_head link; const char *name; const struct irq_domain_ops *ops; void *host_data; unsigned int flags; struct fwnode_handle *fwnode; enum irq_domain_bus_token bus_token; struct irq_domain_chip_generic *gc; struct irq_domain *parent; irq_hw_number_t hwirq_max; unsigned int revmap_direct_max_irq; unsigned int revmap_size; struct radix_tree_root revmap_tree; unsigned int linear_revmap[]; } ;
178 struct gpio_desc ;
296 struct mii_bus ;
297 struct mdio_device { struct device dev; const struct dev_pm_ops *pm_ops; struct mii_bus *bus; int (*bus_match)(struct device *, struct device_driver *); void (*device_free)(struct mdio_device *); void (*device_remove)(struct mdio_device *); int addr; int flags; } ;
30 struct mdio_driver_common { struct device_driver driver; int flags; } ;
233 struct phy_device ;
234 enum ldv_30991 { PHY_INTERFACE_MODE_NA = 0, PHY_INTERFACE_MODE_MII = 1, PHY_INTERFACE_MODE_GMII = 2, PHY_INTERFACE_MODE_SGMII = 3, PHY_INTERFACE_MODE_TBI = 4, PHY_INTERFACE_MODE_REVMII = 5, PHY_INTERFACE_MODE_RMII = 6, PHY_INTERFACE_MODE_RGMII = 7, PHY_INTERFACE_MODE_RGMII_ID = 8, PHY_INTERFACE_MODE_RGMII_RXID = 9, PHY_INTERFACE_MODE_RGMII_TXID = 10, PHY_INTERFACE_MODE_RTBI = 11, PHY_INTERFACE_MODE_SMII = 12, PHY_INTERFACE_MODE_XGMII = 13, PHY_INTERFACE_MODE_MOCA = 14, PHY_INTERFACE_MODE_QSGMII = 15, PHY_INTERFACE_MODE_MAX = 16 } ;
84 typedef enum ldv_30991 phy_interface_t;
130 enum ldv_31042 { MDIOBUS_ALLOCATED = 1, MDIOBUS_REGISTERED = 2, MDIOBUS_UNREGISTERED = 3, MDIOBUS_RELEASED = 4 } ;
137 struct mii_bus { struct module *owner; const char *name; char id[17U]; void *priv; int (*read)(struct mii_bus *, int, int); int (*write)(struct mii_bus *, int, int, u16 ); int (*reset)(struct mii_bus *); struct mutex mdio_lock; struct device *parent; enum ldv_31042 state; struct device dev; struct mdio_device *mdio_map[32U]; u32 phy_mask; u32 phy_ignore_ta_mask; int irq[32U]; } ;
218 enum phy_state { PHY_DOWN = 0, PHY_STARTING = 1, PHY_READY = 2, PHY_PENDING = 3, PHY_UP = 4, PHY_AN = 5, PHY_RUNNING = 6, PHY_NOLINK = 7, PHY_FORCING = 8, PHY_CHANGELINK = 9, PHY_HALTED = 10, PHY_RESUMING = 11 } ;
233 struct phy_c45_device_ids { u32 devices_in_package; u32 device_ids[8U]; } ;
326 struct phy_driver ;
326 struct phy_device { struct mdio_device mdio; struct phy_driver *drv; u32 phy_id; struct phy_c45_device_ids c45_ids; bool is_c45; bool is_internal; bool is_pseudo_fixed_link; bool has_fixups; bool suspended; enum phy_state state; u32 dev_flags; phy_interface_t interface; int speed; int duplex; int pause; int asym_pause; int link; u32 interrupts; u32 supported; u32 advertising; u32 lp_advertising; int autoneg; int link_timeout; int irq; void *priv; struct work_struct phy_queue; struct delayed_work state_queue; atomic_t irq_disable; struct mutex lock; struct net_device *attached_dev; u8 mdix; void (*adjust_link)(struct net_device *); } ;
431 struct phy_driver { struct mdio_driver_common mdiodrv; u32 phy_id; char *name; unsigned int phy_id_mask; u32 features; u32 flags; const void *driver_data; int (*soft_reset)(struct phy_device *); int (*config_init)(struct phy_device *); int (*probe)(struct phy_device *); int (*suspend)(struct phy_device *); int (*resume)(struct phy_device *); int (*config_aneg)(struct phy_device *); int (*aneg_done)(struct phy_device *); int (*read_status)(struct phy_device *); int (*ack_interrupt)(struct phy_device *); int (*config_intr)(struct phy_device *); int (*did_interrupt)(struct phy_device *); void (*remove)(struct phy_device *); int (*match_phy_device)(struct phy_device *); int (*ts_info)(struct phy_device *, struct ethtool_ts_info *); int (*hwtstamp)(struct phy_device *, struct ifreq *); bool (*rxtstamp)(struct phy_device *, struct sk_buff *, int); void (*txtstamp)(struct phy_device *, struct sk_buff *, int); int (*set_wol)(struct phy_device *, struct ethtool_wolinfo *); void (*get_wol)(struct phy_device *, struct ethtool_wolinfo *); void (*link_change_notify)(struct phy_device *); int (*read_mmd_indirect)(struct phy_device *, int, int, int); void (*write_mmd_indirect)(struct phy_device *, int, int, int, u32 ); int (*module_info)(struct phy_device *, struct ethtool_modinfo *); int (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *); int (*get_sset_count)(struct phy_device *); void (*get_strings)(struct phy_device *, u8 *); void (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *); } ;
836 struct fixed_phy_status { int link; int speed; int duplex; int pause; int asym_pause; } ;
27 enum dsa_tag_protocol { DSA_TAG_PROTO_NONE = 0, DSA_TAG_PROTO_DSA = 1, DSA_TAG_PROTO_TRAILER = 2, DSA_TAG_PROTO_EDSA = 3, DSA_TAG_PROTO_BRCM = 4 } ;
35 struct dsa_chip_data { struct device *host_dev; int sw_addr; int eeprom_len; struct device_node *of_node; char *port_names[12U]; struct device_node *port_dn[12U]; s8 *rtable; struct gpio_desc *reset; } ;
76 struct dsa_platform_data { struct device *netdev; struct net_device *of_netdev; int nr_chips; struct dsa_chip_data *chip; } ;
92 struct packet_type ;
93 struct dsa_switch ;
93 struct dsa_switch_tree { struct dsa_platform_data *pd; struct net_device *master_netdev; int (*rcv)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *); enum dsa_tag_protocol tag_protocol; s8 cpu_switch; s8 cpu_port; struct dsa_switch *ds[4U]; } ;
124 struct dsa_switch_driver ;
124 struct dsa_switch { struct dsa_switch_tree *dst; int index; enum dsa_tag_protocol tag_protocol; struct dsa_chip_data *pd; struct dsa_switch_driver *drv; struct device *master_dev; char hwmon_name[24U]; struct device *hwmon_dev; u32 dsa_port_mask; u32 phys_port_mask; u32 phys_mii_mask; struct mii_bus *slave_mii_bus; struct net_device *ports[12U]; } ;
200 struct switchdev_trans ;
201 struct switchdev_obj ;
202 struct switchdev_obj_port_fdb ;
203 struct switchdev_obj_port_vlan ;
204 struct dsa_switch_driver { struct list_head list; enum dsa_tag_protocol tag_protocol; int priv_size; char * (*probe)(struct device *, int); int (*setup)(struct dsa_switch *); int (*set_addr)(struct dsa_switch *, u8 *); u32 (*get_phy_flags)(struct dsa_switch *, int); int (*phy_read)(struct dsa_switch *, int, int); int (*phy_write)(struct dsa_switch *, int, int, u16 ); void (*adjust_link)(struct dsa_switch *, int, struct phy_device *); void (*fixed_link_update)(struct dsa_switch *, int, struct fixed_phy_status *); void (*get_strings)(struct dsa_switch *, int, uint8_t *); void (*get_ethtool_stats)(struct dsa_switch *, int, uint64_t *); int (*get_sset_count)(struct dsa_switch *); void (*get_wol)(struct dsa_switch *, int, struct ethtool_wolinfo *); int (*set_wol)(struct dsa_switch *, int, struct ethtool_wolinfo *); int (*suspend)(struct dsa_switch *); int (*resume)(struct dsa_switch *); int (*port_enable)(struct dsa_switch *, int, struct phy_device *); void (*port_disable)(struct dsa_switch *, int, struct phy_device *); int (*set_eee)(struct dsa_switch *, int, struct phy_device *, struct ethtool_eee *); int (*get_eee)(struct dsa_switch *, int, struct ethtool_eee *); int (*get_temp)(struct dsa_switch *, int *); int (*get_temp_limit)(struct dsa_switch *, int *); int (*set_temp_limit)(struct dsa_switch *, int); int (*get_temp_alarm)(struct dsa_switch *, bool *); int (*get_eeprom_len)(struct dsa_switch *); int (*get_eeprom)(struct dsa_switch *, struct ethtool_eeprom *, u8 *); int (*set_eeprom)(struct dsa_switch *, struct ethtool_eeprom *, u8 *); int (*get_regs_len)(struct dsa_switch *, int); void (*get_regs)(struct dsa_switch *, int, struct ethtool_regs *, void *); int (*port_join_bridge)(struct dsa_switch *, int, u32 ); int (*port_leave_bridge)(struct dsa_switch *, int, u32 ); int (*port_stp_update)(struct dsa_switch *, int, u8 ); int (*port_vlan_prepare)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *, struct switchdev_trans *); int (*port_vlan_add)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *, struct switchdev_trans *); int (*port_vlan_del)(struct dsa_switch *, int, const struct switchdev_obj_port_vlan *); int (*port_pvid_get)(struct dsa_switch *, int, u16 *); int (*vlan_getnext)(struct dsa_switch *, u16 *, unsigned long *, unsigned long *); int (*port_fdb_prepare)(struct dsa_switch *, int, const struct switchdev_obj_port_fdb *, struct switchdev_trans *); int (*port_fdb_add)(struct dsa_switch *, int, const struct switchdev_obj_port_fdb *, struct switchdev_trans *); int (*port_fdb_del)(struct dsa_switch *, int, const struct switchdev_obj_port_fdb *); int (*port_fdb_dump)(struct dsa_switch *, int, struct switchdev_obj_port_fdb *, int (*)(struct switchdev_obj *)); } ;
350 struct ieee_ets { __u8 willing; __u8 ets_cap; __u8 cbs; __u8 tc_tx_bw[8U]; __u8 tc_rx_bw[8U]; __u8 tc_tsa[8U]; __u8 prio_tc[8U]; __u8 tc_reco_bw[8U]; __u8 tc_reco_tsa[8U]; __u8 reco_prio_tc[8U]; } ;
69 struct ieee_maxrate { __u64 tc_maxrate[8U]; } ;
87 struct ieee_qcn { __u8 rpg_enable[8U]; __u32 rppp_max_rps[8U]; __u32 rpg_time_reset[8U]; __u32 rpg_byte_reset[8U]; __u32 rpg_threshold[8U]; __u32 rpg_max_rate[8U]; __u32 rpg_ai_rate[8U]; __u32 rpg_hai_rate[8U]; __u32 rpg_gd[8U]; __u32 rpg_min_dec_fac[8U]; __u32 rpg_min_rate[8U]; __u32 cndd_state_machine[8U]; } ;
132 struct ieee_qcn_stats { __u64 rppp_rp_centiseconds[8U]; __u32 rppp_created_rps[8U]; } ;
144 struct ieee_pfc { __u8 pfc_cap; __u8 pfc_en; __u8 mbc; __u16 delay; __u64 requests[8U]; __u64 indications[8U]; } ;
164 struct cee_pg { __u8 willing; __u8 error; __u8 pg_en; __u8 tcs_supported; __u8 pg_bw[8U]; __u8 prio_pg[8U]; } ;
187 struct cee_pfc { __u8 willing; __u8 error; __u8 pfc_en; __u8 tcs_supported; } ;
202 struct dcb_app { __u8 selector; __u8 priority; __u16 protocol; } ;
236 struct dcb_peer_app_info { __u8 willing; __u8 error; } ;
40 struct dcbnl_rtnl_ops { int (*ieee_getets)(struct net_device *, struct ieee_ets *); int (*ieee_setets)(struct net_device *, struct ieee_ets *); int (*ieee_getmaxrate)(struct net_device *, struct ieee_maxrate *); int (*ieee_setmaxrate)(struct net_device *, struct ieee_maxrate *); int (*ieee_getqcn)(struct net_device *, struct ieee_qcn *); int (*ieee_setqcn)(struct net_device *, struct ieee_qcn *); int (*ieee_getqcnstats)(struct net_device *, struct ieee_qcn_stats *); int (*ieee_getpfc)(struct net_device *, struct ieee_pfc *); int (*ieee_setpfc)(struct net_device *, struct ieee_pfc *); int (*ieee_getapp)(struct net_device *, struct dcb_app *); int (*ieee_setapp)(struct net_device *, struct dcb_app *); int (*ieee_delapp)(struct net_device *, struct dcb_app *); int (*ieee_peer_getets)(struct net_device *, struct ieee_ets *); int (*ieee_peer_getpfc)(struct net_device *, struct ieee_pfc *); u8 (*getstate)(struct net_device *); u8 (*setstate)(struct net_device *, u8 ); void (*getpermhwaddr)(struct net_device *, u8 *); void (*setpgtccfgtx)(struct net_device *, int, u8 , u8 , u8 , u8 ); void (*setpgbwgcfgtx)(struct net_device *, int, u8 ); void (*setpgtccfgrx)(struct net_device *, int, u8 , u8 , u8 , u8 ); void (*setpgbwgcfgrx)(struct net_device *, int, u8 ); void (*getpgtccfgtx)(struct net_device *, int, u8 *, u8 *, u8 *, u8 *); void (*getpgbwgcfgtx)(struct net_device *, int, u8 *); void (*getpgtccfgrx)(struct net_device *, int, u8 *, u8 *, u8 *, u8 *); void (*getpgbwgcfgrx)(struct net_device *, int, u8 *); void (*setpfccfg)(struct net_device *, int, u8 ); void (*getpfccfg)(struct net_device *, int, u8 *); u8 (*setall)(struct net_device *); u8 (*getcap)(struct net_device *, int, u8 *); int (*getnumtcs)(struct net_device *, int, u8 *); int (*setnumtcs)(struct net_device *, int, u8 ); u8 (*getpfcstate)(struct net_device *); void (*setpfcstate)(struct net_device *, u8 ); void (*getbcncfg)(struct net_device *, int, u32 *); void (*setbcncfg)(struct net_device *, int, u32 ); void (*getbcnrp)(struct net_device *, int, u8 *); void (*setbcnrp)(struct net_device *, int, u8 ); int (*setapp)(struct net_device *, u8 , u16 , u8 ); int (*getapp)(struct net_device *, u8 , u16 ); u8 (*getfeatcfg)(struct net_device *, int, u8 *); u8 (*setfeatcfg)(struct net_device *, int, u8 ); u8 (*getdcbx)(struct net_device *); u8 (*setdcbx)(struct net_device *, u8 ); int (*peer_getappinfo)(struct net_device *, struct dcb_peer_app_info *, u16 *); int (*peer_getapptable)(struct net_device *, struct dcb_app *); int (*cee_peer_getpg)(struct net_device *, struct cee_pg *); int (*cee_peer_getpfc)(struct net_device *, struct cee_pfc *); } ;
105 struct taskstats { __u16 version; __u32 ac_exitcode; __u8 ac_flag; __u8 ac_nice; __u64 cpu_count; __u64 cpu_delay_total; __u64 blkio_count; __u64 blkio_delay_total; __u64 swapin_count; __u64 swapin_delay_total; __u64 cpu_run_real_total; __u64 cpu_run_virtual_total; char ac_comm[32U]; __u8 ac_sched; __u8 ac_pad[3U]; __u32 ac_uid; __u32 ac_gid; __u32 ac_pid; __u32 ac_ppid; __u32 ac_btime; __u64 ac_etime; __u64 ac_utime; __u64 ac_stime; __u64 ac_minflt; __u64 ac_majflt; __u64 coremem; __u64 virtmem; __u64 hiwater_rss; __u64 hiwater_vm; __u64 read_char; __u64 write_char; __u64 read_syscalls; __u64 write_syscalls; __u64 read_bytes; __u64 write_bytes; __u64 cancelled_write_bytes; __u64 nvcsw; __u64 nivcsw; __u64 ac_utimescaled; __u64 ac_stimescaled; __u64 cpu_scaled_run_real_total; __u64 freepages_count; __u64 freepages_delay_total; } ;
603 struct netprio_map { struct callback_head rcu; u32 priomap_len; u32 priomap[]; } ;
41 struct nlmsghdr { __u32 nlmsg_len; __u16 nlmsg_type; __u16 nlmsg_flags; __u32 nlmsg_seq; __u32 nlmsg_pid; } ;
149 struct nlattr { __u16 nla_len; __u16 nla_type; } ;
115 struct netlink_callback { struct sk_buff *skb; const struct nlmsghdr *nlh; int (*start)(struct netlink_callback *); int (*dump)(struct sk_buff *, struct netlink_callback *); int (*done)(struct netlink_callback *); void *data; struct module *module; u16 family; u16 min_dump_alloc; unsigned int prev_seq; unsigned int seq; long args[6U]; } ;
193 struct ndmsg { __u8 ndm_family; __u8 ndm_pad1; __u16 ndm_pad2; __s32 ndm_ifindex; __u16 ndm_state; __u8 ndm_flags; __u8 ndm_type; } ;
39 struct rtnl_link_stats64 { __u64 rx_packets; __u64 tx_packets; __u64 rx_bytes; __u64 tx_bytes; __u64 rx_errors; __u64 tx_errors; __u64 rx_dropped; __u64 tx_dropped; __u64 multicast; __u64 collisions; __u64 rx_length_errors; __u64 rx_over_errors; __u64 rx_crc_errors; __u64 rx_frame_errors; __u64 rx_fifo_errors; __u64 rx_missed_errors; __u64 tx_aborted_errors; __u64 tx_carrier_errors; __u64 tx_fifo_errors; __u64 tx_heartbeat_errors; __u64 tx_window_errors; __u64 rx_compressed; __u64 tx_compressed; } ;
719 struct ifla_vf_stats { __u64 rx_packets; __u64 tx_packets; __u64 rx_bytes; __u64 tx_bytes; __u64 broadcast; __u64 multicast; } ;
16 struct ifla_vf_info { __u32 vf; __u8 mac[32U]; __u32 vlan; __u32 qos; __u32 spoofchk; __u32 linkstate; __u32 min_tx_rate; __u32 max_tx_rate; __u32 rss_query_en; __u32 trusted; } ;
118 struct netpoll_info ;
119 struct wireless_dev ;
120 struct wpan_dev ;
121 struct mpls_dev ;
65 enum netdev_tx { __NETDEV_TX_MIN = -2147483648, NETDEV_TX_OK = 0, NETDEV_TX_BUSY = 16, NETDEV_TX_LOCKED = 32 } ;
110 typedef enum netdev_tx netdev_tx_t;
129 struct net_device_stats { unsigned long rx_packets; unsigned long tx_packets; unsigned long rx_bytes; unsigned long tx_bytes; unsigned long rx_errors; unsigned long tx_errors; unsigned long rx_dropped; unsigned long tx_dropped; unsigned long multicast; unsigned long collisions; unsigned long rx_length_errors; unsigned long rx_over_errors; unsigned long rx_crc_errors; unsigned long rx_frame_errors; unsigned long rx_fifo_errors; unsigned long rx_missed_errors; unsigned long tx_aborted_errors; unsigned long tx_carrier_errors; unsigned long tx_fifo_errors; unsigned long tx_heartbeat_errors; unsigned long tx_window_errors; unsigned long rx_compressed; unsigned long tx_compressed; } ;
192 struct neigh_parms ;
213 struct netdev_hw_addr_list { struct list_head list; int count; } ;
218 struct hh_cache { u16 hh_len; u16 __pad; seqlock_t hh_lock; unsigned long hh_data[16U]; } ;
247 struct header_ops { int (*create)(struct sk_buff *, struct net_device *, unsigned short, const void *, const void *, unsigned int); int (*parse)(const struct sk_buff *, unsigned char *); int (*cache)(const struct neighbour *, struct hh_cache *, __be16 ); void (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *); } ;
297 struct napi_struct { struct list_head poll_list; unsigned long state; int weight; unsigned int gro_count; int (*poll)(struct napi_struct *, int); spinlock_t poll_lock; int poll_owner; struct net_device *dev; struct sk_buff *gro_list; struct sk_buff *skb; struct hrtimer timer; struct list_head dev_list; struct hlist_node napi_hash_node; unsigned int napi_id; } ;
343 enum rx_handler_result { RX_HANDLER_CONSUMED = 0, RX_HANDLER_ANOTHER = 1, RX_HANDLER_EXACT = 2, RX_HANDLER_PASS = 3 } ;
391 typedef enum rx_handler_result rx_handler_result_t;
392 typedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);
540 struct Qdisc ;
540 struct netdev_queue { struct net_device *dev; struct Qdisc *qdisc; struct Qdisc *qdisc_sleeping; struct kobject kobj; int numa_node; spinlock_t _xmit_lock; int xmit_lock_owner; unsigned long trans_start; unsigned long trans_timeout; unsigned long state; struct dql dql; unsigned long tx_maxrate; } ;
610 struct rps_map { unsigned int len; struct callback_head rcu; u16 cpus[0U]; } ;
622 struct rps_dev_flow { u16 cpu; u16 filter; unsigned int last_qtail; } ;
634 struct rps_dev_flow_table { unsigned int mask; struct callback_head rcu; struct rps_dev_flow flows[0U]; } ;
686 struct netdev_rx_queue { struct rps_map *rps_map; struct rps_dev_flow_table *rps_flow_table; struct kobject kobj; struct net_device *dev; } ;
709 struct xps_map { unsigned int len; unsigned int alloc_len; struct callback_head rcu; u16 queues[0U]; } ;
722 struct xps_dev_maps { struct callback_head rcu; struct xps_map *cpu_map[0U]; } ;
733 struct netdev_tc_txq { u16 count; u16 offset; } ;
744 struct netdev_fcoe_hbainfo { char manufacturer[64U]; char serial_number[64U]; char hardware_version[64U]; char driver_version[64U]; char optionrom_version[64U]; char firmware_version[64U]; char model[256U]; char model_description[256U]; } ;
760 struct netdev_phys_item_id { unsigned char id[32U]; unsigned char id_len; } ;
780 struct net_device_ops { int (*ndo_init)(struct net_device *); void (*ndo_uninit)(struct net_device *); int (*ndo_open)(struct net_device *); int (*ndo_stop)(struct net_device *); netdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *); netdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t ); u16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, void *, u16 (*)(struct net_device *, struct sk_buff *)); void (*ndo_change_rx_flags)(struct net_device *, int); void (*ndo_set_rx_mode)(struct net_device *); int (*ndo_set_mac_address)(struct net_device *, void *); int (*ndo_validate_addr)(struct net_device *); int (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int); int (*ndo_set_config)(struct net_device *, struct ifmap *); int (*ndo_change_mtu)(struct net_device *, int); int (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *); void (*ndo_tx_timeout)(struct net_device *); struct rtnl_link_stats64 * (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *); struct net_device_stats * (*ndo_get_stats)(struct net_device *); int (*ndo_vlan_rx_add_vid)(struct net_device *, __be16 , u16 ); int (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16 , u16 ); void (*ndo_poll_controller)(struct net_device *); int (*ndo_netpoll_setup)(struct net_device *, struct netpoll_info *); void (*ndo_netpoll_cleanup)(struct net_device *); int (*ndo_busy_poll)(struct napi_struct *); int (*ndo_set_vf_mac)(struct net_device *, int, u8 *); int (*ndo_set_vf_vlan)(struct net_device *, int, u16 , u8 ); int (*ndo_set_vf_rate)(struct net_device *, int, int, int); int (*ndo_set_vf_spoofchk)(struct net_device *, int, bool ); int (*ndo_set_vf_trust)(struct net_device *, int, bool ); int (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *); int (*ndo_set_vf_link_state)(struct net_device *, int, int); int (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *); int (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **); int (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *); int (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool ); int (*ndo_setup_tc)(struct net_device *, u8 ); int (*ndo_fcoe_enable)(struct net_device *); int (*ndo_fcoe_disable)(struct net_device *); int (*ndo_fcoe_ddp_setup)(struct net_device *, u16 , struct scatterlist *, unsigned int); int (*ndo_fcoe_ddp_done)(struct net_device *, u16 ); int (*ndo_fcoe_ddp_target)(struct net_device *, u16 , struct scatterlist *, unsigned int); int (*ndo_fcoe_get_hbainfo)(struct net_device *, struct netdev_fcoe_hbainfo *); int (*ndo_fcoe_get_wwn)(struct net_device *, u64 *, int); int (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16 , u32 ); int (*ndo_add_slave)(struct net_device *, struct net_device *); int (*ndo_del_slave)(struct net_device *, struct net_device *); netdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t ); int (*ndo_set_features)(struct net_device *, netdev_features_t ); int (*ndo_neigh_construct)(struct neighbour *); void (*ndo_neigh_destroy)(struct neighbour *); int (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16 , u16 ); int (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16 ); int (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int); int (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16 ); int (*ndo_bridge_getlink)(struct sk_buff *, u32 , u32 , struct net_device *, u32 , int); int (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16 ); int (*ndo_change_carrier)(struct net_device *, bool ); int (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *); int (*ndo_get_phys_port_name)(struct net_device *, char *, size_t ); void (*ndo_add_vxlan_port)(struct net_device *, sa_family_t , __be16 ); void (*ndo_del_vxlan_port)(struct net_device *, sa_family_t , __be16 ); void (*ndo_add_geneve_port)(struct net_device *, sa_family_t , __be16 ); void (*ndo_del_geneve_port)(struct net_device *, sa_family_t , __be16 ); void * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *); void (*ndo_dfwd_del_station)(struct net_device *, void *); netdev_tx_t (*ndo_dfwd_start_xmit)(struct sk_buff *, struct net_device *, void *); int (*ndo_get_lock_subclass)(struct net_device *); int (*ndo_set_tx_maxrate)(struct net_device *, int, u32 ); int (*ndo_get_iflink)(const struct net_device *); int (*ndo_change_proto_down)(struct net_device *, bool ); int (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *); } ;
1301 struct __anonstruct_adj_list_421 { struct list_head upper; struct list_head lower; } ;
1301 struct __anonstruct_all_adj_list_422 { struct list_head upper; struct list_head lower; } ;
1301 struct iw_handler_def ;
1301 struct iw_public_data ;
1301 struct switchdev_ops ;
1301 struct l3mdev_ops ;
1301 struct vlan_info ;
1301 struct tipc_bearer ;
1301 struct in_device ;
1301 struct dn_dev ;
1301 struct inet6_dev ;
1301 struct tcf_proto ;
1301 struct cpu_rmap ;
1301 struct pcpu_lstats ;
1301 struct pcpu_sw_netstats ;
1301 struct pcpu_dstats ;
1301 struct pcpu_vstats ;
1301 union __anonunion____missing_field_name_423 { void *ml_priv; struct pcpu_lstats *lstats; struct pcpu_sw_netstats *tstats; struct pcpu_dstats *dstats; struct pcpu_vstats *vstats; } ;
1301 struct garp_port ;
1301 struct mrp_port ;
1301 struct rtnl_link_ops ;
1301 struct net_device { char name[16U]; struct hlist_node name_hlist; char *ifalias; unsigned long mem_end; unsigned long mem_start; unsigned long base_addr; int irq; atomic_t carrier_changes; unsigned long state; struct list_head dev_list; struct list_head napi_list; struct list_head unreg_list; struct list_head close_list; struct list_head ptype_all; struct list_head ptype_specific; struct __anonstruct_adj_list_421 adj_list; struct __anonstruct_all_adj_list_422 all_adj_list; netdev_features_t features; netdev_features_t hw_features; netdev_features_t wanted_features; netdev_features_t vlan_features; netdev_features_t hw_enc_features; netdev_features_t mpls_features; int ifindex; int group; struct net_device_stats stats; atomic_long_t rx_dropped; atomic_long_t tx_dropped; const struct iw_handler_def *wireless_handlers; struct iw_public_data *wireless_data; const struct net_device_ops *netdev_ops; const struct ethtool_ops *ethtool_ops; const struct switchdev_ops *switchdev_ops; const struct l3mdev_ops *l3mdev_ops; const struct header_ops *header_ops; unsigned int flags; unsigned int priv_flags; unsigned short gflags; unsigned short padded; unsigned char operstate; unsigned char link_mode; unsigned char if_port; unsigned char dma; unsigned int mtu; unsigned short type; unsigned short hard_header_len; unsigned short needed_headroom; unsigned short needed_tailroom; unsigned char perm_addr[32U]; unsigned char addr_assign_type; unsigned char addr_len; unsigned short neigh_priv_len; unsigned short dev_id; unsigned short dev_port; spinlock_t addr_list_lock; unsigned char name_assign_type; bool uc_promisc; struct netdev_hw_addr_list uc; struct netdev_hw_addr_list mc; struct netdev_hw_addr_list dev_addrs; struct kset *queues_kset; unsigned int promiscuity; unsigned int allmulti; struct vlan_info *vlan_info; struct dsa_switch_tree *dsa_ptr; struct tipc_bearer *tipc_ptr; void *atalk_ptr; struct in_device *ip_ptr; struct dn_dev *dn_ptr; struct inet6_dev *ip6_ptr; void *ax25_ptr; struct wireless_dev *ieee80211_ptr; struct wpan_dev *ieee802154_ptr; struct mpls_dev *mpls_ptr; unsigned long last_rx; unsigned char *dev_addr; struct netdev_rx_queue *_rx; unsigned int num_rx_queues; unsigned int real_num_rx_queues; unsigned long gro_flush_timeout; rx_handler_func_t *rx_handler; void *rx_handler_data; struct tcf_proto *ingress_cl_list; struct netdev_queue *ingress_queue; struct list_head nf_hooks_ingress; unsigned char broadcast[32U]; struct cpu_rmap *rx_cpu_rmap; struct hlist_node index_hlist; struct netdev_queue *_tx; unsigned int num_tx_queues; unsigned int real_num_tx_queues; struct Qdisc *qdisc; unsigned long tx_queue_len; spinlock_t tx_global_lock; int watchdog_timeo; struct xps_dev_maps *xps_maps; struct tcf_proto *egress_cl_list; u32 offload_fwd_mark; unsigned long trans_start; struct timer_list watchdog_timer; int *pcpu_refcnt; struct list_head todo_list; struct list_head link_watch_list; unsigned char reg_state; bool dismantle; unsigned short rtnl_link_state; void (*destructor)(struct net_device *); struct netpoll_info *npinfo; possible_net_t nd_net; union __anonunion____missing_field_name_423 __annonCompField104; struct garp_port *garp_port; struct mrp_port *mrp_port; struct device dev; const struct attribute_group *sysfs_groups[4U]; const struct attribute_group *sysfs_rx_queue_group; const struct rtnl_link_ops *rtnl_link_ops; unsigned int gso_max_size; u16 gso_max_segs; u16 gso_min_segs; const struct dcbnl_rtnl_ops *dcbnl_ops; u8 num_tc; struct netdev_tc_txq tc_to_txq[16U]; u8 prio_tc_map[16U]; unsigned int fcoe_ddp_xid; struct netprio_map *priomap; struct phy_device *phydev; struct lock_class_key *qdisc_tx_busylock; bool proto_down; } ;
2060 struct packet_type { __be16 type; struct net_device *dev; int (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *); bool (*id_match)(struct packet_type *, struct sock *); void *af_packet_priv; struct list_head list; } ;
2107 struct pcpu_sw_netstats { u64 rx_packets; u64 rx_bytes; u64 tx_packets; u64 tx_bytes; struct u64_stats_sync syncp; } ;
313 struct hdlc_proto { int (*open)(struct net_device *); void (*close)(struct net_device *); void (*start)(struct net_device *); void (*stop)(struct net_device *); void (*detach)(struct net_device *); int (*ioctl)(struct net_device *, struct ifreq *); __be16 (*type_trans)(struct sk_buff *, struct net_device *); int (*netif_rx)(struct sk_buff *); netdev_tx_t (*xmit)(struct sk_buff *, struct net_device *); struct module *module; struct hdlc_proto *next; } ;
35 struct hdlc_device { int (*attach)(struct net_device *, unsigned short, unsigned short); netdev_tx_t (*xmit)(struct sk_buff *, struct net_device *); const struct hdlc_proto *proto; int carrier; int open; spinlock_t state_lock; void *state; void *priv; } ;
53 typedef struct hdlc_device hdlc_device;
119 struct _MGSL_PARAMS { unsigned long mode; unsigned char loopback; unsigned short flags; unsigned char encoding; unsigned long clock_speed; unsigned char addr_filter; unsigned short crc_type; unsigned char preamble_length; unsigned char preamble; unsigned long data_rate; unsigned char data_bits; unsigned char stop_bits; unsigned char parity; } ;
169 typedef struct _MGSL_PARAMS MGSL_PARAMS;
170 struct mgsl_icount { __u32 cts; __u32 dsr; __u32 rng; __u32 dcd; __u32 tx; __u32 rx; __u32 frame; __u32 parity; __u32 overrun; __u32 brk; __u32 buf_overrun; __u32 txok; __u32 txunder; __u32 txabort; __u32 txtimeout; __u32 rxshort; __u32 rxlong; __u32 rxabort; __u32 rxover; __u32 rxcrc; __u32 rxok; __u32 exithunt; __u32 rxidle; } ;
229 struct gpio_desc { __u32 state; __u32 smask; __u32 dir; __u32 dmask; } ;
86 struct _SCADESC { u16 next; u16 buf_ptr; u8 buf_base; u8 pad1; u16 length; u8 status; u8 pad2; } ;
121 typedef struct _SCADESC SCADESC;
122 struct _SCADESC_EX { char *virt_addr; u16 phys_entry; } ;
128 typedef struct _SCADESC_EX SCADESC_EX;
129 struct _input_signal_events { int ri_up; int ri_down; int dsr_up; int dsr_down; int dcd_up; int dcd_down; int cts_up; int cts_down; } ;
148 struct _synclinkmp_info { void *if_ptr; int magic; struct tty_port port; int line; unsigned short close_delay; unsigned short closing_wait; struct mgsl_icount icount; int timeout; int x_char; u16 read_status_mask1; u16 read_status_mask2; unsigned char ignore_status_mask1; unsigned char ignore_status_mask2; unsigned char *tx_buf; int tx_put; int tx_get; int tx_count; wait_queue_head_t status_event_wait_q; wait_queue_head_t event_wait_q; struct timer_list tx_timer; struct _synclinkmp_info *next_device; struct timer_list status_timer; spinlock_t lock; struct work_struct task; u32 max_frame_size; u32 pending_bh; bool bh_running; int isr_overflow; bool bh_requested; int dcd_chkcount; int cts_chkcount; int dsr_chkcount; int ri_chkcount; char *buffer_list; unsigned long buffer_list_phys; unsigned int rx_buf_count; SCADESC *rx_buf_list; SCADESC_EX rx_buf_list_ex[128U]; unsigned int current_rx_buf; unsigned int tx_buf_count; SCADESC *tx_buf_list; SCADESC_EX tx_buf_list_ex[128U]; unsigned int last_tx_buf; unsigned char *tmp_rx_buf; unsigned int tmp_rx_buf_count; bool rx_enabled; bool rx_overflow; bool tx_enabled; bool tx_active; u32 idle_mode; unsigned char ie0_value; unsigned char ie1_value; unsigned char ie2_value; unsigned char ctrlreg_value; unsigned char old_signals; char device_name[25U]; int port_count; int adapter_num; int port_num; struct _synclinkmp_info *port_array[4U]; unsigned int bus_type; unsigned int irq_level; unsigned long irq_flags; bool irq_requested; MGSL_PARAMS params; unsigned char serial_signals; bool irq_occurred; unsigned int init_error; u32 last_mem_alloc; unsigned char *memory_base; u32 phys_memory_base; int shared_mem_requested; unsigned char *sca_base; u32 phys_sca_base; u32 sca_offset; bool sca_base_requested; unsigned char *lcr_base; u32 phys_lcr_base; u32 lcr_offset; int lcr_mem_requested; unsigned char *statctrl_base; u32 phys_statctrl_base; u32 statctrl_offset; bool sca_statctrl_requested; u32 misc_ctrl_value; char *flag_buf; bool drop_rts_on_tx_done; struct _input_signal_events input_signal_events; int netcount; spinlock_t netlock; struct net_device *netdev; } ;
279 typedef struct _synclinkmp_info SLMP_INFO;
41 typedef int ldv_func_ret_type;
1 void * __builtin_memcpy(void *, const void *, unsigned long);
1 unsigned long int __builtin_object_size(void *, int);
1 long int __builtin_expect(long, long);
216 void __read_once_size(const volatile void *p, void *res, int size);
241 void __write_once_size(volatile void *p, void *res, int size);
33 extern struct module __this_module;
72 void set_bit(long nr, volatile unsigned long *addr);
110 void clear_bit(long nr, volatile unsigned long *addr);
308 int constant_test_bit(long nr, const volatile unsigned long *addr);
314 int variable_test_bit(long nr, const volatile unsigned long *addr);
142 int printk(const char *, ...);
248 void __might_fault(const char *, int);
403 int sprintf(char *, const char *, ...);
3 bool ldv_is_err(const void *ptr);
25 void INIT_LIST_HEAD(struct list_head *list);
198 int list_empty(const struct list_head *head);
87 void __bad_percpu_size();
10 extern struct task_struct *current_task;
12 struct task_struct * get_current();
31 void * __memcpy(void *, const void *, size_t );
56 void * __memset(void *, int, size_t );
62 int memcmp(const void *, const void *, size_t );
65 char * strcat(char *, const char *);
11 void __xchg_wrong_size();
41 bool IS_ERR(const void *ptr);
90 int test_ti_thread_flag(struct thread_info *ti, int flag);
280 void lockdep_init_map(struct lockdep_map *, const char *, struct lock_class_key *, int);
93 void __raw_spin_lock_init(raw_spinlock_t *, const char *, struct lock_class_key *);
22 void _raw_spin_lock(raw_spinlock_t *);
34 unsigned long int _raw_spin_lock_irqsave(raw_spinlock_t *);
41 void _raw_spin_unlock(raw_spinlock_t *);
45 void _raw_spin_unlock_irqrestore(raw_spinlock_t *, unsigned long);
289 raw_spinlock_t * spinlock_check(spinlock_t *lock);
300 void spin_lock(spinlock_t *lock);
345 void spin_unlock(spinlock_t *lock);
360 void spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags);
14 int default_wake_function(wait_queue_t *, unsigned int, int, void *);
72 void __init_waitqueue_head(wait_queue_head_t *, const char *, struct lock_class_key *);
135 int waitqueue_active(wait_queue_head_t *q);
161 void add_wait_queue(wait_queue_head_t *, wait_queue_t *);
163 void remove_wait_queue(wait_queue_head_t *, wait_queue_t *);
200 void __wake_up(wait_queue_head_t *, unsigned int, int, void *);
138 void mutex_lock_nested(struct mutex *, unsigned int);
174 void mutex_unlock(struct mutex *);
78 extern volatile unsigned long jiffies;
284 unsigned int jiffies_to_msecs(const unsigned long);
292 unsigned long int __msecs_to_jiffies(const unsigned int);
354 unsigned long int msecs_to_jiffies(const unsigned int m);
88 void init_timer_key(struct timer_list *, unsigned int, const char *, struct lock_class_key *);
169 int del_timer(struct timer_list *);
170 int mod_timer(struct timer_list *, unsigned long);
181 void __init_work(struct work_struct *, int);
352 extern struct workqueue_struct *system_wq;
429 bool queue_work_on(int, struct workqueue_struct *, struct work_struct *);
469 bool queue_work(struct workqueue_struct *wq, struct work_struct *work);
528 bool schedule_work(struct work_struct *work);
140 extern struct resource iomem_resource;
193 struct resource * __request_region(struct resource *, resource_size_t , resource_size_t , const char *, int);
202 void __release_region(struct resource *, resource_size_t , resource_size_t );
181 void * ioremap_nocache(resource_size_t , unsigned long);
197 void iounmap(volatile void *);
13 int ldv_register_netdev();
209 bool capable(int);
430 void schedule();
2889 int test_tsk_thread_flag(struct task_struct *tsk, int flag);
2915 int signal_pending(struct task_struct *p);
667 unsigned long int _copy_from_user(void *, const void *, unsigned int);
669 unsigned long int _copy_to_user(void *, const void *, unsigned int);
689 void __copy_from_user_overflow();
694 void __copy_to_user_overflow();
710 unsigned long int copy_from_user(void *to, const void *from, unsigned long n);
745 unsigned long int copy_to_user(void *to, const void *from, unsigned long n);
129 int request_threaded_irq(unsigned int, irqreturn_t (*)(int, void *), irqreturn_t (*)(int, void *), unsigned long, const char *, void *);
134 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *), unsigned long flags, const char *name, void *dev);
148 void free_irq(unsigned int, void *);
114 ssize_t seq_read(struct file *, char *, size_t , loff_t *);
115 loff_t seq_lseek(struct file *, loff_t , int);
122 void seq_printf(struct seq_file *, const char *, ...);
140 int single_open(struct file *, int (*)(struct seq_file *, void *), void *);
142 int single_release(struct inode *, struct file *);
148 void kfree(const void *);
312 void * __kmalloc(size_t , gfp_t );
451 void * kmalloc(size_t size, gfp_t flags);
605 void * kzalloc(size_t size, gfp_t flags);
974 int pci_enable_device(struct pci_dev *);
1182 int __pci_register_driver(struct pci_driver *, struct module *, const char *);
1191 void pci_unregister_driver(struct pci_driver *);
332 struct tty_driver * __tty_alloc_driver(unsigned int, struct module *, unsigned long);
334 void put_tty_driver(struct tty_driver *);
335 void tty_set_operations(struct tty_driver *, const struct tty_operations *);
349 struct tty_driver * alloc_tty_driver(unsigned int lines);
73 unsigned char * char_buf_ptr(struct tty_buffer *b, int ofs);
78 char * flag_buf_ptr(struct tty_buffer *b, int ofs);
396 extern struct ktermios tty_std_termios;
427 int tty_register_driver(struct tty_driver *);
428 int tty_unregister_driver(struct tty_driver *);
455 void tty_hangup(struct tty_struct *);
457 int tty_hung_up_p(struct file *);
458 void do_SAK(struct tty_struct *);
467 speed_t tty_termios_baud_rate(struct ktermios *);
484 speed_t tty_get_baud_rate(struct tty_struct *tty);
493 struct tty_ldisc * tty_ldisc_ref(struct tty_struct *);
494 void tty_ldisc_deref(struct tty_ldisc *);
499 void tty_wakeup(struct tty_struct *);
500 void tty_ldisc_flush(struct tty_struct *);
524 void tty_port_init(struct tty_port *);
536 void tty_port_destroy(struct tty_port *);
547 bool tty_port_cts_enabled(struct tty_port *port);
554 int tty_port_carrier_raised(struct tty_port *);
555 void tty_port_raise_dtr_rts(struct tty_port *);
562 int tty_port_close_start(struct tty_port *, struct tty_struct *, struct file *);
564 void tty_port_close_end(struct tty_port *, struct tty_struct *);
567 int tty_port_install(struct tty_port *, struct tty_driver *, struct tty_struct *);
651 void tty_lock(struct tty_struct *);
652 void tty_unlock(struct tty_struct *);
7 int tty_insert_flip_string_flags(struct tty_port *, const unsigned char *, const char *, size_t );
13 void tty_flip_buffer_push(struct tty_port *);
16 int tty_insert_flip_char(struct tty_port *port, unsigned char ch, char flag);
47 unsigned long int msleep_interruptible(unsigned int);
879 void consume_skb(struct sk_buff *);
1880 unsigned char * skb_put(struct sk_buff *, unsigned int);
2120 void skb_reset_mac_header(struct sk_buff *skb);
2337 struct sk_buff * __netdev_alloc_skb(struct net_device *, unsigned int, gfp_t );
2353 struct sk_buff * netdev_alloc_skb(struct net_device *dev, unsigned int length);
2367 struct sk_buff * dev_alloc_skb(unsigned int length);
1884 struct netdev_queue * netdev_get_tx_queue(const struct net_device *dev, unsigned int index);
1942 void * netdev_priv(const struct net_device *dev);
2317 void free_netdev(struct net_device *);
2715 void netif_tx_start_queue(struct netdev_queue *dev_queue);
2726 void netif_start_queue(struct net_device *dev);
2741 void netif_tx_wake_queue(struct netdev_queue *);
2750 void netif_wake_queue(struct net_device *dev);
2765 void netif_tx_stop_queue(struct netdev_queue *dev_queue);
2777 void netif_stop_queue(struct net_device *dev);
2784 bool netif_tx_queue_stopped(const struct netdev_queue *dev_queue);
2795 bool netif_queue_stopped(const struct net_device *dev);
3141 int netif_rx(struct sk_buff *);
3244 void netif_carrier_on(struct net_device *);
3246 void netif_carrier_off(struct net_device *);
3549 int register_netdev(struct net_device *);
3552 int ldv_register_netdev_5(struct net_device *ldv_func_arg1);
60 int hdlc_ioctl(struct net_device *, struct ifreq *, int);
64 void unregister_hdlc_device(struct net_device *);
70 struct net_device * alloc_hdlcdev(void *);
72 struct hdlc_device * dev_to_hdlc(struct net_device *dev);
93 int hdlc_open(struct net_device *);
95 void hdlc_close(struct net_device *);
97 int hdlc_change_mtu(struct net_device *, int);
99 netdev_tx_t hdlc_start_xmit(struct sk_buff *, struct net_device *);
106 __be16 hdlc_type_trans(struct sk_buff *skb, struct net_device *dev);
85 struct _MGSL_PARAMS default_params = { 2UL, 0U, 1U, 3U, 0UL, 255U, 1U, 0U, 0U, 9600UL, 8U, 1U, 0U };
449 SLMP_INFO *synclinkmp_device_list = (SLMP_INFO *)0;
450 int synclinkmp_adapter_count = -1;
451 int synclinkmp_device_count = 0;
458 _Bool break_on_load = 0;
464 int ttymajor = 0;
469 int debug_level = 0;
470 int maxframe[12U] = { 0 };
477 char *driver_name = (char *)"SyncLink MultiPort driver";
478 char *driver_version = (char *)"$Revision: 4.38 $";
480 int synclinkmp_init_one(struct pci_dev *dev, const struct pci_device_id *ent);
481 void synclinkmp_remove_one(struct pci_dev *dev);
483 struct pci_device_id synclinkmp_pci_tbl[2U] = { { 5056U, 48U, 4294967295U, 4294967295U, 0U, 0U, 0UL }, { 0U, 0U, 0U, 0U, 0U, 0U, 0UL } };
487 const struct pci_device_id __mod_pci__synclinkmp_pci_tbl_device_table[2U] = { };
491 struct pci_driver synclinkmp_pci_driver = { { 0, 0 }, "synclinkmp", (const struct pci_device_id *)(&synclinkmp_pci_tbl), &synclinkmp_init_one, &synclinkmp_remove_one, 0, 0, 0, 0, 0, 0, 0, { 0, 0, 0, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { { { { 0 } }, 0U, 0U, 0, { 0, { 0, 0 }, 0, 0, 0UL } } } }, { 0, 0 } } };
499 struct tty_driver *serial_driver = 0;
507 int open(struct tty_struct *tty, struct file *filp);
508 void close(struct tty_struct *tty, struct file *filp);
509 void hangup(struct tty_struct *tty);
510 void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
512 int write(struct tty_struct *tty, const unsigned char *buf, int count);
513 int put_char(struct tty_struct *tty, unsigned char ch);
514 void send_xchar(struct tty_struct *tty, char ch);
515 void wait_until_sent(struct tty_struct *tty, int timeout);
516 int write_room(struct tty_struct *tty);
517 void flush_chars(struct tty_struct *tty);
518 void flush_buffer(struct tty_struct *tty);
519 void tx_hold(struct tty_struct *tty);
520 void tx_release(struct tty_struct *tty);
522 int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
523 int chars_in_buffer(struct tty_struct *tty);
524 void throttle(struct tty_struct *tty);
525 void unthrottle(struct tty_struct *tty);
526 int set_break(struct tty_struct *tty, int break_state);
530 void hdlcdev_tx_done(SLMP_INFO *info);
531 void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
532 int hdlcdev_init(SLMP_INFO *info);
533 void hdlcdev_exit(SLMP_INFO *info);
538 int get_stats(SLMP_INFO *info, struct mgsl_icount *user_icount);
539 int get_params(SLMP_INFO *info, MGSL_PARAMS *user_params);
540 int set_params(SLMP_INFO *info, MGSL_PARAMS *new_params);
541 int get_txidle(SLMP_INFO *info, int *idle_mode);
542 int set_txidle(SLMP_INFO *info, int idle_mode);
543 int tx_enable(SLMP_INFO *info, int enable);
544 int tx_abort(SLMP_INFO *info);
545 int rx_enable(SLMP_INFO *info, int enable);
546 int modem_input_wait(SLMP_INFO *info, int arg);
547 int wait_mgsl_event(SLMP_INFO *info, int *mask_ptr);
548 int tiocmget(struct tty_struct *tty);
549 int tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear);
553 void add_device(SLMP_INFO *info);
554 void device_init(int adapter_num, struct pci_dev *pdev);
555 int claim_resources(SLMP_INFO *info);
556 void release_resources(SLMP_INFO *info);
558 int startup(SLMP_INFO *info);
559 int block_til_ready(struct tty_struct *tty, struct file *filp, SLMP_INFO *info);
560 int carrier_raised(struct tty_port *port);
561 void shutdown(SLMP_INFO *info);
562 void program_hw(SLMP_INFO *info);
563 void change_params(SLMP_INFO *info);
565 bool init_adapter(SLMP_INFO *info);
566 bool register_test(SLMP_INFO *info);
567 bool irq_test(SLMP_INFO *info);
568 bool loopback_test(SLMP_INFO *info);
569 int adapter_test(SLMP_INFO *info);
570 bool memory_test(SLMP_INFO *info);
572 void reset_adapter(SLMP_INFO *info);
573 void reset_port(SLMP_INFO *info);
574 void async_mode(SLMP_INFO *info);
575 void hdlc_mode(SLMP_INFO *info);
577 void rx_stop(SLMP_INFO *info);
578 void rx_start(SLMP_INFO *info);
579 void rx_reset_buffers(SLMP_INFO *info);
580 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
581 bool rx_get_frame(SLMP_INFO *info);
583 void tx_start(SLMP_INFO *info);
584 void tx_stop(SLMP_INFO *info);
585 void tx_load_fifo(SLMP_INFO *info);
586 void tx_set_idle(SLMP_INFO *info);
587 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
589 void get_signals(SLMP_INFO *info);
590 void set_signals(SLMP_INFO *info);
591 void enable_loopback(SLMP_INFO *info, int enable);
592 void set_rate(SLMP_INFO *info, u32 data_rate);
594 int bh_action(SLMP_INFO *info);
595 void bh_handler(struct work_struct *work);
596 void bh_receive(SLMP_INFO *info);
597 void bh_transmit(SLMP_INFO *info);
598 void bh_status(SLMP_INFO *info);
599 void isr_timer(SLMP_INFO *info);
600 void isr_rxint(SLMP_INFO *info);
601 void isr_rxrdy(SLMP_INFO *info);
602 void isr_txint(SLMP_INFO *info);
603 void isr_txrdy(SLMP_INFO *info);
604 void isr_rxdmaok(SLMP_INFO *info);
605 void isr_rxdmaerror(SLMP_INFO *info);
606 void isr_txdmaok(SLMP_INFO *info);
607 void isr_txdmaerror(SLMP_INFO *info);
608 void isr_io_pin(SLMP_INFO *info, u16 status);
610 int alloc_dma_bufs(SLMP_INFO *info);
611 void free_dma_bufs(SLMP_INFO *info);
612 int alloc_buf_list(SLMP_INFO *info);
613 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list, SCADESC_EX *buf_list_ex, int count);
614 int alloc_tmp_rx_buf(SLMP_INFO *info);
615 void free_tmp_rx_buf(SLMP_INFO *info);
617 void load_pci_memory(SLMP_INFO *info, char *dest, const char *src, unsigned short count);
618 void trace_block(SLMP_INFO *info, const char *data, int count, int xmit);
619 void tx_timeout(unsigned long context);
620 void status_timeout(unsigned long context);
622 unsigned char read_reg(SLMP_INFO *info, unsigned char Addr);
623 void write_reg(SLMP_INFO *info, unsigned char Addr, unsigned char Value);
624 u16 read_reg16(SLMP_INFO *info, unsigned char Addr);
625 void write_reg16(SLMP_INFO *info, unsigned char Addr, u16 Value);
626 unsigned char read_status_reg(SLMP_INFO *info);
627 void write_control_reg(SLMP_INFO *info);
630 unsigned char rx_active_fifo_level = 16U;
631 unsigned char tx_active_fifo_level = 16U;
632 unsigned char tx_negate_fifo_level = 32U;
634 unsigned int misc_ctrl_value = 8273984U;
635 unsigned int lcr1_brdr_value = 8388648U;
637 unsigned int read_ahead_count = 8U;
650 unsigned char dma_priority = 4U;
654 unsigned int sca_pci_load_interval = 64U;
662 void * synclinkmp_get_text_ptr();
665 int sanity_check(SLMP_INFO *info, char *name, const char *routine);
698 void ldisc_receive_buf(struct tty_struct *tty, const __u8 *data, char *flags, int count);
714 int install(struct tty_driver *driver, struct tty_struct *tty);
1313 int get_icount(struct tty_struct *tty, struct serial_icounter_struct *icount);
1343 void line_info(struct seq_file *m, SLMP_INFO *info);
1416 int synclinkmp_proc_show(struct seq_file *m, void *v);
1430 int synclinkmp_proc_open(struct inode *inode, struct file *file);
1435 const struct file_operations synclinkmp_proc_fops = { &__this_module, &seq_lseek, &seq_read, 0, 0, 0, 0, 0, 0, 0, 0, &synclinkmp_proc_open, 0, &single_release, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
1552 int hdlcdev_attach(struct net_device *dev, unsigned short encoding, unsigned short parity);
1597 netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev);
1640 int hdlcdev_open(struct net_device *dev);
1699 int hdlcdev_close(struct net_device *dev);
1730 int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
1830 void hdlcdev_tx_timeout(struct net_device *dev);
1893 const struct net_device_ops hdlcdev_ops = { 0, 0, &hdlcdev_open, &hdlcdev_close, &hdlc_start_xmit, 0, 0, 0, 0, 0, 0, &hdlcdev_ioctl, 0, &hdlc_change_mtu, 0, &hdlcdev_tx_timeout, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
2223 void isr_txeom(SLMP_INFO *info, unsigned char status);
2521 irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id);
3264 void dtr_rts(struct tty_port *port, int on);
3739 const struct tty_port_operations port_ops = { &carrier_raised, &dtr_rts, 0, 0, 0 };
3748 SLMP_INFO * alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev);
3881 const struct tty_operations ops = { 0, &install, 0, &open, &close, 0, 0, &write, &put_char, &flush_chars, &write_room, &chars_in_buffer, &ioctl, 0, &set_termios, &throttle, &unthrottle, &tx_hold, &tx_release, &hangup, &set_break, &flush_buffer, 0, &wait_until_sent, &send_xchar, &tiocmget, &tiocmset, 0, 0, &get_icount, 0, 0, 0, &synclinkmp_proc_fops };
3908 void synclinkmp_cleanup();
3956 int synclinkmp_init();
4012 void synclinkmp_exit();
5139 bool sca_init(SLMP_INFO *info);
5617 void ldv_check_final_state();
5620 void ldv_check_return_value(int);
5623 void ldv_check_return_value_probe(int retval);
5626 void ldv_initialize();
5629 void ldv_handler_precall();
5632 int nondet_int();
5635 int LDV_IN_INTERRUPT = 0;
5638 void ldv_main0_sequence_infinite_withcheck_stateful();
10 void ldv_error();
14 void * ldv_err_ptr(long error);
21 long int ldv_ptr_err(const void *ptr);
28 bool ldv_is_err_or_null(const void *ptr);
14 int ldv_probe_state = 0;
17 int ldv_usb_register();
return ;
}
-entry_point
{
5640 struct pci_dev *var_group1;
5641 const struct pci_device_id *var_synclinkmp_init_one_121_p1;
5642 int res_synclinkmp_init_one_121;
5643 struct inode *var_group2;
5644 struct file *var_group3;
5645 int res_synclinkmp_proc_open_21;
5646 struct net_device *var_group4;
5647 int res_hdlcdev_open_28;
5648 int res_hdlcdev_close_29;
5649 struct ifreq *var_group5;
5650 int var_hdlcdev_ioctl_30_p2;
5651 struct tty_port *var_group6;
5652 int var_dtr_rts_70_p1;
5653 struct tty_driver *var_group7;
5654 struct tty_struct *var_group8;
5655 int res_open_4;
5656 const unsigned char *var_write_8_p1;
5657 int var_write_8_p2;
5658 unsigned char var_put_char_9_p1;
5659 unsigned int var_ioctl_17_p1;
5660 unsigned long var_ioctl_17_p2;
5661 char var_send_xchar_10_p1;
5662 int var_set_break_25_p1;
5663 int var_wait_until_sent_11_p1;
5664 struct ktermios *var_group9;
5665 unsigned int var_tiocmset_68_p1;
5666 unsigned int var_tiocmset_68_p2;
5667 struct serial_icounter_struct *var_group10;
5668 int var_synclinkmp_interrupt_52_p0;
5669 void *var_synclinkmp_interrupt_52_p1;
5670 int ldv_s_synclinkmp_pci_driver_pci_driver;
5671 int ldv_s_synclinkmp_proc_fops_file_operations;
5672 int ldv_s_hdlcdev_ops_net_device_ops;
5673 int ldv_s_ops_tty_operations;
5674 int tmp;
5675 int tmp___0;
5676 int tmp___1;
12697 ldv_s_synclinkmp_pci_driver_pci_driver = 0;
12699 ldv_s_synclinkmp_proc_fops_file_operations = 0;
12701 ldv_s_hdlcdev_ops_net_device_ops = 0;
12706 ldv_s_ops_tty_operations = 0;
12470 LDV_IN_INTERRUPT = 1;
12479 ldv_initialize() { /* Function call is skipped due to function is undefined */}
12673 ldv_handler_precall() { /* Function call is skipped due to function is undefined */}
12674 -synclinkmp_init()
{
3958 int rc;
3960 assume(((int)break_on_load) == 0);
3965 printk("%s %s\n", driver_name, driver_version) { /* Function call is skipped due to function is undefined */}
3967 rc = __pci_register_driver(&synclinkmp_pci_driver, &__this_module, "synclinkmp") { /* Function call is skipped due to function is undefined */}
3967 assume(!(rc < 0));
3972 -alloc_tty_driver(128U)
{
351 struct tty_driver *ret;
352 struct tty_driver *tmp;
353 _Bool tmp___0;
351 tmp = __tty_alloc_driver(lines, &__this_module, 0UL) { /* Function call is skipped due to function is undefined */}
351 ret = tmp;
352 -IS_ERR((const void *)ret)
{
29 _Bool tmp;
30 -ldv_is_err(ptr)
{
10 return ((unsigned long)ptr) > 2012UL;;
}
30 return tmp;;
}
352 assume(((int)tmp___0) == 0);
354 return ret;;
}
3973 assume(!(((unsigned long)serial_driver) == ((unsigned long)((struct tty_driver *)0))));
3980 serial_driver->driver_name = "synclinkmp";
3981 serial_driver->name = "ttySLM";
3982 serial_driver->major = ttymajor;
3983 serial_driver->minor_start = 64;
3984 serial_driver->type = 3;
3985 serial_driver->subtype = 1;
3986 serial_driver->init_termios = tty_std_termios;
3987 serial_driver->init_termios.c_cflag = 3261U;
3989 serial_driver->init_termios.c_ispeed = 9600U;
3990 serial_driver->init_termios.c_ospeed = 9600U;
3991 serial_driver->flags = 4UL;
3992 tty_set_operations(serial_driver, &ops) { /* Function call is skipped due to function is undefined */}
3993 rc = tty_register_driver(serial_driver) { /* Function call is skipped due to function is undefined */}
3993 assume(!(rc < 0));
4001 printk("%s %s, tty major#%d\n", driver_name, driver_version, serial_driver->major) { /* Function call is skipped due to function is undefined */}
4005 return 0;;
}
12674 assume(!(tmp != 0));
12712 goto ldv_50633;
12712 tmp___1 = nondet_int() { /* Function call is skipped due to function is undefined */}
12712 assume(tmp___1 != 0);
12718 goto ldv_50632;
12713 ldv_50632:;
12719 tmp___0 = nondet_int() { /* Function call is skipped due to function is undefined */}
12719 switch (tmp___0);
12720 assume(tmp___0 == 0);
12724 assume(ldv_s_synclinkmp_pci_driver_pci_driver == 0);
12936 -synclinkmp_init_one(var_group1, var_synclinkmp_init_one_121_p1)
{
5588 int tmp;
5589 tmp = pci_enable_device(dev) { /* Function call is skipped due to function is undefined */}
5589 assume(!(tmp != 0));
5593 synclinkmp_adapter_count = synclinkmp_adapter_count + 1;
5593 -device_init(synclinkmp_adapter_count, dev)
{
3826 SLMP_INFO *port_array[4U];
3827 int port;
3828 struct lock_class_key __key;
3829 int tmp;
3830 int tmp___0;
3830 port = 0;
3830 goto ldv_50170;
3830 assume(port <= 3);
3832 goto ldv_50169;
3831 ldv_50169:;
3831 -alloc_dev(adapter_num, port, pdev)
{
3750 SLMP_INFO *info;
3751 void *tmp;
3752 struct lock_class_key __key;
3753 struct __anonstruct_atomic64_t_7 __constr_expr_0;
3754 struct lock_class_key __key___0;
3755 struct lock_class_key __key___1;
3756 struct lock_class_key __key___2;
3757 struct lock_class_key __key___3;
3758 struct lock_class_key __key___4;
3752 -kzalloc(6296UL, 37748928U)
{
607 void *tmp;
607 -kmalloc(size, flags | 32768U)
{
453 void *tmp___2;
468 tmp___2 = __kmalloc(size, flags) { /* Function call is skipped due to function is undefined */}
468 return tmp___2;;
}
607 return tmp;;
}
3752 info = (SLMP_INFO *)tmp;
3755 assume(!(((unsigned long)info) == ((unsigned long)((SLMP_INFO *)0))));
3759 tty_port_init(&(info->port)) { /* Function call is skipped due to function is undefined */}
3760 info->port.ops = &port_ops;
3761 info->magic = 21505;
3762 __init_work(&(info->task), 0) { /* Function call is skipped due to function is undefined */}
3762 __constr_expr_0.counter = 137438953408L;
3762 info->task.data = __constr_expr_0;
3762 lockdep_init_map(&(info->task.lockdep_map), "(&info->task)", &__key, 0) { /* Function call is skipped due to function is undefined */}
3762 -INIT_LIST_HEAD(&(info->task.entry))
{
27 union __anonunion___u_16 __u;
27 __u.__val = list;
27 -__write_once_size((volatile void *)(&(list->next)), (void *)(&(__u.__c)), 8)
{
243 switch (size);
244 assume(!(size == 1));
245 assume(!(size == 2));
246 assume(!(size == 4));
247 assume(size == 8);
247 *((volatile __u64 *)p) = *((__u64 *)res);
247 goto ldv_902;
254 return ;;
}
28 list->prev = list;
29 return ;;
}
3762 info->task.func = &bh_handler;
3763 info->max_frame_size = 4096U;
3764 info->port.close_delay = 125U;
3765 info->port.closing_wait = 7500U;
3766 __init_waitqueue_head(&(info->status_event_wait_q), "&info->status_event_wait_q", &__key___0) { /* Function call is skipped due to function is undefined */}
3767 __init_waitqueue_head(&(info->event_wait_q), "&info->event_wait_q", &__key___1) { /* Function call is skipped due to function is undefined */}
3768 -spinlock_check(&(info->netlock))
{
291 return &(lock->__annonCompField20.rlock);;
}
3768 __raw_spin_lock_init(&(info->netlock.__annonCompField20.rlock), "&(&info->netlock)->rlock", &__key___2) { /* Function call is skipped due to function is undefined */}
3769 __memcpy((void *)(&(info->params)), (const void *)(&default_params), 48UL) { /* Function call is skipped due to function is undefined */}
3770 info->idle_mode = 0U;
3771 info->adapter_num = adapter_num;
3772 info->port_num = port_num;
3775 info->irq_level = pdev->irq;
3776 info->phys_lcr_base = (u32 )(((pdev->resource)[0]).start);
3777 info->phys_sca_base = (u32 )(((pdev->resource)[2]).start);
3778 info->phys_memory_base = (u32 )(((pdev->resource)[3]).start);
3779 info->phys_statctrl_base = (u32 )(((pdev->resource)[4]).start);
3785 info->lcr_offset = (info->phys_lcr_base) & 4095U;
3786 info->phys_lcr_base = (info->phys_lcr_base) & 4294963200U;
3788 info->sca_offset = (info->phys_sca_base) & 4095U;
3789 info->phys_sca_base = (info->phys_sca_base) & 4294963200U;
3791 info->statctrl_offset = (info->phys_statctrl_base) & 4095U;
3792 info->phys_statctrl_base = (info->phys_statctrl_base) & 4294963200U;
3794 info->bus_type = 5U;
3795 info->irq_flags = 128UL;
3797 init_timer_key(&(info->tx_timer), 0U, "((&info->tx_timer))", &__key___3) { /* Function call is skipped due to function is undefined */}
3797 info->tx_timer.function = &tx_timeout;
3797 info->tx_timer.data = (unsigned long)info;
3798 init_timer_key(&(info->status_timer), 0U, "((&info->status_timer))", &__key___4) { /* Function call is skipped due to function is undefined */}
3798 info->status_timer.function = &status_timeout;
3798 info->status_timer.data = (unsigned long)info;
3810 info->misc_ctrl_value = 142492998U;
3818 info->init_error = 4294967295U;
3821 return info;;
}
3832 assume(!(((unsigned long)(port_array[port])) == ((unsigned long)((SLMP_INFO *)0))));
3830 port = port + 1;
3831 ldv_50170:;
3830 assume(port <= 3);
3832 goto ldv_50169;
3831 ldv_50169:;
3831 -alloc_dev(adapter_num, port, pdev)
{
3750 SLMP_INFO *info;
3751 void *tmp;
3752 struct lock_class_key __key;
3753 struct __anonstruct_atomic64_t_7 __constr_expr_0;
3754 struct lock_class_key __key___0;
3755 struct lock_class_key __key___1;
3756 struct lock_class_key __key___2;
3757 struct lock_class_key __key___3;
3758 struct lock_class_key __key___4;
3752 -kzalloc(6296UL, 37748928U)
{
607 void *tmp;
607 -kmalloc(size, flags | 32768U)
{
453 void *tmp___2;
468 tmp___2 = __kmalloc(size, flags) { /* Function call is skipped due to function is undefined */}
468 return tmp___2;;
}
607 return tmp;;
}
3752 info = (SLMP_INFO *)tmp;
3755 assume(!(((unsigned long)info) == ((unsigned long)((SLMP_INFO *)0))));
3759 tty_port_init(&(info->port)) { /* Function call is skipped due to function is undefined */}
3760 info->port.ops = &port_ops;
3761 info->magic = 21505;
3762 __init_work(&(info->task), 0) { /* Function call is skipped due to function is undefined */}
3762 __constr_expr_0.counter = 137438953408L;
3762 info->task.data = __constr_expr_0;
3762 lockdep_init_map(&(info->task.lockdep_map), "(&info->task)", &__key, 0) { /* Function call is skipped due to function is undefined */}
3762 -INIT_LIST_HEAD(&(info->task.entry))
{
27 union __anonunion___u_16 __u;
27 __u.__val = list;
27 -__write_once_size((volatile void *)(&(list->next)), (void *)(&(__u.__c)), 8)
{
243 switch (size);
244 assume(!(size == 1));
245 assume(!(size == 2));
246 assume(!(size == 4));
247 assume(size == 8);
247 *((volatile __u64 *)p) = *((__u64 *)res);
247 goto ldv_902;
254 return ;;
}
28 list->prev = list;
29 return ;;
}
3762 info->task.func = &bh_handler;
3763 info->max_frame_size = 4096U;
3764 info->port.close_delay = 125U;
3765 info->port.closing_wait = 7500U;
3766 __init_waitqueue_head(&(info->status_event_wait_q), "&info->status_event_wait_q", &__key___0) { /* Function call is skipped due to function is undefined */}
3767 __init_waitqueue_head(&(info->event_wait_q), "&info->event_wait_q", &__key___1) { /* Function call is skipped due to function is undefined */}
3768 -spinlock_check(&(info->netlock))
{
291 return &(lock->__annonCompField20.rlock);;
}
3768 __raw_spin_lock_init(&(info->netlock.__annonCompField20.rlock), "&(&info->netlock)->rlock", &__key___2) { /* Function call is skipped due to function is undefined */}
3769 __memcpy((void *)(&(info->params)), (const void *)(&default_params), 48UL) { /* Function call is skipped due to function is undefined */}
3770 info->idle_mode = 0U;
3771 info->adapter_num = adapter_num;
3772 info->port_num = port_num;
3775 info->irq_level = pdev->irq;
3776 info->phys_lcr_base = (u32 )(((pdev->resource)[0]).start);
3777 info->phys_sca_base = (u32 )(((pdev->resource)[2]).start);
3778 info->phys_memory_base = (u32 )(((pdev->resource)[3]).start);
3779 info->phys_statctrl_base = (u32 )(((pdev->resource)[4]).start);
3785 info->lcr_offset = (info->phys_lcr_base) & 4095U;
3786 info->phys_lcr_base = (info->phys_lcr_base) & 4294963200U;
3788 info->sca_offset = (info->phys_sca_base) & 4095U;
3789 info->phys_sca_base = (info->phys_sca_base) & 4294963200U;
3791 info->statctrl_offset = (info->phys_statctrl_base) & 4095U;
3792 info->phys_statctrl_base = (info->phys_statctrl_base) & 4294963200U;
3794 info->bus_type = 5U;
3795 info->irq_flags = 128UL;
3797 init_timer_key(&(info->tx_timer), 0U, "((&info->tx_timer))", &__key___3) { /* Function call is skipped due to function is undefined */}
3797 info->tx_timer.function = &tx_timeout;
3797 info->tx_timer.data = (unsigned long)info;
3798 init_timer_key(&(info->status_timer), 0U, "((&info->status_timer))", &__key___4) { /* Function call is skipped due to function is undefined */}
3798 info->status_timer.function = &status_timeout;
3798 info->status_timer.data = (unsigned long)info;
3810 info->misc_ctrl_value = 142492998U;
3818 info->init_error = 4294967295U;
3821 return info;;
}
3832 assume(!(((unsigned long)(port_array[port])) == ((unsigned long)((SLMP_INFO *)0))));
3830 port = port + 1;
3831 ldv_50170:;
3830 assume(port <= 3);
3832 goto ldv_50169;
3831 ldv_50169:;
3831 -alloc_dev(adapter_num, port, pdev)
{
3750 SLMP_INFO *info;
3751 void *tmp;
3752 struct lock_class_key __key;
3753 struct __anonstruct_atomic64_t_7 __constr_expr_0;
3754 struct lock_class_key __key___0;
3755 struct lock_class_key __key___1;
3756 struct lock_class_key __key___2;
3757 struct lock_class_key __key___3;
3758 struct lock_class_key __key___4;
3752 -kzalloc(6296UL, 37748928U)
{
607 void *tmp;
607 -kmalloc(size, flags | 32768U)
{
453 void *tmp___2;
468 tmp___2 = __kmalloc(size, flags) { /* Function call is skipped due to function is undefined */}
468 return tmp___2;;
}
607 return tmp;;
}
3752 info = (SLMP_INFO *)tmp;
3755 assume(!(((unsigned long)info) == ((unsigned long)((SLMP_INFO *)0))));
3759 tty_port_init(&(info->port)) { /* Function call is skipped due to function is undefined */}
3760 info->port.ops = &port_ops;
3761 info->magic = 21505;
3762 __init_work(&(info->task), 0) { /* Function call is skipped due to function is undefined */}
3762 __constr_expr_0.counter = 137438953408L;
3762 info->task.data = __constr_expr_0;
3762 lockdep_init_map(&(info->task.lockdep_map), "(&info->task)", &__key, 0) { /* Function call is skipped due to function is undefined */}
3762 -INIT_LIST_HEAD(&(info->task.entry))
{
27 union __anonunion___u_16 __u;
27 __u.__val = list;
27 -__write_once_size((volatile void *)(&(list->next)), (void *)(&(__u.__c)), 8)
{
243 switch (size);
244 assume(!(size == 1));
245 assume(!(size == 2));
246 assume(!(size == 4));
247 assume(size == 8);
247 *((volatile __u64 *)p) = *((__u64 *)res);
247 goto ldv_902;
254 return ;;
}
28 list->prev = list;
29 return ;;
}
3762 info->task.func = &bh_handler;
3763 info->max_frame_size = 4096U;
3764 info->port.close_delay = 125U;
3765 info->port.closing_wait = 7500U;
3766 __init_waitqueue_head(&(info->status_event_wait_q), "&info->status_event_wait_q", &__key___0) { /* Function call is skipped due to function is undefined */}
3767 __init_waitqueue_head(&(info->event_wait_q), "&info->event_wait_q", &__key___1) { /* Function call is skipped due to function is undefined */}
3768 -spinlock_check(&(info->netlock))
{
291 return &(lock->__annonCompField20.rlock);;
}
3768 __raw_spin_lock_init(&(info->netlock.__annonCompField20.rlock), "&(&info->netlock)->rlock", &__key___2) { /* Function call is skipped due to function is undefined */}
3769 __memcpy((void *)(&(info->params)), (const void *)(&default_params), 48UL) { /* Function call is skipped due to function is undefined */}
3770 info->idle_mode = 0U;
3771 info->adapter_num = adapter_num;
3772 info->port_num = port_num;
3775 info->irq_level = pdev->irq;
3776 info->phys_lcr_base = (u32 )(((pdev->resource)[0]).start);
3777 info->phys_sca_base = (u32 )(((pdev->resource)[2]).start);
3778 info->phys_memory_base = (u32 )(((pdev->resource)[3]).start);
3779 info->phys_statctrl_base = (u32 )(((pdev->resource)[4]).start);
3785 info->lcr_offset = (info->phys_lcr_base) & 4095U;
3786 info->phys_lcr_base = (info->phys_lcr_base) & 4294963200U;
3788 info->sca_offset = (info->phys_sca_base) & 4095U;
3789 info->phys_sca_base = (info->phys_sca_base) & 4294963200U;
3791 info->statctrl_offset = (info->phys_statctrl_base) & 4095U;
3792 info->phys_statctrl_base = (info->phys_statctrl_base) & 4294963200U;
3794 info->bus_type = 5U;
3795 info->irq_flags = 128UL;
3797 init_timer_key(&(info->tx_timer), 0U, "((&info->tx_timer))", &__key___3) { /* Function call is skipped due to function is undefined */}
3797 info->tx_timer.function = &tx_timeout;
3797 info->tx_timer.data = (unsigned long)info;
3798 init_timer_key(&(info->status_timer), 0U, "((&info->status_timer))", &__key___4) { /* Function call is skipped due to function is undefined */}
3798 info->status_timer.function = &status_timeout;
3798 info->status_timer.data = (unsigned long)info;
3810 info->misc_ctrl_value = 142492998U;
3818 info->init_error = 4294967295U;
3821 return info;;
}
3832 assume(!(((unsigned long)(port_array[port])) == ((unsigned long)((SLMP_INFO *)0))));
3830 port = port + 1;
3831 ldv_50170:;
3830 assume(port <= 3);
3832 goto ldv_50169;
3831 ldv_50169:;
3831 -alloc_dev(adapter_num, port, pdev)
{
3750 SLMP_INFO *info;
3751 void *tmp;
3752 struct lock_class_key __key;
3753 struct __anonstruct_atomic64_t_7 __constr_expr_0;
3754 struct lock_class_key __key___0;
3755 struct lock_class_key __key___1;
3756 struct lock_class_key __key___2;
3757 struct lock_class_key __key___3;
3758 struct lock_class_key __key___4;
3752 -kzalloc(6296UL, 37748928U)
{
607 void *tmp;
607 -kmalloc(size, flags | 32768U)
{
453 void *tmp___2;
468 tmp___2 = __kmalloc(size, flags) { /* Function call is skipped due to function is undefined */}
468 return tmp___2;;
}
607 return tmp;;
}
3752 info = (SLMP_INFO *)tmp;
3755 assume(!(((unsigned long)info) == ((unsigned long)((SLMP_INFO *)0))));
3759 tty_port_init(&(info->port)) { /* Function call is skipped due to function is undefined */}
3760 info->port.ops = &port_ops;
3761 info->magic = 21505;
3762 __init_work(&(info->task), 0) { /* Function call is skipped due to function is undefined */}
3762 __constr_expr_0.counter = 137438953408L;
3762 info->task.data = __constr_expr_0;
3762 lockdep_init_map(&(info->task.lockdep_map), "(&info->task)", &__key, 0) { /* Function call is skipped due to function is undefined */}
3762 -INIT_LIST_HEAD(&(info->task.entry))
{
27 union __anonunion___u_16 __u;
27 __u.__val = list;
27 -__write_once_size((volatile void *)(&(list->next)), (void *)(&(__u.__c)), 8)
{
243 switch (size);
244 assume(!(size == 1));
245 assume(!(size == 2));
246 assume(!(size == 4));
247 assume(size == 8);
247 *((volatile __u64 *)p) = *((__u64 *)res);
247 goto ldv_902;
254 return ;;
}
28 list->prev = list;
29 return ;;
}
3762 info->task.func = &bh_handler;
3763 info->max_frame_size = 4096U;
3764 info->port.close_delay = 125U;
3765 info->port.closing_wait = 7500U;
3766 __init_waitqueue_head(&(info->status_event_wait_q), "&info->status_event_wait_q", &__key___0) { /* Function call is skipped due to function is undefined */}
3767 __init_waitqueue_head(&(info->event_wait_q), "&info->event_wait_q", &__key___1) { /* Function call is skipped due to function is undefined */}
3768 -spinlock_check(&(info->netlock))
{
291 return &(lock->__annonCompField20.rlock);;
}
3768 __raw_spin_lock_init(&(info->netlock.__annonCompField20.rlock), "&(&info->netlock)->rlock", &__key___2) { /* Function call is skipped due to function is undefined */}
3769 __memcpy((void *)(&(info->params)), (const void *)(&default_params), 48UL) { /* Function call is skipped due to function is undefined */}
3770 info->idle_mode = 0U;
3771 info->adapter_num = adapter_num;
3772 info->port_num = port_num;
3775 info->irq_level = pdev->irq;
3776 info->phys_lcr_base = (u32 )(((pdev->resource)[0]).start);
3777 info->phys_sca_base = (u32 )(((pdev->resource)[2]).start);
3778 info->phys_memory_base = (u32 )(((pdev->resource)[3]).start);
3779 info->phys_statctrl_base = (u32 )(((pdev->resource)[4]).start);
3785 info->lcr_offset = (info->phys_lcr_base) & 4095U;
3786 info->phys_lcr_base = (info->phys_lcr_base) & 4294963200U;
3788 info->sca_offset = (info->phys_sca_base) & 4095U;
3789 info->phys_sca_base = (info->phys_sca_base) & 4294963200U;
3791 info->statctrl_offset = (info->phys_statctrl_base) & 4095U;
3792 info->phys_statctrl_base = (info->phys_statctrl_base) & 4294963200U;
3794 info->bus_type = 5U;
3795 info->irq_flags = 128UL;
3797 init_timer_key(&(info->tx_timer), 0U, "((&info->tx_timer))", &__key___3) { /* Function call is skipped due to function is undefined */}
3797 info->tx_timer.function = &tx_timeout;
3797 info->tx_timer.data = (unsigned long)info;
3798 init_timer_key(&(info->status_timer), 0U, "((&info->status_timer))", &__key___4) { /* Function call is skipped due to function is undefined */}
3798 info->status_timer.function = &status_timeout;
3798 info->status_timer.data = (unsigned long)info;
3810 info->misc_ctrl_value = 142492998U;
3818 info->init_error = 4294967295U;
3821 return info;;
}
3832 assume(!(((unsigned long)(port_array[port])) == ((unsigned long)((SLMP_INFO *)0))));
3830 port = port + 1;
3831 ldv_50170:;
3830 assume(!(port <= 3));
3842 port = 0;
3842 goto ldv_50174;
3842 assume(port <= 3);
3844 goto ldv_50173;
3843 ldv_50173:;
3843 __memcpy((void *)(&((port_array[port])->port_array)), (const void *)(&port_array), 32UL) { /* Function call is skipped due to function is undefined */}
3844 -add_device(port_array[port])
{
3699 SLMP_INFO *current_dev;
3699 info->next_device = (struct _synclinkmp_info *)0;
3700 info->line = synclinkmp_device_count;
3701 sprintf((char *)(&(info->device_name)), "ttySLM%dp%d", info->adapter_num, info->port_num) { /* Function call is skipped due to function is undefined */}
3703 assume((info->line) <= 11);
3704 assume(!((maxframe[info->line]) != 0));
3708 synclinkmp_device_count = synclinkmp_device_count + 1;
3710 assume(((unsigned long)synclinkmp_device_list) == ((unsigned long)((SLMP_INFO *)0)));
3711 synclinkmp_device_list = info;
3719 assume(!((info->max_frame_size) <= 4095U));
3721 assume(!((info->max_frame_size) > 65535U));
3724 printk("SyncLink MultiPort %s: Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", (char *)(&(info->device_name)), info->phys_sca_base, info->phys_memory_base, info->phys_statctrl_base, info->phys_lcr_base, info->irq_level, info->max_frame_size) { /* Function call is skipped due to function is undefined */}
3735 -hdlcdev_init(info)
{
1912 int rc;
1913 struct net_device *dev;
1914 hdlc_device *hdlc;
1915 struct hdlc_device *tmp;
1918 dev = alloc_hdlcdev((void *)info) { /* Function call is skipped due to function is undefined */}
1919 assume(!(((unsigned long)dev) == ((unsigned long)((struct net_device *)0))));
1925 unsigned long __CPAchecker_TMP_0 = (unsigned long)(info->phys_sca_base);
1925 dev->mem_start = __CPAchecker_TMP_0;
1926 dev->mem_end = (unsigned long)((info->phys_sca_base) + 511U);
1927 int __CPAchecker_TMP_1 = (int)(info->irq_level);
1927 dev->irq = __CPAchecker_TMP_1;
1930 dev->netdev_ops = &hdlcdev_ops;
1931 dev->watchdog_timeo = 2500;
1932 dev->tx_queue_len = 50UL;
1935 -dev_to_hdlc(dev)
{
74 void *tmp;
74 -netdev_priv((const struct net_device *)dev)
{
1944 return ((void *)dev) + 3072U;;
}
74 return (struct hdlc_device *)tmp;;
}
1935 hdlc = tmp;
1936 hdlc->attach = &hdlcdev_attach;
1937 hdlc->xmit = &hdlcdev_xmit;
1940 -ldv_register_netdev_5(dev)
{
41 int ldv_func_res;
42 int tmp;
43 int tmp___0;
43 tmp = register_netdev(ldv_func_arg1) { /* Function call is skipped due to function is undefined */}
43 ldv_func_res = tmp;
45 -ldv_register_netdev()
{
36 int nondet;
39 assume(!(nondet < 0));
44 assume(nondet >= 0);
46 return 0;;
}
45 return tmp___0;;
}
1941 assume(!(rc != 0));
1947 info->netdev = dev;
1948 return 0;;
}
3736 return ;;
}
3845 -spinlock_check(&((port_array[port])->lock))
{
291 return &(lock->__annonCompField20.rlock);;
}
3845 __raw_spin_lock_init(&((port_array[port])->lock.__annonCompField20.rlock), "&(&port_array[port]->lock)->rlock", &__key) { /* Function call is skipped due to function is undefined */}
3842 port = port + 1;
3843 ldv_50174:;
3842 assume(port <= 3);
3844 goto ldv_50173;
3843 ldv_50173:;
3843 __memcpy((void *)(&((port_array[port])->port_array)), (const void *)(&port_array), 32UL) { /* Function call is skipped due to function is undefined */}
3844 -add_device(port_array[port])
{
3699 SLMP_INFO *current_dev;
3699 info->next_device = (struct _synclinkmp_info *)0;
3700 info->line = synclinkmp_device_count;
3701 sprintf((char *)(&(info->device_name)), "ttySLM%dp%d", info->adapter_num, info->port_num) { /* Function call is skipped due to function is undefined */}
3703 assume((info->line) <= 11);
3704 assume(!((maxframe[info->line]) != 0));
3708 synclinkmp_device_count = synclinkmp_device_count + 1;
3710 assume(!(((unsigned long)synclinkmp_device_list) == ((unsigned long)((SLMP_INFO *)0))));
3713 current_dev = synclinkmp_device_list;
3714 goto ldv_50144;
3714 unsigned long __CPAchecker_TMP_0 = (unsigned long)(current_dev->next_device);
3714 assume(!(__CPAchecker_TMP_0 != ((unsigned long)((struct _synclinkmp_info *)0))));
3716 current_dev->next_device = info;
3719 assume(!((info->max_frame_size) <= 4095U));
3721 assume((info->max_frame_size) > 65535U);
3722 info->max_frame_size = 65535U;
3724 printk("SyncLink MultiPort %s: Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", (char *)(&(info->device_name)), info->phys_sca_base, info->phys_memory_base, info->phys_statctrl_base, info->phys_lcr_base, info->irq_level, info->max_frame_size) { /* Function call is skipped due to function is undefined */}
3735 -hdlcdev_init(info)
{
1912 int rc;
1913 struct net_device *dev;
1914 hdlc_device *hdlc;
1915 struct hdlc_device *tmp;
1918 dev = alloc_hdlcdev((void *)info) { /* Function call is skipped due to function is undefined */}
1919 assume(!(((unsigned long)dev) == ((unsigned long)((struct net_device *)0))));
1925 unsigned long __CPAchecker_TMP_0 = (unsigned long)(info->phys_sca_base);
1925 dev->mem_start = __CPAchecker_TMP_0;
1926 dev->mem_end = (unsigned long)((info->phys_sca_base) + 511U);
1927 int __CPAchecker_TMP_1 = (int)(info->irq_level);
1927 dev->irq = __CPAchecker_TMP_1;
1930 dev->netdev_ops = &hdlcdev_ops;
1931 dev->watchdog_timeo = 2500;
1932 dev->tx_queue_len = 50UL;
1935 -dev_to_hdlc(dev)
{
74 void *tmp;
74 -netdev_priv((const struct net_device *)dev)
{
1944 return ((void *)dev) + 3072U;;
}
74 return (struct hdlc_device *)tmp;;
}
1935 hdlc = tmp;
1936 hdlc->attach = &hdlcdev_attach;
1937 hdlc->xmit = &hdlcdev_xmit;
1940 -ldv_register_netdev_5(dev)
{
41 int ldv_func_res;
42 int tmp;
43 int tmp___0;
43 tmp = register_netdev(ldv_func_arg1) { /* Function call is skipped due to function is undefined */}
43 ldv_func_res = tmp;
45 -ldv_register_netdev()
{
36 int nondet;
39 assume(!(nondet < 0));
44 assume(nondet >= 0);
46 return 0;;
}
45 return tmp___0;;
}
1941 assume(!(rc != 0));
1947 info->netdev = dev;
1948 return 0;;
}
3736 return ;;
}
3845 -spinlock_check(&((port_array[port])->lock))
{
291 return &(lock->__annonCompField20.rlock);;
}
3845 __raw_spin_lock_init(&((port_array[port])->lock.__annonCompField20.rlock), "&(&port_array[port]->lock)->rlock", &__key) { /* Function call is skipped due to function is undefined */}
3842 port = port + 1;
3843 ldv_50174:;
3842 assume(port <= 3);
3844 goto ldv_50173;
3843 ldv_50173:;
3843 __memcpy((void *)(&((port_array[port])->port_array)), (const void *)(&port_array), 32UL) { /* Function call is skipped due to function is undefined */}
3844 -add_device(port_array[port])
{
3699 SLMP_INFO *current_dev;
3699 info->next_device = (struct _synclinkmp_info *)0;
3700 info->line = synclinkmp_device_count;
3701 sprintf((char *)(&(info->device_name)), "ttySLM%dp%d", info->adapter_num, info->port_num) { /* Function call is skipped due to function is undefined */}
3703 assume((info->line) <= 11);
3704 assume(!((maxframe[info->line]) != 0));
3708 synclinkmp_device_count = synclinkmp_device_count + 1;
3710 assume(!(((unsigned long)synclinkmp_device_list) == ((unsigned long)((SLMP_INFO *)0))));
3713 current_dev = synclinkmp_device_list;
3714 goto ldv_50144;
3714 unsigned long __CPAchecker_TMP_0 = (unsigned long)(current_dev->next_device);
3714 assume(!(__CPAchecker_TMP_0 != ((unsigned long)((struct _synclinkmp_info *)0))));
3716 current_dev->next_device = info;
3719 assume(!((info->max_frame_size) <= 4095U));
3721 assume((info->max_frame_size) > 65535U);
3722 info->max_frame_size = 65535U;
3724 printk("SyncLink MultiPort %s: Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", (char *)(&(info->device_name)), info->phys_sca_base, info->phys_memory_base, info->phys_statctrl_base, info->phys_lcr_base, info->irq_level, info->max_frame_size) { /* Function call is skipped due to function is undefined */}
3735 -hdlcdev_init(info)
{
1912 int rc;
1913 struct net_device *dev;
1914 hdlc_device *hdlc;
1915 struct hdlc_device *tmp;
1918 dev = alloc_hdlcdev((void *)info) { /* Function call is skipped due to function is undefined */}
1919 assume(!(((unsigned long)dev) == ((unsigned long)((struct net_device *)0))));
1925 unsigned long __CPAchecker_TMP_0 = (unsigned long)(info->phys_sca_base);
1925 dev->mem_start = __CPAchecker_TMP_0;
1926 dev->mem_end = (unsigned long)((info->phys_sca_base) + 511U);
1927 int __CPAchecker_TMP_1 = (int)(info->irq_level);
1927 dev->irq = __CPAchecker_TMP_1;
1930 dev->netdev_ops = &hdlcdev_ops;
1931 dev->watchdog_timeo = 2500;
1932 dev->tx_queue_len = 50UL;
1935 -dev_to_hdlc(dev)
{
74 void *tmp;
74 -netdev_priv((const struct net_device *)dev)
{
1944 return ((void *)dev) + 3072U;;
}
74 return (struct hdlc_device *)tmp;;
}
1935 hdlc = tmp;
1936 hdlc->attach = &hdlcdev_attach;
1937 hdlc->xmit = &hdlcdev_xmit;
1940 -ldv_register_netdev_5(dev)
{
41 int ldv_func_res;
42 int tmp;
43 int tmp___0;
43 tmp = register_netdev(ldv_func_arg1) { /* Function call is skipped due to function is undefined */}
43 ldv_func_res = tmp;
45 -ldv_register_netdev()
{
36 int nondet;
39 assume(!(nondet < 0));
44 assume(nondet >= 0);
46 return 0;;
}
45 return tmp___0;;
}
1941 assume(!(rc != 0));
1947 info->netdev = dev;
1948 return 0;;
}
3736 return ;;
}
3845 -spinlock_check(&((port_array[port])->lock))
{
291 return &(lock->__annonCompField20.rlock);;
}
3845 __raw_spin_lock_init(&((port_array[port])->lock.__annonCompField20.rlock), "&(&port_array[port]->lock)->rlock", &__key) { /* Function call is skipped due to function is undefined */}
3842 port = port + 1;
3843 ldv_50174:;
3842 assume(port <= 3);
3844 goto ldv_50173;
3843 ldv_50173:;
3843 __memcpy((void *)(&((port_array[port])->port_array)), (const void *)(&port_array), 32UL) { /* Function call is skipped due to function is undefined */}
3844 -add_device(port_array[port])
{
3699 SLMP_INFO *current_dev;
3699 info->next_device = (struct _synclinkmp_info *)0;
3700 info->line = synclinkmp_device_count;
3701 sprintf((char *)(&(info->device_name)), "ttySLM%dp%d", info->adapter_num, info->port_num) { /* Function call is skipped due to function is undefined */}
3703 assume((info->line) <= 11);
3704 assume((maxframe[info->line]) != 0);
3705 info->max_frame_size = (u32 )(maxframe[info->line]);
3708 synclinkmp_device_count = synclinkmp_device_count + 1;
3710 assume(!(((unsigned long)synclinkmp_device_list) == ((unsigned long)((SLMP_INFO *)0))));
3713 current_dev = synclinkmp_device_list;
3714 goto ldv_50144;
3714 unsigned long __CPAchecker_TMP_0 = (unsigned long)(current_dev->next_device);
3714 assume(!(__CPAchecker_TMP_0 != ((unsigned long)((struct _synclinkmp_info *)0))));
3716 current_dev->next_device = info;
3719 assume(!((info->max_frame_size) <= 4095U));
3721 assume((info->max_frame_size) > 65535U);
3722 info->max_frame_size = 65535U;
3724 printk("SyncLink MultiPort %s: Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", (char *)(&(info->device_name)), info->phys_sca_base, info->phys_memory_base, info->phys_statctrl_base, info->phys_lcr_base, info->irq_level, info->max_frame_size) { /* Function call is skipped due to function is undefined */}
3735 -hdlcdev_init(info)
{
1912 int rc;
1913 struct net_device *dev;
1914 hdlc_device *hdlc;
1915 struct hdlc_device *tmp;
1918 dev = alloc_hdlcdev((void *)info) { /* Function call is skipped due to function is undefined */}
1919 assume(!(((unsigned long)dev) == ((unsigned long)((struct net_device *)0))));
1925 unsigned long __CPAchecker_TMP_0 = (unsigned long)(info->phys_sca_base);
1925 dev->mem_start = __CPAchecker_TMP_0;
1926 dev->mem_end = (unsigned long)((info->phys_sca_base) + 511U);
1927 int __CPAchecker_TMP_1 = (int)(info->irq_level);
1927 dev->irq = __CPAchecker_TMP_1;
1930 dev->netdev_ops = &hdlcdev_ops;
1931 dev->watchdog_timeo = 2500;
1932 dev->tx_queue_len = 50UL;
1935 -dev_to_hdlc(dev)
{
74 void *tmp;
74 -netdev_priv((const struct net_device *)dev)
{
1944 return ((void *)dev) + 3072U;;
}
74 return (struct hdlc_device *)tmp;;
}
1935 hdlc = tmp;
1936 hdlc->attach = &hdlcdev_attach;
1937 hdlc->xmit = &hdlcdev_xmit;
1940 -ldv_register_netdev_5(dev)
{
41 int ldv_func_res;
42 int tmp;
43 int tmp___0;
43 tmp = register_netdev(ldv_func_arg1) { /* Function call is skipped due to function is undefined */}
43 ldv_func_res = tmp;
45 -ldv_register_netdev()
{
36 int nondet;
39 assume(nondet < 0);
41 ldv_probe_state = 1;
43 return nondet;;
}
45 return tmp___0;;
}
1941 assume(rc != 0);
1942 printk("\f%s:unable to register hdlc device\n", (char *)"/home/ldvuser/ref_launch/work/current--X--drivers--X--defaultlinux-4.5-rc1.tar.xz--X--134_1a--X--cpachecker/linux-4.5-rc1.tar.xz/csd_deg_dscv/8588/dscv_tempdir/dscv/ri/134_1a/drivers/tty/synclinkmp.c") { /* Function call is skipped due to function is undefined */}
1943 free_netdev(dev) { /* Function call is skipped due to function is undefined */}
1944 return rc;;
}
3736 return ;;
}
3845 -spinlock_check(&((port_array[port])->lock))
{
291 return &(lock->__annonCompField20.rlock);;
}
3845 __raw_spin_lock_init(&((port_array[port])->lock.__annonCompField20.rlock), "&(&port_array[port]->lock)->rlock", &__key) { /* Function call is skipped due to function is undefined */}
3842 port = port + 1;
3843 ldv_50174:;
3842 assume(!(port <= 3));
3849 -claim_resources(port_array[0])
{
3554 struct resource *tmp;
3555 struct resource *tmp___0;
3556 struct resource *tmp___1;
3557 struct resource *tmp___2;
3558 void *tmp___3;
3559 void *tmp___4;
3560 void *tmp___5;
3561 void *tmp___6;
3562 _Bool tmp___7;
3563 int tmp___8;
3554 resource_size_t __CPAchecker_TMP_0 = (resource_size_t )(info->phys_memory_base);
3554 tmp = __request_region(&iomem_resource, __CPAchecker_TMP_0, 262144ULL, "synclinkmp", 0) { /* Function call is skipped due to function is undefined */}
3554 assume(!(((unsigned long)tmp) == ((unsigned long)((struct resource *)0))));
3561 info->shared_mem_requested = 1;
3563 tmp___0 = __request_region(&iomem_resource, (resource_size_t )((info->phys_lcr_base) + (info->lcr_offset)), 128ULL, "synclinkmp", 0) { /* Function call is skipped due to function is undefined */}
3563 assume(((unsigned long)tmp___0) == ((unsigned long)((struct resource *)0)));
3564 printk("%s(%d):%s lcr mem addr conflict, Addr=%08X\n", (char *)"/home/ldvuser/ref_launch/work/current--X--drivers--X--defaultlinux-4.5-rc1.tar.xz--X--134_1a--X--cpachecker/linux-4.5-rc1.tar.xz/csd_deg_dscv/8588/dscv_tempdir/dscv/ri/134_1a/drivers/tty/synclinkmp.c", 3565, (char *)(&(info->device_name)), info->phys_lcr_base) { /* Function call is skipped due to function is undefined */}
3566 info->init_error = 2U;
3567 goto errout;
3635 errout:;
3637 -release_resources(info)
{
3643 assume(!(debug_level > 2));
3647 int __CPAchecker_TMP_0 = (int)(info->irq_requested);
3647 assume(!(__CPAchecker_TMP_0 == 0));
3648 free_irq(info->irq_level, (void *)info) { /* Function call is skipped due to function is undefined */}
3649 info->irq_requested = 0;
3652 assume((info->shared_mem_requested) != 0);
3653 resource_size_t __CPAchecker_TMP_1 = (resource_size_t )(info->phys_memory_base);
3653 __release_region(&iomem_resource, __CPAchecker_TMP_1, 262144ULL) { /* Function call is skipped due to function is undefined */}
3654 info->shared_mem_requested = 0;
3656 assume(!((info->lcr_mem_requested) != 0));
3660 int __CPAchecker_TMP_2 = (int)(info->sca_base_requested);
3660 assume(!(__CPAchecker_TMP_2 == 0));
3661 __release_region(&iomem_resource, (resource_size_t )((info->phys_sca_base) + (info->sca_offset)), 512ULL) { /* Function call is skipped due to function is undefined */}
3662 info->sca_base_requested = 0;
3664 int __CPAchecker_TMP_3 = (int)(info->sca_statctrl_requested);
3664 assume(!(__CPAchecker_TMP_3 == 0));
3665 __release_region(&iomem_resource, (resource_size_t )((info->phys_statctrl_base) + (info->statctrl_offset)), 16ULL) { /* Function call is skipped due to function is undefined */}
3666 info->sca_statctrl_requested = 0;
3669 unsigned long __CPAchecker_TMP_4 = (unsigned long)(info->memory_base);
3669 assume(__CPAchecker_TMP_4 != ((unsigned long)((unsigned char *)0U)));
3670 volatile void *__CPAchecker_TMP_5 = (volatile void *)(info->memory_base);
3670 iounmap(__CPAchecker_TMP_5) { /* Function call is skipped due to function is undefined */}
3671 info->memory_base = (unsigned char *)0U;
3674 unsigned long __CPAchecker_TMP_6 = (unsigned long)(info->sca_base);
3674 assume(!(__CPAchecker_TMP_6 != ((unsigned long)((unsigned char *)0U))));
3679 unsigned long __CPAchecker_TMP_8 = (unsigned long)(info->statctrl_base);
3679 assume(!(__CPAchecker_TMP_8 != ((unsigned long)((unsigned char *)0U))));
3684 unsigned long __CPAchecker_TMP_10 = (unsigned long)(info->lcr_base);
3684 assume(!(__CPAchecker_TMP_10 != ((unsigned long)((unsigned char *)0U))));
3689 assume(!(debug_level > 2));
3692 return ;;
}
3638 return -19;;
}
3849 assume(!(tmp___0 == 0));
3879 return ;;
}
5594 return 0;;
}
12937 ldv_check_return_value(res_synclinkmp_init_one_121) { /* Function call is skipped due to function is undefined */}
12938 -ldv_check_return_value_probe(res_synclinkmp_init_one_121)
{
53 assume(ldv_probe_state == 1);
54 assume(retval == 0);
54 -ldv_error()
{
15 LDV_ERROR:;
}
}
}
Source code
1 2 /* 3 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $ 4 * 5 * Device driver for Microgate SyncLink Multiport 6 * high speed multiprotocol serial adapter. 7 * 8 * written by Paul Fulghum for Microgate Corporation 9 * paulkf@microgate.com 10 * 11 * Microgate and SyncLink are trademarks of Microgate Corporation 12 * 13 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds 14 * This code is released under the GNU General Public License (GPL) 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 26 * OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 30 #if defined(__i386__) 31 # define BREAKPOINT() asm(" int $3"); 32 #else 33 # define BREAKPOINT() { } 34 #endif 35 36 #define MAX_DEVICES 12 37 38 #include <linux/module.h> 39 #include <linux/errno.h> 40 #include <linux/signal.h> 41 #include <linux/sched.h> 42 #include <linux/timer.h> 43 #include <linux/interrupt.h> 44 #include <linux/pci.h> 45 #include <linux/tty.h> 46 #include <linux/tty_flip.h> 47 #include <linux/serial.h> 48 #include <linux/major.h> 49 #include <linux/string.h> 50 #include <linux/fcntl.h> 51 #include <linux/ptrace.h> 52 #include <linux/ioport.h> 53 #include <linux/mm.h> 54 #include <linux/seq_file.h> 55 #include <linux/slab.h> 56 #include <linux/netdevice.h> 57 #include <linux/vmalloc.h> 58 #include <linux/init.h> 59 #include <linux/delay.h> 60 #include <linux/ioctl.h> 61 62 #include <asm/io.h> 63 #include <asm/irq.h> 64 #include <asm/dma.h> 65 #include <linux/bitops.h> 66 #include <asm/types.h> 67 #include <linux/termios.h> 68 #include <linux/workqueue.h> 69 #include <linux/hdlc.h> 70 #include <linux/synclink.h> 71 72 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 73 #define SYNCLINK_GENERIC_HDLC 1 74 #else 75 #define SYNCLINK_GENERIC_HDLC 0 76 #endif 77 78 #define GET_USER(error,value,addr) error = get_user(value,addr) 79 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 80 #define PUT_USER(error,value,addr) error = put_user(value,addr) 81 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 82 83 #include <asm/uaccess.h> 84 85 static MGSL_PARAMS default_params = { 86 MGSL_MODE_HDLC, /* unsigned long mode */ 87 0, /* unsigned char loopback; */ 88 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ 89 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ 90 0, /* unsigned long clock_speed; */ 91 0xff, /* unsigned char addr_filter; */ 92 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ 93 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ 94 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ 95 9600, /* unsigned long data_rate; */ 96 8, /* unsigned char data_bits; */ 97 1, /* unsigned char stop_bits; */ 98 ASYNC_PARITY_NONE /* unsigned char parity; */ 99 }; 100 101 /* size in bytes of DMA data buffers */ 102 #define SCABUFSIZE 1024 103 #define SCA_MEM_SIZE 0x40000 104 #define SCA_BASE_SIZE 512 105 #define SCA_REG_SIZE 16 106 #define SCA_MAX_PORTS 4 107 #define SCAMAXDESC 128 108 109 #define BUFFERLISTSIZE 4096 110 111 /* SCA-I style DMA buffer descriptor */ 112 typedef struct _SCADESC 113 { 114 u16 next; /* lower l6 bits of next descriptor addr */ 115 u16 buf_ptr; /* lower 16 bits of buffer addr */ 116 u8 buf_base; /* upper 8 bits of buffer addr */ 117 u8 pad1; 118 u16 length; /* length of buffer */ 119 u8 status; /* status of buffer */ 120 u8 pad2; 121 } SCADESC, *PSCADESC; 122 123 typedef struct _SCADESC_EX 124 { 125 /* device driver bookkeeping section */ 126 char *virt_addr; /* virtual address of data buffer */ 127 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */ 128 } SCADESC_EX, *PSCADESC_EX; 129 130 /* The queue of BH actions to be performed */ 131 132 #define BH_RECEIVE 1 133 #define BH_TRANSMIT 2 134 #define BH_STATUS 4 135 136 #define IO_PIN_SHUTDOWN_LIMIT 100 137 138 struct _input_signal_events { 139 int ri_up; 140 int ri_down; 141 int dsr_up; 142 int dsr_down; 143 int dcd_up; 144 int dcd_down; 145 int cts_up; 146 int cts_down; 147 }; 148 149 /* 150 * Device instance data structure 151 */ 152 typedef struct _synclinkmp_info { 153 void *if_ptr; /* General purpose pointer (used by SPPP) */ 154 int magic; 155 struct tty_port port; 156 int line; 157 unsigned short close_delay; 158 unsigned short closing_wait; /* time to wait before closing */ 159 160 struct mgsl_icount icount; 161 162 int timeout; 163 int x_char; /* xon/xoff character */ 164 u16 read_status_mask1; /* break detection (SR1 indications) */ 165 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */ 166 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */ 167 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */ 168 unsigned char *tx_buf; 169 int tx_put; 170 int tx_get; 171 int tx_count; 172 173 wait_queue_head_t status_event_wait_q; 174 wait_queue_head_t event_wait_q; 175 struct timer_list tx_timer; /* HDLC transmit timeout timer */ 176 struct _synclinkmp_info *next_device; /* device list link */ 177 struct timer_list status_timer; /* input signal status check timer */ 178 179 spinlock_t lock; /* spinlock for synchronizing with ISR */ 180 struct work_struct task; /* task structure for scheduling bh */ 181 182 u32 max_frame_size; /* as set by device config */ 183 184 u32 pending_bh; 185 186 bool bh_running; /* Protection from multiple */ 187 int isr_overflow; 188 bool bh_requested; 189 190 int dcd_chkcount; /* check counts to prevent */ 191 int cts_chkcount; /* too many IRQs if a signal */ 192 int dsr_chkcount; /* is floating */ 193 int ri_chkcount; 194 195 char *buffer_list; /* virtual address of Rx & Tx buffer lists */ 196 unsigned long buffer_list_phys; 197 198 unsigned int rx_buf_count; /* count of total allocated Rx buffers */ 199 SCADESC *rx_buf_list; /* list of receive buffer entries */ 200 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */ 201 unsigned int current_rx_buf; 202 203 unsigned int tx_buf_count; /* count of total allocated Tx buffers */ 204 SCADESC *tx_buf_list; /* list of transmit buffer entries */ 205 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */ 206 unsigned int last_tx_buf; 207 208 unsigned char *tmp_rx_buf; 209 unsigned int tmp_rx_buf_count; 210 211 bool rx_enabled; 212 bool rx_overflow; 213 214 bool tx_enabled; 215 bool tx_active; 216 u32 idle_mode; 217 218 unsigned char ie0_value; 219 unsigned char ie1_value; 220 unsigned char ie2_value; 221 unsigned char ctrlreg_value; 222 unsigned char old_signals; 223 224 char device_name[25]; /* device instance name */ 225 226 int port_count; 227 int adapter_num; 228 int port_num; 229 230 struct _synclinkmp_info *port_array[SCA_MAX_PORTS]; 231 232 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */ 233 234 unsigned int irq_level; /* interrupt level */ 235 unsigned long irq_flags; 236 bool irq_requested; /* true if IRQ requested */ 237 238 MGSL_PARAMS params; /* communications parameters */ 239 240 unsigned char serial_signals; /* current serial signal states */ 241 242 bool irq_occurred; /* for diagnostics use */ 243 unsigned int init_error; /* Initialization startup error */ 244 245 u32 last_mem_alloc; 246 unsigned char* memory_base; /* shared memory address (PCI only) */ 247 u32 phys_memory_base; 248 int shared_mem_requested; 249 250 unsigned char* sca_base; /* HD64570 SCA Memory address */ 251 u32 phys_sca_base; 252 u32 sca_offset; 253 bool sca_base_requested; 254 255 unsigned char* lcr_base; /* local config registers (PCI only) */ 256 u32 phys_lcr_base; 257 u32 lcr_offset; 258 int lcr_mem_requested; 259 260 unsigned char* statctrl_base; /* status/control register memory */ 261 u32 phys_statctrl_base; 262 u32 statctrl_offset; 263 bool sca_statctrl_requested; 264 265 u32 misc_ctrl_value; 266 char *flag_buf; 267 bool drop_rts_on_tx_done; 268 269 struct _input_signal_events input_signal_events; 270 271 /* SPPP/Cisco HDLC device parts */ 272 int netcount; 273 spinlock_t netlock; 274 275 #if SYNCLINK_GENERIC_HDLC 276 struct net_device *netdev; 277 #endif 278 279 } SLMP_INFO; 280 281 #define MGSL_MAGIC 0x5401 282 283 /* 284 * define serial signal status change macros 285 */ 286 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */ 287 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */ 288 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */ 289 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */ 290 291 /* Common Register macros */ 292 #define LPR 0x00 293 #define PABR0 0x02 294 #define PABR1 0x03 295 #define WCRL 0x04 296 #define WCRM 0x05 297 #define WCRH 0x06 298 #define DPCR 0x08 299 #define DMER 0x09 300 #define ISR0 0x10 301 #define ISR1 0x11 302 #define ISR2 0x12 303 #define IER0 0x14 304 #define IER1 0x15 305 #define IER2 0x16 306 #define ITCR 0x18 307 #define INTVR 0x1a 308 #define IMVR 0x1c 309 310 /* MSCI Register macros */ 311 #define TRB 0x20 312 #define TRBL 0x20 313 #define TRBH 0x21 314 #define SR0 0x22 315 #define SR1 0x23 316 #define SR2 0x24 317 #define SR3 0x25 318 #define FST 0x26 319 #define IE0 0x28 320 #define IE1 0x29 321 #define IE2 0x2a 322 #define FIE 0x2b 323 #define CMD 0x2c 324 #define MD0 0x2e 325 #define MD1 0x2f 326 #define MD2 0x30 327 #define CTL 0x31 328 #define SA0 0x32 329 #define SA1 0x33 330 #define IDL 0x34 331 #define TMC 0x35 332 #define RXS 0x36 333 #define TXS 0x37 334 #define TRC0 0x38 335 #define TRC1 0x39 336 #define RRC 0x3a 337 #define CST0 0x3c 338 #define CST1 0x3d 339 340 /* Timer Register Macros */ 341 #define TCNT 0x60 342 #define TCNTL 0x60 343 #define TCNTH 0x61 344 #define TCONR 0x62 345 #define TCONRL 0x62 346 #define TCONRH 0x63 347 #define TMCS 0x64 348 #define TEPR 0x65 349 350 /* DMA Controller Register macros */ 351 #define DARL 0x80 352 #define DARH 0x81 353 #define DARB 0x82 354 #define BAR 0x80 355 #define BARL 0x80 356 #define BARH 0x81 357 #define BARB 0x82 358 #define SAR 0x84 359 #define SARL 0x84 360 #define SARH 0x85 361 #define SARB 0x86 362 #define CPB 0x86 363 #define CDA 0x88 364 #define CDAL 0x88 365 #define CDAH 0x89 366 #define EDA 0x8a 367 #define EDAL 0x8a 368 #define EDAH 0x8b 369 #define BFL 0x8c 370 #define BFLL 0x8c 371 #define BFLH 0x8d 372 #define BCR 0x8e 373 #define BCRL 0x8e 374 #define BCRH 0x8f 375 #define DSR 0x90 376 #define DMR 0x91 377 #define FCT 0x93 378 #define DIR 0x94 379 #define DCMD 0x95 380 381 /* combine with timer or DMA register address */ 382 #define TIMER0 0x00 383 #define TIMER1 0x08 384 #define TIMER2 0x10 385 #define TIMER3 0x18 386 #define RXDMA 0x00 387 #define TXDMA 0x20 388 389 /* SCA Command Codes */ 390 #define NOOP 0x00 391 #define TXRESET 0x01 392 #define TXENABLE 0x02 393 #define TXDISABLE 0x03 394 #define TXCRCINIT 0x04 395 #define TXCRCEXCL 0x05 396 #define TXEOM 0x06 397 #define TXABORT 0x07 398 #define MPON 0x08 399 #define TXBUFCLR 0x09 400 #define RXRESET 0x11 401 #define RXENABLE 0x12 402 #define RXDISABLE 0x13 403 #define RXCRCINIT 0x14 404 #define RXREJECT 0x15 405 #define SEARCHMP 0x16 406 #define RXCRCEXCL 0x17 407 #define RXCRCCALC 0x18 408 #define CHRESET 0x21 409 #define HUNT 0x31 410 411 /* DMA command codes */ 412 #define SWABORT 0x01 413 #define FEICLEAR 0x02 414 415 /* IE0 */ 416 #define TXINTE BIT7 417 #define RXINTE BIT6 418 #define TXRDYE BIT1 419 #define RXRDYE BIT0 420 421 /* IE1 & SR1 */ 422 #define UDRN BIT7 423 #define IDLE BIT6 424 #define SYNCD BIT4 425 #define FLGD BIT4 426 #define CCTS BIT3 427 #define CDCD BIT2 428 #define BRKD BIT1 429 #define ABTD BIT1 430 #define GAPD BIT1 431 #define BRKE BIT0 432 #define IDLD BIT0 433 434 /* IE2 & SR2 */ 435 #define EOM BIT7 436 #define PMP BIT6 437 #define SHRT BIT6 438 #define PE BIT5 439 #define ABT BIT5 440 #define FRME BIT4 441 #define RBIT BIT4 442 #define OVRN BIT3 443 #define CRCE BIT2 444 445 446 /* 447 * Global linked list of SyncLink devices 448 */ 449 static SLMP_INFO *synclinkmp_device_list = NULL; 450 static int synclinkmp_adapter_count = -1; 451 static int synclinkmp_device_count = 0; 452 453 /* 454 * Set this param to non-zero to load eax with the 455 * .text section address and breakpoint on module load. 456 * This is useful for use with gdb and add-symbol-file command. 457 */ 458 static bool break_on_load = 0; 459 460 /* 461 * Driver major number, defaults to zero to get auto 462 * assigned major number. May be forced as module parameter. 463 */ 464 static int ttymajor = 0; 465 466 /* 467 * Array of user specified options for ISA adapters. 468 */ 469 static int debug_level = 0; 470 static int maxframe[MAX_DEVICES] = {0,}; 471 472 module_param(break_on_load, bool, 0); 473 module_param(ttymajor, int, 0); 474 module_param(debug_level, int, 0); 475 module_param_array(maxframe, int, NULL, 0); 476 477 static char *driver_name = "SyncLink MultiPort driver"; 478 static char *driver_version = "$Revision: 4.38 $"; 479 480 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent); 481 static void synclinkmp_remove_one(struct pci_dev *dev); 482 483 static struct pci_device_id synclinkmp_pci_tbl[] = { 484 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, }, 485 { 0, }, /* terminate list */ 486 }; 487 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl); 488 489 MODULE_LICENSE("GPL"); 490 491 static struct pci_driver synclinkmp_pci_driver = { 492 .name = "synclinkmp", 493 .id_table = synclinkmp_pci_tbl, 494 .probe = synclinkmp_init_one, 495 .remove = synclinkmp_remove_one, 496 }; 497 498 499 static struct tty_driver *serial_driver; 500 501 /* number of characters left in xmit buffer before we ask for more */ 502 #define WAKEUP_CHARS 256 503 504 505 /* tty callbacks */ 506 507 static int open(struct tty_struct *tty, struct file * filp); 508 static void close(struct tty_struct *tty, struct file * filp); 509 static void hangup(struct tty_struct *tty); 510 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); 511 512 static int write(struct tty_struct *tty, const unsigned char *buf, int count); 513 static int put_char(struct tty_struct *tty, unsigned char ch); 514 static void send_xchar(struct tty_struct *tty, char ch); 515 static void wait_until_sent(struct tty_struct *tty, int timeout); 516 static int write_room(struct tty_struct *tty); 517 static void flush_chars(struct tty_struct *tty); 518 static void flush_buffer(struct tty_struct *tty); 519 static void tx_hold(struct tty_struct *tty); 520 static void tx_release(struct tty_struct *tty); 521 522 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg); 523 static int chars_in_buffer(struct tty_struct *tty); 524 static void throttle(struct tty_struct * tty); 525 static void unthrottle(struct tty_struct * tty); 526 static int set_break(struct tty_struct *tty, int break_state); 527 528 #if SYNCLINK_GENERIC_HDLC 529 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 530 static void hdlcdev_tx_done(SLMP_INFO *info); 531 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size); 532 static int hdlcdev_init(SLMP_INFO *info); 533 static void hdlcdev_exit(SLMP_INFO *info); 534 #endif 535 536 /* ioctl handlers */ 537 538 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount); 539 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params); 540 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params); 541 static int get_txidle(SLMP_INFO *info, int __user *idle_mode); 542 static int set_txidle(SLMP_INFO *info, int idle_mode); 543 static int tx_enable(SLMP_INFO *info, int enable); 544 static int tx_abort(SLMP_INFO *info); 545 static int rx_enable(SLMP_INFO *info, int enable); 546 static int modem_input_wait(SLMP_INFO *info,int arg); 547 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr); 548 static int tiocmget(struct tty_struct *tty); 549 static int tiocmset(struct tty_struct *tty, 550 unsigned int set, unsigned int clear); 551 static int set_break(struct tty_struct *tty, int break_state); 552 553 static void add_device(SLMP_INFO *info); 554 static void device_init(int adapter_num, struct pci_dev *pdev); 555 static int claim_resources(SLMP_INFO *info); 556 static void release_resources(SLMP_INFO *info); 557 558 static int startup(SLMP_INFO *info); 559 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info); 560 static int carrier_raised(struct tty_port *port); 561 static void shutdown(SLMP_INFO *info); 562 static void program_hw(SLMP_INFO *info); 563 static void change_params(SLMP_INFO *info); 564 565 static bool init_adapter(SLMP_INFO *info); 566 static bool register_test(SLMP_INFO *info); 567 static bool irq_test(SLMP_INFO *info); 568 static bool loopback_test(SLMP_INFO *info); 569 static int adapter_test(SLMP_INFO *info); 570 static bool memory_test(SLMP_INFO *info); 571 572 static void reset_adapter(SLMP_INFO *info); 573 static void reset_port(SLMP_INFO *info); 574 static void async_mode(SLMP_INFO *info); 575 static void hdlc_mode(SLMP_INFO *info); 576 577 static void rx_stop(SLMP_INFO *info); 578 static void rx_start(SLMP_INFO *info); 579 static void rx_reset_buffers(SLMP_INFO *info); 580 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last); 581 static bool rx_get_frame(SLMP_INFO *info); 582 583 static void tx_start(SLMP_INFO *info); 584 static void tx_stop(SLMP_INFO *info); 585 static void tx_load_fifo(SLMP_INFO *info); 586 static void tx_set_idle(SLMP_INFO *info); 587 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count); 588 589 static void get_signals(SLMP_INFO *info); 590 static void set_signals(SLMP_INFO *info); 591 static void enable_loopback(SLMP_INFO *info, int enable); 592 static void set_rate(SLMP_INFO *info, u32 data_rate); 593 594 static int bh_action(SLMP_INFO *info); 595 static void bh_handler(struct work_struct *work); 596 static void bh_receive(SLMP_INFO *info); 597 static void bh_transmit(SLMP_INFO *info); 598 static void bh_status(SLMP_INFO *info); 599 static void isr_timer(SLMP_INFO *info); 600 static void isr_rxint(SLMP_INFO *info); 601 static void isr_rxrdy(SLMP_INFO *info); 602 static void isr_txint(SLMP_INFO *info); 603 static void isr_txrdy(SLMP_INFO *info); 604 static void isr_rxdmaok(SLMP_INFO *info); 605 static void isr_rxdmaerror(SLMP_INFO *info); 606 static void isr_txdmaok(SLMP_INFO *info); 607 static void isr_txdmaerror(SLMP_INFO *info); 608 static void isr_io_pin(SLMP_INFO *info, u16 status); 609 610 static int alloc_dma_bufs(SLMP_INFO *info); 611 static void free_dma_bufs(SLMP_INFO *info); 612 static int alloc_buf_list(SLMP_INFO *info); 613 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count); 614 static int alloc_tmp_rx_buf(SLMP_INFO *info); 615 static void free_tmp_rx_buf(SLMP_INFO *info); 616 617 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count); 618 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit); 619 static void tx_timeout(unsigned long context); 620 static void status_timeout(unsigned long context); 621 622 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr); 623 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val); 624 static u16 read_reg16(SLMP_INFO *info, unsigned char addr); 625 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val); 626 static unsigned char read_status_reg(SLMP_INFO * info); 627 static void write_control_reg(SLMP_INFO * info); 628 629 630 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes 631 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes 632 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes 633 634 static u32 misc_ctrl_value = 0x007e4040; 635 static u32 lcr1_brdr_value = 0x00800028; 636 637 static u32 read_ahead_count = 8; 638 639 /* DPCR, DMA Priority Control 640 * 641 * 07..05 Not used, must be 0 642 * 04 BRC, bus release condition: 0=all transfers complete 643 * 1=release after 1 xfer on all channels 644 * 03 CCC, channel change condition: 0=every cycle 645 * 1=after each channel completes all xfers 646 * 02..00 PR<2..0>, priority 100=round robin 647 * 648 * 00000100 = 0x00 649 */ 650 static unsigned char dma_priority = 0x04; 651 652 // Number of bytes that can be written to shared RAM 653 // in a single write operation 654 static u32 sca_pci_load_interval = 64; 655 656 /* 657 * 1st function defined in .text section. Calling this function in 658 * init_module() followed by a breakpoint allows a remote debugger 659 * (gdb) to get the .text address for the add-symbol-file command. 660 * This allows remote debugging of dynamically loadable modules. 661 */ 662 static void* synclinkmp_get_text_ptr(void); 663 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;} 664 665 static inline int sanity_check(SLMP_INFO *info, 666 char *name, const char *routine) 667 { 668 #ifdef SANITY_CHECK 669 static const char *badmagic = 670 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n"; 671 static const char *badinfo = 672 "Warning: null synclinkmp_struct for (%s) in %s\n"; 673 674 if (!info) { 675 printk(badinfo, name, routine); 676 return 1; 677 } 678 if (info->magic != MGSL_MAGIC) { 679 printk(badmagic, name, routine); 680 return 1; 681 } 682 #else 683 if (!info) 684 return 1; 685 #endif 686 return 0; 687 } 688 689 /** 690 * line discipline callback wrappers 691 * 692 * The wrappers maintain line discipline references 693 * while calling into the line discipline. 694 * 695 * ldisc_receive_buf - pass receive data to line discipline 696 */ 697 698 static void ldisc_receive_buf(struct tty_struct *tty, 699 const __u8 *data, char *flags, int count) 700 { 701 struct tty_ldisc *ld; 702 if (!tty) 703 return; 704 ld = tty_ldisc_ref(tty); 705 if (ld) { 706 if (ld->ops->receive_buf) 707 ld->ops->receive_buf(tty, data, flags, count); 708 tty_ldisc_deref(ld); 709 } 710 } 711 712 /* tty callbacks */ 713 714 static int install(struct tty_driver *driver, struct tty_struct *tty) 715 { 716 SLMP_INFO *info; 717 int line = tty->index; 718 719 if (line >= synclinkmp_device_count) { 720 printk("%s(%d): open with invalid line #%d.\n", 721 __FILE__,__LINE__,line); 722 return -ENODEV; 723 } 724 725 info = synclinkmp_device_list; 726 while (info && info->line != line) 727 info = info->next_device; 728 if (sanity_check(info, tty->name, "open")) 729 return -ENODEV; 730 if (info->init_error) { 731 printk("%s(%d):%s device is not allocated, init error=%d\n", 732 __FILE__, __LINE__, info->device_name, 733 info->init_error); 734 return -ENODEV; 735 } 736 737 tty->driver_data = info; 738 739 return tty_port_install(&info->port, driver, tty); 740 } 741 742 /* Called when a port is opened. Init and enable port. 743 */ 744 static int open(struct tty_struct *tty, struct file *filp) 745 { 746 SLMP_INFO *info = tty->driver_data; 747 unsigned long flags; 748 int retval; 749 750 info->port.tty = tty; 751 752 if (debug_level >= DEBUG_LEVEL_INFO) 753 printk("%s(%d):%s open(), old ref count = %d\n", 754 __FILE__,__LINE__,tty->driver->name, info->port.count); 755 756 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; 757 758 spin_lock_irqsave(&info->netlock, flags); 759 if (info->netcount) { 760 retval = -EBUSY; 761 spin_unlock_irqrestore(&info->netlock, flags); 762 goto cleanup; 763 } 764 info->port.count++; 765 spin_unlock_irqrestore(&info->netlock, flags); 766 767 if (info->port.count == 1) { 768 /* 1st open on this device, init hardware */ 769 retval = startup(info); 770 if (retval < 0) 771 goto cleanup; 772 } 773 774 retval = block_til_ready(tty, filp, info); 775 if (retval) { 776 if (debug_level >= DEBUG_LEVEL_INFO) 777 printk("%s(%d):%s block_til_ready() returned %d\n", 778 __FILE__,__LINE__, info->device_name, retval); 779 goto cleanup; 780 } 781 782 if (debug_level >= DEBUG_LEVEL_INFO) 783 printk("%s(%d):%s open() success\n", 784 __FILE__,__LINE__, info->device_name); 785 retval = 0; 786 787 cleanup: 788 if (retval) { 789 if (tty->count == 1) 790 info->port.tty = NULL; /* tty layer will release tty struct */ 791 if(info->port.count) 792 info->port.count--; 793 } 794 795 return retval; 796 } 797 798 /* Called when port is closed. Wait for remaining data to be 799 * sent. Disable port and free resources. 800 */ 801 static void close(struct tty_struct *tty, struct file *filp) 802 { 803 SLMP_INFO * info = tty->driver_data; 804 805 if (sanity_check(info, tty->name, "close")) 806 return; 807 808 if (debug_level >= DEBUG_LEVEL_INFO) 809 printk("%s(%d):%s close() entry, count=%d\n", 810 __FILE__,__LINE__, info->device_name, info->port.count); 811 812 if (tty_port_close_start(&info->port, tty, filp) == 0) 813 goto cleanup; 814 815 mutex_lock(&info->port.mutex); 816 if (info->port.flags & ASYNC_INITIALIZED) 817 wait_until_sent(tty, info->timeout); 818 819 flush_buffer(tty); 820 tty_ldisc_flush(tty); 821 shutdown(info); 822 mutex_unlock(&info->port.mutex); 823 824 tty_port_close_end(&info->port, tty); 825 info->port.tty = NULL; 826 cleanup: 827 if (debug_level >= DEBUG_LEVEL_INFO) 828 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__, 829 tty->driver->name, info->port.count); 830 } 831 832 /* Called by tty_hangup() when a hangup is signaled. 833 * This is the same as closing all open descriptors for the port. 834 */ 835 static void hangup(struct tty_struct *tty) 836 { 837 SLMP_INFO *info = tty->driver_data; 838 unsigned long flags; 839 840 if (debug_level >= DEBUG_LEVEL_INFO) 841 printk("%s(%d):%s hangup()\n", 842 __FILE__,__LINE__, info->device_name ); 843 844 if (sanity_check(info, tty->name, "hangup")) 845 return; 846 847 mutex_lock(&info->port.mutex); 848 flush_buffer(tty); 849 shutdown(info); 850 851 spin_lock_irqsave(&info->port.lock, flags); 852 info->port.count = 0; 853 info->port.flags &= ~ASYNC_NORMAL_ACTIVE; 854 info->port.tty = NULL; 855 spin_unlock_irqrestore(&info->port.lock, flags); 856 mutex_unlock(&info->port.mutex); 857 858 wake_up_interruptible(&info->port.open_wait); 859 } 860 861 /* Set new termios settings 862 */ 863 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) 864 { 865 SLMP_INFO *info = tty->driver_data; 866 unsigned long flags; 867 868 if (debug_level >= DEBUG_LEVEL_INFO) 869 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__, 870 tty->driver->name ); 871 872 change_params(info); 873 874 /* Handle transition to B0 status */ 875 if (old_termios->c_cflag & CBAUD && 876 !(tty->termios.c_cflag & CBAUD)) { 877 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 878 spin_lock_irqsave(&info->lock,flags); 879 set_signals(info); 880 spin_unlock_irqrestore(&info->lock,flags); 881 } 882 883 /* Handle transition away from B0 status */ 884 if (!(old_termios->c_cflag & CBAUD) && 885 tty->termios.c_cflag & CBAUD) { 886 info->serial_signals |= SerialSignal_DTR; 887 if (!(tty->termios.c_cflag & CRTSCTS) || 888 !test_bit(TTY_THROTTLED, &tty->flags)) { 889 info->serial_signals |= SerialSignal_RTS; 890 } 891 spin_lock_irqsave(&info->lock,flags); 892 set_signals(info); 893 spin_unlock_irqrestore(&info->lock,flags); 894 } 895 896 /* Handle turning off CRTSCTS */ 897 if (old_termios->c_cflag & CRTSCTS && 898 !(tty->termios.c_cflag & CRTSCTS)) { 899 tty->hw_stopped = 0; 900 tx_release(tty); 901 } 902 } 903 904 /* Send a block of data 905 * 906 * Arguments: 907 * 908 * tty pointer to tty information structure 909 * buf pointer to buffer containing send data 910 * count size of send data in bytes 911 * 912 * Return Value: number of characters written 913 */ 914 static int write(struct tty_struct *tty, 915 const unsigned char *buf, int count) 916 { 917 int c, ret = 0; 918 SLMP_INFO *info = tty->driver_data; 919 unsigned long flags; 920 921 if (debug_level >= DEBUG_LEVEL_INFO) 922 printk("%s(%d):%s write() count=%d\n", 923 __FILE__,__LINE__,info->device_name,count); 924 925 if (sanity_check(info, tty->name, "write")) 926 goto cleanup; 927 928 if (!info->tx_buf) 929 goto cleanup; 930 931 if (info->params.mode == MGSL_MODE_HDLC) { 932 if (count > info->max_frame_size) { 933 ret = -EIO; 934 goto cleanup; 935 } 936 if (info->tx_active) 937 goto cleanup; 938 if (info->tx_count) { 939 /* send accumulated data from send_char() calls */ 940 /* as frame and wait before accepting more data. */ 941 tx_load_dma_buffer(info, info->tx_buf, info->tx_count); 942 goto start; 943 } 944 ret = info->tx_count = count; 945 tx_load_dma_buffer(info, buf, count); 946 goto start; 947 } 948 949 for (;;) { 950 c = min_t(int, count, 951 min(info->max_frame_size - info->tx_count - 1, 952 info->max_frame_size - info->tx_put)); 953 if (c <= 0) 954 break; 955 956 memcpy(info->tx_buf + info->tx_put, buf, c); 957 958 spin_lock_irqsave(&info->lock,flags); 959 info->tx_put += c; 960 if (info->tx_put >= info->max_frame_size) 961 info->tx_put -= info->max_frame_size; 962 info->tx_count += c; 963 spin_unlock_irqrestore(&info->lock,flags); 964 965 buf += c; 966 count -= c; 967 ret += c; 968 } 969 970 if (info->params.mode == MGSL_MODE_HDLC) { 971 if (count) { 972 ret = info->tx_count = 0; 973 goto cleanup; 974 } 975 tx_load_dma_buffer(info, info->tx_buf, info->tx_count); 976 } 977 start: 978 if (info->tx_count && !tty->stopped && !tty->hw_stopped) { 979 spin_lock_irqsave(&info->lock,flags); 980 if (!info->tx_active) 981 tx_start(info); 982 spin_unlock_irqrestore(&info->lock,flags); 983 } 984 985 cleanup: 986 if (debug_level >= DEBUG_LEVEL_INFO) 987 printk( "%s(%d):%s write() returning=%d\n", 988 __FILE__,__LINE__,info->device_name,ret); 989 return ret; 990 } 991 992 /* Add a character to the transmit buffer. 993 */ 994 static int put_char(struct tty_struct *tty, unsigned char ch) 995 { 996 SLMP_INFO *info = tty->driver_data; 997 unsigned long flags; 998 int ret = 0; 999 1000 if ( debug_level >= DEBUG_LEVEL_INFO ) { 1001 printk( "%s(%d):%s put_char(%d)\n", 1002 __FILE__,__LINE__,info->device_name,ch); 1003 } 1004 1005 if (sanity_check(info, tty->name, "put_char")) 1006 return 0; 1007 1008 if (!info->tx_buf) 1009 return 0; 1010 1011 spin_lock_irqsave(&info->lock,flags); 1012 1013 if ( (info->params.mode != MGSL_MODE_HDLC) || 1014 !info->tx_active ) { 1015 1016 if (info->tx_count < info->max_frame_size - 1) { 1017 info->tx_buf[info->tx_put++] = ch; 1018 if (info->tx_put >= info->max_frame_size) 1019 info->tx_put -= info->max_frame_size; 1020 info->tx_count++; 1021 ret = 1; 1022 } 1023 } 1024 1025 spin_unlock_irqrestore(&info->lock,flags); 1026 return ret; 1027 } 1028 1029 /* Send a high-priority XON/XOFF character 1030 */ 1031 static void send_xchar(struct tty_struct *tty, char ch) 1032 { 1033 SLMP_INFO *info = tty->driver_data; 1034 unsigned long flags; 1035 1036 if (debug_level >= DEBUG_LEVEL_INFO) 1037 printk("%s(%d):%s send_xchar(%d)\n", 1038 __FILE__,__LINE__, info->device_name, ch ); 1039 1040 if (sanity_check(info, tty->name, "send_xchar")) 1041 return; 1042 1043 info->x_char = ch; 1044 if (ch) { 1045 /* Make sure transmit interrupts are on */ 1046 spin_lock_irqsave(&info->lock,flags); 1047 if (!info->tx_enabled) 1048 tx_start(info); 1049 spin_unlock_irqrestore(&info->lock,flags); 1050 } 1051 } 1052 1053 /* Wait until the transmitter is empty. 1054 */ 1055 static void wait_until_sent(struct tty_struct *tty, int timeout) 1056 { 1057 SLMP_INFO * info = tty->driver_data; 1058 unsigned long orig_jiffies, char_time; 1059 1060 if (!info ) 1061 return; 1062 1063 if (debug_level >= DEBUG_LEVEL_INFO) 1064 printk("%s(%d):%s wait_until_sent() entry\n", 1065 __FILE__,__LINE__, info->device_name ); 1066 1067 if (sanity_check(info, tty->name, "wait_until_sent")) 1068 return; 1069 1070 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags)) 1071 goto exit; 1072 1073 orig_jiffies = jiffies; 1074 1075 /* Set check interval to 1/5 of estimated time to 1076 * send a character, and make it at least 1. The check 1077 * interval should also be less than the timeout. 1078 * Note: use tight timings here to satisfy the NIST-PCTS. 1079 */ 1080 1081 if ( info->params.data_rate ) { 1082 char_time = info->timeout/(32 * 5); 1083 if (!char_time) 1084 char_time++; 1085 } else 1086 char_time = 1; 1087 1088 if (timeout) 1089 char_time = min_t(unsigned long, char_time, timeout); 1090 1091 if ( info->params.mode == MGSL_MODE_HDLC ) { 1092 while (info->tx_active) { 1093 msleep_interruptible(jiffies_to_msecs(char_time)); 1094 if (signal_pending(current)) 1095 break; 1096 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 1097 break; 1098 } 1099 } else { 1100 /* 1101 * TODO: determine if there is something similar to USC16C32 1102 * TXSTATUS_ALL_SENT status 1103 */ 1104 while ( info->tx_active && info->tx_enabled) { 1105 msleep_interruptible(jiffies_to_msecs(char_time)); 1106 if (signal_pending(current)) 1107 break; 1108 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 1109 break; 1110 } 1111 } 1112 1113 exit: 1114 if (debug_level >= DEBUG_LEVEL_INFO) 1115 printk("%s(%d):%s wait_until_sent() exit\n", 1116 __FILE__,__LINE__, info->device_name ); 1117 } 1118 1119 /* Return the count of free bytes in transmit buffer 1120 */ 1121 static int write_room(struct tty_struct *tty) 1122 { 1123 SLMP_INFO *info = tty->driver_data; 1124 int ret; 1125 1126 if (sanity_check(info, tty->name, "write_room")) 1127 return 0; 1128 1129 if (info->params.mode == MGSL_MODE_HDLC) { 1130 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; 1131 } else { 1132 ret = info->max_frame_size - info->tx_count - 1; 1133 if (ret < 0) 1134 ret = 0; 1135 } 1136 1137 if (debug_level >= DEBUG_LEVEL_INFO) 1138 printk("%s(%d):%s write_room()=%d\n", 1139 __FILE__, __LINE__, info->device_name, ret); 1140 1141 return ret; 1142 } 1143 1144 /* enable transmitter and send remaining buffered characters 1145 */ 1146 static void flush_chars(struct tty_struct *tty) 1147 { 1148 SLMP_INFO *info = tty->driver_data; 1149 unsigned long flags; 1150 1151 if ( debug_level >= DEBUG_LEVEL_INFO ) 1152 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n", 1153 __FILE__,__LINE__,info->device_name,info->tx_count); 1154 1155 if (sanity_check(info, tty->name, "flush_chars")) 1156 return; 1157 1158 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped || 1159 !info->tx_buf) 1160 return; 1161 1162 if ( debug_level >= DEBUG_LEVEL_INFO ) 1163 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n", 1164 __FILE__,__LINE__,info->device_name ); 1165 1166 spin_lock_irqsave(&info->lock,flags); 1167 1168 if (!info->tx_active) { 1169 if ( (info->params.mode == MGSL_MODE_HDLC) && 1170 info->tx_count ) { 1171 /* operating in synchronous (frame oriented) mode */ 1172 /* copy data from circular tx_buf to */ 1173 /* transmit DMA buffer. */ 1174 tx_load_dma_buffer(info, 1175 info->tx_buf,info->tx_count); 1176 } 1177 tx_start(info); 1178 } 1179 1180 spin_unlock_irqrestore(&info->lock,flags); 1181 } 1182 1183 /* Discard all data in the send buffer 1184 */ 1185 static void flush_buffer(struct tty_struct *tty) 1186 { 1187 SLMP_INFO *info = tty->driver_data; 1188 unsigned long flags; 1189 1190 if (debug_level >= DEBUG_LEVEL_INFO) 1191 printk("%s(%d):%s flush_buffer() entry\n", 1192 __FILE__,__LINE__, info->device_name ); 1193 1194 if (sanity_check(info, tty->name, "flush_buffer")) 1195 return; 1196 1197 spin_lock_irqsave(&info->lock,flags); 1198 info->tx_count = info->tx_put = info->tx_get = 0; 1199 del_timer(&info->tx_timer); 1200 spin_unlock_irqrestore(&info->lock,flags); 1201 1202 tty_wakeup(tty); 1203 } 1204 1205 /* throttle (stop) transmitter 1206 */ 1207 static void tx_hold(struct tty_struct *tty) 1208 { 1209 SLMP_INFO *info = tty->driver_data; 1210 unsigned long flags; 1211 1212 if (sanity_check(info, tty->name, "tx_hold")) 1213 return; 1214 1215 if ( debug_level >= DEBUG_LEVEL_INFO ) 1216 printk("%s(%d):%s tx_hold()\n", 1217 __FILE__,__LINE__,info->device_name); 1218 1219 spin_lock_irqsave(&info->lock,flags); 1220 if (info->tx_enabled) 1221 tx_stop(info); 1222 spin_unlock_irqrestore(&info->lock,flags); 1223 } 1224 1225 /* release (start) transmitter 1226 */ 1227 static void tx_release(struct tty_struct *tty) 1228 { 1229 SLMP_INFO *info = tty->driver_data; 1230 unsigned long flags; 1231 1232 if (sanity_check(info, tty->name, "tx_release")) 1233 return; 1234 1235 if ( debug_level >= DEBUG_LEVEL_INFO ) 1236 printk("%s(%d):%s tx_release()\n", 1237 __FILE__,__LINE__,info->device_name); 1238 1239 spin_lock_irqsave(&info->lock,flags); 1240 if (!info->tx_enabled) 1241 tx_start(info); 1242 spin_unlock_irqrestore(&info->lock,flags); 1243 } 1244 1245 /* Service an IOCTL request 1246 * 1247 * Arguments: 1248 * 1249 * tty pointer to tty instance data 1250 * cmd IOCTL command code 1251 * arg command argument/context 1252 * 1253 * Return Value: 0 if success, otherwise error code 1254 */ 1255 static int ioctl(struct tty_struct *tty, 1256 unsigned int cmd, unsigned long arg) 1257 { 1258 SLMP_INFO *info = tty->driver_data; 1259 void __user *argp = (void __user *)arg; 1260 1261 if (debug_level >= DEBUG_LEVEL_INFO) 1262 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__, 1263 info->device_name, cmd ); 1264 1265 if (sanity_check(info, tty->name, "ioctl")) 1266 return -ENODEV; 1267 1268 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && 1269 (cmd != TIOCMIWAIT)) { 1270 if (tty->flags & (1 << TTY_IO_ERROR)) 1271 return -EIO; 1272 } 1273 1274 switch (cmd) { 1275 case MGSL_IOCGPARAMS: 1276 return get_params(info, argp); 1277 case MGSL_IOCSPARAMS: 1278 return set_params(info, argp); 1279 case MGSL_IOCGTXIDLE: 1280 return get_txidle(info, argp); 1281 case MGSL_IOCSTXIDLE: 1282 return set_txidle(info, (int)arg); 1283 case MGSL_IOCTXENABLE: 1284 return tx_enable(info, (int)arg); 1285 case MGSL_IOCRXENABLE: 1286 return rx_enable(info, (int)arg); 1287 case MGSL_IOCTXABORT: 1288 return tx_abort(info); 1289 case MGSL_IOCGSTATS: 1290 return get_stats(info, argp); 1291 case MGSL_IOCWAITEVENT: 1292 return wait_mgsl_event(info, argp); 1293 case MGSL_IOCLOOPTXDONE: 1294 return 0; // TODO: Not supported, need to document 1295 /* Wait for modem input (DCD,RI,DSR,CTS) change 1296 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS) 1297 */ 1298 case TIOCMIWAIT: 1299 return modem_input_wait(info,(int)arg); 1300 1301 /* 1302 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) 1303 * Return: write counters to the user passed counter struct 1304 * NB: both 1->0 and 0->1 transitions are counted except for 1305 * RI where only 0->1 is counted. 1306 */ 1307 default: 1308 return -ENOIOCTLCMD; 1309 } 1310 return 0; 1311 } 1312 1313 static int get_icount(struct tty_struct *tty, 1314 struct serial_icounter_struct *icount) 1315 { 1316 SLMP_INFO *info = tty->driver_data; 1317 struct mgsl_icount cnow; /* kernel counter temps */ 1318 unsigned long flags; 1319 1320 spin_lock_irqsave(&info->lock,flags); 1321 cnow = info->icount; 1322 spin_unlock_irqrestore(&info->lock,flags); 1323 1324 icount->cts = cnow.cts; 1325 icount->dsr = cnow.dsr; 1326 icount->rng = cnow.rng; 1327 icount->dcd = cnow.dcd; 1328 icount->rx = cnow.rx; 1329 icount->tx = cnow.tx; 1330 icount->frame = cnow.frame; 1331 icount->overrun = cnow.overrun; 1332 icount->parity = cnow.parity; 1333 icount->brk = cnow.brk; 1334 icount->buf_overrun = cnow.buf_overrun; 1335 1336 return 0; 1337 } 1338 1339 /* 1340 * /proc fs routines.... 1341 */ 1342 1343 static inline void line_info(struct seq_file *m, SLMP_INFO *info) 1344 { 1345 char stat_buf[30]; 1346 unsigned long flags; 1347 1348 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n" 1349 "\tIRQ=%d MaxFrameSize=%u\n", 1350 info->device_name, 1351 info->phys_sca_base, 1352 info->phys_memory_base, 1353 info->phys_statctrl_base, 1354 info->phys_lcr_base, 1355 info->irq_level, 1356 info->max_frame_size ); 1357 1358 /* output current serial signal states */ 1359 spin_lock_irqsave(&info->lock,flags); 1360 get_signals(info); 1361 spin_unlock_irqrestore(&info->lock,flags); 1362 1363 stat_buf[0] = 0; 1364 stat_buf[1] = 0; 1365 if (info->serial_signals & SerialSignal_RTS) 1366 strcat(stat_buf, "|RTS"); 1367 if (info->serial_signals & SerialSignal_CTS) 1368 strcat(stat_buf, "|CTS"); 1369 if (info->serial_signals & SerialSignal_DTR) 1370 strcat(stat_buf, "|DTR"); 1371 if (info->serial_signals & SerialSignal_DSR) 1372 strcat(stat_buf, "|DSR"); 1373 if (info->serial_signals & SerialSignal_DCD) 1374 strcat(stat_buf, "|CD"); 1375 if (info->serial_signals & SerialSignal_RI) 1376 strcat(stat_buf, "|RI"); 1377 1378 if (info->params.mode == MGSL_MODE_HDLC) { 1379 seq_printf(m, "\tHDLC txok:%d rxok:%d", 1380 info->icount.txok, info->icount.rxok); 1381 if (info->icount.txunder) 1382 seq_printf(m, " txunder:%d", info->icount.txunder); 1383 if (info->icount.txabort) 1384 seq_printf(m, " txabort:%d", info->icount.txabort); 1385 if (info->icount.rxshort) 1386 seq_printf(m, " rxshort:%d", info->icount.rxshort); 1387 if (info->icount.rxlong) 1388 seq_printf(m, " rxlong:%d", info->icount.rxlong); 1389 if (info->icount.rxover) 1390 seq_printf(m, " rxover:%d", info->icount.rxover); 1391 if (info->icount.rxcrc) 1392 seq_printf(m, " rxlong:%d", info->icount.rxcrc); 1393 } else { 1394 seq_printf(m, "\tASYNC tx:%d rx:%d", 1395 info->icount.tx, info->icount.rx); 1396 if (info->icount.frame) 1397 seq_printf(m, " fe:%d", info->icount.frame); 1398 if (info->icount.parity) 1399 seq_printf(m, " pe:%d", info->icount.parity); 1400 if (info->icount.brk) 1401 seq_printf(m, " brk:%d", info->icount.brk); 1402 if (info->icount.overrun) 1403 seq_printf(m, " oe:%d", info->icount.overrun); 1404 } 1405 1406 /* Append serial signal status to end */ 1407 seq_printf(m, " %s\n", stat_buf+1); 1408 1409 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 1410 info->tx_active,info->bh_requested,info->bh_running, 1411 info->pending_bh); 1412 } 1413 1414 /* Called to print information about devices 1415 */ 1416 static int synclinkmp_proc_show(struct seq_file *m, void *v) 1417 { 1418 SLMP_INFO *info; 1419 1420 seq_printf(m, "synclinkmp driver:%s\n", driver_version); 1421 1422 info = synclinkmp_device_list; 1423 while( info ) { 1424 line_info(m, info); 1425 info = info->next_device; 1426 } 1427 return 0; 1428 } 1429 1430 static int synclinkmp_proc_open(struct inode *inode, struct file *file) 1431 { 1432 return single_open(file, synclinkmp_proc_show, NULL); 1433 } 1434 1435 static const struct file_operations synclinkmp_proc_fops = { 1436 .owner = THIS_MODULE, 1437 .open = synclinkmp_proc_open, 1438 .read = seq_read, 1439 .llseek = seq_lseek, 1440 .release = single_release, 1441 }; 1442 1443 /* Return the count of bytes in transmit buffer 1444 */ 1445 static int chars_in_buffer(struct tty_struct *tty) 1446 { 1447 SLMP_INFO *info = tty->driver_data; 1448 1449 if (sanity_check(info, tty->name, "chars_in_buffer")) 1450 return 0; 1451 1452 if (debug_level >= DEBUG_LEVEL_INFO) 1453 printk("%s(%d):%s chars_in_buffer()=%d\n", 1454 __FILE__, __LINE__, info->device_name, info->tx_count); 1455 1456 return info->tx_count; 1457 } 1458 1459 /* Signal remote device to throttle send data (our receive data) 1460 */ 1461 static void throttle(struct tty_struct * tty) 1462 { 1463 SLMP_INFO *info = tty->driver_data; 1464 unsigned long flags; 1465 1466 if (debug_level >= DEBUG_LEVEL_INFO) 1467 printk("%s(%d):%s throttle() entry\n", 1468 __FILE__,__LINE__, info->device_name ); 1469 1470 if (sanity_check(info, tty->name, "throttle")) 1471 return; 1472 1473 if (I_IXOFF(tty)) 1474 send_xchar(tty, STOP_CHAR(tty)); 1475 1476 if (tty->termios.c_cflag & CRTSCTS) { 1477 spin_lock_irqsave(&info->lock,flags); 1478 info->serial_signals &= ~SerialSignal_RTS; 1479 set_signals(info); 1480 spin_unlock_irqrestore(&info->lock,flags); 1481 } 1482 } 1483 1484 /* Signal remote device to stop throttling send data (our receive data) 1485 */ 1486 static void unthrottle(struct tty_struct * tty) 1487 { 1488 SLMP_INFO *info = tty->driver_data; 1489 unsigned long flags; 1490 1491 if (debug_level >= DEBUG_LEVEL_INFO) 1492 printk("%s(%d):%s unthrottle() entry\n", 1493 __FILE__,__LINE__, info->device_name ); 1494 1495 if (sanity_check(info, tty->name, "unthrottle")) 1496 return; 1497 1498 if (I_IXOFF(tty)) { 1499 if (info->x_char) 1500 info->x_char = 0; 1501 else 1502 send_xchar(tty, START_CHAR(tty)); 1503 } 1504 1505 if (tty->termios.c_cflag & CRTSCTS) { 1506 spin_lock_irqsave(&info->lock,flags); 1507 info->serial_signals |= SerialSignal_RTS; 1508 set_signals(info); 1509 spin_unlock_irqrestore(&info->lock,flags); 1510 } 1511 } 1512 1513 /* set or clear transmit break condition 1514 * break_state -1=set break condition, 0=clear 1515 */ 1516 static int set_break(struct tty_struct *tty, int break_state) 1517 { 1518 unsigned char RegValue; 1519 SLMP_INFO * info = tty->driver_data; 1520 unsigned long flags; 1521 1522 if (debug_level >= DEBUG_LEVEL_INFO) 1523 printk("%s(%d):%s set_break(%d)\n", 1524 __FILE__,__LINE__, info->device_name, break_state); 1525 1526 if (sanity_check(info, tty->name, "set_break")) 1527 return -EINVAL; 1528 1529 spin_lock_irqsave(&info->lock,flags); 1530 RegValue = read_reg(info, CTL); 1531 if (break_state == -1) 1532 RegValue |= BIT3; 1533 else 1534 RegValue &= ~BIT3; 1535 write_reg(info, CTL, RegValue); 1536 spin_unlock_irqrestore(&info->lock,flags); 1537 return 0; 1538 } 1539 1540 #if SYNCLINK_GENERIC_HDLC 1541 1542 /** 1543 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 1544 * set encoding and frame check sequence (FCS) options 1545 * 1546 * dev pointer to network device structure 1547 * encoding serial encoding setting 1548 * parity FCS setting 1549 * 1550 * returns 0 if success, otherwise error code 1551 */ 1552 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 1553 unsigned short parity) 1554 { 1555 SLMP_INFO *info = dev_to_port(dev); 1556 unsigned char new_encoding; 1557 unsigned short new_crctype; 1558 1559 /* return error if TTY interface open */ 1560 if (info->port.count) 1561 return -EBUSY; 1562 1563 switch (encoding) 1564 { 1565 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 1566 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 1567 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 1568 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 1569 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 1570 default: return -EINVAL; 1571 } 1572 1573 switch (parity) 1574 { 1575 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 1576 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 1577 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 1578 default: return -EINVAL; 1579 } 1580 1581 info->params.encoding = new_encoding; 1582 info->params.crc_type = new_crctype; 1583 1584 /* if network interface up, reprogram hardware */ 1585 if (info->netcount) 1586 program_hw(info); 1587 1588 return 0; 1589 } 1590 1591 /** 1592 * called by generic HDLC layer to send frame 1593 * 1594 * skb socket buffer containing HDLC frame 1595 * dev pointer to network device structure 1596 */ 1597 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 1598 struct net_device *dev) 1599 { 1600 SLMP_INFO *info = dev_to_port(dev); 1601 unsigned long flags; 1602 1603 if (debug_level >= DEBUG_LEVEL_INFO) 1604 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); 1605 1606 /* stop sending until this frame completes */ 1607 netif_stop_queue(dev); 1608 1609 /* copy data to device buffers */ 1610 info->tx_count = skb->len; 1611 tx_load_dma_buffer(info, skb->data, skb->len); 1612 1613 /* update network statistics */ 1614 dev->stats.tx_packets++; 1615 dev->stats.tx_bytes += skb->len; 1616 1617 /* done with socket buffer, so free it */ 1618 dev_kfree_skb(skb); 1619 1620 /* save start time for transmit timeout detection */ 1621 dev->trans_start = jiffies; 1622 1623 /* start hardware transmitter if necessary */ 1624 spin_lock_irqsave(&info->lock,flags); 1625 if (!info->tx_active) 1626 tx_start(info); 1627 spin_unlock_irqrestore(&info->lock,flags); 1628 1629 return NETDEV_TX_OK; 1630 } 1631 1632 /** 1633 * called by network layer when interface enabled 1634 * claim resources and initialize hardware 1635 * 1636 * dev pointer to network device structure 1637 * 1638 * returns 0 if success, otherwise error code 1639 */ 1640 static int hdlcdev_open(struct net_device *dev) 1641 { 1642 SLMP_INFO *info = dev_to_port(dev); 1643 int rc; 1644 unsigned long flags; 1645 1646 if (debug_level >= DEBUG_LEVEL_INFO) 1647 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); 1648 1649 /* generic HDLC layer open processing */ 1650 rc = hdlc_open(dev); 1651 if (rc) 1652 return rc; 1653 1654 /* arbitrate between network and tty opens */ 1655 spin_lock_irqsave(&info->netlock, flags); 1656 if (info->port.count != 0 || info->netcount != 0) { 1657 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); 1658 spin_unlock_irqrestore(&info->netlock, flags); 1659 return -EBUSY; 1660 } 1661 info->netcount=1; 1662 spin_unlock_irqrestore(&info->netlock, flags); 1663 1664 /* claim resources and init adapter */ 1665 if ((rc = startup(info)) != 0) { 1666 spin_lock_irqsave(&info->netlock, flags); 1667 info->netcount=0; 1668 spin_unlock_irqrestore(&info->netlock, flags); 1669 return rc; 1670 } 1671 1672 /* assert RTS and DTR, apply hardware settings */ 1673 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; 1674 program_hw(info); 1675 1676 /* enable network layer transmit */ 1677 dev->trans_start = jiffies; 1678 netif_start_queue(dev); 1679 1680 /* inform generic HDLC layer of current DCD status */ 1681 spin_lock_irqsave(&info->lock, flags); 1682 get_signals(info); 1683 spin_unlock_irqrestore(&info->lock, flags); 1684 if (info->serial_signals & SerialSignal_DCD) 1685 netif_carrier_on(dev); 1686 else 1687 netif_carrier_off(dev); 1688 return 0; 1689 } 1690 1691 /** 1692 * called by network layer when interface is disabled 1693 * shutdown hardware and release resources 1694 * 1695 * dev pointer to network device structure 1696 * 1697 * returns 0 if success, otherwise error code 1698 */ 1699 static int hdlcdev_close(struct net_device *dev) 1700 { 1701 SLMP_INFO *info = dev_to_port(dev); 1702 unsigned long flags; 1703 1704 if (debug_level >= DEBUG_LEVEL_INFO) 1705 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); 1706 1707 netif_stop_queue(dev); 1708 1709 /* shutdown adapter and release resources */ 1710 shutdown(info); 1711 1712 hdlc_close(dev); 1713 1714 spin_lock_irqsave(&info->netlock, flags); 1715 info->netcount=0; 1716 spin_unlock_irqrestore(&info->netlock, flags); 1717 1718 return 0; 1719 } 1720 1721 /** 1722 * called by network layer to process IOCTL call to network device 1723 * 1724 * dev pointer to network device structure 1725 * ifr pointer to network interface request structure 1726 * cmd IOCTL command code 1727 * 1728 * returns 0 if success, otherwise error code 1729 */ 1730 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1731 { 1732 const size_t size = sizeof(sync_serial_settings); 1733 sync_serial_settings new_line; 1734 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1735 SLMP_INFO *info = dev_to_port(dev); 1736 unsigned int flags; 1737 1738 if (debug_level >= DEBUG_LEVEL_INFO) 1739 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); 1740 1741 /* return error if TTY interface open */ 1742 if (info->port.count) 1743 return -EBUSY; 1744 1745 if (cmd != SIOCWANDEV) 1746 return hdlc_ioctl(dev, ifr, cmd); 1747 1748 switch(ifr->ifr_settings.type) { 1749 case IF_GET_IFACE: /* return current sync_serial_settings */ 1750 1751 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 1752 if (ifr->ifr_settings.size < size) { 1753 ifr->ifr_settings.size = size; /* data size wanted */ 1754 return -ENOBUFS; 1755 } 1756 1757 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1758 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1759 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1760 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1761 1762 memset(&new_line, 0, sizeof(new_line)); 1763 switch (flags){ 1764 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1765 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1766 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1767 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1768 default: new_line.clock_type = CLOCK_DEFAULT; 1769 } 1770 1771 new_line.clock_rate = info->params.clock_speed; 1772 new_line.loopback = info->params.loopback ? 1:0; 1773 1774 if (copy_to_user(line, &new_line, size)) 1775 return -EFAULT; 1776 return 0; 1777 1778 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 1779 1780 if(!capable(CAP_NET_ADMIN)) 1781 return -EPERM; 1782 if (copy_from_user(&new_line, line, size)) 1783 return -EFAULT; 1784 1785 switch (new_line.clock_type) 1786 { 1787 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 1788 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 1789 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 1790 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 1791 case CLOCK_DEFAULT: flags = info->params.flags & 1792 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1793 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1794 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1795 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 1796 default: return -EINVAL; 1797 } 1798 1799 if (new_line.loopback != 0 && new_line.loopback != 1) 1800 return -EINVAL; 1801 1802 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1803 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1804 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1805 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1806 info->params.flags |= flags; 1807 1808 info->params.loopback = new_line.loopback; 1809 1810 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 1811 info->params.clock_speed = new_line.clock_rate; 1812 else 1813 info->params.clock_speed = 0; 1814 1815 /* if network interface up, reprogram hardware */ 1816 if (info->netcount) 1817 program_hw(info); 1818 return 0; 1819 1820 default: 1821 return hdlc_ioctl(dev, ifr, cmd); 1822 } 1823 } 1824 1825 /** 1826 * called by network layer when transmit timeout is detected 1827 * 1828 * dev pointer to network device structure 1829 */ 1830 static void hdlcdev_tx_timeout(struct net_device *dev) 1831 { 1832 SLMP_INFO *info = dev_to_port(dev); 1833 unsigned long flags; 1834 1835 if (debug_level >= DEBUG_LEVEL_INFO) 1836 printk("hdlcdev_tx_timeout(%s)\n",dev->name); 1837 1838 dev->stats.tx_errors++; 1839 dev->stats.tx_aborted_errors++; 1840 1841 spin_lock_irqsave(&info->lock,flags); 1842 tx_stop(info); 1843 spin_unlock_irqrestore(&info->lock,flags); 1844 1845 netif_wake_queue(dev); 1846 } 1847 1848 /** 1849 * called by device driver when transmit completes 1850 * reenable network layer transmit if stopped 1851 * 1852 * info pointer to device instance information 1853 */ 1854 static void hdlcdev_tx_done(SLMP_INFO *info) 1855 { 1856 if (netif_queue_stopped(info->netdev)) 1857 netif_wake_queue(info->netdev); 1858 } 1859 1860 /** 1861 * called by device driver when frame received 1862 * pass frame to network layer 1863 * 1864 * info pointer to device instance information 1865 * buf pointer to buffer contianing frame data 1866 * size count of data bytes in buf 1867 */ 1868 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size) 1869 { 1870 struct sk_buff *skb = dev_alloc_skb(size); 1871 struct net_device *dev = info->netdev; 1872 1873 if (debug_level >= DEBUG_LEVEL_INFO) 1874 printk("hdlcdev_rx(%s)\n",dev->name); 1875 1876 if (skb == NULL) { 1877 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", 1878 dev->name); 1879 dev->stats.rx_dropped++; 1880 return; 1881 } 1882 1883 memcpy(skb_put(skb, size), buf, size); 1884 1885 skb->protocol = hdlc_type_trans(skb, dev); 1886 1887 dev->stats.rx_packets++; 1888 dev->stats.rx_bytes += size; 1889 1890 netif_rx(skb); 1891 } 1892 1893 static const struct net_device_ops hdlcdev_ops = { 1894 .ndo_open = hdlcdev_open, 1895 .ndo_stop = hdlcdev_close, 1896 .ndo_change_mtu = hdlc_change_mtu, 1897 .ndo_start_xmit = hdlc_start_xmit, 1898 .ndo_do_ioctl = hdlcdev_ioctl, 1899 .ndo_tx_timeout = hdlcdev_tx_timeout, 1900 }; 1901 1902 /** 1903 * called by device driver when adding device instance 1904 * do generic HDLC initialization 1905 * 1906 * info pointer to device instance information 1907 * 1908 * returns 0 if success, otherwise error code 1909 */ 1910 static int hdlcdev_init(SLMP_INFO *info) 1911 { 1912 int rc; 1913 struct net_device *dev; 1914 hdlc_device *hdlc; 1915 1916 /* allocate and initialize network and HDLC layer objects */ 1917 1918 dev = alloc_hdlcdev(info); 1919 if (!dev) { 1920 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); 1921 return -ENOMEM; 1922 } 1923 1924 /* for network layer reporting purposes only */ 1925 dev->mem_start = info->phys_sca_base; 1926 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1; 1927 dev->irq = info->irq_level; 1928 1929 /* network layer callbacks and settings */ 1930 dev->netdev_ops = &hdlcdev_ops; 1931 dev->watchdog_timeo = 10 * HZ; 1932 dev->tx_queue_len = 50; 1933 1934 /* generic HDLC layer callbacks and settings */ 1935 hdlc = dev_to_hdlc(dev); 1936 hdlc->attach = hdlcdev_attach; 1937 hdlc->xmit = hdlcdev_xmit; 1938 1939 /* register objects with HDLC layer */ 1940 rc = register_hdlc_device(dev); 1941 if (rc) { 1942 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 1943 free_netdev(dev); 1944 return rc; 1945 } 1946 1947 info->netdev = dev; 1948 return 0; 1949 } 1950 1951 /** 1952 * called by device driver when removing device instance 1953 * do generic HDLC cleanup 1954 * 1955 * info pointer to device instance information 1956 */ 1957 static void hdlcdev_exit(SLMP_INFO *info) 1958 { 1959 unregister_hdlc_device(info->netdev); 1960 free_netdev(info->netdev); 1961 info->netdev = NULL; 1962 } 1963 1964 #endif /* CONFIG_HDLC */ 1965 1966 1967 /* Return next bottom half action to perform. 1968 * Return Value: BH action code or 0 if nothing to do. 1969 */ 1970 static int bh_action(SLMP_INFO *info) 1971 { 1972 unsigned long flags; 1973 int rc = 0; 1974 1975 spin_lock_irqsave(&info->lock,flags); 1976 1977 if (info->pending_bh & BH_RECEIVE) { 1978 info->pending_bh &= ~BH_RECEIVE; 1979 rc = BH_RECEIVE; 1980 } else if (info->pending_bh & BH_TRANSMIT) { 1981 info->pending_bh &= ~BH_TRANSMIT; 1982 rc = BH_TRANSMIT; 1983 } else if (info->pending_bh & BH_STATUS) { 1984 info->pending_bh &= ~BH_STATUS; 1985 rc = BH_STATUS; 1986 } 1987 1988 if (!rc) { 1989 /* Mark BH routine as complete */ 1990 info->bh_running = false; 1991 info->bh_requested = false; 1992 } 1993 1994 spin_unlock_irqrestore(&info->lock,flags); 1995 1996 return rc; 1997 } 1998 1999 /* Perform bottom half processing of work items queued by ISR. 2000 */ 2001 static void bh_handler(struct work_struct *work) 2002 { 2003 SLMP_INFO *info = container_of(work, SLMP_INFO, task); 2004 int action; 2005 2006 if ( debug_level >= DEBUG_LEVEL_BH ) 2007 printk( "%s(%d):%s bh_handler() entry\n", 2008 __FILE__,__LINE__,info->device_name); 2009 2010 info->bh_running = true; 2011 2012 while((action = bh_action(info)) != 0) { 2013 2014 /* Process work item */ 2015 if ( debug_level >= DEBUG_LEVEL_BH ) 2016 printk( "%s(%d):%s bh_handler() work item action=%d\n", 2017 __FILE__,__LINE__,info->device_name, action); 2018 2019 switch (action) { 2020 2021 case BH_RECEIVE: 2022 bh_receive(info); 2023 break; 2024 case BH_TRANSMIT: 2025 bh_transmit(info); 2026 break; 2027 case BH_STATUS: 2028 bh_status(info); 2029 break; 2030 default: 2031 /* unknown work item ID */ 2032 printk("%s(%d):%s Unknown work item ID=%08X!\n", 2033 __FILE__,__LINE__,info->device_name,action); 2034 break; 2035 } 2036 } 2037 2038 if ( debug_level >= DEBUG_LEVEL_BH ) 2039 printk( "%s(%d):%s bh_handler() exit\n", 2040 __FILE__,__LINE__,info->device_name); 2041 } 2042 2043 static void bh_receive(SLMP_INFO *info) 2044 { 2045 if ( debug_level >= DEBUG_LEVEL_BH ) 2046 printk( "%s(%d):%s bh_receive()\n", 2047 __FILE__,__LINE__,info->device_name); 2048 2049 while( rx_get_frame(info) ); 2050 } 2051 2052 static void bh_transmit(SLMP_INFO *info) 2053 { 2054 struct tty_struct *tty = info->port.tty; 2055 2056 if ( debug_level >= DEBUG_LEVEL_BH ) 2057 printk( "%s(%d):%s bh_transmit() entry\n", 2058 __FILE__,__LINE__,info->device_name); 2059 2060 if (tty) 2061 tty_wakeup(tty); 2062 } 2063 2064 static void bh_status(SLMP_INFO *info) 2065 { 2066 if ( debug_level >= DEBUG_LEVEL_BH ) 2067 printk( "%s(%d):%s bh_status() entry\n", 2068 __FILE__,__LINE__,info->device_name); 2069 2070 info->ri_chkcount = 0; 2071 info->dsr_chkcount = 0; 2072 info->dcd_chkcount = 0; 2073 info->cts_chkcount = 0; 2074 } 2075 2076 static void isr_timer(SLMP_INFO * info) 2077 { 2078 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; 2079 2080 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */ 2081 write_reg(info, IER2, 0); 2082 2083 /* TMCS, Timer Control/Status Register 2084 * 2085 * 07 CMF, Compare match flag (read only) 1=match 2086 * 06 ECMI, CMF Interrupt Enable: 0=disabled 2087 * 05 Reserved, must be 0 2088 * 04 TME, Timer Enable 2089 * 03..00 Reserved, must be 0 2090 * 2091 * 0000 0000 2092 */ 2093 write_reg(info, (unsigned char)(timer + TMCS), 0); 2094 2095 info->irq_occurred = true; 2096 2097 if ( debug_level >= DEBUG_LEVEL_ISR ) 2098 printk("%s(%d):%s isr_timer()\n", 2099 __FILE__,__LINE__,info->device_name); 2100 } 2101 2102 static void isr_rxint(SLMP_INFO * info) 2103 { 2104 struct tty_struct *tty = info->port.tty; 2105 struct mgsl_icount *icount = &info->icount; 2106 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD); 2107 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN; 2108 2109 /* clear status bits */ 2110 if (status) 2111 write_reg(info, SR1, status); 2112 2113 if (status2) 2114 write_reg(info, SR2, status2); 2115 2116 if ( debug_level >= DEBUG_LEVEL_ISR ) 2117 printk("%s(%d):%s isr_rxint status=%02X %02x\n", 2118 __FILE__,__LINE__,info->device_name,status,status2); 2119 2120 if (info->params.mode == MGSL_MODE_ASYNC) { 2121 if (status & BRKD) { 2122 icount->brk++; 2123 2124 /* process break detection if tty control 2125 * is not set to ignore it 2126 */ 2127 if (!(status & info->ignore_status_mask1)) { 2128 if (info->read_status_mask1 & BRKD) { 2129 tty_insert_flip_char(&info->port, 0, TTY_BREAK); 2130 if (tty && (info->port.flags & ASYNC_SAK)) 2131 do_SAK(tty); 2132 } 2133 } 2134 } 2135 } 2136 else { 2137 if (status & (FLGD|IDLD)) { 2138 if (status & FLGD) 2139 info->icount.exithunt++; 2140 else if (status & IDLD) 2141 info->icount.rxidle++; 2142 wake_up_interruptible(&info->event_wait_q); 2143 } 2144 } 2145 2146 if (status & CDCD) { 2147 /* simulate a common modem status change interrupt 2148 * for our handler 2149 */ 2150 get_signals( info ); 2151 isr_io_pin(info, 2152 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD)); 2153 } 2154 } 2155 2156 /* 2157 * handle async rx data interrupts 2158 */ 2159 static void isr_rxrdy(SLMP_INFO * info) 2160 { 2161 u16 status; 2162 unsigned char DataByte; 2163 struct mgsl_icount *icount = &info->icount; 2164 2165 if ( debug_level >= DEBUG_LEVEL_ISR ) 2166 printk("%s(%d):%s isr_rxrdy\n", 2167 __FILE__,__LINE__,info->device_name); 2168 2169 while((status = read_reg(info,CST0)) & BIT0) 2170 { 2171 int flag = 0; 2172 bool over = false; 2173 DataByte = read_reg(info,TRB); 2174 2175 icount->rx++; 2176 2177 if ( status & (PE + FRME + OVRN) ) { 2178 printk("%s(%d):%s rxerr=%04X\n", 2179 __FILE__,__LINE__,info->device_name,status); 2180 2181 /* update error statistics */ 2182 if (status & PE) 2183 icount->parity++; 2184 else if (status & FRME) 2185 icount->frame++; 2186 else if (status & OVRN) 2187 icount->overrun++; 2188 2189 /* discard char if tty control flags say so */ 2190 if (status & info->ignore_status_mask2) 2191 continue; 2192 2193 status &= info->read_status_mask2; 2194 2195 if (status & PE) 2196 flag = TTY_PARITY; 2197 else if (status & FRME) 2198 flag = TTY_FRAME; 2199 if (status & OVRN) { 2200 /* Overrun is special, since it's 2201 * reported immediately, and doesn't 2202 * affect the current character 2203 */ 2204 over = true; 2205 } 2206 } /* end of if (error) */ 2207 2208 tty_insert_flip_char(&info->port, DataByte, flag); 2209 if (over) 2210 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN); 2211 } 2212 2213 if ( debug_level >= DEBUG_LEVEL_ISR ) { 2214 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n", 2215 __FILE__,__LINE__,info->device_name, 2216 icount->rx,icount->brk,icount->parity, 2217 icount->frame,icount->overrun); 2218 } 2219 2220 tty_flip_buffer_push(&info->port); 2221 } 2222 2223 static void isr_txeom(SLMP_INFO * info, unsigned char status) 2224 { 2225 if ( debug_level >= DEBUG_LEVEL_ISR ) 2226 printk("%s(%d):%s isr_txeom status=%02x\n", 2227 __FILE__,__LINE__,info->device_name,status); 2228 2229 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ 2230 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ 2231 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 2232 2233 if (status & UDRN) { 2234 write_reg(info, CMD, TXRESET); 2235 write_reg(info, CMD, TXENABLE); 2236 } else 2237 write_reg(info, CMD, TXBUFCLR); 2238 2239 /* disable and clear tx interrupts */ 2240 info->ie0_value &= ~TXRDYE; 2241 info->ie1_value &= ~(IDLE + UDRN); 2242 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); 2243 write_reg(info, SR1, (unsigned char)(UDRN + IDLE)); 2244 2245 if ( info->tx_active ) { 2246 if (info->params.mode != MGSL_MODE_ASYNC) { 2247 if (status & UDRN) 2248 info->icount.txunder++; 2249 else if (status & IDLE) 2250 info->icount.txok++; 2251 } 2252 2253 info->tx_active = false; 2254 info->tx_count = info->tx_put = info->tx_get = 0; 2255 2256 del_timer(&info->tx_timer); 2257 2258 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) { 2259 info->serial_signals &= ~SerialSignal_RTS; 2260 info->drop_rts_on_tx_done = false; 2261 set_signals(info); 2262 } 2263 2264 #if SYNCLINK_GENERIC_HDLC 2265 if (info->netcount) 2266 hdlcdev_tx_done(info); 2267 else 2268 #endif 2269 { 2270 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2271 tx_stop(info); 2272 return; 2273 } 2274 info->pending_bh |= BH_TRANSMIT; 2275 } 2276 } 2277 } 2278 2279 2280 /* 2281 * handle tx status interrupts 2282 */ 2283 static void isr_txint(SLMP_INFO * info) 2284 { 2285 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS); 2286 2287 /* clear status bits */ 2288 write_reg(info, SR1, status); 2289 2290 if ( debug_level >= DEBUG_LEVEL_ISR ) 2291 printk("%s(%d):%s isr_txint status=%02x\n", 2292 __FILE__,__LINE__,info->device_name,status); 2293 2294 if (status & (UDRN + IDLE)) 2295 isr_txeom(info, status); 2296 2297 if (status & CCTS) { 2298 /* simulate a common modem status change interrupt 2299 * for our handler 2300 */ 2301 get_signals( info ); 2302 isr_io_pin(info, 2303 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS)); 2304 2305 } 2306 } 2307 2308 /* 2309 * handle async tx data interrupts 2310 */ 2311 static void isr_txrdy(SLMP_INFO * info) 2312 { 2313 if ( debug_level >= DEBUG_LEVEL_ISR ) 2314 printk("%s(%d):%s isr_txrdy() tx_count=%d\n", 2315 __FILE__,__LINE__,info->device_name,info->tx_count); 2316 2317 if (info->params.mode != MGSL_MODE_ASYNC) { 2318 /* disable TXRDY IRQ, enable IDLE IRQ */ 2319 info->ie0_value &= ~TXRDYE; 2320 info->ie1_value |= IDLE; 2321 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); 2322 return; 2323 } 2324 2325 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2326 tx_stop(info); 2327 return; 2328 } 2329 2330 if ( info->tx_count ) 2331 tx_load_fifo( info ); 2332 else { 2333 info->tx_active = false; 2334 info->ie0_value &= ~TXRDYE; 2335 write_reg(info, IE0, info->ie0_value); 2336 } 2337 2338 if (info->tx_count < WAKEUP_CHARS) 2339 info->pending_bh |= BH_TRANSMIT; 2340 } 2341 2342 static void isr_rxdmaok(SLMP_INFO * info) 2343 { 2344 /* BIT7 = EOT (end of transfer) 2345 * BIT6 = EOM (end of message/frame) 2346 */ 2347 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0; 2348 2349 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2350 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); 2351 2352 if ( debug_level >= DEBUG_LEVEL_ISR ) 2353 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n", 2354 __FILE__,__LINE__,info->device_name,status); 2355 2356 info->pending_bh |= BH_RECEIVE; 2357 } 2358 2359 static void isr_rxdmaerror(SLMP_INFO * info) 2360 { 2361 /* BIT5 = BOF (buffer overflow) 2362 * BIT4 = COF (counter overflow) 2363 */ 2364 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30; 2365 2366 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2367 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); 2368 2369 if ( debug_level >= DEBUG_LEVEL_ISR ) 2370 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n", 2371 __FILE__,__LINE__,info->device_name,status); 2372 2373 info->rx_overflow = true; 2374 info->pending_bh |= BH_RECEIVE; 2375 } 2376 2377 static void isr_txdmaok(SLMP_INFO * info) 2378 { 2379 unsigned char status_reg1 = read_reg(info, SR1); 2380 2381 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ 2382 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ 2383 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 2384 2385 if ( debug_level >= DEBUG_LEVEL_ISR ) 2386 printk("%s(%d):%s isr_txdmaok(), status=%02x\n", 2387 __FILE__,__LINE__,info->device_name,status_reg1); 2388 2389 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */ 2390 write_reg16(info, TRC0, 0); 2391 info->ie0_value |= TXRDYE; 2392 write_reg(info, IE0, info->ie0_value); 2393 } 2394 2395 static void isr_txdmaerror(SLMP_INFO * info) 2396 { 2397 /* BIT5 = BOF (buffer overflow) 2398 * BIT4 = COF (counter overflow) 2399 */ 2400 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30; 2401 2402 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2403 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); 2404 2405 if ( debug_level >= DEBUG_LEVEL_ISR ) 2406 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n", 2407 __FILE__,__LINE__,info->device_name,status); 2408 } 2409 2410 /* handle input serial signal changes 2411 */ 2412 static void isr_io_pin( SLMP_INFO *info, u16 status ) 2413 { 2414 struct mgsl_icount *icount; 2415 2416 if ( debug_level >= DEBUG_LEVEL_ISR ) 2417 printk("%s(%d):isr_io_pin status=%04X\n", 2418 __FILE__,__LINE__,status); 2419 2420 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED | 2421 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) { 2422 icount = &info->icount; 2423 /* update input line counters */ 2424 if (status & MISCSTATUS_RI_LATCHED) { 2425 icount->rng++; 2426 if ( status & SerialSignal_RI ) 2427 info->input_signal_events.ri_up++; 2428 else 2429 info->input_signal_events.ri_down++; 2430 } 2431 if (status & MISCSTATUS_DSR_LATCHED) { 2432 icount->dsr++; 2433 if ( status & SerialSignal_DSR ) 2434 info->input_signal_events.dsr_up++; 2435 else 2436 info->input_signal_events.dsr_down++; 2437 } 2438 if (status & MISCSTATUS_DCD_LATCHED) { 2439 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { 2440 info->ie1_value &= ~CDCD; 2441 write_reg(info, IE1, info->ie1_value); 2442 } 2443 icount->dcd++; 2444 if (status & SerialSignal_DCD) { 2445 info->input_signal_events.dcd_up++; 2446 } else 2447 info->input_signal_events.dcd_down++; 2448 #if SYNCLINK_GENERIC_HDLC 2449 if (info->netcount) { 2450 if (status & SerialSignal_DCD) 2451 netif_carrier_on(info->netdev); 2452 else 2453 netif_carrier_off(info->netdev); 2454 } 2455 #endif 2456 } 2457 if (status & MISCSTATUS_CTS_LATCHED) 2458 { 2459 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { 2460 info->ie1_value &= ~CCTS; 2461 write_reg(info, IE1, info->ie1_value); 2462 } 2463 icount->cts++; 2464 if ( status & SerialSignal_CTS ) 2465 info->input_signal_events.cts_up++; 2466 else 2467 info->input_signal_events.cts_down++; 2468 } 2469 wake_up_interruptible(&info->status_event_wait_q); 2470 wake_up_interruptible(&info->event_wait_q); 2471 2472 if ( (info->port.flags & ASYNC_CHECK_CD) && 2473 (status & MISCSTATUS_DCD_LATCHED) ) { 2474 if ( debug_level >= DEBUG_LEVEL_ISR ) 2475 printk("%s CD now %s...", info->device_name, 2476 (status & SerialSignal_DCD) ? "on" : "off"); 2477 if (status & SerialSignal_DCD) 2478 wake_up_interruptible(&info->port.open_wait); 2479 else { 2480 if ( debug_level >= DEBUG_LEVEL_ISR ) 2481 printk("doing serial hangup..."); 2482 if (info->port.tty) 2483 tty_hangup(info->port.tty); 2484 } 2485 } 2486 2487 if (tty_port_cts_enabled(&info->port) && 2488 (status & MISCSTATUS_CTS_LATCHED) ) { 2489 if ( info->port.tty ) { 2490 if (info->port.tty->hw_stopped) { 2491 if (status & SerialSignal_CTS) { 2492 if ( debug_level >= DEBUG_LEVEL_ISR ) 2493 printk("CTS tx start..."); 2494 info->port.tty->hw_stopped = 0; 2495 tx_start(info); 2496 info->pending_bh |= BH_TRANSMIT; 2497 return; 2498 } 2499 } else { 2500 if (!(status & SerialSignal_CTS)) { 2501 if ( debug_level >= DEBUG_LEVEL_ISR ) 2502 printk("CTS tx stop..."); 2503 info->port.tty->hw_stopped = 1; 2504 tx_stop(info); 2505 } 2506 } 2507 } 2508 } 2509 } 2510 2511 info->pending_bh |= BH_STATUS; 2512 } 2513 2514 /* Interrupt service routine entry point. 2515 * 2516 * Arguments: 2517 * irq interrupt number that caused interrupt 2518 * dev_id device ID supplied during interrupt registration 2519 * regs interrupted processor context 2520 */ 2521 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id) 2522 { 2523 SLMP_INFO *info = dev_id; 2524 unsigned char status, status0, status1=0; 2525 unsigned char dmastatus, dmastatus0, dmastatus1=0; 2526 unsigned char timerstatus0, timerstatus1=0; 2527 unsigned char shift; 2528 unsigned int i; 2529 unsigned short tmp; 2530 2531 if ( debug_level >= DEBUG_LEVEL_ISR ) 2532 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n", 2533 __FILE__, __LINE__, info->irq_level); 2534 2535 spin_lock(&info->lock); 2536 2537 for(;;) { 2538 2539 /* get status for SCA0 (ports 0-1) */ 2540 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */ 2541 status0 = (unsigned char)tmp; 2542 dmastatus0 = (unsigned char)(tmp>>8); 2543 timerstatus0 = read_reg(info, ISR2); 2544 2545 if ( debug_level >= DEBUG_LEVEL_ISR ) 2546 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n", 2547 __FILE__, __LINE__, info->device_name, 2548 status0, dmastatus0, timerstatus0); 2549 2550 if (info->port_count == 4) { 2551 /* get status for SCA1 (ports 2-3) */ 2552 tmp = read_reg16(info->port_array[2], ISR0); 2553 status1 = (unsigned char)tmp; 2554 dmastatus1 = (unsigned char)(tmp>>8); 2555 timerstatus1 = read_reg(info->port_array[2], ISR2); 2556 2557 if ( debug_level >= DEBUG_LEVEL_ISR ) 2558 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n", 2559 __FILE__,__LINE__,info->device_name, 2560 status1,dmastatus1,timerstatus1); 2561 } 2562 2563 if (!status0 && !dmastatus0 && !timerstatus0 && 2564 !status1 && !dmastatus1 && !timerstatus1) 2565 break; 2566 2567 for(i=0; i < info->port_count ; i++) { 2568 if (info->port_array[i] == NULL) 2569 continue; 2570 if (i < 2) { 2571 status = status0; 2572 dmastatus = dmastatus0; 2573 } else { 2574 status = status1; 2575 dmastatus = dmastatus1; 2576 } 2577 2578 shift = i & 1 ? 4 :0; 2579 2580 if (status & BIT0 << shift) 2581 isr_rxrdy(info->port_array[i]); 2582 if (status & BIT1 << shift) 2583 isr_txrdy(info->port_array[i]); 2584 if (status & BIT2 << shift) 2585 isr_rxint(info->port_array[i]); 2586 if (status & BIT3 << shift) 2587 isr_txint(info->port_array[i]); 2588 2589 if (dmastatus & BIT0 << shift) 2590 isr_rxdmaerror(info->port_array[i]); 2591 if (dmastatus & BIT1 << shift) 2592 isr_rxdmaok(info->port_array[i]); 2593 if (dmastatus & BIT2 << shift) 2594 isr_txdmaerror(info->port_array[i]); 2595 if (dmastatus & BIT3 << shift) 2596 isr_txdmaok(info->port_array[i]); 2597 } 2598 2599 if (timerstatus0 & (BIT5 | BIT4)) 2600 isr_timer(info->port_array[0]); 2601 if (timerstatus0 & (BIT7 | BIT6)) 2602 isr_timer(info->port_array[1]); 2603 if (timerstatus1 & (BIT5 | BIT4)) 2604 isr_timer(info->port_array[2]); 2605 if (timerstatus1 & (BIT7 | BIT6)) 2606 isr_timer(info->port_array[3]); 2607 } 2608 2609 for(i=0; i < info->port_count ; i++) { 2610 SLMP_INFO * port = info->port_array[i]; 2611 2612 /* Request bottom half processing if there's something 2613 * for it to do and the bh is not already running. 2614 * 2615 * Note: startup adapter diags require interrupts. 2616 * do not request bottom half processing if the 2617 * device is not open in a normal mode. 2618 */ 2619 if ( port && (port->port.count || port->netcount) && 2620 port->pending_bh && !port->bh_running && 2621 !port->bh_requested ) { 2622 if ( debug_level >= DEBUG_LEVEL_ISR ) 2623 printk("%s(%d):%s queueing bh task.\n", 2624 __FILE__,__LINE__,port->device_name); 2625 schedule_work(&port->task); 2626 port->bh_requested = true; 2627 } 2628 } 2629 2630 spin_unlock(&info->lock); 2631 2632 if ( debug_level >= DEBUG_LEVEL_ISR ) 2633 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n", 2634 __FILE__, __LINE__, info->irq_level); 2635 return IRQ_HANDLED; 2636 } 2637 2638 /* Initialize and start device. 2639 */ 2640 static int startup(SLMP_INFO * info) 2641 { 2642 if ( debug_level >= DEBUG_LEVEL_INFO ) 2643 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name); 2644 2645 if (info->port.flags & ASYNC_INITIALIZED) 2646 return 0; 2647 2648 if (!info->tx_buf) { 2649 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 2650 if (!info->tx_buf) { 2651 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", 2652 __FILE__,__LINE__,info->device_name); 2653 return -ENOMEM; 2654 } 2655 } 2656 2657 info->pending_bh = 0; 2658 2659 memset(&info->icount, 0, sizeof(info->icount)); 2660 2661 /* program hardware for current parameters */ 2662 reset_port(info); 2663 2664 change_params(info); 2665 2666 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); 2667 2668 if (info->port.tty) 2669 clear_bit(TTY_IO_ERROR, &info->port.tty->flags); 2670 2671 info->port.flags |= ASYNC_INITIALIZED; 2672 2673 return 0; 2674 } 2675 2676 /* Called by close() and hangup() to shutdown hardware 2677 */ 2678 static void shutdown(SLMP_INFO * info) 2679 { 2680 unsigned long flags; 2681 2682 if (!(info->port.flags & ASYNC_INITIALIZED)) 2683 return; 2684 2685 if (debug_level >= DEBUG_LEVEL_INFO) 2686 printk("%s(%d):%s synclinkmp_shutdown()\n", 2687 __FILE__,__LINE__, info->device_name ); 2688 2689 /* clear status wait queue because status changes */ 2690 /* can't happen after shutting down the hardware */ 2691 wake_up_interruptible(&info->status_event_wait_q); 2692 wake_up_interruptible(&info->event_wait_q); 2693 2694 del_timer(&info->tx_timer); 2695 del_timer(&info->status_timer); 2696 2697 kfree(info->tx_buf); 2698 info->tx_buf = NULL; 2699 2700 spin_lock_irqsave(&info->lock,flags); 2701 2702 reset_port(info); 2703 2704 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { 2705 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2706 set_signals(info); 2707 } 2708 2709 spin_unlock_irqrestore(&info->lock,flags); 2710 2711 if (info->port.tty) 2712 set_bit(TTY_IO_ERROR, &info->port.tty->flags); 2713 2714 info->port.flags &= ~ASYNC_INITIALIZED; 2715 } 2716 2717 static void program_hw(SLMP_INFO *info) 2718 { 2719 unsigned long flags; 2720 2721 spin_lock_irqsave(&info->lock,flags); 2722 2723 rx_stop(info); 2724 tx_stop(info); 2725 2726 info->tx_count = info->tx_put = info->tx_get = 0; 2727 2728 if (info->params.mode == MGSL_MODE_HDLC || info->netcount) 2729 hdlc_mode(info); 2730 else 2731 async_mode(info); 2732 2733 set_signals(info); 2734 2735 info->dcd_chkcount = 0; 2736 info->cts_chkcount = 0; 2737 info->ri_chkcount = 0; 2738 info->dsr_chkcount = 0; 2739 2740 info->ie1_value |= (CDCD|CCTS); 2741 write_reg(info, IE1, info->ie1_value); 2742 2743 get_signals(info); 2744 2745 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) ) 2746 rx_start(info); 2747 2748 spin_unlock_irqrestore(&info->lock,flags); 2749 } 2750 2751 /* Reconfigure adapter based on new parameters 2752 */ 2753 static void change_params(SLMP_INFO *info) 2754 { 2755 unsigned cflag; 2756 int bits_per_char; 2757 2758 if (!info->port.tty) 2759 return; 2760 2761 if (debug_level >= DEBUG_LEVEL_INFO) 2762 printk("%s(%d):%s change_params()\n", 2763 __FILE__,__LINE__, info->device_name ); 2764 2765 cflag = info->port.tty->termios.c_cflag; 2766 2767 /* if B0 rate (hangup) specified then negate RTS and DTR */ 2768 /* otherwise assert RTS and DTR */ 2769 if (cflag & CBAUD) 2770 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; 2771 else 2772 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2773 2774 /* byte size and parity */ 2775 2776 switch (cflag & CSIZE) { 2777 case CS5: info->params.data_bits = 5; break; 2778 case CS6: info->params.data_bits = 6; break; 2779 case CS7: info->params.data_bits = 7; break; 2780 case CS8: info->params.data_bits = 8; break; 2781 /* Never happens, but GCC is too dumb to figure it out */ 2782 default: info->params.data_bits = 7; break; 2783 } 2784 2785 if (cflag & CSTOPB) 2786 info->params.stop_bits = 2; 2787 else 2788 info->params.stop_bits = 1; 2789 2790 info->params.parity = ASYNC_PARITY_NONE; 2791 if (cflag & PARENB) { 2792 if (cflag & PARODD) 2793 info->params.parity = ASYNC_PARITY_ODD; 2794 else 2795 info->params.parity = ASYNC_PARITY_EVEN; 2796 #ifdef CMSPAR 2797 if (cflag & CMSPAR) 2798 info->params.parity = ASYNC_PARITY_SPACE; 2799 #endif 2800 } 2801 2802 /* calculate number of jiffies to transmit a full 2803 * FIFO (32 bytes) at specified data rate 2804 */ 2805 bits_per_char = info->params.data_bits + 2806 info->params.stop_bits + 1; 2807 2808 /* if port data rate is set to 460800 or less then 2809 * allow tty settings to override, otherwise keep the 2810 * current data rate. 2811 */ 2812 if (info->params.data_rate <= 460800) { 2813 info->params.data_rate = tty_get_baud_rate(info->port.tty); 2814 } 2815 2816 if ( info->params.data_rate ) { 2817 info->timeout = (32*HZ*bits_per_char) / 2818 info->params.data_rate; 2819 } 2820 info->timeout += HZ/50; /* Add .02 seconds of slop */ 2821 2822 if (cflag & CRTSCTS) 2823 info->port.flags |= ASYNC_CTS_FLOW; 2824 else 2825 info->port.flags &= ~ASYNC_CTS_FLOW; 2826 2827 if (cflag & CLOCAL) 2828 info->port.flags &= ~ASYNC_CHECK_CD; 2829 else 2830 info->port.flags |= ASYNC_CHECK_CD; 2831 2832 /* process tty input control flags */ 2833 2834 info->read_status_mask2 = OVRN; 2835 if (I_INPCK(info->port.tty)) 2836 info->read_status_mask2 |= PE | FRME; 2837 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) 2838 info->read_status_mask1 |= BRKD; 2839 if (I_IGNPAR(info->port.tty)) 2840 info->ignore_status_mask2 |= PE | FRME; 2841 if (I_IGNBRK(info->port.tty)) { 2842 info->ignore_status_mask1 |= BRKD; 2843 /* If ignoring parity and break indicators, ignore 2844 * overruns too. (For real raw support). 2845 */ 2846 if (I_IGNPAR(info->port.tty)) 2847 info->ignore_status_mask2 |= OVRN; 2848 } 2849 2850 program_hw(info); 2851 } 2852 2853 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount) 2854 { 2855 int err; 2856 2857 if (debug_level >= DEBUG_LEVEL_INFO) 2858 printk("%s(%d):%s get_params()\n", 2859 __FILE__,__LINE__, info->device_name); 2860 2861 if (!user_icount) { 2862 memset(&info->icount, 0, sizeof(info->icount)); 2863 } else { 2864 mutex_lock(&info->port.mutex); 2865 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); 2866 mutex_unlock(&info->port.mutex); 2867 if (err) 2868 return -EFAULT; 2869 } 2870 2871 return 0; 2872 } 2873 2874 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params) 2875 { 2876 int err; 2877 if (debug_level >= DEBUG_LEVEL_INFO) 2878 printk("%s(%d):%s get_params()\n", 2879 __FILE__,__LINE__, info->device_name); 2880 2881 mutex_lock(&info->port.mutex); 2882 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); 2883 mutex_unlock(&info->port.mutex); 2884 if (err) { 2885 if ( debug_level >= DEBUG_LEVEL_INFO ) 2886 printk( "%s(%d):%s get_params() user buffer copy failed\n", 2887 __FILE__,__LINE__,info->device_name); 2888 return -EFAULT; 2889 } 2890 2891 return 0; 2892 } 2893 2894 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params) 2895 { 2896 unsigned long flags; 2897 MGSL_PARAMS tmp_params; 2898 int err; 2899 2900 if (debug_level >= DEBUG_LEVEL_INFO) 2901 printk("%s(%d):%s set_params\n", 2902 __FILE__,__LINE__,info->device_name ); 2903 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); 2904 if (err) { 2905 if ( debug_level >= DEBUG_LEVEL_INFO ) 2906 printk( "%s(%d):%s set_params() user buffer copy failed\n", 2907 __FILE__,__LINE__,info->device_name); 2908 return -EFAULT; 2909 } 2910 2911 mutex_lock(&info->port.mutex); 2912 spin_lock_irqsave(&info->lock,flags); 2913 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); 2914 spin_unlock_irqrestore(&info->lock,flags); 2915 2916 change_params(info); 2917 mutex_unlock(&info->port.mutex); 2918 2919 return 0; 2920 } 2921 2922 static int get_txidle(SLMP_INFO * info, int __user *idle_mode) 2923 { 2924 int err; 2925 2926 if (debug_level >= DEBUG_LEVEL_INFO) 2927 printk("%s(%d):%s get_txidle()=%d\n", 2928 __FILE__,__LINE__, info->device_name, info->idle_mode); 2929 2930 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); 2931 if (err) { 2932 if ( debug_level >= DEBUG_LEVEL_INFO ) 2933 printk( "%s(%d):%s get_txidle() user buffer copy failed\n", 2934 __FILE__,__LINE__,info->device_name); 2935 return -EFAULT; 2936 } 2937 2938 return 0; 2939 } 2940 2941 static int set_txidle(SLMP_INFO * info, int idle_mode) 2942 { 2943 unsigned long flags; 2944 2945 if (debug_level >= DEBUG_LEVEL_INFO) 2946 printk("%s(%d):%s set_txidle(%d)\n", 2947 __FILE__,__LINE__,info->device_name, idle_mode ); 2948 2949 spin_lock_irqsave(&info->lock,flags); 2950 info->idle_mode = idle_mode; 2951 tx_set_idle( info ); 2952 spin_unlock_irqrestore(&info->lock,flags); 2953 return 0; 2954 } 2955 2956 static int tx_enable(SLMP_INFO * info, int enable) 2957 { 2958 unsigned long flags; 2959 2960 if (debug_level >= DEBUG_LEVEL_INFO) 2961 printk("%s(%d):%s tx_enable(%d)\n", 2962 __FILE__,__LINE__,info->device_name, enable); 2963 2964 spin_lock_irqsave(&info->lock,flags); 2965 if ( enable ) { 2966 if ( !info->tx_enabled ) { 2967 tx_start(info); 2968 } 2969 } else { 2970 if ( info->tx_enabled ) 2971 tx_stop(info); 2972 } 2973 spin_unlock_irqrestore(&info->lock,flags); 2974 return 0; 2975 } 2976 2977 /* abort send HDLC frame 2978 */ 2979 static int tx_abort(SLMP_INFO * info) 2980 { 2981 unsigned long flags; 2982 2983 if (debug_level >= DEBUG_LEVEL_INFO) 2984 printk("%s(%d):%s tx_abort()\n", 2985 __FILE__,__LINE__,info->device_name); 2986 2987 spin_lock_irqsave(&info->lock,flags); 2988 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) { 2989 info->ie1_value &= ~UDRN; 2990 info->ie1_value |= IDLE; 2991 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ 2992 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ 2993 2994 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 2995 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 2996 2997 write_reg(info, CMD, TXABORT); 2998 } 2999 spin_unlock_irqrestore(&info->lock,flags); 3000 return 0; 3001 } 3002 3003 static int rx_enable(SLMP_INFO * info, int enable) 3004 { 3005 unsigned long flags; 3006 3007 if (debug_level >= DEBUG_LEVEL_INFO) 3008 printk("%s(%d):%s rx_enable(%d)\n", 3009 __FILE__,__LINE__,info->device_name,enable); 3010 3011 spin_lock_irqsave(&info->lock,flags); 3012 if ( enable ) { 3013 if ( !info->rx_enabled ) 3014 rx_start(info); 3015 } else { 3016 if ( info->rx_enabled ) 3017 rx_stop(info); 3018 } 3019 spin_unlock_irqrestore(&info->lock,flags); 3020 return 0; 3021 } 3022 3023 /* wait for specified event to occur 3024 */ 3025 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr) 3026 { 3027 unsigned long flags; 3028 int s; 3029 int rc=0; 3030 struct mgsl_icount cprev, cnow; 3031 int events; 3032 int mask; 3033 struct _input_signal_events oldsigs, newsigs; 3034 DECLARE_WAITQUEUE(wait, current); 3035 3036 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); 3037 if (rc) { 3038 return -EFAULT; 3039 } 3040 3041 if (debug_level >= DEBUG_LEVEL_INFO) 3042 printk("%s(%d):%s wait_mgsl_event(%d)\n", 3043 __FILE__,__LINE__,info->device_name,mask); 3044 3045 spin_lock_irqsave(&info->lock,flags); 3046 3047 /* return immediately if state matches requested events */ 3048 get_signals(info); 3049 s = info->serial_signals; 3050 3051 events = mask & 3052 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 3053 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 3054 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 3055 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 3056 if (events) { 3057 spin_unlock_irqrestore(&info->lock,flags); 3058 goto exit; 3059 } 3060 3061 /* save current irq counts */ 3062 cprev = info->icount; 3063 oldsigs = info->input_signal_events; 3064 3065 /* enable hunt and idle irqs if needed */ 3066 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { 3067 unsigned char oldval = info->ie1_value; 3068 unsigned char newval = oldval + 3069 (mask & MgslEvent_ExitHuntMode ? FLGD:0) + 3070 (mask & MgslEvent_IdleReceived ? IDLD:0); 3071 if ( oldval != newval ) { 3072 info->ie1_value = newval; 3073 write_reg(info, IE1, info->ie1_value); 3074 } 3075 } 3076 3077 set_current_state(TASK_INTERRUPTIBLE); 3078 add_wait_queue(&info->event_wait_q, &wait); 3079 3080 spin_unlock_irqrestore(&info->lock,flags); 3081 3082 for(;;) { 3083 schedule(); 3084 if (signal_pending(current)) { 3085 rc = -ERESTARTSYS; 3086 break; 3087 } 3088 3089 /* get current irq counts */ 3090 spin_lock_irqsave(&info->lock,flags); 3091 cnow = info->icount; 3092 newsigs = info->input_signal_events; 3093 set_current_state(TASK_INTERRUPTIBLE); 3094 spin_unlock_irqrestore(&info->lock,flags); 3095 3096 /* if no change, wait aborted for some reason */ 3097 if (newsigs.dsr_up == oldsigs.dsr_up && 3098 newsigs.dsr_down == oldsigs.dsr_down && 3099 newsigs.dcd_up == oldsigs.dcd_up && 3100 newsigs.dcd_down == oldsigs.dcd_down && 3101 newsigs.cts_up == oldsigs.cts_up && 3102 newsigs.cts_down == oldsigs.cts_down && 3103 newsigs.ri_up == oldsigs.ri_up && 3104 newsigs.ri_down == oldsigs.ri_down && 3105 cnow.exithunt == cprev.exithunt && 3106 cnow.rxidle == cprev.rxidle) { 3107 rc = -EIO; 3108 break; 3109 } 3110 3111 events = mask & 3112 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 3113 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 3114 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 3115 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 3116 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 3117 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 3118 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 3119 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 3120 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 3121 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 3122 if (events) 3123 break; 3124 3125 cprev = cnow; 3126 oldsigs = newsigs; 3127 } 3128 3129 remove_wait_queue(&info->event_wait_q, &wait); 3130 set_current_state(TASK_RUNNING); 3131 3132 3133 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { 3134 spin_lock_irqsave(&info->lock,flags); 3135 if (!waitqueue_active(&info->event_wait_q)) { 3136 /* disable enable exit hunt mode/idle rcvd IRQs */ 3137 info->ie1_value &= ~(FLGD|IDLD); 3138 write_reg(info, IE1, info->ie1_value); 3139 } 3140 spin_unlock_irqrestore(&info->lock,flags); 3141 } 3142 exit: 3143 if ( rc == 0 ) 3144 PUT_USER(rc, events, mask_ptr); 3145 3146 return rc; 3147 } 3148 3149 static int modem_input_wait(SLMP_INFO *info,int arg) 3150 { 3151 unsigned long flags; 3152 int rc; 3153 struct mgsl_icount cprev, cnow; 3154 DECLARE_WAITQUEUE(wait, current); 3155 3156 /* save current irq counts */ 3157 spin_lock_irqsave(&info->lock,flags); 3158 cprev = info->icount; 3159 add_wait_queue(&info->status_event_wait_q, &wait); 3160 set_current_state(TASK_INTERRUPTIBLE); 3161 spin_unlock_irqrestore(&info->lock,flags); 3162 3163 for(;;) { 3164 schedule(); 3165 if (signal_pending(current)) { 3166 rc = -ERESTARTSYS; 3167 break; 3168 } 3169 3170 /* get new irq counts */ 3171 spin_lock_irqsave(&info->lock,flags); 3172 cnow = info->icount; 3173 set_current_state(TASK_INTERRUPTIBLE); 3174 spin_unlock_irqrestore(&info->lock,flags); 3175 3176 /* if no change, wait aborted for some reason */ 3177 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 3178 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 3179 rc = -EIO; 3180 break; 3181 } 3182 3183 /* check for change in caller specified modem input */ 3184 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 3185 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 3186 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 3187 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 3188 rc = 0; 3189 break; 3190 } 3191 3192 cprev = cnow; 3193 } 3194 remove_wait_queue(&info->status_event_wait_q, &wait); 3195 set_current_state(TASK_RUNNING); 3196 return rc; 3197 } 3198 3199 /* return the state of the serial control and status signals 3200 */ 3201 static int tiocmget(struct tty_struct *tty) 3202 { 3203 SLMP_INFO *info = tty->driver_data; 3204 unsigned int result; 3205 unsigned long flags; 3206 3207 spin_lock_irqsave(&info->lock,flags); 3208 get_signals(info); 3209 spin_unlock_irqrestore(&info->lock,flags); 3210 3211 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) | 3212 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) | 3213 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) | 3214 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) | 3215 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) | 3216 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0); 3217 3218 if (debug_level >= DEBUG_LEVEL_INFO) 3219 printk("%s(%d):%s tiocmget() value=%08X\n", 3220 __FILE__,__LINE__, info->device_name, result ); 3221 return result; 3222 } 3223 3224 /* set modem control signals (DTR/RTS) 3225 */ 3226 static int tiocmset(struct tty_struct *tty, 3227 unsigned int set, unsigned int clear) 3228 { 3229 SLMP_INFO *info = tty->driver_data; 3230 unsigned long flags; 3231 3232 if (debug_level >= DEBUG_LEVEL_INFO) 3233 printk("%s(%d):%s tiocmset(%x,%x)\n", 3234 __FILE__,__LINE__,info->device_name, set, clear); 3235 3236 if (set & TIOCM_RTS) 3237 info->serial_signals |= SerialSignal_RTS; 3238 if (set & TIOCM_DTR) 3239 info->serial_signals |= SerialSignal_DTR; 3240 if (clear & TIOCM_RTS) 3241 info->serial_signals &= ~SerialSignal_RTS; 3242 if (clear & TIOCM_DTR) 3243 info->serial_signals &= ~SerialSignal_DTR; 3244 3245 spin_lock_irqsave(&info->lock,flags); 3246 set_signals(info); 3247 spin_unlock_irqrestore(&info->lock,flags); 3248 3249 return 0; 3250 } 3251 3252 static int carrier_raised(struct tty_port *port) 3253 { 3254 SLMP_INFO *info = container_of(port, SLMP_INFO, port); 3255 unsigned long flags; 3256 3257 spin_lock_irqsave(&info->lock,flags); 3258 get_signals(info); 3259 spin_unlock_irqrestore(&info->lock,flags); 3260 3261 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0; 3262 } 3263 3264 static void dtr_rts(struct tty_port *port, int on) 3265 { 3266 SLMP_INFO *info = container_of(port, SLMP_INFO, port); 3267 unsigned long flags; 3268 3269 spin_lock_irqsave(&info->lock,flags); 3270 if (on) 3271 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; 3272 else 3273 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 3274 set_signals(info); 3275 spin_unlock_irqrestore(&info->lock,flags); 3276 } 3277 3278 /* Block the current process until the specified port is ready to open. 3279 */ 3280 static int block_til_ready(struct tty_struct *tty, struct file *filp, 3281 SLMP_INFO *info) 3282 { 3283 DECLARE_WAITQUEUE(wait, current); 3284 int retval; 3285 bool do_clocal = false; 3286 unsigned long flags; 3287 int cd; 3288 struct tty_port *port = &info->port; 3289 3290 if (debug_level >= DEBUG_LEVEL_INFO) 3291 printk("%s(%d):%s block_til_ready()\n", 3292 __FILE__,__LINE__, tty->driver->name ); 3293 3294 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ 3295 /* nonblock mode is set or port is not enabled */ 3296 /* just verify that callout device is not active */ 3297 port->flags |= ASYNC_NORMAL_ACTIVE; 3298 return 0; 3299 } 3300 3301 if (tty->termios.c_cflag & CLOCAL) 3302 do_clocal = true; 3303 3304 /* Wait for carrier detect and the line to become 3305 * free (i.e., not in use by the callout). While we are in 3306 * this loop, port->count is dropped by one, so that 3307 * close() knows when to free things. We restore it upon 3308 * exit, either normal or abnormal. 3309 */ 3310 3311 retval = 0; 3312 add_wait_queue(&port->open_wait, &wait); 3313 3314 if (debug_level >= DEBUG_LEVEL_INFO) 3315 printk("%s(%d):%s block_til_ready() before block, count=%d\n", 3316 __FILE__,__LINE__, tty->driver->name, port->count ); 3317 3318 spin_lock_irqsave(&info->lock, flags); 3319 port->count--; 3320 spin_unlock_irqrestore(&info->lock, flags); 3321 port->blocked_open++; 3322 3323 while (1) { 3324 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags)) 3325 tty_port_raise_dtr_rts(port); 3326 3327 set_current_state(TASK_INTERRUPTIBLE); 3328 3329 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ 3330 retval = (port->flags & ASYNC_HUP_NOTIFY) ? 3331 -EAGAIN : -ERESTARTSYS; 3332 break; 3333 } 3334 3335 cd = tty_port_carrier_raised(port); 3336 if (do_clocal || cd) 3337 break; 3338 3339 if (signal_pending(current)) { 3340 retval = -ERESTARTSYS; 3341 break; 3342 } 3343 3344 if (debug_level >= DEBUG_LEVEL_INFO) 3345 printk("%s(%d):%s block_til_ready() count=%d\n", 3346 __FILE__,__LINE__, tty->driver->name, port->count ); 3347 3348 tty_unlock(tty); 3349 schedule(); 3350 tty_lock(tty); 3351 } 3352 3353 set_current_state(TASK_RUNNING); 3354 remove_wait_queue(&port->open_wait, &wait); 3355 if (!tty_hung_up_p(filp)) 3356 port->count++; 3357 port->blocked_open--; 3358 3359 if (debug_level >= DEBUG_LEVEL_INFO) 3360 printk("%s(%d):%s block_til_ready() after, count=%d\n", 3361 __FILE__,__LINE__, tty->driver->name, port->count ); 3362 3363 if (!retval) 3364 port->flags |= ASYNC_NORMAL_ACTIVE; 3365 3366 return retval; 3367 } 3368 3369 static int alloc_dma_bufs(SLMP_INFO *info) 3370 { 3371 unsigned short BuffersPerFrame; 3372 unsigned short BufferCount; 3373 3374 // Force allocation to start at 64K boundary for each port. 3375 // This is necessary because *all* buffer descriptors for a port 3376 // *must* be in the same 64K block. All descriptors on a port 3377 // share a common 'base' address (upper 8 bits of 24 bits) programmed 3378 // into the CBP register. 3379 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num; 3380 3381 /* Calculate the number of DMA buffers necessary to hold the */ 3382 /* largest allowable frame size. Note: If the max frame size is */ 3383 /* not an even multiple of the DMA buffer size then we need to */ 3384 /* round the buffer count per frame up one. */ 3385 3386 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE); 3387 if ( info->max_frame_size % SCABUFSIZE ) 3388 BuffersPerFrame++; 3389 3390 /* calculate total number of data buffers (SCABUFSIZE) possible 3391 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory 3392 * for the descriptor list (BUFFERLISTSIZE). 3393 */ 3394 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE; 3395 3396 /* limit number of buffers to maximum amount of descriptors */ 3397 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC)) 3398 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC); 3399 3400 /* use enough buffers to transmit one max size frame */ 3401 info->tx_buf_count = BuffersPerFrame + 1; 3402 3403 /* never use more than half the available buffers for transmit */ 3404 if (info->tx_buf_count > (BufferCount/2)) 3405 info->tx_buf_count = BufferCount/2; 3406 3407 if (info->tx_buf_count > SCAMAXDESC) 3408 info->tx_buf_count = SCAMAXDESC; 3409 3410 /* use remaining buffers for receive */ 3411 info->rx_buf_count = BufferCount - info->tx_buf_count; 3412 3413 if (info->rx_buf_count > SCAMAXDESC) 3414 info->rx_buf_count = SCAMAXDESC; 3415 3416 if ( debug_level >= DEBUG_LEVEL_INFO ) 3417 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n", 3418 __FILE__,__LINE__, info->device_name, 3419 info->tx_buf_count,info->rx_buf_count); 3420 3421 if ( alloc_buf_list( info ) < 0 || 3422 alloc_frame_bufs(info, 3423 info->rx_buf_list, 3424 info->rx_buf_list_ex, 3425 info->rx_buf_count) < 0 || 3426 alloc_frame_bufs(info, 3427 info->tx_buf_list, 3428 info->tx_buf_list_ex, 3429 info->tx_buf_count) < 0 || 3430 alloc_tmp_rx_buf(info) < 0 ) { 3431 printk("%s(%d):%s Can't allocate DMA buffer memory\n", 3432 __FILE__,__LINE__, info->device_name); 3433 return -ENOMEM; 3434 } 3435 3436 rx_reset_buffers( info ); 3437 3438 return 0; 3439 } 3440 3441 /* Allocate DMA buffers for the transmit and receive descriptor lists. 3442 */ 3443 static int alloc_buf_list(SLMP_INFO *info) 3444 { 3445 unsigned int i; 3446 3447 /* build list in adapter shared memory */ 3448 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc; 3449 info->buffer_list_phys = info->port_array[0]->last_mem_alloc; 3450 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE; 3451 3452 memset(info->buffer_list, 0, BUFFERLISTSIZE); 3453 3454 /* Save virtual address pointers to the receive and */ 3455 /* transmit buffer lists. (Receive 1st). These pointers will */ 3456 /* be used by the processor to access the lists. */ 3457 info->rx_buf_list = (SCADESC *)info->buffer_list; 3458 3459 info->tx_buf_list = (SCADESC *)info->buffer_list; 3460 info->tx_buf_list += info->rx_buf_count; 3461 3462 /* Build links for circular buffer entry lists (tx and rx) 3463 * 3464 * Note: links are physical addresses read by the SCA device 3465 * to determine the next buffer entry to use. 3466 */ 3467 3468 for ( i = 0; i < info->rx_buf_count; i++ ) { 3469 /* calculate and store physical address of this buffer entry */ 3470 info->rx_buf_list_ex[i].phys_entry = 3471 info->buffer_list_phys + (i * SCABUFSIZE); 3472 3473 /* calculate and store physical address of */ 3474 /* next entry in cirular list of entries */ 3475 info->rx_buf_list[i].next = info->buffer_list_phys; 3476 if ( i < info->rx_buf_count - 1 ) 3477 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC); 3478 3479 info->rx_buf_list[i].length = SCABUFSIZE; 3480 } 3481 3482 for ( i = 0; i < info->tx_buf_count; i++ ) { 3483 /* calculate and store physical address of this buffer entry */ 3484 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys + 3485 ((info->rx_buf_count + i) * sizeof(SCADESC)); 3486 3487 /* calculate and store physical address of */ 3488 /* next entry in cirular list of entries */ 3489 3490 info->tx_buf_list[i].next = info->buffer_list_phys + 3491 info->rx_buf_count * sizeof(SCADESC); 3492 3493 if ( i < info->tx_buf_count - 1 ) 3494 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC); 3495 } 3496 3497 return 0; 3498 } 3499 3500 /* Allocate the frame DMA buffers used by the specified buffer list. 3501 */ 3502 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count) 3503 { 3504 int i; 3505 unsigned long phys_addr; 3506 3507 for ( i = 0; i < count; i++ ) { 3508 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc; 3509 phys_addr = info->port_array[0]->last_mem_alloc; 3510 info->port_array[0]->last_mem_alloc += SCABUFSIZE; 3511 3512 buf_list[i].buf_ptr = (unsigned short)phys_addr; 3513 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16); 3514 } 3515 3516 return 0; 3517 } 3518 3519 static void free_dma_bufs(SLMP_INFO *info) 3520 { 3521 info->buffer_list = NULL; 3522 info->rx_buf_list = NULL; 3523 info->tx_buf_list = NULL; 3524 } 3525 3526 /* allocate buffer large enough to hold max_frame_size. 3527 * This buffer is used to pass an assembled frame to the line discipline. 3528 */ 3529 static int alloc_tmp_rx_buf(SLMP_INFO *info) 3530 { 3531 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 3532 if (info->tmp_rx_buf == NULL) 3533 return -ENOMEM; 3534 /* unused flag buffer to satisfy receive_buf calling interface */ 3535 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL); 3536 if (!info->flag_buf) { 3537 kfree(info->tmp_rx_buf); 3538 info->tmp_rx_buf = NULL; 3539 return -ENOMEM; 3540 } 3541 return 0; 3542 } 3543 3544 static void free_tmp_rx_buf(SLMP_INFO *info) 3545 { 3546 kfree(info->tmp_rx_buf); 3547 info->tmp_rx_buf = NULL; 3548 kfree(info->flag_buf); 3549 info->flag_buf = NULL; 3550 } 3551 3552 static int claim_resources(SLMP_INFO *info) 3553 { 3554 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) { 3555 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n", 3556 __FILE__,__LINE__,info->device_name, info->phys_memory_base); 3557 info->init_error = DiagStatus_AddressConflict; 3558 goto errout; 3559 } 3560 else 3561 info->shared_mem_requested = true; 3562 3563 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) { 3564 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n", 3565 __FILE__,__LINE__,info->device_name, info->phys_lcr_base); 3566 info->init_error = DiagStatus_AddressConflict; 3567 goto errout; 3568 } 3569 else 3570 info->lcr_mem_requested = true; 3571 3572 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) { 3573 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n", 3574 __FILE__,__LINE__,info->device_name, info->phys_sca_base); 3575 info->init_error = DiagStatus_AddressConflict; 3576 goto errout; 3577 } 3578 else 3579 info->sca_base_requested = true; 3580 3581 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) { 3582 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n", 3583 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base); 3584 info->init_error = DiagStatus_AddressConflict; 3585 goto errout; 3586 } 3587 else 3588 info->sca_statctrl_requested = true; 3589 3590 info->memory_base = ioremap_nocache(info->phys_memory_base, 3591 SCA_MEM_SIZE); 3592 if (!info->memory_base) { 3593 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n", 3594 __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 3595 info->init_error = DiagStatus_CantAssignPciResources; 3596 goto errout; 3597 } 3598 3599 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE); 3600 if (!info->lcr_base) { 3601 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n", 3602 __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); 3603 info->init_error = DiagStatus_CantAssignPciResources; 3604 goto errout; 3605 } 3606 info->lcr_base += info->lcr_offset; 3607 3608 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE); 3609 if (!info->sca_base) { 3610 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n", 3611 __FILE__,__LINE__,info->device_name, info->phys_sca_base ); 3612 info->init_error = DiagStatus_CantAssignPciResources; 3613 goto errout; 3614 } 3615 info->sca_base += info->sca_offset; 3616 3617 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base, 3618 PAGE_SIZE); 3619 if (!info->statctrl_base) { 3620 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n", 3621 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base ); 3622 info->init_error = DiagStatus_CantAssignPciResources; 3623 goto errout; 3624 } 3625 info->statctrl_base += info->statctrl_offset; 3626 3627 if ( !memory_test(info) ) { 3628 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n", 3629 __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 3630 info->init_error = DiagStatus_MemoryError; 3631 goto errout; 3632 } 3633 3634 return 0; 3635 3636 errout: 3637 release_resources( info ); 3638 return -ENODEV; 3639 } 3640 3641 static void release_resources(SLMP_INFO *info) 3642 { 3643 if ( debug_level >= DEBUG_LEVEL_INFO ) 3644 printk( "%s(%d):%s release_resources() entry\n", 3645 __FILE__,__LINE__,info->device_name ); 3646 3647 if ( info->irq_requested ) { 3648 free_irq(info->irq_level, info); 3649 info->irq_requested = false; 3650 } 3651 3652 if ( info->shared_mem_requested ) { 3653 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE); 3654 info->shared_mem_requested = false; 3655 } 3656 if ( info->lcr_mem_requested ) { 3657 release_mem_region(info->phys_lcr_base + info->lcr_offset,128); 3658 info->lcr_mem_requested = false; 3659 } 3660 if ( info->sca_base_requested ) { 3661 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE); 3662 info->sca_base_requested = false; 3663 } 3664 if ( info->sca_statctrl_requested ) { 3665 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE); 3666 info->sca_statctrl_requested = false; 3667 } 3668 3669 if (info->memory_base){ 3670 iounmap(info->memory_base); 3671 info->memory_base = NULL; 3672 } 3673 3674 if (info->sca_base) { 3675 iounmap(info->sca_base - info->sca_offset); 3676 info->sca_base=NULL; 3677 } 3678 3679 if (info->statctrl_base) { 3680 iounmap(info->statctrl_base - info->statctrl_offset); 3681 info->statctrl_base=NULL; 3682 } 3683 3684 if (info->lcr_base){ 3685 iounmap(info->lcr_base - info->lcr_offset); 3686 info->lcr_base = NULL; 3687 } 3688 3689 if ( debug_level >= DEBUG_LEVEL_INFO ) 3690 printk( "%s(%d):%s release_resources() exit\n", 3691 __FILE__,__LINE__,info->device_name ); 3692 } 3693 3694 /* Add the specified device instance data structure to the 3695 * global linked list of devices and increment the device count. 3696 */ 3697 static void add_device(SLMP_INFO *info) 3698 { 3699 info->next_device = NULL; 3700 info->line = synclinkmp_device_count; 3701 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num); 3702 3703 if (info->line < MAX_DEVICES) { 3704 if (maxframe[info->line]) 3705 info->max_frame_size = maxframe[info->line]; 3706 } 3707 3708 synclinkmp_device_count++; 3709 3710 if ( !synclinkmp_device_list ) 3711 synclinkmp_device_list = info; 3712 else { 3713 SLMP_INFO *current_dev = synclinkmp_device_list; 3714 while( current_dev->next_device ) 3715 current_dev = current_dev->next_device; 3716 current_dev->next_device = info; 3717 } 3718 3719 if ( info->max_frame_size < 4096 ) 3720 info->max_frame_size = 4096; 3721 else if ( info->max_frame_size > 65535 ) 3722 info->max_frame_size = 65535; 3723 3724 printk( "SyncLink MultiPort %s: " 3725 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", 3726 info->device_name, 3727 info->phys_sca_base, 3728 info->phys_memory_base, 3729 info->phys_statctrl_base, 3730 info->phys_lcr_base, 3731 info->irq_level, 3732 info->max_frame_size ); 3733 3734 #if SYNCLINK_GENERIC_HDLC 3735 hdlcdev_init(info); 3736 #endif 3737 } 3738 3739 static const struct tty_port_operations port_ops = { 3740 .carrier_raised = carrier_raised, 3741 .dtr_rts = dtr_rts, 3742 }; 3743 3744 /* Allocate and initialize a device instance structure 3745 * 3746 * Return Value: pointer to SLMP_INFO if success, otherwise NULL 3747 */ 3748 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) 3749 { 3750 SLMP_INFO *info; 3751 3752 info = kzalloc(sizeof(SLMP_INFO), 3753 GFP_KERNEL); 3754 3755 if (!info) { 3756 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n", 3757 __FILE__,__LINE__, adapter_num, port_num); 3758 } else { 3759 tty_port_init(&info->port); 3760 info->port.ops = &port_ops; 3761 info->magic = MGSL_MAGIC; 3762 INIT_WORK(&info->task, bh_handler); 3763 info->max_frame_size = 4096; 3764 info->port.close_delay = 5*HZ/10; 3765 info->port.closing_wait = 30*HZ; 3766 init_waitqueue_head(&info->status_event_wait_q); 3767 init_waitqueue_head(&info->event_wait_q); 3768 spin_lock_init(&info->netlock); 3769 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 3770 info->idle_mode = HDLC_TXIDLE_FLAGS; 3771 info->adapter_num = adapter_num; 3772 info->port_num = port_num; 3773 3774 /* Copy configuration info to device instance data */ 3775 info->irq_level = pdev->irq; 3776 info->phys_lcr_base = pci_resource_start(pdev,0); 3777 info->phys_sca_base = pci_resource_start(pdev,2); 3778 info->phys_memory_base = pci_resource_start(pdev,3); 3779 info->phys_statctrl_base = pci_resource_start(pdev,4); 3780 3781 /* Because veremap only works on page boundaries we must map 3782 * a larger area than is actually implemented for the LCR 3783 * memory range. We map a full page starting at the page boundary. 3784 */ 3785 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1); 3786 info->phys_lcr_base &= ~(PAGE_SIZE-1); 3787 3788 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1); 3789 info->phys_sca_base &= ~(PAGE_SIZE-1); 3790 3791 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1); 3792 info->phys_statctrl_base &= ~(PAGE_SIZE-1); 3793 3794 info->bus_type = MGSL_BUS_TYPE_PCI; 3795 info->irq_flags = IRQF_SHARED; 3796 3797 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); 3798 setup_timer(&info->status_timer, status_timeout, 3799 (unsigned long)info); 3800 3801 /* Store the PCI9050 misc control register value because a flaw 3802 * in the PCI9050 prevents LCR registers from being read if 3803 * BIOS assigns an LCR base address with bit 7 set. 3804 * 3805 * Only the misc control register is accessed for which only 3806 * write access is needed, so set an initial value and change 3807 * bits to the device instance data as we write the value 3808 * to the actual misc control register. 3809 */ 3810 info->misc_ctrl_value = 0x087e4546; 3811 3812 /* initial port state is unknown - if startup errors 3813 * occur, init_error will be set to indicate the 3814 * problem. Once the port is fully initialized, 3815 * this value will be set to 0 to indicate the 3816 * port is available. 3817 */ 3818 info->init_error = -1; 3819 } 3820 3821 return info; 3822 } 3823 3824 static void device_init(int adapter_num, struct pci_dev *pdev) 3825 { 3826 SLMP_INFO *port_array[SCA_MAX_PORTS]; 3827 int port; 3828 3829 /* allocate device instances for up to SCA_MAX_PORTS devices */ 3830 for ( port = 0; port < SCA_MAX_PORTS; ++port ) { 3831 port_array[port] = alloc_dev(adapter_num,port,pdev); 3832 if( port_array[port] == NULL ) { 3833 for (--port; port >= 0; --port) { 3834 tty_port_destroy(&port_array[port]->port); 3835 kfree(port_array[port]); 3836 } 3837 return; 3838 } 3839 } 3840 3841 /* give copy of port_array to all ports and add to device list */ 3842 for ( port = 0; port < SCA_MAX_PORTS; ++port ) { 3843 memcpy(port_array[port]->port_array,port_array,sizeof(port_array)); 3844 add_device( port_array[port] ); 3845 spin_lock_init(&port_array[port]->lock); 3846 } 3847 3848 /* Allocate and claim adapter resources */ 3849 if ( !claim_resources(port_array[0]) ) { 3850 3851 alloc_dma_bufs(port_array[0]); 3852 3853 /* copy resource information from first port to others */ 3854 for ( port = 1; port < SCA_MAX_PORTS; ++port ) { 3855 port_array[port]->lock = port_array[0]->lock; 3856 port_array[port]->irq_level = port_array[0]->irq_level; 3857 port_array[port]->memory_base = port_array[0]->memory_base; 3858 port_array[port]->sca_base = port_array[0]->sca_base; 3859 port_array[port]->statctrl_base = port_array[0]->statctrl_base; 3860 port_array[port]->lcr_base = port_array[0]->lcr_base; 3861 alloc_dma_bufs(port_array[port]); 3862 } 3863 3864 if ( request_irq(port_array[0]->irq_level, 3865 synclinkmp_interrupt, 3866 port_array[0]->irq_flags, 3867 port_array[0]->device_name, 3868 port_array[0]) < 0 ) { 3869 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n", 3870 __FILE__,__LINE__, 3871 port_array[0]->device_name, 3872 port_array[0]->irq_level ); 3873 } 3874 else { 3875 port_array[0]->irq_requested = true; 3876 adapter_test(port_array[0]); 3877 } 3878 } 3879 } 3880 3881 static const struct tty_operations ops = { 3882 .install = install, 3883 .open = open, 3884 .close = close, 3885 .write = write, 3886 .put_char = put_char, 3887 .flush_chars = flush_chars, 3888 .write_room = write_room, 3889 .chars_in_buffer = chars_in_buffer, 3890 .flush_buffer = flush_buffer, 3891 .ioctl = ioctl, 3892 .throttle = throttle, 3893 .unthrottle = unthrottle, 3894 .send_xchar = send_xchar, 3895 .break_ctl = set_break, 3896 .wait_until_sent = wait_until_sent, 3897 .set_termios = set_termios, 3898 .stop = tx_hold, 3899 .start = tx_release, 3900 .hangup = hangup, 3901 .tiocmget = tiocmget, 3902 .tiocmset = tiocmset, 3903 .get_icount = get_icount, 3904 .proc_fops = &synclinkmp_proc_fops, 3905 }; 3906 3907 3908 static void synclinkmp_cleanup(void) 3909 { 3910 int rc; 3911 SLMP_INFO *info; 3912 SLMP_INFO *tmp; 3913 3914 printk("Unloading %s %s\n", driver_name, driver_version); 3915 3916 if (serial_driver) { 3917 rc = tty_unregister_driver(serial_driver); 3918 if (rc) 3919 printk("%s(%d) failed to unregister tty driver err=%d\n", 3920 __FILE__,__LINE__,rc); 3921 put_tty_driver(serial_driver); 3922 } 3923 3924 /* reset devices */ 3925 info = synclinkmp_device_list; 3926 while(info) { 3927 reset_port(info); 3928 info = info->next_device; 3929 } 3930 3931 /* release devices */ 3932 info = synclinkmp_device_list; 3933 while(info) { 3934 #if SYNCLINK_GENERIC_HDLC 3935 hdlcdev_exit(info); 3936 #endif 3937 free_dma_bufs(info); 3938 free_tmp_rx_buf(info); 3939 if ( info->port_num == 0 ) { 3940 if (info->sca_base) 3941 write_reg(info, LPR, 1); /* set low power mode */ 3942 release_resources(info); 3943 } 3944 tmp = info; 3945 info = info->next_device; 3946 tty_port_destroy(&tmp->port); 3947 kfree(tmp); 3948 } 3949 3950 pci_unregister_driver(&synclinkmp_pci_driver); 3951 } 3952 3953 /* Driver initialization entry point. 3954 */ 3955 3956 static int __init synclinkmp_init(void) 3957 { 3958 int rc; 3959 3960 if (break_on_load) { 3961 synclinkmp_get_text_ptr(); 3962 BREAKPOINT(); 3963 } 3964 3965 printk("%s %s\n", driver_name, driver_version); 3966 3967 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) { 3968 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); 3969 return rc; 3970 } 3971 3972 serial_driver = alloc_tty_driver(128); 3973 if (!serial_driver) { 3974 rc = -ENOMEM; 3975 goto error; 3976 } 3977 3978 /* Initialize the tty_driver structure */ 3979 3980 serial_driver->driver_name = "synclinkmp"; 3981 serial_driver->name = "ttySLM"; 3982 serial_driver->major = ttymajor; 3983 serial_driver->minor_start = 64; 3984 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 3985 serial_driver->subtype = SERIAL_TYPE_NORMAL; 3986 serial_driver->init_termios = tty_std_termios; 3987 serial_driver->init_termios.c_cflag = 3988 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 3989 serial_driver->init_termios.c_ispeed = 9600; 3990 serial_driver->init_termios.c_ospeed = 9600; 3991 serial_driver->flags = TTY_DRIVER_REAL_RAW; 3992 tty_set_operations(serial_driver, &ops); 3993 if ((rc = tty_register_driver(serial_driver)) < 0) { 3994 printk("%s(%d):Couldn't register serial driver\n", 3995 __FILE__,__LINE__); 3996 put_tty_driver(serial_driver); 3997 serial_driver = NULL; 3998 goto error; 3999 } 4000 4001 printk("%s %s, tty major#%d\n", 4002 driver_name, driver_version, 4003 serial_driver->major); 4004 4005 return 0; 4006 4007 error: 4008 synclinkmp_cleanup(); 4009 return rc; 4010 } 4011 4012 static void __exit synclinkmp_exit(void) 4013 { 4014 synclinkmp_cleanup(); 4015 } 4016 4017 module_init(synclinkmp_init); 4018 module_exit(synclinkmp_exit); 4019 4020 /* Set the port for internal loopback mode. 4021 * The TxCLK and RxCLK signals are generated from the BRG and 4022 * the TxD is looped back to the RxD internally. 4023 */ 4024 static void enable_loopback(SLMP_INFO *info, int enable) 4025 { 4026 if (enable) { 4027 /* MD2 (Mode Register 2) 4028 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback 4029 */ 4030 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); 4031 4032 /* degate external TxC clock source */ 4033 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4034 write_control_reg(info); 4035 4036 /* RXS/TXS (Rx/Tx clock source) 4037 * 07 Reserved, must be 0 4038 * 06..04 Clock Source, 100=BRG 4039 * 03..00 Clock Divisor, 0000=1 4040 */ 4041 write_reg(info, RXS, 0x40); 4042 write_reg(info, TXS, 0x40); 4043 4044 } else { 4045 /* MD2 (Mode Register 2) 4046 * 01..00 CNCT<1..0> Channel connection, 0=normal 4047 */ 4048 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); 4049 4050 /* RXS/TXS (Rx/Tx clock source) 4051 * 07 Reserved, must be 0 4052 * 06..04 Clock Source, 000=RxC/TxC Pin 4053 * 03..00 Clock Divisor, 0000=1 4054 */ 4055 write_reg(info, RXS, 0x00); 4056 write_reg(info, TXS, 0x00); 4057 } 4058 4059 /* set LinkSpeed if available, otherwise default to 2Mbps */ 4060 if (info->params.clock_speed) 4061 set_rate(info, info->params.clock_speed); 4062 else 4063 set_rate(info, 3686400); 4064 } 4065 4066 /* Set the baud rate register to the desired speed 4067 * 4068 * data_rate data rate of clock in bits per second 4069 * A data rate of 0 disables the AUX clock. 4070 */ 4071 static void set_rate( SLMP_INFO *info, u32 data_rate ) 4072 { 4073 u32 TMCValue; 4074 unsigned char BRValue; 4075 u32 Divisor=0; 4076 4077 /* fBRG = fCLK/(TMC * 2^BR) 4078 */ 4079 if (data_rate != 0) { 4080 Divisor = 14745600/data_rate; 4081 if (!Divisor) 4082 Divisor = 1; 4083 4084 TMCValue = Divisor; 4085 4086 BRValue = 0; 4087 if (TMCValue != 1 && TMCValue != 2) { 4088 /* BRValue of 0 provides 50/50 duty cycle *only* when 4089 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides 4090 * 50/50 duty cycle. 4091 */ 4092 BRValue = 1; 4093 TMCValue >>= 1; 4094 } 4095 4096 /* while TMCValue is too big for TMC register, divide 4097 * by 2 and increment BR exponent. 4098 */ 4099 for(; TMCValue > 256 && BRValue < 10; BRValue++) 4100 TMCValue >>= 1; 4101 4102 write_reg(info, TXS, 4103 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue)); 4104 write_reg(info, RXS, 4105 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue)); 4106 write_reg(info, TMC, (unsigned char)TMCValue); 4107 } 4108 else { 4109 write_reg(info, TXS,0); 4110 write_reg(info, RXS,0); 4111 write_reg(info, TMC, 0); 4112 } 4113 } 4114 4115 /* Disable receiver 4116 */ 4117 static void rx_stop(SLMP_INFO *info) 4118 { 4119 if (debug_level >= DEBUG_LEVEL_ISR) 4120 printk("%s(%d):%s rx_stop()\n", 4121 __FILE__,__LINE__, info->device_name ); 4122 4123 write_reg(info, CMD, RXRESET); 4124 4125 info->ie0_value &= ~RXRDYE; 4126 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */ 4127 4128 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ 4129 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ 4130 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */ 4131 4132 info->rx_enabled = false; 4133 info->rx_overflow = false; 4134 } 4135 4136 /* enable the receiver 4137 */ 4138 static void rx_start(SLMP_INFO *info) 4139 { 4140 int i; 4141 4142 if (debug_level >= DEBUG_LEVEL_ISR) 4143 printk("%s(%d):%s rx_start()\n", 4144 __FILE__,__LINE__, info->device_name ); 4145 4146 write_reg(info, CMD, RXRESET); 4147 4148 if ( info->params.mode == MGSL_MODE_HDLC ) { 4149 /* HDLC, disabe IRQ on rxdata */ 4150 info->ie0_value &= ~RXRDYE; 4151 write_reg(info, IE0, info->ie0_value); 4152 4153 /* Reset all Rx DMA buffers and program rx dma */ 4154 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ 4155 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ 4156 4157 for (i = 0; i < info->rx_buf_count; i++) { 4158 info->rx_buf_list[i].status = 0xff; 4159 4160 // throttle to 4 shared memory writes at a time to prevent 4161 // hogging local bus (keep latency time for DMA requests low). 4162 if (!(i % 4)) 4163 read_status_reg(info); 4164 } 4165 info->current_rx_buf = 0; 4166 4167 /* set current/1st descriptor address */ 4168 write_reg16(info, RXDMA + CDA, 4169 info->rx_buf_list_ex[0].phys_entry); 4170 4171 /* set new last rx descriptor address */ 4172 write_reg16(info, RXDMA + EDA, 4173 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry); 4174 4175 /* set buffer length (shared by all rx dma data buffers) */ 4176 write_reg16(info, RXDMA + BFL, SCABUFSIZE); 4177 4178 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */ 4179 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ 4180 } else { 4181 /* async, enable IRQ on rxdata */ 4182 info->ie0_value |= RXRDYE; 4183 write_reg(info, IE0, info->ie0_value); 4184 } 4185 4186 write_reg(info, CMD, RXENABLE); 4187 4188 info->rx_overflow = false; 4189 info->rx_enabled = true; 4190 } 4191 4192 /* Enable the transmitter and send a transmit frame if 4193 * one is loaded in the DMA buffers. 4194 */ 4195 static void tx_start(SLMP_INFO *info) 4196 { 4197 if (debug_level >= DEBUG_LEVEL_ISR) 4198 printk("%s(%d):%s tx_start() tx_count=%d\n", 4199 __FILE__,__LINE__, info->device_name,info->tx_count ); 4200 4201 if (!info->tx_enabled ) { 4202 write_reg(info, CMD, TXRESET); 4203 write_reg(info, CMD, TXENABLE); 4204 info->tx_enabled = true; 4205 } 4206 4207 if ( info->tx_count ) { 4208 4209 /* If auto RTS enabled and RTS is inactive, then assert */ 4210 /* RTS and set a flag indicating that the driver should */ 4211 /* negate RTS when the transmission completes. */ 4212 4213 info->drop_rts_on_tx_done = false; 4214 4215 if (info->params.mode != MGSL_MODE_ASYNC) { 4216 4217 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { 4218 get_signals( info ); 4219 if ( !(info->serial_signals & SerialSignal_RTS) ) { 4220 info->serial_signals |= SerialSignal_RTS; 4221 set_signals( info ); 4222 info->drop_rts_on_tx_done = true; 4223 } 4224 } 4225 4226 write_reg16(info, TRC0, 4227 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level)); 4228 4229 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 4230 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 4231 4232 /* set TX CDA (current descriptor address) */ 4233 write_reg16(info, TXDMA + CDA, 4234 info->tx_buf_list_ex[0].phys_entry); 4235 4236 /* set TX EDA (last descriptor address) */ 4237 write_reg16(info, TXDMA + EDA, 4238 info->tx_buf_list_ex[info->last_tx_buf].phys_entry); 4239 4240 /* enable underrun IRQ */ 4241 info->ie1_value &= ~IDLE; 4242 info->ie1_value |= UDRN; 4243 write_reg(info, IE1, info->ie1_value); 4244 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); 4245 4246 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */ 4247 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ 4248 4249 mod_timer(&info->tx_timer, jiffies + 4250 msecs_to_jiffies(5000)); 4251 } 4252 else { 4253 tx_load_fifo(info); 4254 /* async, enable IRQ on txdata */ 4255 info->ie0_value |= TXRDYE; 4256 write_reg(info, IE0, info->ie0_value); 4257 } 4258 4259 info->tx_active = true; 4260 } 4261 } 4262 4263 /* stop the transmitter and DMA 4264 */ 4265 static void tx_stop( SLMP_INFO *info ) 4266 { 4267 if (debug_level >= DEBUG_LEVEL_ISR) 4268 printk("%s(%d):%s tx_stop()\n", 4269 __FILE__,__LINE__, info->device_name ); 4270 4271 del_timer(&info->tx_timer); 4272 4273 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 4274 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 4275 4276 write_reg(info, CMD, TXRESET); 4277 4278 info->ie1_value &= ~(UDRN + IDLE); 4279 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ 4280 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ 4281 4282 info->ie0_value &= ~TXRDYE; 4283 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */ 4284 4285 info->tx_enabled = false; 4286 info->tx_active = false; 4287 } 4288 4289 /* Fill the transmit FIFO until the FIFO is full or 4290 * there is no more data to load. 4291 */ 4292 static void tx_load_fifo(SLMP_INFO *info) 4293 { 4294 u8 TwoBytes[2]; 4295 4296 /* do nothing is now tx data available and no XON/XOFF pending */ 4297 4298 if ( !info->tx_count && !info->x_char ) 4299 return; 4300 4301 /* load the Transmit FIFO until FIFOs full or all data sent */ 4302 4303 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { 4304 4305 /* there is more space in the transmit FIFO and */ 4306 /* there is more data in transmit buffer */ 4307 4308 if ( (info->tx_count > 1) && !info->x_char ) { 4309 /* write 16-bits */ 4310 TwoBytes[0] = info->tx_buf[info->tx_get++]; 4311 if (info->tx_get >= info->max_frame_size) 4312 info->tx_get -= info->max_frame_size; 4313 TwoBytes[1] = info->tx_buf[info->tx_get++]; 4314 if (info->tx_get >= info->max_frame_size) 4315 info->tx_get -= info->max_frame_size; 4316 4317 write_reg16(info, TRB, *((u16 *)TwoBytes)); 4318 4319 info->tx_count -= 2; 4320 info->icount.tx += 2; 4321 } else { 4322 /* only 1 byte left to transmit or 1 FIFO slot left */ 4323 4324 if (info->x_char) { 4325 /* transmit pending high priority char */ 4326 write_reg(info, TRB, info->x_char); 4327 info->x_char = 0; 4328 } else { 4329 write_reg(info, TRB, info->tx_buf[info->tx_get++]); 4330 if (info->tx_get >= info->max_frame_size) 4331 info->tx_get -= info->max_frame_size; 4332 info->tx_count--; 4333 } 4334 info->icount.tx++; 4335 } 4336 } 4337 } 4338 4339 /* Reset a port to a known state 4340 */ 4341 static void reset_port(SLMP_INFO *info) 4342 { 4343 if (info->sca_base) { 4344 4345 tx_stop(info); 4346 rx_stop(info); 4347 4348 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 4349 set_signals(info); 4350 4351 /* disable all port interrupts */ 4352 info->ie0_value = 0; 4353 info->ie1_value = 0; 4354 info->ie2_value = 0; 4355 write_reg(info, IE0, info->ie0_value); 4356 write_reg(info, IE1, info->ie1_value); 4357 write_reg(info, IE2, info->ie2_value); 4358 4359 write_reg(info, CMD, CHRESET); 4360 } 4361 } 4362 4363 /* Reset all the ports to a known state. 4364 */ 4365 static void reset_adapter(SLMP_INFO *info) 4366 { 4367 int i; 4368 4369 for ( i=0; i < SCA_MAX_PORTS; ++i) { 4370 if (info->port_array[i]) 4371 reset_port(info->port_array[i]); 4372 } 4373 } 4374 4375 /* Program port for asynchronous communications. 4376 */ 4377 static void async_mode(SLMP_INFO *info) 4378 { 4379 4380 unsigned char RegValue; 4381 4382 tx_stop(info); 4383 rx_stop(info); 4384 4385 /* MD0, Mode Register 0 4386 * 4387 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async 4388 * 04 AUTO, Auto-enable (RTS/CTS/DCD) 4389 * 03 Reserved, must be 0 4390 * 02 CRCCC, CRC Calculation, 0=disabled 4391 * 01..00 STOP<1..0> Stop bits (00=1,10=2) 4392 * 4393 * 0000 0000 4394 */ 4395 RegValue = 0x00; 4396 if (info->params.stop_bits != 1) 4397 RegValue |= BIT1; 4398 write_reg(info, MD0, RegValue); 4399 4400 /* MD1, Mode Register 1 4401 * 4402 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64 4403 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5 4404 * 03..02 RXCHR<1..0>, rx char size 4405 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd 4406 * 4407 * 0100 0000 4408 */ 4409 RegValue = 0x40; 4410 switch (info->params.data_bits) { 4411 case 7: RegValue |= BIT4 + BIT2; break; 4412 case 6: RegValue |= BIT5 + BIT3; break; 4413 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; 4414 } 4415 if (info->params.parity != ASYNC_PARITY_NONE) { 4416 RegValue |= BIT1; 4417 if (info->params.parity == ASYNC_PARITY_ODD) 4418 RegValue |= BIT0; 4419 } 4420 write_reg(info, MD1, RegValue); 4421 4422 /* MD2, Mode Register 2 4423 * 4424 * 07..02 Reserved, must be 0 4425 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback 4426 * 4427 * 0000 0000 4428 */ 4429 RegValue = 0x00; 4430 if (info->params.loopback) 4431 RegValue |= (BIT1 + BIT0); 4432 write_reg(info, MD2, RegValue); 4433 4434 /* RXS, Receive clock source 4435 * 4436 * 07 Reserved, must be 0 4437 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL 4438 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4439 */ 4440 RegValue=BIT6; 4441 write_reg(info, RXS, RegValue); 4442 4443 /* TXS, Transmit clock source 4444 * 4445 * 07 Reserved, must be 0 4446 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock 4447 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4448 */ 4449 RegValue=BIT6; 4450 write_reg(info, TXS, RegValue); 4451 4452 /* Control Register 4453 * 4454 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out 4455 */ 4456 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4457 write_control_reg(info); 4458 4459 tx_set_idle(info); 4460 4461 /* RRC Receive Ready Control 0 4462 * 4463 * 07..05 Reserved, must be 0 4464 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte 4465 */ 4466 write_reg(info, RRC, 0x00); 4467 4468 /* TRC0 Transmit Ready Control 0 4469 * 4470 * 07..05 Reserved, must be 0 4471 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes 4472 */ 4473 write_reg(info, TRC0, 0x10); 4474 4475 /* TRC1 Transmit Ready Control 1 4476 * 4477 * 07..05 Reserved, must be 0 4478 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1) 4479 */ 4480 write_reg(info, TRC1, 0x1e); 4481 4482 /* CTL, MSCI control register 4483 * 4484 * 07..06 Reserved, set to 0 4485 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) 4486 * 04 IDLC, idle control, 0=mark 1=idle register 4487 * 03 BRK, break, 0=off 1 =on (async) 4488 * 02 SYNCLD, sync char load enable (BSC) 1=enabled 4489 * 01 GOP, go active on poll (LOOP mode) 1=enabled 4490 * 00 RTS, RTS output control, 0=active 1=inactive 4491 * 4492 * 0001 0001 4493 */ 4494 RegValue = 0x10; 4495 if (!(info->serial_signals & SerialSignal_RTS)) 4496 RegValue |= 0x01; 4497 write_reg(info, CTL, RegValue); 4498 4499 /* enable status interrupts */ 4500 info->ie0_value |= TXINTE + RXINTE; 4501 write_reg(info, IE0, info->ie0_value); 4502 4503 /* enable break detect interrupt */ 4504 info->ie1_value = BRKD; 4505 write_reg(info, IE1, info->ie1_value); 4506 4507 /* enable rx overrun interrupt */ 4508 info->ie2_value = OVRN; 4509 write_reg(info, IE2, info->ie2_value); 4510 4511 set_rate( info, info->params.data_rate * 16 ); 4512 } 4513 4514 /* Program the SCA for HDLC communications. 4515 */ 4516 static void hdlc_mode(SLMP_INFO *info) 4517 { 4518 unsigned char RegValue; 4519 u32 DpllDivisor; 4520 4521 // Can't use DPLL because SCA outputs recovered clock on RxC when 4522 // DPLL mode selected. This causes output contention with RxC receiver. 4523 // Use of DPLL would require external hardware to disable RxC receiver 4524 // when DPLL mode selected. 4525 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL); 4526 4527 /* disable DMA interrupts */ 4528 write_reg(info, TXDMA + DIR, 0); 4529 write_reg(info, RXDMA + DIR, 0); 4530 4531 /* MD0, Mode Register 0 4532 * 4533 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC 4534 * 04 AUTO, Auto-enable (RTS/CTS/DCD) 4535 * 03 Reserved, must be 0 4536 * 02 CRCCC, CRC Calculation, 1=enabled 4537 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16 4538 * 00 CRC0, CRC initial value, 1 = all 1s 4539 * 4540 * 1000 0001 4541 */ 4542 RegValue = 0x81; 4543 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4544 RegValue |= BIT4; 4545 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4546 RegValue |= BIT4; 4547 if (info->params.crc_type == HDLC_CRC_16_CCITT) 4548 RegValue |= BIT2 + BIT1; 4549 write_reg(info, MD0, RegValue); 4550 4551 /* MD1, Mode Register 1 4552 * 4553 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check 4554 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits 4555 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits 4556 * 01..00 PMPM<1..0>, Parity mode, 00=no parity 4557 * 4558 * 0000 0000 4559 */ 4560 RegValue = 0x00; 4561 write_reg(info, MD1, RegValue); 4562 4563 /* MD2, Mode Register 2 4564 * 4565 * 07 NRZFM, 0=NRZ, 1=FM 4566 * 06..05 CODE<1..0> Encoding, 00=NRZ 4567 * 04..03 DRATE<1..0> DPLL Divisor, 00=8 4568 * 02 Reserved, must be 0 4569 * 01..00 CNCT<1..0> Channel connection, 0=normal 4570 * 4571 * 0000 0000 4572 */ 4573 RegValue = 0x00; 4574 switch(info->params.encoding) { 4575 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; 4576 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ 4577 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ 4578 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */ 4579 #if 0 4580 case HDLC_ENCODING_NRZB: /* not supported */ 4581 case HDLC_ENCODING_NRZI_MARK: /* not supported */ 4582 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */ 4583 #endif 4584 } 4585 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) { 4586 DpllDivisor = 16; 4587 RegValue |= BIT3; 4588 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) { 4589 DpllDivisor = 8; 4590 } else { 4591 DpllDivisor = 32; 4592 RegValue |= BIT4; 4593 } 4594 write_reg(info, MD2, RegValue); 4595 4596 4597 /* RXS, Receive clock source 4598 * 4599 * 07 Reserved, must be 0 4600 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL 4601 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4602 */ 4603 RegValue=0; 4604 if (info->params.flags & HDLC_FLAG_RXC_BRG) 4605 RegValue |= BIT6; 4606 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4607 RegValue |= BIT6 + BIT5; 4608 write_reg(info, RXS, RegValue); 4609 4610 /* TXS, Transmit clock source 4611 * 4612 * 07 Reserved, must be 0 4613 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock 4614 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4615 */ 4616 RegValue=0; 4617 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4618 RegValue |= BIT6; 4619 if (info->params.flags & HDLC_FLAG_TXC_DPLL) 4620 RegValue |= BIT6 + BIT5; 4621 write_reg(info, TXS, RegValue); 4622 4623 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4624 set_rate(info, info->params.clock_speed * DpllDivisor); 4625 else 4626 set_rate(info, info->params.clock_speed); 4627 4628 /* GPDATA (General Purpose I/O Data Register) 4629 * 4630 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out 4631 */ 4632 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4633 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4634 else 4635 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2)); 4636 write_control_reg(info); 4637 4638 /* RRC Receive Ready Control 0 4639 * 4640 * 07..05 Reserved, must be 0 4641 * 04..00 RRC<4..0> Rx FIFO trigger active 4642 */ 4643 write_reg(info, RRC, rx_active_fifo_level); 4644 4645 /* TRC0 Transmit Ready Control 0 4646 * 4647 * 07..05 Reserved, must be 0 4648 * 04..00 TRC<4..0> Tx FIFO trigger active 4649 */ 4650 write_reg(info, TRC0, tx_active_fifo_level); 4651 4652 /* TRC1 Transmit Ready Control 1 4653 * 4654 * 07..05 Reserved, must be 0 4655 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full) 4656 */ 4657 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1)); 4658 4659 /* DMR, DMA Mode Register 4660 * 4661 * 07..05 Reserved, must be 0 4662 * 04 TMOD, Transfer Mode: 1=chained-block 4663 * 03 Reserved, must be 0 4664 * 02 NF, Number of Frames: 1=multi-frame 4665 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled 4666 * 00 Reserved, must be 0 4667 * 4668 * 0001 0100 4669 */ 4670 write_reg(info, TXDMA + DMR, 0x14); 4671 write_reg(info, RXDMA + DMR, 0x14); 4672 4673 /* Set chain pointer base (upper 8 bits of 24 bit addr) */ 4674 write_reg(info, RXDMA + CPB, 4675 (unsigned char)(info->buffer_list_phys >> 16)); 4676 4677 /* Set chain pointer base (upper 8 bits of 24 bit addr) */ 4678 write_reg(info, TXDMA + CPB, 4679 (unsigned char)(info->buffer_list_phys >> 16)); 4680 4681 /* enable status interrupts. other code enables/disables 4682 * the individual sources for these two interrupt classes. 4683 */ 4684 info->ie0_value |= TXINTE + RXINTE; 4685 write_reg(info, IE0, info->ie0_value); 4686 4687 /* CTL, MSCI control register 4688 * 4689 * 07..06 Reserved, set to 0 4690 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) 4691 * 04 IDLC, idle control, 0=mark 1=idle register 4692 * 03 BRK, break, 0=off 1 =on (async) 4693 * 02 SYNCLD, sync char load enable (BSC) 1=enabled 4694 * 01 GOP, go active on poll (LOOP mode) 1=enabled 4695 * 00 RTS, RTS output control, 0=active 1=inactive 4696 * 4697 * 0001 0001 4698 */ 4699 RegValue = 0x10; 4700 if (!(info->serial_signals & SerialSignal_RTS)) 4701 RegValue |= 0x01; 4702 write_reg(info, CTL, RegValue); 4703 4704 /* preamble not supported ! */ 4705 4706 tx_set_idle(info); 4707 tx_stop(info); 4708 rx_stop(info); 4709 4710 set_rate(info, info->params.clock_speed); 4711 4712 if (info->params.loopback) 4713 enable_loopback(info,1); 4714 } 4715 4716 /* Set the transmit HDLC idle mode 4717 */ 4718 static void tx_set_idle(SLMP_INFO *info) 4719 { 4720 unsigned char RegValue = 0xff; 4721 4722 /* Map API idle mode to SCA register bits */ 4723 switch(info->idle_mode) { 4724 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break; 4725 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break; 4726 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break; 4727 case HDLC_TXIDLE_ONES: RegValue = 0xff; break; 4728 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break; 4729 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break; 4730 case HDLC_TXIDLE_MARK: RegValue = 0xff; break; 4731 } 4732 4733 write_reg(info, IDL, RegValue); 4734 } 4735 4736 /* Query the adapter for the state of the V24 status (input) signals. 4737 */ 4738 static void get_signals(SLMP_INFO *info) 4739 { 4740 u16 status = read_reg(info, SR3); 4741 u16 gpstatus = read_status_reg(info); 4742 u16 testbit; 4743 4744 /* clear all serial signals except RTS and DTR */ 4745 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR; 4746 4747 /* set serial signal bits to reflect MISR */ 4748 4749 if (!(status & BIT3)) 4750 info->serial_signals |= SerialSignal_CTS; 4751 4752 if ( !(status & BIT2)) 4753 info->serial_signals |= SerialSignal_DCD; 4754 4755 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7> 4756 if (!(gpstatus & testbit)) 4757 info->serial_signals |= SerialSignal_RI; 4758 4759 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6> 4760 if (!(gpstatus & testbit)) 4761 info->serial_signals |= SerialSignal_DSR; 4762 } 4763 4764 /* Set the state of RTS and DTR based on contents of 4765 * serial_signals member of device context. 4766 */ 4767 static void set_signals(SLMP_INFO *info) 4768 { 4769 unsigned char RegValue; 4770 u16 EnableBit; 4771 4772 RegValue = read_reg(info, CTL); 4773 if (info->serial_signals & SerialSignal_RTS) 4774 RegValue &= ~BIT0; 4775 else 4776 RegValue |= BIT0; 4777 write_reg(info, CTL, RegValue); 4778 4779 // Port 0..3 DTR is ctrl reg <1,3,5,7> 4780 EnableBit = BIT1 << (info->port_num*2); 4781 if (info->serial_signals & SerialSignal_DTR) 4782 info->port_array[0]->ctrlreg_value &= ~EnableBit; 4783 else 4784 info->port_array[0]->ctrlreg_value |= EnableBit; 4785 write_control_reg(info); 4786 } 4787 4788 /*******************/ 4789 /* DMA Buffer Code */ 4790 /*******************/ 4791 4792 /* Set the count for all receive buffers to SCABUFSIZE 4793 * and set the current buffer to the first buffer. This effectively 4794 * makes all buffers free and discards any data in buffers. 4795 */ 4796 static void rx_reset_buffers(SLMP_INFO *info) 4797 { 4798 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1); 4799 } 4800 4801 /* Free the buffers used by a received frame 4802 * 4803 * info pointer to device instance data 4804 * first index of 1st receive buffer of frame 4805 * last index of last receive buffer of frame 4806 */ 4807 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last) 4808 { 4809 bool done = false; 4810 4811 while(!done) { 4812 /* reset current buffer for reuse */ 4813 info->rx_buf_list[first].status = 0xff; 4814 4815 if (first == last) { 4816 done = true; 4817 /* set new last rx descriptor address */ 4818 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry); 4819 } 4820 4821 first++; 4822 if (first == info->rx_buf_count) 4823 first = 0; 4824 } 4825 4826 /* set current buffer to next buffer after last buffer of frame */ 4827 info->current_rx_buf = first; 4828 } 4829 4830 /* Return a received frame from the receive DMA buffers. 4831 * Only frames received without errors are returned. 4832 * 4833 * Return Value: true if frame returned, otherwise false 4834 */ 4835 static bool rx_get_frame(SLMP_INFO *info) 4836 { 4837 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ 4838 unsigned short status; 4839 unsigned int framesize = 0; 4840 bool ReturnCode = false; 4841 unsigned long flags; 4842 struct tty_struct *tty = info->port.tty; 4843 unsigned char addr_field = 0xff; 4844 SCADESC *desc; 4845 SCADESC_EX *desc_ex; 4846 4847 CheckAgain: 4848 /* assume no frame returned, set zero length */ 4849 framesize = 0; 4850 addr_field = 0xff; 4851 4852 /* 4853 * current_rx_buf points to the 1st buffer of the next available 4854 * receive frame. To find the last buffer of the frame look for 4855 * a non-zero status field in the buffer entries. (The status 4856 * field is set by the 16C32 after completing a receive frame. 4857 */ 4858 StartIndex = EndIndex = info->current_rx_buf; 4859 4860 for ( ;; ) { 4861 desc = &info->rx_buf_list[EndIndex]; 4862 desc_ex = &info->rx_buf_list_ex[EndIndex]; 4863 4864 if (desc->status == 0xff) 4865 goto Cleanup; /* current desc still in use, no frames available */ 4866 4867 if (framesize == 0 && info->params.addr_filter != 0xff) 4868 addr_field = desc_ex->virt_addr[0]; 4869 4870 framesize += desc->length; 4871 4872 /* Status != 0 means last buffer of frame */ 4873 if (desc->status) 4874 break; 4875 4876 EndIndex++; 4877 if (EndIndex == info->rx_buf_count) 4878 EndIndex = 0; 4879 4880 if (EndIndex == info->current_rx_buf) { 4881 /* all buffers have been 'used' but none mark */ 4882 /* the end of a frame. Reset buffers and receiver. */ 4883 if ( info->rx_enabled ){ 4884 spin_lock_irqsave(&info->lock,flags); 4885 rx_start(info); 4886 spin_unlock_irqrestore(&info->lock,flags); 4887 } 4888 goto Cleanup; 4889 } 4890 4891 } 4892 4893 /* check status of receive frame */ 4894 4895 /* frame status is byte stored after frame data 4896 * 4897 * 7 EOM (end of msg), 1 = last buffer of frame 4898 * 6 Short Frame, 1 = short frame 4899 * 5 Abort, 1 = frame aborted 4900 * 4 Residue, 1 = last byte is partial 4901 * 3 Overrun, 1 = overrun occurred during frame reception 4902 * 2 CRC, 1 = CRC error detected 4903 * 4904 */ 4905 status = desc->status; 4906 4907 /* ignore CRC bit if not using CRC (bit is undefined) */ 4908 /* Note:CRC is not save to data buffer */ 4909 if (info->params.crc_type == HDLC_CRC_NONE) 4910 status &= ~BIT2; 4911 4912 if (framesize == 0 || 4913 (addr_field != 0xff && addr_field != info->params.addr_filter)) { 4914 /* discard 0 byte frames, this seems to occur sometime 4915 * when remote is idling flags. 4916 */ 4917 rx_free_frame_buffers(info, StartIndex, EndIndex); 4918 goto CheckAgain; 4919 } 4920 4921 if (framesize < 2) 4922 status |= BIT6; 4923 4924 if (status & (BIT6+BIT5+BIT3+BIT2)) { 4925 /* received frame has errors, 4926 * update counts and mark frame size as 0 4927 */ 4928 if (status & BIT6) 4929 info->icount.rxshort++; 4930 else if (status & BIT5) 4931 info->icount.rxabort++; 4932 else if (status & BIT3) 4933 info->icount.rxover++; 4934 else 4935 info->icount.rxcrc++; 4936 4937 framesize = 0; 4938 #if SYNCLINK_GENERIC_HDLC 4939 { 4940 info->netdev->stats.rx_errors++; 4941 info->netdev->stats.rx_frame_errors++; 4942 } 4943 #endif 4944 } 4945 4946 if ( debug_level >= DEBUG_LEVEL_BH ) 4947 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n", 4948 __FILE__,__LINE__,info->device_name,status,framesize); 4949 4950 if ( debug_level >= DEBUG_LEVEL_DATA ) 4951 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr, 4952 min_t(unsigned int, framesize, SCABUFSIZE), 0); 4953 4954 if (framesize) { 4955 if (framesize > info->max_frame_size) 4956 info->icount.rxlong++; 4957 else { 4958 /* copy dma buffer(s) to contiguous intermediate buffer */ 4959 int copy_count = framesize; 4960 int index = StartIndex; 4961 unsigned char *ptmp = info->tmp_rx_buf; 4962 info->tmp_rx_buf_count = framesize; 4963 4964 info->icount.rxok++; 4965 4966 while(copy_count) { 4967 int partial_count = min(copy_count,SCABUFSIZE); 4968 memcpy( ptmp, 4969 info->rx_buf_list_ex[index].virt_addr, 4970 partial_count ); 4971 ptmp += partial_count; 4972 copy_count -= partial_count; 4973 4974 if ( ++index == info->rx_buf_count ) 4975 index = 0; 4976 } 4977 4978 #if SYNCLINK_GENERIC_HDLC 4979 if (info->netcount) 4980 hdlcdev_rx(info,info->tmp_rx_buf,framesize); 4981 else 4982 #endif 4983 ldisc_receive_buf(tty,info->tmp_rx_buf, 4984 info->flag_buf, framesize); 4985 } 4986 } 4987 /* Free the buffers used by this frame. */ 4988 rx_free_frame_buffers( info, StartIndex, EndIndex ); 4989 4990 ReturnCode = true; 4991 4992 Cleanup: 4993 if ( info->rx_enabled && info->rx_overflow ) { 4994 /* Receiver is enabled, but needs to restarted due to 4995 * rx buffer overflow. If buffers are empty, restart receiver. 4996 */ 4997 if (info->rx_buf_list[EndIndex].status == 0xff) { 4998 spin_lock_irqsave(&info->lock,flags); 4999 rx_start(info); 5000 spin_unlock_irqrestore(&info->lock,flags); 5001 } 5002 } 5003 5004 return ReturnCode; 5005 } 5006 5007 /* load the transmit DMA buffer with data 5008 */ 5009 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count) 5010 { 5011 unsigned short copy_count; 5012 unsigned int i = 0; 5013 SCADESC *desc; 5014 SCADESC_EX *desc_ex; 5015 5016 if ( debug_level >= DEBUG_LEVEL_DATA ) 5017 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1); 5018 5019 /* Copy source buffer to one or more DMA buffers, starting with 5020 * the first transmit dma buffer. 5021 */ 5022 for(i=0;;) 5023 { 5024 copy_count = min_t(unsigned int, count, SCABUFSIZE); 5025 5026 desc = &info->tx_buf_list[i]; 5027 desc_ex = &info->tx_buf_list_ex[i]; 5028 5029 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count); 5030 5031 desc->length = copy_count; 5032 desc->status = 0; 5033 5034 buf += copy_count; 5035 count -= copy_count; 5036 5037 if (!count) 5038 break; 5039 5040 i++; 5041 if (i >= info->tx_buf_count) 5042 i = 0; 5043 } 5044 5045 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */ 5046 info->last_tx_buf = ++i; 5047 } 5048 5049 static bool register_test(SLMP_INFO *info) 5050 { 5051 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96}; 5052 static unsigned int count = ARRAY_SIZE(testval); 5053 unsigned int i; 5054 bool rc = true; 5055 unsigned long flags; 5056 5057 spin_lock_irqsave(&info->lock,flags); 5058 reset_port(info); 5059 5060 /* assume failure */ 5061 info->init_error = DiagStatus_AddressFailure; 5062 5063 /* Write bit patterns to various registers but do it out of */ 5064 /* sync, then read back and verify values. */ 5065 5066 for (i = 0 ; i < count ; i++) { 5067 write_reg(info, TMC, testval[i]); 5068 write_reg(info, IDL, testval[(i+1)%count]); 5069 write_reg(info, SA0, testval[(i+2)%count]); 5070 write_reg(info, SA1, testval[(i+3)%count]); 5071 5072 if ( (read_reg(info, TMC) != testval[i]) || 5073 (read_reg(info, IDL) != testval[(i+1)%count]) || 5074 (read_reg(info, SA0) != testval[(i+2)%count]) || 5075 (read_reg(info, SA1) != testval[(i+3)%count]) ) 5076 { 5077 rc = false; 5078 break; 5079 } 5080 } 5081 5082 reset_port(info); 5083 spin_unlock_irqrestore(&info->lock,flags); 5084 5085 return rc; 5086 } 5087 5088 static bool irq_test(SLMP_INFO *info) 5089 { 5090 unsigned long timeout; 5091 unsigned long flags; 5092 5093 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; 5094 5095 spin_lock_irqsave(&info->lock,flags); 5096 reset_port(info); 5097 5098 /* assume failure */ 5099 info->init_error = DiagStatus_IrqFailure; 5100 info->irq_occurred = false; 5101 5102 /* setup timer0 on SCA0 to interrupt */ 5103 5104 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */ 5105 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); 5106 5107 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */ 5108 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */ 5109 5110 5111 /* TMCS, Timer Control/Status Register 5112 * 5113 * 07 CMF, Compare match flag (read only) 1=match 5114 * 06 ECMI, CMF Interrupt Enable: 1=enabled 5115 * 05 Reserved, must be 0 5116 * 04 TME, Timer Enable 5117 * 03..00 Reserved, must be 0 5118 * 5119 * 0101 0000 5120 */ 5121 write_reg(info, (unsigned char)(timer + TMCS), 0x50); 5122 5123 spin_unlock_irqrestore(&info->lock,flags); 5124 5125 timeout=100; 5126 while( timeout-- && !info->irq_occurred ) { 5127 msleep_interruptible(10); 5128 } 5129 5130 spin_lock_irqsave(&info->lock,flags); 5131 reset_port(info); 5132 spin_unlock_irqrestore(&info->lock,flags); 5133 5134 return info->irq_occurred; 5135 } 5136 5137 /* initialize individual SCA device (2 ports) 5138 */ 5139 static bool sca_init(SLMP_INFO *info) 5140 { 5141 /* set wait controller to single mem partition (low), no wait states */ 5142 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */ 5143 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */ 5144 write_reg(info, WCRL, 0); /* wait controller low range */ 5145 write_reg(info, WCRM, 0); /* wait controller mid range */ 5146 write_reg(info, WCRH, 0); /* wait controller high range */ 5147 5148 /* DPCR, DMA Priority Control 5149 * 5150 * 07..05 Not used, must be 0 5151 * 04 BRC, bus release condition: 0=all transfers complete 5152 * 03 CCC, channel change condition: 0=every cycle 5153 * 02..00 PR<2..0>, priority 100=round robin 5154 * 5155 * 00000100 = 0x04 5156 */ 5157 write_reg(info, DPCR, dma_priority); 5158 5159 /* DMA Master Enable, BIT7: 1=enable all channels */ 5160 write_reg(info, DMER, 0x80); 5161 5162 /* enable all interrupt classes */ 5163 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */ 5164 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */ 5165 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */ 5166 5167 /* ITCR, interrupt control register 5168 * 07 IPC, interrupt priority, 0=MSCI->DMA 5169 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle 5170 * 04 VOS, Vector Output, 0=unmodified vector 5171 * 03..00 Reserved, must be 0 5172 */ 5173 write_reg(info, ITCR, 0); 5174 5175 return true; 5176 } 5177 5178 /* initialize adapter hardware 5179 */ 5180 static bool init_adapter(SLMP_INFO *info) 5181 { 5182 int i; 5183 5184 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */ 5185 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); 5186 u32 readval; 5187 5188 info->misc_ctrl_value |= BIT30; 5189 *MiscCtrl = info->misc_ctrl_value; 5190 5191 /* 5192 * Force at least 170ns delay before clearing 5193 * reset bit. Each read from LCR takes at least 5194 * 30ns so 10 times for 300ns to be safe. 5195 */ 5196 for(i=0;i<10;i++) 5197 readval = *MiscCtrl; 5198 5199 info->misc_ctrl_value &= ~BIT30; 5200 *MiscCtrl = info->misc_ctrl_value; 5201 5202 /* init control reg (all DTRs off, all clksel=input) */ 5203 info->ctrlreg_value = 0xaa; 5204 write_control_reg(info); 5205 5206 { 5207 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c); 5208 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3); 5209 5210 switch(read_ahead_count) 5211 { 5212 case 16: 5213 lcr1_brdr_value |= BIT5 + BIT4 + BIT3; 5214 break; 5215 case 8: 5216 lcr1_brdr_value |= BIT5 + BIT4; 5217 break; 5218 case 4: 5219 lcr1_brdr_value |= BIT5 + BIT3; 5220 break; 5221 case 0: 5222 lcr1_brdr_value |= BIT5; 5223 break; 5224 } 5225 5226 *LCR1BRDR = lcr1_brdr_value; 5227 *MiscCtrl = misc_ctrl_value; 5228 } 5229 5230 sca_init(info->port_array[0]); 5231 sca_init(info->port_array[2]); 5232 5233 return true; 5234 } 5235 5236 /* Loopback an HDLC frame to test the hardware 5237 * interrupt and DMA functions. 5238 */ 5239 static bool loopback_test(SLMP_INFO *info) 5240 { 5241 #define TESTFRAMESIZE 20 5242 5243 unsigned long timeout; 5244 u16 count = TESTFRAMESIZE; 5245 unsigned char buf[TESTFRAMESIZE]; 5246 bool rc = false; 5247 unsigned long flags; 5248 5249 struct tty_struct *oldtty = info->port.tty; 5250 u32 speed = info->params.clock_speed; 5251 5252 info->params.clock_speed = 3686400; 5253 info->port.tty = NULL; 5254 5255 /* assume failure */ 5256 info->init_error = DiagStatus_DmaFailure; 5257 5258 /* build and send transmit frame */ 5259 for (count = 0; count < TESTFRAMESIZE;++count) 5260 buf[count] = (unsigned char)count; 5261 5262 memset(info->tmp_rx_buf,0,TESTFRAMESIZE); 5263 5264 /* program hardware for HDLC and enabled receiver */ 5265 spin_lock_irqsave(&info->lock,flags); 5266 hdlc_mode(info); 5267 enable_loopback(info,1); 5268 rx_start(info); 5269 info->tx_count = count; 5270 tx_load_dma_buffer(info,buf,count); 5271 tx_start(info); 5272 spin_unlock_irqrestore(&info->lock,flags); 5273 5274 /* wait for receive complete */ 5275 /* Set a timeout for waiting for interrupt. */ 5276 for ( timeout = 100; timeout; --timeout ) { 5277 msleep_interruptible(10); 5278 5279 if (rx_get_frame(info)) { 5280 rc = true; 5281 break; 5282 } 5283 } 5284 5285 /* verify received frame length and contents */ 5286 if (rc && 5287 ( info->tmp_rx_buf_count != count || 5288 memcmp(buf, info->tmp_rx_buf,count))) { 5289 rc = false; 5290 } 5291 5292 spin_lock_irqsave(&info->lock,flags); 5293 reset_adapter(info); 5294 spin_unlock_irqrestore(&info->lock,flags); 5295 5296 info->params.clock_speed = speed; 5297 info->port.tty = oldtty; 5298 5299 return rc; 5300 } 5301 5302 /* Perform diagnostics on hardware 5303 */ 5304 static int adapter_test( SLMP_INFO *info ) 5305 { 5306 unsigned long flags; 5307 if ( debug_level >= DEBUG_LEVEL_INFO ) 5308 printk( "%s(%d):Testing device %s\n", 5309 __FILE__,__LINE__,info->device_name ); 5310 5311 spin_lock_irqsave(&info->lock,flags); 5312 init_adapter(info); 5313 spin_unlock_irqrestore(&info->lock,flags); 5314 5315 info->port_array[0]->port_count = 0; 5316 5317 if ( register_test(info->port_array[0]) && 5318 register_test(info->port_array[1])) { 5319 5320 info->port_array[0]->port_count = 2; 5321 5322 if ( register_test(info->port_array[2]) && 5323 register_test(info->port_array[3]) ) 5324 info->port_array[0]->port_count += 2; 5325 } 5326 else { 5327 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n", 5328 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base)); 5329 return -ENODEV; 5330 } 5331 5332 if ( !irq_test(info->port_array[0]) || 5333 !irq_test(info->port_array[1]) || 5334 (info->port_count == 4 && !irq_test(info->port_array[2])) || 5335 (info->port_count == 4 && !irq_test(info->port_array[3]))) { 5336 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", 5337 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); 5338 return -ENODEV; 5339 } 5340 5341 if (!loopback_test(info->port_array[0]) || 5342 !loopback_test(info->port_array[1]) || 5343 (info->port_count == 4 && !loopback_test(info->port_array[2])) || 5344 (info->port_count == 4 && !loopback_test(info->port_array[3]))) { 5345 printk( "%s(%d):DMA test failure for device %s\n", 5346 __FILE__,__LINE__,info->device_name); 5347 return -ENODEV; 5348 } 5349 5350 if ( debug_level >= DEBUG_LEVEL_INFO ) 5351 printk( "%s(%d):device %s passed diagnostics\n", 5352 __FILE__,__LINE__,info->device_name ); 5353 5354 info->port_array[0]->init_error = 0; 5355 info->port_array[1]->init_error = 0; 5356 if ( info->port_count > 2 ) { 5357 info->port_array[2]->init_error = 0; 5358 info->port_array[3]->init_error = 0; 5359 } 5360 5361 return 0; 5362 } 5363 5364 /* Test the shared memory on a PCI adapter. 5365 */ 5366 static bool memory_test(SLMP_INFO *info) 5367 { 5368 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa, 5369 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; 5370 unsigned long count = ARRAY_SIZE(testval); 5371 unsigned long i; 5372 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long); 5373 unsigned long * addr = (unsigned long *)info->memory_base; 5374 5375 /* Test data lines with test pattern at one location. */ 5376 5377 for ( i = 0 ; i < count ; i++ ) { 5378 *addr = testval[i]; 5379 if ( *addr != testval[i] ) 5380 return false; 5381 } 5382 5383 /* Test address lines with incrementing pattern over */ 5384 /* entire address range. */ 5385 5386 for ( i = 0 ; i < limit ; i++ ) { 5387 *addr = i * 4; 5388 addr++; 5389 } 5390 5391 addr = (unsigned long *)info->memory_base; 5392 5393 for ( i = 0 ; i < limit ; i++ ) { 5394 if ( *addr != i * 4 ) 5395 return false; 5396 addr++; 5397 } 5398 5399 memset( info->memory_base, 0, SCA_MEM_SIZE ); 5400 return true; 5401 } 5402 5403 /* Load data into PCI adapter shared memory. 5404 * 5405 * The PCI9050 releases control of the local bus 5406 * after completing the current read or write operation. 5407 * 5408 * While the PCI9050 write FIFO not empty, the 5409 * PCI9050 treats all of the writes as a single transaction 5410 * and does not release the bus. This causes DMA latency problems 5411 * at high speeds when copying large data blocks to the shared memory. 5412 * 5413 * This function breaks a write into multiple transations by 5414 * interleaving a read which flushes the write FIFO and 'completes' 5415 * the write transation. This allows any pending DMA request to gain control 5416 * of the local bus in a timely fasion. 5417 */ 5418 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count) 5419 { 5420 /* A load interval of 16 allows for 4 32-bit writes at */ 5421 /* 136ns each for a maximum latency of 542ns on the local bus.*/ 5422 5423 unsigned short interval = count / sca_pci_load_interval; 5424 unsigned short i; 5425 5426 for ( i = 0 ; i < interval ; i++ ) 5427 { 5428 memcpy(dest, src, sca_pci_load_interval); 5429 read_status_reg(info); 5430 dest += sca_pci_load_interval; 5431 src += sca_pci_load_interval; 5432 } 5433 5434 memcpy(dest, src, count % sca_pci_load_interval); 5435 } 5436 5437 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit) 5438 { 5439 int i; 5440 int linecount; 5441 if (xmit) 5442 printk("%s tx data:\n",info->device_name); 5443 else 5444 printk("%s rx data:\n",info->device_name); 5445 5446 while(count) { 5447 if (count > 16) 5448 linecount = 16; 5449 else 5450 linecount = count; 5451 5452 for(i=0;i<linecount;i++) 5453 printk("%02X ",(unsigned char)data[i]); 5454 for(;i<17;i++) 5455 printk(" "); 5456 for(i=0;i<linecount;i++) { 5457 if (data[i]>=040 && data[i]<=0176) 5458 printk("%c",data[i]); 5459 else 5460 printk("."); 5461 } 5462 printk("\n"); 5463 5464 data += linecount; 5465 count -= linecount; 5466 } 5467 } /* end of trace_block() */ 5468 5469 /* called when HDLC frame times out 5470 * update stats and do tx completion processing 5471 */ 5472 static void tx_timeout(unsigned long context) 5473 { 5474 SLMP_INFO *info = (SLMP_INFO*)context; 5475 unsigned long flags; 5476 5477 if ( debug_level >= DEBUG_LEVEL_INFO ) 5478 printk( "%s(%d):%s tx_timeout()\n", 5479 __FILE__,__LINE__,info->device_name); 5480 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { 5481 info->icount.txtimeout++; 5482 } 5483 spin_lock_irqsave(&info->lock,flags); 5484 info->tx_active = false; 5485 info->tx_count = info->tx_put = info->tx_get = 0; 5486 5487 spin_unlock_irqrestore(&info->lock,flags); 5488 5489 #if SYNCLINK_GENERIC_HDLC 5490 if (info->netcount) 5491 hdlcdev_tx_done(info); 5492 else 5493 #endif 5494 bh_transmit(info); 5495 } 5496 5497 /* called to periodically check the DSR/RI modem signal input status 5498 */ 5499 static void status_timeout(unsigned long context) 5500 { 5501 u16 status = 0; 5502 SLMP_INFO *info = (SLMP_INFO*)context; 5503 unsigned long flags; 5504 unsigned char delta; 5505 5506 5507 spin_lock_irqsave(&info->lock,flags); 5508 get_signals(info); 5509 spin_unlock_irqrestore(&info->lock,flags); 5510 5511 /* check for DSR/RI state change */ 5512 5513 delta = info->old_signals ^ info->serial_signals; 5514 info->old_signals = info->serial_signals; 5515 5516 if (delta & SerialSignal_DSR) 5517 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR); 5518 5519 if (delta & SerialSignal_RI) 5520 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI); 5521 5522 if (delta & SerialSignal_DCD) 5523 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD); 5524 5525 if (delta & SerialSignal_CTS) 5526 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS); 5527 5528 if (status) 5529 isr_io_pin(info,status); 5530 5531 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); 5532 } 5533 5534 5535 /* Register Access Routines - 5536 * All registers are memory mapped 5537 */ 5538 #define CALC_REGADDR() \ 5539 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 5540 if (info->port_num > 1) \ 5541 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \ 5542 if ( info->port_num & 1) { \ 5543 if (Addr > 0x7f) \ 5544 RegAddr += 0x40; /* DMA access */ \ 5545 else if (Addr > 0x1f && Addr < 0x60) \ 5546 RegAddr += 0x20; /* MSCI access */ \ 5547 } 5548 5549 5550 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr) 5551 { 5552 CALC_REGADDR(); 5553 return *RegAddr; 5554 } 5555 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) 5556 { 5557 CALC_REGADDR(); 5558 *RegAddr = Value; 5559 } 5560 5561 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr) 5562 { 5563 CALC_REGADDR(); 5564 return *((u16 *)RegAddr); 5565 } 5566 5567 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value) 5568 { 5569 CALC_REGADDR(); 5570 *((u16 *)RegAddr) = Value; 5571 } 5572 5573 static unsigned char read_status_reg(SLMP_INFO * info) 5574 { 5575 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; 5576 return *RegAddr; 5577 } 5578 5579 static void write_control_reg(SLMP_INFO * info) 5580 { 5581 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; 5582 *RegAddr = info->port_array[0]->ctrlreg_value; 5583 } 5584 5585 5586 static int synclinkmp_init_one (struct pci_dev *dev, 5587 const struct pci_device_id *ent) 5588 { 5589 if (pci_enable_device(dev)) { 5590 printk("error enabling pci device %p\n", dev); 5591 return -EIO; 5592 } 5593 device_init( ++synclinkmp_adapter_count, dev ); 5594 return 0; 5595 } 5596 5597 static void synclinkmp_remove_one (struct pci_dev *dev) 5598 { 5599 } 5600 5601 5602 5603 5604 5605 /* LDV_COMMENT_BEGIN_MAIN */ 5606 #ifdef LDV_MAIN0_sequence_infinite_withcheck_stateful 5607 5608 /*###########################################################################*/ 5609 5610 /*############## Driver Environment Generator 0.2 output ####################*/ 5611 5612 /*###########################################################################*/ 5613 5614 5615 5616 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test if all kernel resources are correctly released by driver before driver will be unloaded. */ 5617 void ldv_check_final_state(void); 5618 5619 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result. */ 5620 void ldv_check_return_value(int res); 5621 5622 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result of probe() function. */ 5623 void ldv_check_return_value_probe(int res); 5624 5625 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Initializes the model. */ 5626 void ldv_initialize(void); 5627 5628 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Reinitializes the model between distinct model function calls. */ 5629 void ldv_handler_precall(void); 5630 5631 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Returns arbitrary interger value. */ 5632 int nondet_int(void); 5633 5634 /* LDV_COMMENT_VAR_DECLARE_LDV Special variable for LDV verifier. */ 5635 int LDV_IN_INTERRUPT; 5636 5637 /* LDV_COMMENT_FUNCTION_MAIN Main function for LDV verifier. */ 5638 void ldv_main0_sequence_infinite_withcheck_stateful(void) { 5639 5640 5641 5642 /* LDV_COMMENT_BEGIN_VARIABLE_DECLARATION_PART */ 5643 /*============================= VARIABLE DECLARATION PART =============================*/ 5644 /** STRUCT: struct type: pci_driver, struct name: synclinkmp_pci_driver **/ 5645 /* content: static int synclinkmp_init_one (struct pci_dev *dev, const struct pci_device_id *ent)*/ 5646 /* LDV_COMMENT_BEGIN_PREP */ 5647 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 5648 #if defined(__i386__) 5649 # define BREAKPOINT() asm(" int $3"); 5650 #else 5651 # define BREAKPOINT() { } 5652 #endif 5653 #define MAX_DEVICES 12 5654 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 5655 #define SYNCLINK_GENERIC_HDLC 1 5656 #else 5657 #define SYNCLINK_GENERIC_HDLC 0 5658 #endif 5659 #define GET_USER(error,value,addr) error = get_user(value,addr) 5660 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 5661 #define PUT_USER(error,value,addr) error = put_user(value,addr) 5662 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 5663 #define SCABUFSIZE 1024 5664 #define SCA_MEM_SIZE 0x40000 5665 #define SCA_BASE_SIZE 512 5666 #define SCA_REG_SIZE 16 5667 #define SCA_MAX_PORTS 4 5668 #define SCAMAXDESC 128 5669 #define BUFFERLISTSIZE 4096 5670 #define BH_RECEIVE 1 5671 #define BH_TRANSMIT 2 5672 #define BH_STATUS 4 5673 #define IO_PIN_SHUTDOWN_LIMIT 100 5674 #if SYNCLINK_GENERIC_HDLC 5675 #endif 5676 #define MGSL_MAGIC 0x5401 5677 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 5678 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 5679 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 5680 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 5681 #define LPR 0x00 5682 #define PABR0 0x02 5683 #define PABR1 0x03 5684 #define WCRL 0x04 5685 #define WCRM 0x05 5686 #define WCRH 0x06 5687 #define DPCR 0x08 5688 #define DMER 0x09 5689 #define ISR0 0x10 5690 #define ISR1 0x11 5691 #define ISR2 0x12 5692 #define IER0 0x14 5693 #define IER1 0x15 5694 #define IER2 0x16 5695 #define ITCR 0x18 5696 #define INTVR 0x1a 5697 #define IMVR 0x1c 5698 #define TRB 0x20 5699 #define TRBL 0x20 5700 #define TRBH 0x21 5701 #define SR0 0x22 5702 #define SR1 0x23 5703 #define SR2 0x24 5704 #define SR3 0x25 5705 #define FST 0x26 5706 #define IE0 0x28 5707 #define IE1 0x29 5708 #define IE2 0x2a 5709 #define FIE 0x2b 5710 #define CMD 0x2c 5711 #define MD0 0x2e 5712 #define MD1 0x2f 5713 #define MD2 0x30 5714 #define CTL 0x31 5715 #define SA0 0x32 5716 #define SA1 0x33 5717 #define IDL 0x34 5718 #define TMC 0x35 5719 #define RXS 0x36 5720 #define TXS 0x37 5721 #define TRC0 0x38 5722 #define TRC1 0x39 5723 #define RRC 0x3a 5724 #define CST0 0x3c 5725 #define CST1 0x3d 5726 #define TCNT 0x60 5727 #define TCNTL 0x60 5728 #define TCNTH 0x61 5729 #define TCONR 0x62 5730 #define TCONRL 0x62 5731 #define TCONRH 0x63 5732 #define TMCS 0x64 5733 #define TEPR 0x65 5734 #define DARL 0x80 5735 #define DARH 0x81 5736 #define DARB 0x82 5737 #define BAR 0x80 5738 #define BARL 0x80 5739 #define BARH 0x81 5740 #define BARB 0x82 5741 #define SAR 0x84 5742 #define SARL 0x84 5743 #define SARH 0x85 5744 #define SARB 0x86 5745 #define CPB 0x86 5746 #define CDA 0x88 5747 #define CDAL 0x88 5748 #define CDAH 0x89 5749 #define EDA 0x8a 5750 #define EDAL 0x8a 5751 #define EDAH 0x8b 5752 #define BFL 0x8c 5753 #define BFLL 0x8c 5754 #define BFLH 0x8d 5755 #define BCR 0x8e 5756 #define BCRL 0x8e 5757 #define BCRH 0x8f 5758 #define DSR 0x90 5759 #define DMR 0x91 5760 #define FCT 0x93 5761 #define DIR 0x94 5762 #define DCMD 0x95 5763 #define TIMER0 0x00 5764 #define TIMER1 0x08 5765 #define TIMER2 0x10 5766 #define TIMER3 0x18 5767 #define RXDMA 0x00 5768 #define TXDMA 0x20 5769 #define NOOP 0x00 5770 #define TXRESET 0x01 5771 #define TXENABLE 0x02 5772 #define TXDISABLE 0x03 5773 #define TXCRCINIT 0x04 5774 #define TXCRCEXCL 0x05 5775 #define TXEOM 0x06 5776 #define TXABORT 0x07 5777 #define MPON 0x08 5778 #define TXBUFCLR 0x09 5779 #define RXRESET 0x11 5780 #define RXENABLE 0x12 5781 #define RXDISABLE 0x13 5782 #define RXCRCINIT 0x14 5783 #define RXREJECT 0x15 5784 #define SEARCHMP 0x16 5785 #define RXCRCEXCL 0x17 5786 #define RXCRCCALC 0x18 5787 #define CHRESET 0x21 5788 #define HUNT 0x31 5789 #define SWABORT 0x01 5790 #define FEICLEAR 0x02 5791 #define TXINTE BIT7 5792 #define RXINTE BIT6 5793 #define TXRDYE BIT1 5794 #define RXRDYE BIT0 5795 #define UDRN BIT7 5796 #define IDLE BIT6 5797 #define SYNCD BIT4 5798 #define FLGD BIT4 5799 #define CCTS BIT3 5800 #define CDCD BIT2 5801 #define BRKD BIT1 5802 #define ABTD BIT1 5803 #define GAPD BIT1 5804 #define BRKE BIT0 5805 #define IDLD BIT0 5806 #define EOM BIT7 5807 #define PMP BIT6 5808 #define SHRT BIT6 5809 #define PE BIT5 5810 #define ABT BIT5 5811 #define FRME BIT4 5812 #define RBIT BIT4 5813 #define OVRN BIT3 5814 #define CRCE BIT2 5815 #define WAKEUP_CHARS 256 5816 #if SYNCLINK_GENERIC_HDLC 5817 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 5818 #endif 5819 #ifdef SANITY_CHECK 5820 #else 5821 #endif 5822 #if SYNCLINK_GENERIC_HDLC 5823 #endif 5824 #if SYNCLINK_GENERIC_HDLC 5825 #endif 5826 #if SYNCLINK_GENERIC_HDLC 5827 #endif 5828 #ifdef CMSPAR 5829 #endif 5830 #if SYNCLINK_GENERIC_HDLC 5831 #endif 5832 #if SYNCLINK_GENERIC_HDLC 5833 #endif 5834 #if 0 5835 #endif 5836 #if SYNCLINK_GENERIC_HDLC 5837 #endif 5838 #if SYNCLINK_GENERIC_HDLC 5839 #endif 5840 #define TESTFRAMESIZE 20 5841 #if SYNCLINK_GENERIC_HDLC 5842 #endif 5843 #define CALC_REGADDR() \ 5844 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 5845 if (info->port_num > 1) \ 5846 RegAddr += 256; \ 5847 if ( info->port_num & 1) { \ 5848 if (Addr > 0x7f) \ 5849 RegAddr += 0x40; \ 5850 else if (Addr > 0x1f && Addr < 0x60) \ 5851 RegAddr += 0x20; \ 5852 } 5853 /* LDV_COMMENT_END_PREP */ 5854 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_init_one" */ 5855 struct pci_dev * var_group1; 5856 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_init_one" */ 5857 const struct pci_device_id * var_synclinkmp_init_one_121_p1; 5858 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "synclinkmp_init_one" */ 5859 static int res_synclinkmp_init_one_121; 5860 /* content: static void synclinkmp_remove_one (struct pci_dev *dev)*/ 5861 /* LDV_COMMENT_BEGIN_PREP */ 5862 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 5863 #if defined(__i386__) 5864 # define BREAKPOINT() asm(" int $3"); 5865 #else 5866 # define BREAKPOINT() { } 5867 #endif 5868 #define MAX_DEVICES 12 5869 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 5870 #define SYNCLINK_GENERIC_HDLC 1 5871 #else 5872 #define SYNCLINK_GENERIC_HDLC 0 5873 #endif 5874 #define GET_USER(error,value,addr) error = get_user(value,addr) 5875 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 5876 #define PUT_USER(error,value,addr) error = put_user(value,addr) 5877 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 5878 #define SCABUFSIZE 1024 5879 #define SCA_MEM_SIZE 0x40000 5880 #define SCA_BASE_SIZE 512 5881 #define SCA_REG_SIZE 16 5882 #define SCA_MAX_PORTS 4 5883 #define SCAMAXDESC 128 5884 #define BUFFERLISTSIZE 4096 5885 #define BH_RECEIVE 1 5886 #define BH_TRANSMIT 2 5887 #define BH_STATUS 4 5888 #define IO_PIN_SHUTDOWN_LIMIT 100 5889 #if SYNCLINK_GENERIC_HDLC 5890 #endif 5891 #define MGSL_MAGIC 0x5401 5892 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 5893 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 5894 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 5895 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 5896 #define LPR 0x00 5897 #define PABR0 0x02 5898 #define PABR1 0x03 5899 #define WCRL 0x04 5900 #define WCRM 0x05 5901 #define WCRH 0x06 5902 #define DPCR 0x08 5903 #define DMER 0x09 5904 #define ISR0 0x10 5905 #define ISR1 0x11 5906 #define ISR2 0x12 5907 #define IER0 0x14 5908 #define IER1 0x15 5909 #define IER2 0x16 5910 #define ITCR 0x18 5911 #define INTVR 0x1a 5912 #define IMVR 0x1c 5913 #define TRB 0x20 5914 #define TRBL 0x20 5915 #define TRBH 0x21 5916 #define SR0 0x22 5917 #define SR1 0x23 5918 #define SR2 0x24 5919 #define SR3 0x25 5920 #define FST 0x26 5921 #define IE0 0x28 5922 #define IE1 0x29 5923 #define IE2 0x2a 5924 #define FIE 0x2b 5925 #define CMD 0x2c 5926 #define MD0 0x2e 5927 #define MD1 0x2f 5928 #define MD2 0x30 5929 #define CTL 0x31 5930 #define SA0 0x32 5931 #define SA1 0x33 5932 #define IDL 0x34 5933 #define TMC 0x35 5934 #define RXS 0x36 5935 #define TXS 0x37 5936 #define TRC0 0x38 5937 #define TRC1 0x39 5938 #define RRC 0x3a 5939 #define CST0 0x3c 5940 #define CST1 0x3d 5941 #define TCNT 0x60 5942 #define TCNTL 0x60 5943 #define TCNTH 0x61 5944 #define TCONR 0x62 5945 #define TCONRL 0x62 5946 #define TCONRH 0x63 5947 #define TMCS 0x64 5948 #define TEPR 0x65 5949 #define DARL 0x80 5950 #define DARH 0x81 5951 #define DARB 0x82 5952 #define BAR 0x80 5953 #define BARL 0x80 5954 #define BARH 0x81 5955 #define BARB 0x82 5956 #define SAR 0x84 5957 #define SARL 0x84 5958 #define SARH 0x85 5959 #define SARB 0x86 5960 #define CPB 0x86 5961 #define CDA 0x88 5962 #define CDAL 0x88 5963 #define CDAH 0x89 5964 #define EDA 0x8a 5965 #define EDAL 0x8a 5966 #define EDAH 0x8b 5967 #define BFL 0x8c 5968 #define BFLL 0x8c 5969 #define BFLH 0x8d 5970 #define BCR 0x8e 5971 #define BCRL 0x8e 5972 #define BCRH 0x8f 5973 #define DSR 0x90 5974 #define DMR 0x91 5975 #define FCT 0x93 5976 #define DIR 0x94 5977 #define DCMD 0x95 5978 #define TIMER0 0x00 5979 #define TIMER1 0x08 5980 #define TIMER2 0x10 5981 #define TIMER3 0x18 5982 #define RXDMA 0x00 5983 #define TXDMA 0x20 5984 #define NOOP 0x00 5985 #define TXRESET 0x01 5986 #define TXENABLE 0x02 5987 #define TXDISABLE 0x03 5988 #define TXCRCINIT 0x04 5989 #define TXCRCEXCL 0x05 5990 #define TXEOM 0x06 5991 #define TXABORT 0x07 5992 #define MPON 0x08 5993 #define TXBUFCLR 0x09 5994 #define RXRESET 0x11 5995 #define RXENABLE 0x12 5996 #define RXDISABLE 0x13 5997 #define RXCRCINIT 0x14 5998 #define RXREJECT 0x15 5999 #define SEARCHMP 0x16 6000 #define RXCRCEXCL 0x17 6001 #define RXCRCCALC 0x18 6002 #define CHRESET 0x21 6003 #define HUNT 0x31 6004 #define SWABORT 0x01 6005 #define FEICLEAR 0x02 6006 #define TXINTE BIT7 6007 #define RXINTE BIT6 6008 #define TXRDYE BIT1 6009 #define RXRDYE BIT0 6010 #define UDRN BIT7 6011 #define IDLE BIT6 6012 #define SYNCD BIT4 6013 #define FLGD BIT4 6014 #define CCTS BIT3 6015 #define CDCD BIT2 6016 #define BRKD BIT1 6017 #define ABTD BIT1 6018 #define GAPD BIT1 6019 #define BRKE BIT0 6020 #define IDLD BIT0 6021 #define EOM BIT7 6022 #define PMP BIT6 6023 #define SHRT BIT6 6024 #define PE BIT5 6025 #define ABT BIT5 6026 #define FRME BIT4 6027 #define RBIT BIT4 6028 #define OVRN BIT3 6029 #define CRCE BIT2 6030 #define WAKEUP_CHARS 256 6031 #if SYNCLINK_GENERIC_HDLC 6032 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6033 #endif 6034 #ifdef SANITY_CHECK 6035 #else 6036 #endif 6037 #if SYNCLINK_GENERIC_HDLC 6038 #endif 6039 #if SYNCLINK_GENERIC_HDLC 6040 #endif 6041 #if SYNCLINK_GENERIC_HDLC 6042 #endif 6043 #ifdef CMSPAR 6044 #endif 6045 #if SYNCLINK_GENERIC_HDLC 6046 #endif 6047 #if SYNCLINK_GENERIC_HDLC 6048 #endif 6049 #if 0 6050 #endif 6051 #if SYNCLINK_GENERIC_HDLC 6052 #endif 6053 #if SYNCLINK_GENERIC_HDLC 6054 #endif 6055 #define TESTFRAMESIZE 20 6056 #if SYNCLINK_GENERIC_HDLC 6057 #endif 6058 #define CALC_REGADDR() \ 6059 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6060 if (info->port_num > 1) \ 6061 RegAddr += 256; \ 6062 if ( info->port_num & 1) { \ 6063 if (Addr > 0x7f) \ 6064 RegAddr += 0x40; \ 6065 else if (Addr > 0x1f && Addr < 0x60) \ 6066 RegAddr += 0x20; \ 6067 } 6068 /* LDV_COMMENT_END_PREP */ 6069 6070 /** STRUCT: struct type: file_operations, struct name: synclinkmp_proc_fops **/ 6071 /* content: static int synclinkmp_proc_open(struct inode *inode, struct file *file)*/ 6072 /* LDV_COMMENT_BEGIN_PREP */ 6073 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6074 #if defined(__i386__) 6075 # define BREAKPOINT() asm(" int $3"); 6076 #else 6077 # define BREAKPOINT() { } 6078 #endif 6079 #define MAX_DEVICES 12 6080 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6081 #define SYNCLINK_GENERIC_HDLC 1 6082 #else 6083 #define SYNCLINK_GENERIC_HDLC 0 6084 #endif 6085 #define GET_USER(error,value,addr) error = get_user(value,addr) 6086 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6087 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6088 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6089 #define SCABUFSIZE 1024 6090 #define SCA_MEM_SIZE 0x40000 6091 #define SCA_BASE_SIZE 512 6092 #define SCA_REG_SIZE 16 6093 #define SCA_MAX_PORTS 4 6094 #define SCAMAXDESC 128 6095 #define BUFFERLISTSIZE 4096 6096 #define BH_RECEIVE 1 6097 #define BH_TRANSMIT 2 6098 #define BH_STATUS 4 6099 #define IO_PIN_SHUTDOWN_LIMIT 100 6100 #if SYNCLINK_GENERIC_HDLC 6101 #endif 6102 #define MGSL_MAGIC 0x5401 6103 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6104 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6105 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6106 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6107 #define LPR 0x00 6108 #define PABR0 0x02 6109 #define PABR1 0x03 6110 #define WCRL 0x04 6111 #define WCRM 0x05 6112 #define WCRH 0x06 6113 #define DPCR 0x08 6114 #define DMER 0x09 6115 #define ISR0 0x10 6116 #define ISR1 0x11 6117 #define ISR2 0x12 6118 #define IER0 0x14 6119 #define IER1 0x15 6120 #define IER2 0x16 6121 #define ITCR 0x18 6122 #define INTVR 0x1a 6123 #define IMVR 0x1c 6124 #define TRB 0x20 6125 #define TRBL 0x20 6126 #define TRBH 0x21 6127 #define SR0 0x22 6128 #define SR1 0x23 6129 #define SR2 0x24 6130 #define SR3 0x25 6131 #define FST 0x26 6132 #define IE0 0x28 6133 #define IE1 0x29 6134 #define IE2 0x2a 6135 #define FIE 0x2b 6136 #define CMD 0x2c 6137 #define MD0 0x2e 6138 #define MD1 0x2f 6139 #define MD2 0x30 6140 #define CTL 0x31 6141 #define SA0 0x32 6142 #define SA1 0x33 6143 #define IDL 0x34 6144 #define TMC 0x35 6145 #define RXS 0x36 6146 #define TXS 0x37 6147 #define TRC0 0x38 6148 #define TRC1 0x39 6149 #define RRC 0x3a 6150 #define CST0 0x3c 6151 #define CST1 0x3d 6152 #define TCNT 0x60 6153 #define TCNTL 0x60 6154 #define TCNTH 0x61 6155 #define TCONR 0x62 6156 #define TCONRL 0x62 6157 #define TCONRH 0x63 6158 #define TMCS 0x64 6159 #define TEPR 0x65 6160 #define DARL 0x80 6161 #define DARH 0x81 6162 #define DARB 0x82 6163 #define BAR 0x80 6164 #define BARL 0x80 6165 #define BARH 0x81 6166 #define BARB 0x82 6167 #define SAR 0x84 6168 #define SARL 0x84 6169 #define SARH 0x85 6170 #define SARB 0x86 6171 #define CPB 0x86 6172 #define CDA 0x88 6173 #define CDAL 0x88 6174 #define CDAH 0x89 6175 #define EDA 0x8a 6176 #define EDAL 0x8a 6177 #define EDAH 0x8b 6178 #define BFL 0x8c 6179 #define BFLL 0x8c 6180 #define BFLH 0x8d 6181 #define BCR 0x8e 6182 #define BCRL 0x8e 6183 #define BCRH 0x8f 6184 #define DSR 0x90 6185 #define DMR 0x91 6186 #define FCT 0x93 6187 #define DIR 0x94 6188 #define DCMD 0x95 6189 #define TIMER0 0x00 6190 #define TIMER1 0x08 6191 #define TIMER2 0x10 6192 #define TIMER3 0x18 6193 #define RXDMA 0x00 6194 #define TXDMA 0x20 6195 #define NOOP 0x00 6196 #define TXRESET 0x01 6197 #define TXENABLE 0x02 6198 #define TXDISABLE 0x03 6199 #define TXCRCINIT 0x04 6200 #define TXCRCEXCL 0x05 6201 #define TXEOM 0x06 6202 #define TXABORT 0x07 6203 #define MPON 0x08 6204 #define TXBUFCLR 0x09 6205 #define RXRESET 0x11 6206 #define RXENABLE 0x12 6207 #define RXDISABLE 0x13 6208 #define RXCRCINIT 0x14 6209 #define RXREJECT 0x15 6210 #define SEARCHMP 0x16 6211 #define RXCRCEXCL 0x17 6212 #define RXCRCCALC 0x18 6213 #define CHRESET 0x21 6214 #define HUNT 0x31 6215 #define SWABORT 0x01 6216 #define FEICLEAR 0x02 6217 #define TXINTE BIT7 6218 #define RXINTE BIT6 6219 #define TXRDYE BIT1 6220 #define RXRDYE BIT0 6221 #define UDRN BIT7 6222 #define IDLE BIT6 6223 #define SYNCD BIT4 6224 #define FLGD BIT4 6225 #define CCTS BIT3 6226 #define CDCD BIT2 6227 #define BRKD BIT1 6228 #define ABTD BIT1 6229 #define GAPD BIT1 6230 #define BRKE BIT0 6231 #define IDLD BIT0 6232 #define EOM BIT7 6233 #define PMP BIT6 6234 #define SHRT BIT6 6235 #define PE BIT5 6236 #define ABT BIT5 6237 #define FRME BIT4 6238 #define RBIT BIT4 6239 #define OVRN BIT3 6240 #define CRCE BIT2 6241 #define WAKEUP_CHARS 256 6242 #if SYNCLINK_GENERIC_HDLC 6243 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6244 #endif 6245 #ifdef SANITY_CHECK 6246 #else 6247 #endif 6248 /* LDV_COMMENT_END_PREP */ 6249 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_proc_open" */ 6250 struct inode * var_group2; 6251 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_proc_open" */ 6252 struct file * var_group3; 6253 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "synclinkmp_proc_open" */ 6254 static int res_synclinkmp_proc_open_21; 6255 /* LDV_COMMENT_BEGIN_PREP */ 6256 #if SYNCLINK_GENERIC_HDLC 6257 #endif 6258 #if SYNCLINK_GENERIC_HDLC 6259 #endif 6260 #if SYNCLINK_GENERIC_HDLC 6261 #endif 6262 #ifdef CMSPAR 6263 #endif 6264 #if SYNCLINK_GENERIC_HDLC 6265 #endif 6266 #if SYNCLINK_GENERIC_HDLC 6267 #endif 6268 #if 0 6269 #endif 6270 #if SYNCLINK_GENERIC_HDLC 6271 #endif 6272 #if SYNCLINK_GENERIC_HDLC 6273 #endif 6274 #define TESTFRAMESIZE 20 6275 #if SYNCLINK_GENERIC_HDLC 6276 #endif 6277 #define CALC_REGADDR() \ 6278 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6279 if (info->port_num > 1) \ 6280 RegAddr += 256; \ 6281 if ( info->port_num & 1) { \ 6282 if (Addr > 0x7f) \ 6283 RegAddr += 0x40; \ 6284 else if (Addr > 0x1f && Addr < 0x60) \ 6285 RegAddr += 0x20; \ 6286 } 6287 /* LDV_COMMENT_END_PREP */ 6288 6289 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 6290 /* content: static int hdlcdev_open(struct net_device *dev)*/ 6291 /* LDV_COMMENT_BEGIN_PREP */ 6292 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6293 #if defined(__i386__) 6294 # define BREAKPOINT() asm(" int $3"); 6295 #else 6296 # define BREAKPOINT() { } 6297 #endif 6298 #define MAX_DEVICES 12 6299 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6300 #define SYNCLINK_GENERIC_HDLC 1 6301 #else 6302 #define SYNCLINK_GENERIC_HDLC 0 6303 #endif 6304 #define GET_USER(error,value,addr) error = get_user(value,addr) 6305 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6306 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6307 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6308 #define SCABUFSIZE 1024 6309 #define SCA_MEM_SIZE 0x40000 6310 #define SCA_BASE_SIZE 512 6311 #define SCA_REG_SIZE 16 6312 #define SCA_MAX_PORTS 4 6313 #define SCAMAXDESC 128 6314 #define BUFFERLISTSIZE 4096 6315 #define BH_RECEIVE 1 6316 #define BH_TRANSMIT 2 6317 #define BH_STATUS 4 6318 #define IO_PIN_SHUTDOWN_LIMIT 100 6319 #if SYNCLINK_GENERIC_HDLC 6320 #endif 6321 #define MGSL_MAGIC 0x5401 6322 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6323 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6324 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6325 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6326 #define LPR 0x00 6327 #define PABR0 0x02 6328 #define PABR1 0x03 6329 #define WCRL 0x04 6330 #define WCRM 0x05 6331 #define WCRH 0x06 6332 #define DPCR 0x08 6333 #define DMER 0x09 6334 #define ISR0 0x10 6335 #define ISR1 0x11 6336 #define ISR2 0x12 6337 #define IER0 0x14 6338 #define IER1 0x15 6339 #define IER2 0x16 6340 #define ITCR 0x18 6341 #define INTVR 0x1a 6342 #define IMVR 0x1c 6343 #define TRB 0x20 6344 #define TRBL 0x20 6345 #define TRBH 0x21 6346 #define SR0 0x22 6347 #define SR1 0x23 6348 #define SR2 0x24 6349 #define SR3 0x25 6350 #define FST 0x26 6351 #define IE0 0x28 6352 #define IE1 0x29 6353 #define IE2 0x2a 6354 #define FIE 0x2b 6355 #define CMD 0x2c 6356 #define MD0 0x2e 6357 #define MD1 0x2f 6358 #define MD2 0x30 6359 #define CTL 0x31 6360 #define SA0 0x32 6361 #define SA1 0x33 6362 #define IDL 0x34 6363 #define TMC 0x35 6364 #define RXS 0x36 6365 #define TXS 0x37 6366 #define TRC0 0x38 6367 #define TRC1 0x39 6368 #define RRC 0x3a 6369 #define CST0 0x3c 6370 #define CST1 0x3d 6371 #define TCNT 0x60 6372 #define TCNTL 0x60 6373 #define TCNTH 0x61 6374 #define TCONR 0x62 6375 #define TCONRL 0x62 6376 #define TCONRH 0x63 6377 #define TMCS 0x64 6378 #define TEPR 0x65 6379 #define DARL 0x80 6380 #define DARH 0x81 6381 #define DARB 0x82 6382 #define BAR 0x80 6383 #define BARL 0x80 6384 #define BARH 0x81 6385 #define BARB 0x82 6386 #define SAR 0x84 6387 #define SARL 0x84 6388 #define SARH 0x85 6389 #define SARB 0x86 6390 #define CPB 0x86 6391 #define CDA 0x88 6392 #define CDAL 0x88 6393 #define CDAH 0x89 6394 #define EDA 0x8a 6395 #define EDAL 0x8a 6396 #define EDAH 0x8b 6397 #define BFL 0x8c 6398 #define BFLL 0x8c 6399 #define BFLH 0x8d 6400 #define BCR 0x8e 6401 #define BCRL 0x8e 6402 #define BCRH 0x8f 6403 #define DSR 0x90 6404 #define DMR 0x91 6405 #define FCT 0x93 6406 #define DIR 0x94 6407 #define DCMD 0x95 6408 #define TIMER0 0x00 6409 #define TIMER1 0x08 6410 #define TIMER2 0x10 6411 #define TIMER3 0x18 6412 #define RXDMA 0x00 6413 #define TXDMA 0x20 6414 #define NOOP 0x00 6415 #define TXRESET 0x01 6416 #define TXENABLE 0x02 6417 #define TXDISABLE 0x03 6418 #define TXCRCINIT 0x04 6419 #define TXCRCEXCL 0x05 6420 #define TXEOM 0x06 6421 #define TXABORT 0x07 6422 #define MPON 0x08 6423 #define TXBUFCLR 0x09 6424 #define RXRESET 0x11 6425 #define RXENABLE 0x12 6426 #define RXDISABLE 0x13 6427 #define RXCRCINIT 0x14 6428 #define RXREJECT 0x15 6429 #define SEARCHMP 0x16 6430 #define RXCRCEXCL 0x17 6431 #define RXCRCCALC 0x18 6432 #define CHRESET 0x21 6433 #define HUNT 0x31 6434 #define SWABORT 0x01 6435 #define FEICLEAR 0x02 6436 #define TXINTE BIT7 6437 #define RXINTE BIT6 6438 #define TXRDYE BIT1 6439 #define RXRDYE BIT0 6440 #define UDRN BIT7 6441 #define IDLE BIT6 6442 #define SYNCD BIT4 6443 #define FLGD BIT4 6444 #define CCTS BIT3 6445 #define CDCD BIT2 6446 #define BRKD BIT1 6447 #define ABTD BIT1 6448 #define GAPD BIT1 6449 #define BRKE BIT0 6450 #define IDLD BIT0 6451 #define EOM BIT7 6452 #define PMP BIT6 6453 #define SHRT BIT6 6454 #define PE BIT5 6455 #define ABT BIT5 6456 #define FRME BIT4 6457 #define RBIT BIT4 6458 #define OVRN BIT3 6459 #define CRCE BIT2 6460 #define WAKEUP_CHARS 256 6461 #if SYNCLINK_GENERIC_HDLC 6462 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6463 #endif 6464 #ifdef SANITY_CHECK 6465 #else 6466 #endif 6467 #if SYNCLINK_GENERIC_HDLC 6468 /* LDV_COMMENT_END_PREP */ 6469 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "hdlcdev_open" */ 6470 struct net_device * var_group4; 6471 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "hdlcdev_open" */ 6472 static int res_hdlcdev_open_28; 6473 /* LDV_COMMENT_BEGIN_PREP */ 6474 #endif 6475 #if SYNCLINK_GENERIC_HDLC 6476 #endif 6477 #if SYNCLINK_GENERIC_HDLC 6478 #endif 6479 #ifdef CMSPAR 6480 #endif 6481 #if SYNCLINK_GENERIC_HDLC 6482 #endif 6483 #if SYNCLINK_GENERIC_HDLC 6484 #endif 6485 #if 0 6486 #endif 6487 #if SYNCLINK_GENERIC_HDLC 6488 #endif 6489 #if SYNCLINK_GENERIC_HDLC 6490 #endif 6491 #define TESTFRAMESIZE 20 6492 #if SYNCLINK_GENERIC_HDLC 6493 #endif 6494 #define CALC_REGADDR() \ 6495 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6496 if (info->port_num > 1) \ 6497 RegAddr += 256; \ 6498 if ( info->port_num & 1) { \ 6499 if (Addr > 0x7f) \ 6500 RegAddr += 0x40; \ 6501 else if (Addr > 0x1f && Addr < 0x60) \ 6502 RegAddr += 0x20; \ 6503 } 6504 /* LDV_COMMENT_END_PREP */ 6505 /* content: static int hdlcdev_close(struct net_device *dev)*/ 6506 /* LDV_COMMENT_BEGIN_PREP */ 6507 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6508 #if defined(__i386__) 6509 # define BREAKPOINT() asm(" int $3"); 6510 #else 6511 # define BREAKPOINT() { } 6512 #endif 6513 #define MAX_DEVICES 12 6514 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6515 #define SYNCLINK_GENERIC_HDLC 1 6516 #else 6517 #define SYNCLINK_GENERIC_HDLC 0 6518 #endif 6519 #define GET_USER(error,value,addr) error = get_user(value,addr) 6520 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6521 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6522 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6523 #define SCABUFSIZE 1024 6524 #define SCA_MEM_SIZE 0x40000 6525 #define SCA_BASE_SIZE 512 6526 #define SCA_REG_SIZE 16 6527 #define SCA_MAX_PORTS 4 6528 #define SCAMAXDESC 128 6529 #define BUFFERLISTSIZE 4096 6530 #define BH_RECEIVE 1 6531 #define BH_TRANSMIT 2 6532 #define BH_STATUS 4 6533 #define IO_PIN_SHUTDOWN_LIMIT 100 6534 #if SYNCLINK_GENERIC_HDLC 6535 #endif 6536 #define MGSL_MAGIC 0x5401 6537 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6538 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6539 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6540 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6541 #define LPR 0x00 6542 #define PABR0 0x02 6543 #define PABR1 0x03 6544 #define WCRL 0x04 6545 #define WCRM 0x05 6546 #define WCRH 0x06 6547 #define DPCR 0x08 6548 #define DMER 0x09 6549 #define ISR0 0x10 6550 #define ISR1 0x11 6551 #define ISR2 0x12 6552 #define IER0 0x14 6553 #define IER1 0x15 6554 #define IER2 0x16 6555 #define ITCR 0x18 6556 #define INTVR 0x1a 6557 #define IMVR 0x1c 6558 #define TRB 0x20 6559 #define TRBL 0x20 6560 #define TRBH 0x21 6561 #define SR0 0x22 6562 #define SR1 0x23 6563 #define SR2 0x24 6564 #define SR3 0x25 6565 #define FST 0x26 6566 #define IE0 0x28 6567 #define IE1 0x29 6568 #define IE2 0x2a 6569 #define FIE 0x2b 6570 #define CMD 0x2c 6571 #define MD0 0x2e 6572 #define MD1 0x2f 6573 #define MD2 0x30 6574 #define CTL 0x31 6575 #define SA0 0x32 6576 #define SA1 0x33 6577 #define IDL 0x34 6578 #define TMC 0x35 6579 #define RXS 0x36 6580 #define TXS 0x37 6581 #define TRC0 0x38 6582 #define TRC1 0x39 6583 #define RRC 0x3a 6584 #define CST0 0x3c 6585 #define CST1 0x3d 6586 #define TCNT 0x60 6587 #define TCNTL 0x60 6588 #define TCNTH 0x61 6589 #define TCONR 0x62 6590 #define TCONRL 0x62 6591 #define TCONRH 0x63 6592 #define TMCS 0x64 6593 #define TEPR 0x65 6594 #define DARL 0x80 6595 #define DARH 0x81 6596 #define DARB 0x82 6597 #define BAR 0x80 6598 #define BARL 0x80 6599 #define BARH 0x81 6600 #define BARB 0x82 6601 #define SAR 0x84 6602 #define SARL 0x84 6603 #define SARH 0x85 6604 #define SARB 0x86 6605 #define CPB 0x86 6606 #define CDA 0x88 6607 #define CDAL 0x88 6608 #define CDAH 0x89 6609 #define EDA 0x8a 6610 #define EDAL 0x8a 6611 #define EDAH 0x8b 6612 #define BFL 0x8c 6613 #define BFLL 0x8c 6614 #define BFLH 0x8d 6615 #define BCR 0x8e 6616 #define BCRL 0x8e 6617 #define BCRH 0x8f 6618 #define DSR 0x90 6619 #define DMR 0x91 6620 #define FCT 0x93 6621 #define DIR 0x94 6622 #define DCMD 0x95 6623 #define TIMER0 0x00 6624 #define TIMER1 0x08 6625 #define TIMER2 0x10 6626 #define TIMER3 0x18 6627 #define RXDMA 0x00 6628 #define TXDMA 0x20 6629 #define NOOP 0x00 6630 #define TXRESET 0x01 6631 #define TXENABLE 0x02 6632 #define TXDISABLE 0x03 6633 #define TXCRCINIT 0x04 6634 #define TXCRCEXCL 0x05 6635 #define TXEOM 0x06 6636 #define TXABORT 0x07 6637 #define MPON 0x08 6638 #define TXBUFCLR 0x09 6639 #define RXRESET 0x11 6640 #define RXENABLE 0x12 6641 #define RXDISABLE 0x13 6642 #define RXCRCINIT 0x14 6643 #define RXREJECT 0x15 6644 #define SEARCHMP 0x16 6645 #define RXCRCEXCL 0x17 6646 #define RXCRCCALC 0x18 6647 #define CHRESET 0x21 6648 #define HUNT 0x31 6649 #define SWABORT 0x01 6650 #define FEICLEAR 0x02 6651 #define TXINTE BIT7 6652 #define RXINTE BIT6 6653 #define TXRDYE BIT1 6654 #define RXRDYE BIT0 6655 #define UDRN BIT7 6656 #define IDLE BIT6 6657 #define SYNCD BIT4 6658 #define FLGD BIT4 6659 #define CCTS BIT3 6660 #define CDCD BIT2 6661 #define BRKD BIT1 6662 #define ABTD BIT1 6663 #define GAPD BIT1 6664 #define BRKE BIT0 6665 #define IDLD BIT0 6666 #define EOM BIT7 6667 #define PMP BIT6 6668 #define SHRT BIT6 6669 #define PE BIT5 6670 #define ABT BIT5 6671 #define FRME BIT4 6672 #define RBIT BIT4 6673 #define OVRN BIT3 6674 #define CRCE BIT2 6675 #define WAKEUP_CHARS 256 6676 #if SYNCLINK_GENERIC_HDLC 6677 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6678 #endif 6679 #ifdef SANITY_CHECK 6680 #else 6681 #endif 6682 #if SYNCLINK_GENERIC_HDLC 6683 /* LDV_COMMENT_END_PREP */ 6684 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "hdlcdev_close" */ 6685 static int res_hdlcdev_close_29; 6686 /* LDV_COMMENT_BEGIN_PREP */ 6687 #endif 6688 #if SYNCLINK_GENERIC_HDLC 6689 #endif 6690 #if SYNCLINK_GENERIC_HDLC 6691 #endif 6692 #ifdef CMSPAR 6693 #endif 6694 #if SYNCLINK_GENERIC_HDLC 6695 #endif 6696 #if SYNCLINK_GENERIC_HDLC 6697 #endif 6698 #if 0 6699 #endif 6700 #if SYNCLINK_GENERIC_HDLC 6701 #endif 6702 #if SYNCLINK_GENERIC_HDLC 6703 #endif 6704 #define TESTFRAMESIZE 20 6705 #if SYNCLINK_GENERIC_HDLC 6706 #endif 6707 #define CALC_REGADDR() \ 6708 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6709 if (info->port_num > 1) \ 6710 RegAddr += 256; \ 6711 if ( info->port_num & 1) { \ 6712 if (Addr > 0x7f) \ 6713 RegAddr += 0x40; \ 6714 else if (Addr > 0x1f && Addr < 0x60) \ 6715 RegAddr += 0x20; \ 6716 } 6717 /* LDV_COMMENT_END_PREP */ 6718 /* content: static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)*/ 6719 /* LDV_COMMENT_BEGIN_PREP */ 6720 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6721 #if defined(__i386__) 6722 # define BREAKPOINT() asm(" int $3"); 6723 #else 6724 # define BREAKPOINT() { } 6725 #endif 6726 #define MAX_DEVICES 12 6727 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6728 #define SYNCLINK_GENERIC_HDLC 1 6729 #else 6730 #define SYNCLINK_GENERIC_HDLC 0 6731 #endif 6732 #define GET_USER(error,value,addr) error = get_user(value,addr) 6733 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6734 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6735 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6736 #define SCABUFSIZE 1024 6737 #define SCA_MEM_SIZE 0x40000 6738 #define SCA_BASE_SIZE 512 6739 #define SCA_REG_SIZE 16 6740 #define SCA_MAX_PORTS 4 6741 #define SCAMAXDESC 128 6742 #define BUFFERLISTSIZE 4096 6743 #define BH_RECEIVE 1 6744 #define BH_TRANSMIT 2 6745 #define BH_STATUS 4 6746 #define IO_PIN_SHUTDOWN_LIMIT 100 6747 #if SYNCLINK_GENERIC_HDLC 6748 #endif 6749 #define MGSL_MAGIC 0x5401 6750 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6751 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6752 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6753 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6754 #define LPR 0x00 6755 #define PABR0 0x02 6756 #define PABR1 0x03 6757 #define WCRL 0x04 6758 #define WCRM 0x05 6759 #define WCRH 0x06 6760 #define DPCR 0x08 6761 #define DMER 0x09 6762 #define ISR0 0x10 6763 #define ISR1 0x11 6764 #define ISR2 0x12 6765 #define IER0 0x14 6766 #define IER1 0x15 6767 #define IER2 0x16 6768 #define ITCR 0x18 6769 #define INTVR 0x1a 6770 #define IMVR 0x1c 6771 #define TRB 0x20 6772 #define TRBL 0x20 6773 #define TRBH 0x21 6774 #define SR0 0x22 6775 #define SR1 0x23 6776 #define SR2 0x24 6777 #define SR3 0x25 6778 #define FST 0x26 6779 #define IE0 0x28 6780 #define IE1 0x29 6781 #define IE2 0x2a 6782 #define FIE 0x2b 6783 #define CMD 0x2c 6784 #define MD0 0x2e 6785 #define MD1 0x2f 6786 #define MD2 0x30 6787 #define CTL 0x31 6788 #define SA0 0x32 6789 #define SA1 0x33 6790 #define IDL 0x34 6791 #define TMC 0x35 6792 #define RXS 0x36 6793 #define TXS 0x37 6794 #define TRC0 0x38 6795 #define TRC1 0x39 6796 #define RRC 0x3a 6797 #define CST0 0x3c 6798 #define CST1 0x3d 6799 #define TCNT 0x60 6800 #define TCNTL 0x60 6801 #define TCNTH 0x61 6802 #define TCONR 0x62 6803 #define TCONRL 0x62 6804 #define TCONRH 0x63 6805 #define TMCS 0x64 6806 #define TEPR 0x65 6807 #define DARL 0x80 6808 #define DARH 0x81 6809 #define DARB 0x82 6810 #define BAR 0x80 6811 #define BARL 0x80 6812 #define BARH 0x81 6813 #define BARB 0x82 6814 #define SAR 0x84 6815 #define SARL 0x84 6816 #define SARH 0x85 6817 #define SARB 0x86 6818 #define CPB 0x86 6819 #define CDA 0x88 6820 #define CDAL 0x88 6821 #define CDAH 0x89 6822 #define EDA 0x8a 6823 #define EDAL 0x8a 6824 #define EDAH 0x8b 6825 #define BFL 0x8c 6826 #define BFLL 0x8c 6827 #define BFLH 0x8d 6828 #define BCR 0x8e 6829 #define BCRL 0x8e 6830 #define BCRH 0x8f 6831 #define DSR 0x90 6832 #define DMR 0x91 6833 #define FCT 0x93 6834 #define DIR 0x94 6835 #define DCMD 0x95 6836 #define TIMER0 0x00 6837 #define TIMER1 0x08 6838 #define TIMER2 0x10 6839 #define TIMER3 0x18 6840 #define RXDMA 0x00 6841 #define TXDMA 0x20 6842 #define NOOP 0x00 6843 #define TXRESET 0x01 6844 #define TXENABLE 0x02 6845 #define TXDISABLE 0x03 6846 #define TXCRCINIT 0x04 6847 #define TXCRCEXCL 0x05 6848 #define TXEOM 0x06 6849 #define TXABORT 0x07 6850 #define MPON 0x08 6851 #define TXBUFCLR 0x09 6852 #define RXRESET 0x11 6853 #define RXENABLE 0x12 6854 #define RXDISABLE 0x13 6855 #define RXCRCINIT 0x14 6856 #define RXREJECT 0x15 6857 #define SEARCHMP 0x16 6858 #define RXCRCEXCL 0x17 6859 #define RXCRCCALC 0x18 6860 #define CHRESET 0x21 6861 #define HUNT 0x31 6862 #define SWABORT 0x01 6863 #define FEICLEAR 0x02 6864 #define TXINTE BIT7 6865 #define RXINTE BIT6 6866 #define TXRDYE BIT1 6867 #define RXRDYE BIT0 6868 #define UDRN BIT7 6869 #define IDLE BIT6 6870 #define SYNCD BIT4 6871 #define FLGD BIT4 6872 #define CCTS BIT3 6873 #define CDCD BIT2 6874 #define BRKD BIT1 6875 #define ABTD BIT1 6876 #define GAPD BIT1 6877 #define BRKE BIT0 6878 #define IDLD BIT0 6879 #define EOM BIT7 6880 #define PMP BIT6 6881 #define SHRT BIT6 6882 #define PE BIT5 6883 #define ABT BIT5 6884 #define FRME BIT4 6885 #define RBIT BIT4 6886 #define OVRN BIT3 6887 #define CRCE BIT2 6888 #define WAKEUP_CHARS 256 6889 #if SYNCLINK_GENERIC_HDLC 6890 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6891 #endif 6892 #ifdef SANITY_CHECK 6893 #else 6894 #endif 6895 #if SYNCLINK_GENERIC_HDLC 6896 /* LDV_COMMENT_END_PREP */ 6897 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "hdlcdev_ioctl" */ 6898 struct ifreq * var_group5; 6899 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "hdlcdev_ioctl" */ 6900 int var_hdlcdev_ioctl_30_p2; 6901 /* LDV_COMMENT_BEGIN_PREP */ 6902 #endif 6903 #if SYNCLINK_GENERIC_HDLC 6904 #endif 6905 #if SYNCLINK_GENERIC_HDLC 6906 #endif 6907 #ifdef CMSPAR 6908 #endif 6909 #if SYNCLINK_GENERIC_HDLC 6910 #endif 6911 #if SYNCLINK_GENERIC_HDLC 6912 #endif 6913 #if 0 6914 #endif 6915 #if SYNCLINK_GENERIC_HDLC 6916 #endif 6917 #if SYNCLINK_GENERIC_HDLC 6918 #endif 6919 #define TESTFRAMESIZE 20 6920 #if SYNCLINK_GENERIC_HDLC 6921 #endif 6922 #define CALC_REGADDR() \ 6923 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6924 if (info->port_num > 1) \ 6925 RegAddr += 256; \ 6926 if ( info->port_num & 1) { \ 6927 if (Addr > 0x7f) \ 6928 RegAddr += 0x40; \ 6929 else if (Addr > 0x1f && Addr < 0x60) \ 6930 RegAddr += 0x20; \ 6931 } 6932 /* LDV_COMMENT_END_PREP */ 6933 /* content: static void hdlcdev_tx_timeout(struct net_device *dev)*/ 6934 /* LDV_COMMENT_BEGIN_PREP */ 6935 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6936 #if defined(__i386__) 6937 # define BREAKPOINT() asm(" int $3"); 6938 #else 6939 # define BREAKPOINT() { } 6940 #endif 6941 #define MAX_DEVICES 12 6942 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6943 #define SYNCLINK_GENERIC_HDLC 1 6944 #else 6945 #define SYNCLINK_GENERIC_HDLC 0 6946 #endif 6947 #define GET_USER(error,value,addr) error = get_user(value,addr) 6948 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6949 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6950 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6951 #define SCABUFSIZE 1024 6952 #define SCA_MEM_SIZE 0x40000 6953 #define SCA_BASE_SIZE 512 6954 #define SCA_REG_SIZE 16 6955 #define SCA_MAX_PORTS 4 6956 #define SCAMAXDESC 128 6957 #define BUFFERLISTSIZE 4096 6958 #define BH_RECEIVE 1 6959 #define BH_TRANSMIT 2 6960 #define BH_STATUS 4 6961 #define IO_PIN_SHUTDOWN_LIMIT 100 6962 #if SYNCLINK_GENERIC_HDLC 6963 #endif 6964 #define MGSL_MAGIC 0x5401 6965 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6966 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6967 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6968 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6969 #define LPR 0x00 6970 #define PABR0 0x02 6971 #define PABR1 0x03 6972 #define WCRL 0x04 6973 #define WCRM 0x05 6974 #define WCRH 0x06 6975 #define DPCR 0x08 6976 #define DMER 0x09 6977 #define ISR0 0x10 6978 #define ISR1 0x11 6979 #define ISR2 0x12 6980 #define IER0 0x14 6981 #define IER1 0x15 6982 #define IER2 0x16 6983 #define ITCR 0x18 6984 #define INTVR 0x1a 6985 #define IMVR 0x1c 6986 #define TRB 0x20 6987 #define TRBL 0x20 6988 #define TRBH 0x21 6989 #define SR0 0x22 6990 #define SR1 0x23 6991 #define SR2 0x24 6992 #define SR3 0x25 6993 #define FST 0x26 6994 #define IE0 0x28 6995 #define IE1 0x29 6996 #define IE2 0x2a 6997 #define FIE 0x2b 6998 #define CMD 0x2c 6999 #define MD0 0x2e 7000 #define MD1 0x2f 7001 #define MD2 0x30 7002 #define CTL 0x31 7003 #define SA0 0x32 7004 #define SA1 0x33 7005 #define IDL 0x34 7006 #define TMC 0x35 7007 #define RXS 0x36 7008 #define TXS 0x37 7009 #define TRC0 0x38 7010 #define TRC1 0x39 7011 #define RRC 0x3a 7012 #define CST0 0x3c 7013 #define CST1 0x3d 7014 #define TCNT 0x60 7015 #define TCNTL 0x60 7016 #define TCNTH 0x61 7017 #define TCONR 0x62 7018 #define TCONRL 0x62 7019 #define TCONRH 0x63 7020 #define TMCS 0x64 7021 #define TEPR 0x65 7022 #define DARL 0x80 7023 #define DARH 0x81 7024 #define DARB 0x82 7025 #define BAR 0x80 7026 #define BARL 0x80 7027 #define BARH 0x81 7028 #define BARB 0x82 7029 #define SAR 0x84 7030 #define SARL 0x84 7031 #define SARH 0x85 7032 #define SARB 0x86 7033 #define CPB 0x86 7034 #define CDA 0x88 7035 #define CDAL 0x88 7036 #define CDAH 0x89 7037 #define EDA 0x8a 7038 #define EDAL 0x8a 7039 #define EDAH 0x8b 7040 #define BFL 0x8c 7041 #define BFLL 0x8c 7042 #define BFLH 0x8d 7043 #define BCR 0x8e 7044 #define BCRL 0x8e 7045 #define BCRH 0x8f 7046 #define DSR 0x90 7047 #define DMR 0x91 7048 #define FCT 0x93 7049 #define DIR 0x94 7050 #define DCMD 0x95 7051 #define TIMER0 0x00 7052 #define TIMER1 0x08 7053 #define TIMER2 0x10 7054 #define TIMER3 0x18 7055 #define RXDMA 0x00 7056 #define TXDMA 0x20 7057 #define NOOP 0x00 7058 #define TXRESET 0x01 7059 #define TXENABLE 0x02 7060 #define TXDISABLE 0x03 7061 #define TXCRCINIT 0x04 7062 #define TXCRCEXCL 0x05 7063 #define TXEOM 0x06 7064 #define TXABORT 0x07 7065 #define MPON 0x08 7066 #define TXBUFCLR 0x09 7067 #define RXRESET 0x11 7068 #define RXENABLE 0x12 7069 #define RXDISABLE 0x13 7070 #define RXCRCINIT 0x14 7071 #define RXREJECT 0x15 7072 #define SEARCHMP 0x16 7073 #define RXCRCEXCL 0x17 7074 #define RXCRCCALC 0x18 7075 #define CHRESET 0x21 7076 #define HUNT 0x31 7077 #define SWABORT 0x01 7078 #define FEICLEAR 0x02 7079 #define TXINTE BIT7 7080 #define RXINTE BIT6 7081 #define TXRDYE BIT1 7082 #define RXRDYE BIT0 7083 #define UDRN BIT7 7084 #define IDLE BIT6 7085 #define SYNCD BIT4 7086 #define FLGD BIT4 7087 #define CCTS BIT3 7088 #define CDCD BIT2 7089 #define BRKD BIT1 7090 #define ABTD BIT1 7091 #define GAPD BIT1 7092 #define BRKE BIT0 7093 #define IDLD BIT0 7094 #define EOM BIT7 7095 #define PMP BIT6 7096 #define SHRT BIT6 7097 #define PE BIT5 7098 #define ABT BIT5 7099 #define FRME BIT4 7100 #define RBIT BIT4 7101 #define OVRN BIT3 7102 #define CRCE BIT2 7103 #define WAKEUP_CHARS 256 7104 #if SYNCLINK_GENERIC_HDLC 7105 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7106 #endif 7107 #ifdef SANITY_CHECK 7108 #else 7109 #endif 7110 #if SYNCLINK_GENERIC_HDLC 7111 /* LDV_COMMENT_END_PREP */ 7112 /* LDV_COMMENT_BEGIN_PREP */ 7113 #endif 7114 #if SYNCLINK_GENERIC_HDLC 7115 #endif 7116 #if SYNCLINK_GENERIC_HDLC 7117 #endif 7118 #ifdef CMSPAR 7119 #endif 7120 #if SYNCLINK_GENERIC_HDLC 7121 #endif 7122 #if SYNCLINK_GENERIC_HDLC 7123 #endif 7124 #if 0 7125 #endif 7126 #if SYNCLINK_GENERIC_HDLC 7127 #endif 7128 #if SYNCLINK_GENERIC_HDLC 7129 #endif 7130 #define TESTFRAMESIZE 20 7131 #if SYNCLINK_GENERIC_HDLC 7132 #endif 7133 #define CALC_REGADDR() \ 7134 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7135 if (info->port_num > 1) \ 7136 RegAddr += 256; \ 7137 if ( info->port_num & 1) { \ 7138 if (Addr > 0x7f) \ 7139 RegAddr += 0x40; \ 7140 else if (Addr > 0x1f && Addr < 0x60) \ 7141 RegAddr += 0x20; \ 7142 } 7143 /* LDV_COMMENT_END_PREP */ 7144 7145 /** STRUCT: struct type: tty_port_operations, struct name: port_ops **/ 7146 /* content: static int carrier_raised(struct tty_port *port)*/ 7147 /* LDV_COMMENT_BEGIN_PREP */ 7148 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 7149 #if defined(__i386__) 7150 # define BREAKPOINT() asm(" int $3"); 7151 #else 7152 # define BREAKPOINT() { } 7153 #endif 7154 #define MAX_DEVICES 12 7155 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 7156 #define SYNCLINK_GENERIC_HDLC 1 7157 #else 7158 #define SYNCLINK_GENERIC_HDLC 0 7159 #endif 7160 #define GET_USER(error,value,addr) error = get_user(value,addr) 7161 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 7162 #define PUT_USER(error,value,addr) error = put_user(value,addr) 7163 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 7164 #define SCABUFSIZE 1024 7165 #define SCA_MEM_SIZE 0x40000 7166 #define SCA_BASE_SIZE 512 7167 #define SCA_REG_SIZE 16 7168 #define SCA_MAX_PORTS 4 7169 #define SCAMAXDESC 128 7170 #define BUFFERLISTSIZE 4096 7171 #define BH_RECEIVE 1 7172 #define BH_TRANSMIT 2 7173 #define BH_STATUS 4 7174 #define IO_PIN_SHUTDOWN_LIMIT 100 7175 #if SYNCLINK_GENERIC_HDLC 7176 #endif 7177 #define MGSL_MAGIC 0x5401 7178 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 7179 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 7180 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 7181 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 7182 #define LPR 0x00 7183 #define PABR0 0x02 7184 #define PABR1 0x03 7185 #define WCRL 0x04 7186 #define WCRM 0x05 7187 #define WCRH 0x06 7188 #define DPCR 0x08 7189 #define DMER 0x09 7190 #define ISR0 0x10 7191 #define ISR1 0x11 7192 #define ISR2 0x12 7193 #define IER0 0x14 7194 #define IER1 0x15 7195 #define IER2 0x16 7196 #define ITCR 0x18 7197 #define INTVR 0x1a 7198 #define IMVR 0x1c 7199 #define TRB 0x20 7200 #define TRBL 0x20 7201 #define TRBH 0x21 7202 #define SR0 0x22 7203 #define SR1 0x23 7204 #define SR2 0x24 7205 #define SR3 0x25 7206 #define FST 0x26 7207 #define IE0 0x28 7208 #define IE1 0x29 7209 #define IE2 0x2a 7210 #define FIE 0x2b 7211 #define CMD 0x2c 7212 #define MD0 0x2e 7213 #define MD1 0x2f 7214 #define MD2 0x30 7215 #define CTL 0x31 7216 #define SA0 0x32 7217 #define SA1 0x33 7218 #define IDL 0x34 7219 #define TMC 0x35 7220 #define RXS 0x36 7221 #define TXS 0x37 7222 #define TRC0 0x38 7223 #define TRC1 0x39 7224 #define RRC 0x3a 7225 #define CST0 0x3c 7226 #define CST1 0x3d 7227 #define TCNT 0x60 7228 #define TCNTL 0x60 7229 #define TCNTH 0x61 7230 #define TCONR 0x62 7231 #define TCONRL 0x62 7232 #define TCONRH 0x63 7233 #define TMCS 0x64 7234 #define TEPR 0x65 7235 #define DARL 0x80 7236 #define DARH 0x81 7237 #define DARB 0x82 7238 #define BAR 0x80 7239 #define BARL 0x80 7240 #define BARH 0x81 7241 #define BARB 0x82 7242 #define SAR 0x84 7243 #define SARL 0x84 7244 #define SARH 0x85 7245 #define SARB 0x86 7246 #define CPB 0x86 7247 #define CDA 0x88 7248 #define CDAL 0x88 7249 #define CDAH 0x89 7250 #define EDA 0x8a 7251 #define EDAL 0x8a 7252 #define EDAH 0x8b 7253 #define BFL 0x8c 7254 #define BFLL 0x8c 7255 #define BFLH 0x8d 7256 #define BCR 0x8e 7257 #define BCRL 0x8e 7258 #define BCRH 0x8f 7259 #define DSR 0x90 7260 #define DMR 0x91 7261 #define FCT 0x93 7262 #define DIR 0x94 7263 #define DCMD 0x95 7264 #define TIMER0 0x00 7265 #define TIMER1 0x08 7266 #define TIMER2 0x10 7267 #define TIMER3 0x18 7268 #define RXDMA 0x00 7269 #define TXDMA 0x20 7270 #define NOOP 0x00 7271 #define TXRESET 0x01 7272 #define TXENABLE 0x02 7273 #define TXDISABLE 0x03 7274 #define TXCRCINIT 0x04 7275 #define TXCRCEXCL 0x05 7276 #define TXEOM 0x06 7277 #define TXABORT 0x07 7278 #define MPON 0x08 7279 #define TXBUFCLR 0x09 7280 #define RXRESET 0x11 7281 #define RXENABLE 0x12 7282 #define RXDISABLE 0x13 7283 #define RXCRCINIT 0x14 7284 #define RXREJECT 0x15 7285 #define SEARCHMP 0x16 7286 #define RXCRCEXCL 0x17 7287 #define RXCRCCALC 0x18 7288 #define CHRESET 0x21 7289 #define HUNT 0x31 7290 #define SWABORT 0x01 7291 #define FEICLEAR 0x02 7292 #define TXINTE BIT7 7293 #define RXINTE BIT6 7294 #define TXRDYE BIT1 7295 #define RXRDYE BIT0 7296 #define UDRN BIT7 7297 #define IDLE BIT6 7298 #define SYNCD BIT4 7299 #define FLGD BIT4 7300 #define CCTS BIT3 7301 #define CDCD BIT2 7302 #define BRKD BIT1 7303 #define ABTD BIT1 7304 #define GAPD BIT1 7305 #define BRKE BIT0 7306 #define IDLD BIT0 7307 #define EOM BIT7 7308 #define PMP BIT6 7309 #define SHRT BIT6 7310 #define PE BIT5 7311 #define ABT BIT5 7312 #define FRME BIT4 7313 #define RBIT BIT4 7314 #define OVRN BIT3 7315 #define CRCE BIT2 7316 #define WAKEUP_CHARS 256 7317 #if SYNCLINK_GENERIC_HDLC 7318 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7319 #endif 7320 #ifdef SANITY_CHECK 7321 #else 7322 #endif 7323 #if SYNCLINK_GENERIC_HDLC 7324 #endif 7325 #if SYNCLINK_GENERIC_HDLC 7326 #endif 7327 #if SYNCLINK_GENERIC_HDLC 7328 #endif 7329 #ifdef CMSPAR 7330 #endif 7331 /* LDV_COMMENT_END_PREP */ 7332 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "carrier_raised" */ 7333 struct tty_port * var_group6; 7334 /* LDV_COMMENT_BEGIN_PREP */ 7335 #if SYNCLINK_GENERIC_HDLC 7336 #endif 7337 #if SYNCLINK_GENERIC_HDLC 7338 #endif 7339 #if 0 7340 #endif 7341 #if SYNCLINK_GENERIC_HDLC 7342 #endif 7343 #if SYNCLINK_GENERIC_HDLC 7344 #endif 7345 #define TESTFRAMESIZE 20 7346 #if SYNCLINK_GENERIC_HDLC 7347 #endif 7348 #define CALC_REGADDR() \ 7349 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7350 if (info->port_num > 1) \ 7351 RegAddr += 256; \ 7352 if ( info->port_num & 1) { \ 7353 if (Addr > 0x7f) \ 7354 RegAddr += 0x40; \ 7355 else if (Addr > 0x1f && Addr < 0x60) \ 7356 RegAddr += 0x20; \ 7357 } 7358 /* LDV_COMMENT_END_PREP */ 7359 /* content: static void dtr_rts(struct tty_port *port, int on)*/ 7360 /* LDV_COMMENT_BEGIN_PREP */ 7361 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 7362 #if defined(__i386__) 7363 # define BREAKPOINT() asm(" int $3"); 7364 #else 7365 # define BREAKPOINT() { } 7366 #endif 7367 #define MAX_DEVICES 12 7368 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 7369 #define SYNCLINK_GENERIC_HDLC 1 7370 #else 7371 #define SYNCLINK_GENERIC_HDLC 0 7372 #endif 7373 #define GET_USER(error,value,addr) error = get_user(value,addr) 7374 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 7375 #define PUT_USER(error,value,addr) error = put_user(value,addr) 7376 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 7377 #define SCABUFSIZE 1024 7378 #define SCA_MEM_SIZE 0x40000 7379 #define SCA_BASE_SIZE 512 7380 #define SCA_REG_SIZE 16 7381 #define SCA_MAX_PORTS 4 7382 #define SCAMAXDESC 128 7383 #define BUFFERLISTSIZE 4096 7384 #define BH_RECEIVE 1 7385 #define BH_TRANSMIT 2 7386 #define BH_STATUS 4 7387 #define IO_PIN_SHUTDOWN_LIMIT 100 7388 #if SYNCLINK_GENERIC_HDLC 7389 #endif 7390 #define MGSL_MAGIC 0x5401 7391 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 7392 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 7393 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 7394 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 7395 #define LPR 0x00 7396 #define PABR0 0x02 7397 #define PABR1 0x03 7398 #define WCRL 0x04 7399 #define WCRM 0x05 7400 #define WCRH 0x06 7401 #define DPCR 0x08 7402 #define DMER 0x09 7403 #define ISR0 0x10 7404 #define ISR1 0x11 7405 #define ISR2 0x12 7406 #define IER0 0x14 7407 #define IER1 0x15 7408 #define IER2 0x16 7409 #define ITCR 0x18 7410 #define INTVR 0x1a 7411 #define IMVR 0x1c 7412 #define TRB 0x20 7413 #define TRBL 0x20 7414 #define TRBH 0x21 7415 #define SR0 0x22 7416 #define SR1 0x23 7417 #define SR2 0x24 7418 #define SR3 0x25 7419 #define FST 0x26 7420 #define IE0 0x28 7421 #define IE1 0x29 7422 #define IE2 0x2a 7423 #define FIE 0x2b 7424 #define CMD 0x2c 7425 #define MD0 0x2e 7426 #define MD1 0x2f 7427 #define MD2 0x30 7428 #define CTL 0x31 7429 #define SA0 0x32 7430 #define SA1 0x33 7431 #define IDL 0x34 7432 #define TMC 0x35 7433 #define RXS 0x36 7434 #define TXS 0x37 7435 #define TRC0 0x38 7436 #define TRC1 0x39 7437 #define RRC 0x3a 7438 #define CST0 0x3c 7439 #define CST1 0x3d 7440 #define TCNT 0x60 7441 #define TCNTL 0x60 7442 #define TCNTH 0x61 7443 #define TCONR 0x62 7444 #define TCONRL 0x62 7445 #define TCONRH 0x63 7446 #define TMCS 0x64 7447 #define TEPR 0x65 7448 #define DARL 0x80 7449 #define DARH 0x81 7450 #define DARB 0x82 7451 #define BAR 0x80 7452 #define BARL 0x80 7453 #define BARH 0x81 7454 #define BARB 0x82 7455 #define SAR 0x84 7456 #define SARL 0x84 7457 #define SARH 0x85 7458 #define SARB 0x86 7459 #define CPB 0x86 7460 #define CDA 0x88 7461 #define CDAL 0x88 7462 #define CDAH 0x89 7463 #define EDA 0x8a 7464 #define EDAL 0x8a 7465 #define EDAH 0x8b 7466 #define BFL 0x8c 7467 #define BFLL 0x8c 7468 #define BFLH 0x8d 7469 #define BCR 0x8e 7470 #define BCRL 0x8e 7471 #define BCRH 0x8f 7472 #define DSR 0x90 7473 #define DMR 0x91 7474 #define FCT 0x93 7475 #define DIR 0x94 7476 #define DCMD 0x95 7477 #define TIMER0 0x00 7478 #define TIMER1 0x08 7479 #define TIMER2 0x10 7480 #define TIMER3 0x18 7481 #define RXDMA 0x00 7482 #define TXDMA 0x20 7483 #define NOOP 0x00 7484 #define TXRESET 0x01 7485 #define TXENABLE 0x02 7486 #define TXDISABLE 0x03 7487 #define TXCRCINIT 0x04 7488 #define TXCRCEXCL 0x05 7489 #define TXEOM 0x06 7490 #define TXABORT 0x07 7491 #define MPON 0x08 7492 #define TXBUFCLR 0x09 7493 #define RXRESET 0x11 7494 #define RXENABLE 0x12 7495 #define RXDISABLE 0x13 7496 #define RXCRCINIT 0x14 7497 #define RXREJECT 0x15 7498 #define SEARCHMP 0x16 7499 #define RXCRCEXCL 0x17 7500 #define RXCRCCALC 0x18 7501 #define CHRESET 0x21 7502 #define HUNT 0x31 7503 #define SWABORT 0x01 7504 #define FEICLEAR 0x02 7505 #define TXINTE BIT7 7506 #define RXINTE BIT6 7507 #define TXRDYE BIT1 7508 #define RXRDYE BIT0 7509 #define UDRN BIT7 7510 #define IDLE BIT6 7511 #define SYNCD BIT4 7512 #define FLGD BIT4 7513 #define CCTS BIT3 7514 #define CDCD BIT2 7515 #define BRKD BIT1 7516 #define ABTD BIT1 7517 #define GAPD BIT1 7518 #define BRKE BIT0 7519 #define IDLD BIT0 7520 #define EOM BIT7 7521 #define PMP BIT6 7522 #define SHRT BIT6 7523 #define PE BIT5 7524 #define ABT BIT5 7525 #define FRME BIT4 7526 #define RBIT BIT4 7527 #define OVRN BIT3 7528 #define CRCE BIT2 7529 #define WAKEUP_CHARS 256 7530 #if SYNCLINK_GENERIC_HDLC 7531 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7532 #endif 7533 #ifdef SANITY_CHECK 7534 #else 7535 #endif 7536 #if SYNCLINK_GENERIC_HDLC 7537 #endif 7538 #if SYNCLINK_GENERIC_HDLC 7539 #endif 7540 #if SYNCLINK_GENERIC_HDLC 7541 #endif 7542 #ifdef CMSPAR 7543 #endif 7544 /* LDV_COMMENT_END_PREP */ 7545 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "dtr_rts" */ 7546 int var_dtr_rts_70_p1; 7547 /* LDV_COMMENT_BEGIN_PREP */ 7548 #if SYNCLINK_GENERIC_HDLC 7549 #endif 7550 #if SYNCLINK_GENERIC_HDLC 7551 #endif 7552 #if 0 7553 #endif 7554 #if SYNCLINK_GENERIC_HDLC 7555 #endif 7556 #if SYNCLINK_GENERIC_HDLC 7557 #endif 7558 #define TESTFRAMESIZE 20 7559 #if SYNCLINK_GENERIC_HDLC 7560 #endif 7561 #define CALC_REGADDR() \ 7562 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7563 if (info->port_num > 1) \ 7564 RegAddr += 256; \ 7565 if ( info->port_num & 1) { \ 7566 if (Addr > 0x7f) \ 7567 RegAddr += 0x40; \ 7568 else if (Addr > 0x1f && Addr < 0x60) \ 7569 RegAddr += 0x20; \ 7570 } 7571 /* LDV_COMMENT_END_PREP */ 7572 7573 /** STRUCT: struct type: tty_operations, struct name: ops **/ 7574 /* content: static int install(struct tty_driver *driver, struct tty_struct *tty)*/ 7575 /* LDV_COMMENT_BEGIN_PREP */ 7576 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 7577 #if defined(__i386__) 7578 # define BREAKPOINT() asm(" int $3"); 7579 #else 7580 # define BREAKPOINT() { } 7581 #endif 7582 #define MAX_DEVICES 12 7583 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 7584 #define SYNCLINK_GENERIC_HDLC 1 7585 #else 7586 #define SYNCLINK_GENERIC_HDLC 0 7587 #endif 7588 #define GET_USER(error,value,addr) error = get_user(value,addr) 7589 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 7590 #define PUT_USER(error,value,addr) error = put_user(value,addr) 7591 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 7592 #define SCABUFSIZE 1024 7593 #define SCA_MEM_SIZE 0x40000 7594 #define SCA_BASE_SIZE 512 7595 #define SCA_REG_SIZE 16 7596 #define SCA_MAX_PORTS 4 7597 #define SCAMAXDESC 128 7598 #define BUFFERLISTSIZE 4096 7599 #define BH_RECEIVE 1 7600 #define BH_TRANSMIT 2 7601 #define BH_STATUS 4 7602 #define IO_PIN_SHUTDOWN_LIMIT 100 7603 #if SYNCLINK_GENERIC_HDLC 7604 #endif 7605 #define MGSL_MAGIC 0x5401 7606 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 7607 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 7608 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 7609 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 7610 #define LPR 0x00 7611 #define PABR0 0x02 7612 #define PABR1 0x03 7613 #define WCRL 0x04 7614 #define WCRM 0x05 7615 #define WCRH 0x06 7616 #define DPCR 0x08 7617 #define DMER 0x09 7618 #define ISR0 0x10 7619 #define ISR1 0x11 7620 #define ISR2 0x12 7621 #define IER0 0x14 7622 #define IER1 0x15 7623 #define IER2 0x16 7624 #define ITCR 0x18 7625 #define INTVR 0x1a 7626 #define IMVR 0x1c 7627 #define TRB 0x20 7628 #define TRBL 0x20 7629 #define TRBH 0x21 7630 #define SR0 0x22 7631 #define SR1 0x23 7632 #define SR2 0x24 7633 #define SR3 0x25 7634 #define FST 0x26 7635 #define IE0 0x28 7636 #define IE1 0x29 7637 #define IE2 0x2a 7638 #define FIE 0x2b 7639 #define CMD 0x2c 7640 #define MD0 0x2e 7641 #define MD1 0x2f 7642 #define MD2 0x30 7643 #define CTL 0x31 7644 #define SA0 0x32 7645 #define SA1 0x33 7646 #define IDL 0x34 7647 #define TMC 0x35 7648 #define RXS 0x36 7649 #define TXS 0x37 7650 #define TRC0 0x38 7651 #define TRC1 0x39 7652 #define RRC 0x3a 7653 #define CST0 0x3c 7654 #define CST1 0x3d 7655 #define TCNT 0x60 7656 #define TCNTL 0x60 7657 #define TCNTH 0x61 7658 #define TCONR 0x62 7659 #define TCONRL 0x62 7660 #define TCONRH 0x63 7661 #define TMCS 0x64 7662 #define TEPR 0x65 7663 #define DARL 0x80 7664 #define DARH 0x81 7665 #define DARB 0x82 7666 #define BAR 0x80 7667 #define BARL 0x80 7668 #define BARH 0x81 7669 #define BARB 0x82 7670 #define SAR 0x84 7671 #define SARL 0x84 7672 #define SARH 0x85 7673 #define SARB 0x86 7674 #define CPB 0x86 7675 #define CDA 0x88 7676 #define CDAL 0x88 7677 #define CDAH 0x89 7678 #define EDA 0x8a 7679 #define EDAL 0x8a 7680 #define EDAH 0x8b 7681 #define BFL 0x8c 7682 #define BFLL 0x8c 7683 #define BFLH 0x8d 7684 #define BCR 0x8e 7685 #define BCRL 0x8e 7686 #define BCRH 0x8f 7687 #define DSR 0x90 7688 #define DMR 0x91 7689 #define FCT 0x93 7690 #define DIR 0x94 7691 #define DCMD 0x95 7692 #define TIMER0 0x00 7693 #define TIMER1 0x08 7694 #define TIMER2 0x10 7695 #define TIMER3 0x18 7696 #define RXDMA 0x00 7697 #define TXDMA 0x20 7698 #define NOOP 0x00 7699 #define TXRESET 0x01 7700 #define TXENABLE 0x02 7701 #define TXDISABLE 0x03 7702 #define TXCRCINIT 0x04 7703 #define TXCRCEXCL 0x05 7704 #define TXEOM 0x06 7705 #define TXABORT 0x07 7706 #define MPON 0x08 7707 #define TXBUFCLR 0x09 7708 #define RXRESET 0x11 7709 #define RXENABLE 0x12 7710 #define RXDISABLE 0x13 7711 #define RXCRCINIT 0x14 7712 #define RXREJECT 0x15 7713 #define SEARCHMP 0x16 7714 #define RXCRCEXCL 0x17 7715 #define RXCRCCALC 0x18 7716 #define CHRESET 0x21 7717 #define HUNT 0x31 7718 #define SWABORT 0x01 7719 #define FEICLEAR 0x02 7720 #define TXINTE BIT7 7721 #define RXINTE BIT6 7722 #define TXRDYE BIT1 7723 #define RXRDYE BIT0 7724 #define UDRN BIT7 7725 #define IDLE BIT6 7726 #define SYNCD BIT4 7727 #define FLGD BIT4 7728 #define CCTS BIT3 7729 #define CDCD BIT2 7730 #define BRKD BIT1 7731 #define ABTD BIT1 7732 #define GAPD BIT1 7733 #define BRKE BIT0 7734 #define IDLD BIT0 7735 #define EOM BIT7 7736 #define PMP BIT6 7737 #define SHRT BIT6 7738 #define PE BIT5 7739 #define ABT BIT5 7740 #define FRME BIT4 7741 #define RBIT BIT4 7742 #define OVRN BIT3 7743 #define CRCE BIT2 7744 #define WAKEUP_CHARS 256 7745 #if SYNCLINK_GENERIC_HDLC 7746 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7747 #endif 7748 #ifdef SANITY_CHECK 7749 #else 7750 #endif 7751 /* LDV_COMMENT_END_PREP */ 7752 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "install" */ 7753 struct tty_driver * var_group7; 7754 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "install" */ 7755 struct tty_struct * var_group8; 7756 /* LDV_COMMENT_BEGIN_PREP */ 7757 #if SYNCLINK_GENERIC_HDLC 7758 #endif 7759 #if SYNCLINK_GENERIC_HDLC 7760 #endif 7761 #if SYNCLINK_GENERIC_HDLC 7762 #endif 7763 #ifdef CMSPAR 7764 #endif 7765 #if SYNCLINK_GENERIC_HDLC 7766 #endif 7767 #if SYNCLINK_GENERIC_HDLC 7768 #endif 7769 #if 0 7770 #endif 7771 #if SYNCLINK_GENERIC_HDLC 7772 #endif 7773 #if SYNCLINK_GENERIC_HDLC 7774 #endif 7775 #define TESTFRAMESIZE 20 7776 #if SYNCLINK_GENERIC_HDLC 7777 #endif 7778 #define CALC_REGADDR() \ 7779 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7780 if (info->port_num > 1) \ 7781 RegAddr += 256; \ 7782 if ( info->port_num & 1) { \ 7783 if (Addr > 0x7f) \ 7784 RegAddr += 0x40; \ 7785 else if (Addr > 0x1f && Addr < 0x60) \ 7786 RegAddr += 0x20; \ 7787 } 7788 /* LDV_COMMENT_END_PREP */ 7789 /* content: static int open(struct tty_struct *tty, struct file *filp)*/ 7790 /* LDV_COMMENT_BEGIN_PREP */ 7791 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 7792 #if defined(__i386__) 7793 # define BREAKPOINT() asm(" int $3"); 7794 #else 7795 # define BREAKPOINT() { } 7796 #endif 7797 #define MAX_DEVICES 12 7798 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 7799 #define SYNCLINK_GENERIC_HDLC 1 7800 #else 7801 #define SYNCLINK_GENERIC_HDLC 0 7802 #endif 7803 #define GET_USER(error,value,addr) error = get_user(value,addr) 7804 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 7805 #define PUT_USER(error,value,addr) error = put_user(value,addr) 7806 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 7807 #define SCABUFSIZE 1024 7808 #define SCA_MEM_SIZE 0x40000 7809 #define SCA_BASE_SIZE 512 7810 #define SCA_REG_SIZE 16 7811 #define SCA_MAX_PORTS 4 7812 #define SCAMAXDESC 128 7813 #define BUFFERLISTSIZE 4096 7814 #define BH_RECEIVE 1 7815 #define BH_TRANSMIT 2 7816 #define BH_STATUS 4 7817 #define IO_PIN_SHUTDOWN_LIMIT 100 7818 #if SYNCLINK_GENERIC_HDLC 7819 #endif 7820 #define MGSL_MAGIC 0x5401 7821 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 7822 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 7823 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 7824 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 7825 #define LPR 0x00 7826 #define PABR0 0x02 7827 #define PABR1 0x03 7828 #define WCRL 0x04 7829 #define WCRM 0x05 7830 #define WCRH 0x06 7831 #define DPCR 0x08 7832 #define DMER 0x09 7833 #define ISR0 0x10 7834 #define ISR1 0x11 7835 #define ISR2 0x12 7836 #define IER0 0x14 7837 #define IER1 0x15 7838 #define IER2 0x16 7839 #define ITCR 0x18 7840 #define INTVR 0x1a 7841 #define IMVR 0x1c 7842 #define TRB 0x20 7843 #define TRBL 0x20 7844 #define TRBH 0x21 7845 #define SR0 0x22 7846 #define SR1 0x23 7847 #define SR2 0x24 7848 #define SR3 0x25 7849 #define FST 0x26 7850 #define IE0 0x28 7851 #define IE1 0x29 7852 #define IE2 0x2a 7853 #define FIE 0x2b 7854 #define CMD 0x2c 7855 #define MD0 0x2e 7856 #define MD1 0x2f 7857 #define MD2 0x30 7858 #define CTL 0x31 7859 #define SA0 0x32 7860 #define SA1 0x33 7861 #define IDL 0x34 7862 #define TMC 0x35 7863 #define RXS 0x36 7864 #define TXS 0x37 7865 #define TRC0 0x38 7866 #define TRC1 0x39 7867 #define RRC 0x3a 7868 #define CST0 0x3c 7869 #define CST1 0x3d 7870 #define TCNT 0x60 7871 #define TCNTL 0x60 7872 #define TCNTH 0x61 7873 #define TCONR 0x62 7874 #define TCONRL 0x62 7875 #define TCONRH 0x63 7876 #define TMCS 0x64 7877 #define TEPR 0x65 7878 #define DARL 0x80 7879 #define DARH 0x81 7880 #define DARB 0x82 7881 #define BAR 0x80 7882 #define BARL 0x80 7883 #define BARH 0x81 7884 #define BARB 0x82 7885 #define SAR 0x84 7886 #define SARL 0x84 7887 #define SARH 0x85 7888 #define SARB 0x86 7889 #define CPB 0x86 7890 #define CDA 0x88 7891 #define CDAL 0x88 7892 #define CDAH 0x89 7893 #define EDA 0x8a 7894 #define EDAL 0x8a 7895 #define EDAH 0x8b 7896 #define BFL 0x8c 7897 #define BFLL 0x8c 7898 #define BFLH 0x8d 7899 #define BCR 0x8e 7900 #define BCRL 0x8e 7901 #define BCRH 0x8f 7902 #define DSR 0x90 7903 #define DMR 0x91 7904 #define FCT 0x93 7905 #define DIR 0x94 7906 #define DCMD 0x95 7907 #define TIMER0 0x00 7908 #define TIMER1 0x08 7909 #define TIMER2 0x10 7910 #define TIMER3 0x18 7911 #define RXDMA 0x00 7912 #define TXDMA 0x20 7913 #define NOOP 0x00 7914 #define TXRESET 0x01 7915 #define TXENABLE 0x02 7916 #define TXDISABLE 0x03 7917 #define TXCRCINIT 0x04 7918 #define TXCRCEXCL 0x05 7919 #define TXEOM 0x06 7920 #define TXABORT 0x07 7921 #define MPON 0x08 7922 #define TXBUFCLR 0x09 7923 #define RXRESET 0x11 7924 #define RXENABLE 0x12 7925 #define RXDISABLE 0x13 7926 #define RXCRCINIT 0x14 7927 #define RXREJECT 0x15 7928 #define SEARCHMP 0x16 7929 #define RXCRCEXCL 0x17 7930 #define RXCRCCALC 0x18 7931 #define CHRESET 0x21 7932 #define HUNT 0x31 7933 #define SWABORT 0x01 7934 #define FEICLEAR 0x02 7935 #define TXINTE BIT7 7936 #define RXINTE BIT6 7937 #define TXRDYE BIT1 7938 #define RXRDYE BIT0 7939 #define UDRN BIT7 7940 #define IDLE BIT6 7941 #define SYNCD BIT4 7942 #define FLGD BIT4 7943 #define CCTS BIT3 7944 #define CDCD BIT2 7945 #define BRKD BIT1 7946 #define ABTD BIT1 7947 #define GAPD BIT1 7948 #define BRKE BIT0 7949 #define IDLD BIT0 7950 #define EOM BIT7 7951 #define PMP BIT6 7952 #define SHRT BIT6 7953 #define PE BIT5 7954 #define ABT BIT5 7955 #define FRME BIT4 7956 #define RBIT BIT4 7957 #define OVRN BIT3 7958 #define CRCE BIT2 7959 #define WAKEUP_CHARS 256 7960 #if SYNCLINK_GENERIC_HDLC 7961 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7962 #endif 7963 #ifdef SANITY_CHECK 7964 #else 7965 #endif 7966 /* LDV_COMMENT_END_PREP */ 7967 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "open" */ 7968 static int res_open_4; 7969 /* LDV_COMMENT_BEGIN_PREP */ 7970 #if SYNCLINK_GENERIC_HDLC 7971 #endif 7972 #if SYNCLINK_GENERIC_HDLC 7973 #endif 7974 #if SYNCLINK_GENERIC_HDLC 7975 #endif 7976 #ifdef CMSPAR 7977 #endif 7978 #if SYNCLINK_GENERIC_HDLC 7979 #endif 7980 #if SYNCLINK_GENERIC_HDLC 7981 #endif 7982 #if 0 7983 #endif 7984 #if SYNCLINK_GENERIC_HDLC 7985 #endif 7986 #if SYNCLINK_GENERIC_HDLC 7987 #endif 7988 #define TESTFRAMESIZE 20 7989 #if SYNCLINK_GENERIC_HDLC 7990 #endif 7991 #define CALC_REGADDR() \ 7992 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7993 if (info->port_num > 1) \ 7994 RegAddr += 256; \ 7995 if ( info->port_num & 1) { \ 7996 if (Addr > 0x7f) \ 7997 RegAddr += 0x40; \ 7998 else if (Addr > 0x1f && Addr < 0x60) \ 7999 RegAddr += 0x20; \ 8000 } 8001 /* LDV_COMMENT_END_PREP */ 8002 /* content: static void close(struct tty_struct *tty, struct file *filp)*/ 8003 /* LDV_COMMENT_BEGIN_PREP */ 8004 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8005 #if defined(__i386__) 8006 # define BREAKPOINT() asm(" int $3"); 8007 #else 8008 # define BREAKPOINT() { } 8009 #endif 8010 #define MAX_DEVICES 12 8011 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8012 #define SYNCLINK_GENERIC_HDLC 1 8013 #else 8014 #define SYNCLINK_GENERIC_HDLC 0 8015 #endif 8016 #define GET_USER(error,value,addr) error = get_user(value,addr) 8017 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8018 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8019 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8020 #define SCABUFSIZE 1024 8021 #define SCA_MEM_SIZE 0x40000 8022 #define SCA_BASE_SIZE 512 8023 #define SCA_REG_SIZE 16 8024 #define SCA_MAX_PORTS 4 8025 #define SCAMAXDESC 128 8026 #define BUFFERLISTSIZE 4096 8027 #define BH_RECEIVE 1 8028 #define BH_TRANSMIT 2 8029 #define BH_STATUS 4 8030 #define IO_PIN_SHUTDOWN_LIMIT 100 8031 #if SYNCLINK_GENERIC_HDLC 8032 #endif 8033 #define MGSL_MAGIC 0x5401 8034 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8035 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8036 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8037 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8038 #define LPR 0x00 8039 #define PABR0 0x02 8040 #define PABR1 0x03 8041 #define WCRL 0x04 8042 #define WCRM 0x05 8043 #define WCRH 0x06 8044 #define DPCR 0x08 8045 #define DMER 0x09 8046 #define ISR0 0x10 8047 #define ISR1 0x11 8048 #define ISR2 0x12 8049 #define IER0 0x14 8050 #define IER1 0x15 8051 #define IER2 0x16 8052 #define ITCR 0x18 8053 #define INTVR 0x1a 8054 #define IMVR 0x1c 8055 #define TRB 0x20 8056 #define TRBL 0x20 8057 #define TRBH 0x21 8058 #define SR0 0x22 8059 #define SR1 0x23 8060 #define SR2 0x24 8061 #define SR3 0x25 8062 #define FST 0x26 8063 #define IE0 0x28 8064 #define IE1 0x29 8065 #define IE2 0x2a 8066 #define FIE 0x2b 8067 #define CMD 0x2c 8068 #define MD0 0x2e 8069 #define MD1 0x2f 8070 #define MD2 0x30 8071 #define CTL 0x31 8072 #define SA0 0x32 8073 #define SA1 0x33 8074 #define IDL 0x34 8075 #define TMC 0x35 8076 #define RXS 0x36 8077 #define TXS 0x37 8078 #define TRC0 0x38 8079 #define TRC1 0x39 8080 #define RRC 0x3a 8081 #define CST0 0x3c 8082 #define CST1 0x3d 8083 #define TCNT 0x60 8084 #define TCNTL 0x60 8085 #define TCNTH 0x61 8086 #define TCONR 0x62 8087 #define TCONRL 0x62 8088 #define TCONRH 0x63 8089 #define TMCS 0x64 8090 #define TEPR 0x65 8091 #define DARL 0x80 8092 #define DARH 0x81 8093 #define DARB 0x82 8094 #define BAR 0x80 8095 #define BARL 0x80 8096 #define BARH 0x81 8097 #define BARB 0x82 8098 #define SAR 0x84 8099 #define SARL 0x84 8100 #define SARH 0x85 8101 #define SARB 0x86 8102 #define CPB 0x86 8103 #define CDA 0x88 8104 #define CDAL 0x88 8105 #define CDAH 0x89 8106 #define EDA 0x8a 8107 #define EDAL 0x8a 8108 #define EDAH 0x8b 8109 #define BFL 0x8c 8110 #define BFLL 0x8c 8111 #define BFLH 0x8d 8112 #define BCR 0x8e 8113 #define BCRL 0x8e 8114 #define BCRH 0x8f 8115 #define DSR 0x90 8116 #define DMR 0x91 8117 #define FCT 0x93 8118 #define DIR 0x94 8119 #define DCMD 0x95 8120 #define TIMER0 0x00 8121 #define TIMER1 0x08 8122 #define TIMER2 0x10 8123 #define TIMER3 0x18 8124 #define RXDMA 0x00 8125 #define TXDMA 0x20 8126 #define NOOP 0x00 8127 #define TXRESET 0x01 8128 #define TXENABLE 0x02 8129 #define TXDISABLE 0x03 8130 #define TXCRCINIT 0x04 8131 #define TXCRCEXCL 0x05 8132 #define TXEOM 0x06 8133 #define TXABORT 0x07 8134 #define MPON 0x08 8135 #define TXBUFCLR 0x09 8136 #define RXRESET 0x11 8137 #define RXENABLE 0x12 8138 #define RXDISABLE 0x13 8139 #define RXCRCINIT 0x14 8140 #define RXREJECT 0x15 8141 #define SEARCHMP 0x16 8142 #define RXCRCEXCL 0x17 8143 #define RXCRCCALC 0x18 8144 #define CHRESET 0x21 8145 #define HUNT 0x31 8146 #define SWABORT 0x01 8147 #define FEICLEAR 0x02 8148 #define TXINTE BIT7 8149 #define RXINTE BIT6 8150 #define TXRDYE BIT1 8151 #define RXRDYE BIT0 8152 #define UDRN BIT7 8153 #define IDLE BIT6 8154 #define SYNCD BIT4 8155 #define FLGD BIT4 8156 #define CCTS BIT3 8157 #define CDCD BIT2 8158 #define BRKD BIT1 8159 #define ABTD BIT1 8160 #define GAPD BIT1 8161 #define BRKE BIT0 8162 #define IDLD BIT0 8163 #define EOM BIT7 8164 #define PMP BIT6 8165 #define SHRT BIT6 8166 #define PE BIT5 8167 #define ABT BIT5 8168 #define FRME BIT4 8169 #define RBIT BIT4 8170 #define OVRN BIT3 8171 #define CRCE BIT2 8172 #define WAKEUP_CHARS 256 8173 #if SYNCLINK_GENERIC_HDLC 8174 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 8175 #endif 8176 #ifdef SANITY_CHECK 8177 #else 8178 #endif 8179 /* LDV_COMMENT_END_PREP */ 8180 /* LDV_COMMENT_BEGIN_PREP */ 8181 #if SYNCLINK_GENERIC_HDLC 8182 #endif 8183 #if SYNCLINK_GENERIC_HDLC 8184 #endif 8185 #if SYNCLINK_GENERIC_HDLC 8186 #endif 8187 #ifdef CMSPAR 8188 #endif 8189 #if SYNCLINK_GENERIC_HDLC 8190 #endif 8191 #if SYNCLINK_GENERIC_HDLC 8192 #endif 8193 #if 0 8194 #endif 8195 #if SYNCLINK_GENERIC_HDLC 8196 #endif 8197 #if SYNCLINK_GENERIC_HDLC 8198 #endif 8199 #define TESTFRAMESIZE 20 8200 #if SYNCLINK_GENERIC_HDLC 8201 #endif 8202 #define CALC_REGADDR() \ 8203 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8204 if (info->port_num > 1) \ 8205 RegAddr += 256; \ 8206 if ( info->port_num & 1) { \ 8207 if (Addr > 0x7f) \ 8208 RegAddr += 0x40; \ 8209 else if (Addr > 0x1f && Addr < 0x60) \ 8210 RegAddr += 0x20; \ 8211 } 8212 /* LDV_COMMENT_END_PREP */ 8213 /* content: static int write(struct tty_struct *tty, const unsigned char *buf, int count)*/ 8214 /* LDV_COMMENT_BEGIN_PREP */ 8215 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8216 #if defined(__i386__) 8217 # define BREAKPOINT() asm(" int $3"); 8218 #else 8219 # define BREAKPOINT() { } 8220 #endif 8221 #define MAX_DEVICES 12 8222 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8223 #define SYNCLINK_GENERIC_HDLC 1 8224 #else 8225 #define SYNCLINK_GENERIC_HDLC 0 8226 #endif 8227 #define GET_USER(error,value,addr) error = get_user(value,addr) 8228 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8229 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8230 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8231 #define SCABUFSIZE 1024 8232 #define SCA_MEM_SIZE 0x40000 8233 #define SCA_BASE_SIZE 512 8234 #define SCA_REG_SIZE 16 8235 #define SCA_MAX_PORTS 4 8236 #define SCAMAXDESC 128 8237 #define BUFFERLISTSIZE 4096 8238 #define BH_RECEIVE 1 8239 #define BH_TRANSMIT 2 8240 #define BH_STATUS 4 8241 #define IO_PIN_SHUTDOWN_LIMIT 100 8242 #if SYNCLINK_GENERIC_HDLC 8243 #endif 8244 #define MGSL_MAGIC 0x5401 8245 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8246 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8247 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8248 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8249 #define LPR 0x00 8250 #define PABR0 0x02 8251 #define PABR1 0x03 8252 #define WCRL 0x04 8253 #define WCRM 0x05 8254 #define WCRH 0x06 8255 #define DPCR 0x08 8256 #define DMER 0x09 8257 #define ISR0 0x10 8258 #define ISR1 0x11 8259 #define ISR2 0x12 8260 #define IER0 0x14 8261 #define IER1 0x15 8262 #define IER2 0x16 8263 #define ITCR 0x18 8264 #define INTVR 0x1a 8265 #define IMVR 0x1c 8266 #define TRB 0x20 8267 #define TRBL 0x20 8268 #define TRBH 0x21 8269 #define SR0 0x22 8270 #define SR1 0x23 8271 #define SR2 0x24 8272 #define SR3 0x25 8273 #define FST 0x26 8274 #define IE0 0x28 8275 #define IE1 0x29 8276 #define IE2 0x2a 8277 #define FIE 0x2b 8278 #define CMD 0x2c 8279 #define MD0 0x2e 8280 #define MD1 0x2f 8281 #define MD2 0x30 8282 #define CTL 0x31 8283 #define SA0 0x32 8284 #define SA1 0x33 8285 #define IDL 0x34 8286 #define TMC 0x35 8287 #define RXS 0x36 8288 #define TXS 0x37 8289 #define TRC0 0x38 8290 #define TRC1 0x39 8291 #define RRC 0x3a 8292 #define CST0 0x3c 8293 #define CST1 0x3d 8294 #define TCNT 0x60 8295 #define TCNTL 0x60 8296 #define TCNTH 0x61 8297 #define TCONR 0x62 8298 #define TCONRL 0x62 8299 #define TCONRH 0x63 8300 #define TMCS 0x64 8301 #define TEPR 0x65 8302 #define DARL 0x80 8303 #define DARH 0x81 8304 #define DARB 0x82 8305 #define BAR 0x80 8306 #define BARL 0x80 8307 #define BARH 0x81 8308 #define BARB 0x82 8309 #define SAR 0x84 8310 #define SARL 0x84 8311 #define SARH 0x85 8312 #define SARB 0x86 8313 #define CPB 0x86 8314 #define CDA 0x88 8315 #define CDAL 0x88 8316 #define CDAH 0x89 8317 #define EDA 0x8a 8318 #define EDAL 0x8a 8319 #define EDAH 0x8b 8320 #define BFL 0x8c 8321 #define BFLL 0x8c 8322 #define BFLH 0x8d 8323 #define BCR 0x8e 8324 #define BCRL 0x8e 8325 #define BCRH 0x8f 8326 #define DSR 0x90 8327 #define DMR 0x91 8328 #define FCT 0x93 8329 #define DIR 0x94 8330 #define DCMD 0x95 8331 #define TIMER0 0x00 8332 #define TIMER1 0x08 8333 #define TIMER2 0x10 8334 #define TIMER3 0x18 8335 #define RXDMA 0x00 8336 #define TXDMA 0x20 8337 #define NOOP 0x00 8338 #define TXRESET 0x01 8339 #define TXENABLE 0x02 8340 #define TXDISABLE 0x03 8341 #define TXCRCINIT 0x04 8342 #define TXCRCEXCL 0x05 8343 #define TXEOM 0x06 8344 #define TXABORT 0x07 8345 #define MPON 0x08 8346 #define TXBUFCLR 0x09 8347 #define RXRESET 0x11 8348 #define RXENABLE 0x12 8349 #define RXDISABLE 0x13 8350 #define RXCRCINIT 0x14 8351 #define RXREJECT 0x15 8352 #define SEARCHMP 0x16 8353 #define RXCRCEXCL 0x17 8354 #define RXCRCCALC 0x18 8355 #define CHRESET 0x21 8356 #define HUNT 0x31 8357 #define SWABORT 0x01 8358 #define FEICLEAR 0x02 8359 #define TXINTE BIT7 8360 #define RXINTE BIT6 8361 #define TXRDYE BIT1 8362 #define RXRDYE BIT0 8363 #define UDRN BIT7 8364 #define IDLE BIT6 8365 #define SYNCD BIT4 8366 #define FLGD BIT4 8367 #define CCTS BIT3 8368 #define CDCD BIT2 8369 #define BRKD BIT1 8370 #define ABTD BIT1 8371 #define GAPD BIT1 8372 #define BRKE BIT0 8373 #define IDLD BIT0 8374 #define EOM BIT7 8375 #define PMP BIT6 8376 #define SHRT BIT6 8377 #define PE BIT5 8378 #define ABT BIT5 8379 #define FRME BIT4 8380 #define RBIT BIT4 8381 #define OVRN BIT3 8382 #define CRCE BIT2 8383 #define WAKEUP_CHARS 256 8384 #if SYNCLINK_GENERIC_HDLC 8385 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 8386 #endif 8387 #ifdef SANITY_CHECK 8388 #else 8389 #endif 8390 /* LDV_COMMENT_END_PREP */ 8391 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "write" */ 8392 const unsigned char * var_write_8_p1; 8393 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "write" */ 8394 int var_write_8_p2; 8395 /* LDV_COMMENT_BEGIN_PREP */ 8396 #if SYNCLINK_GENERIC_HDLC 8397 #endif 8398 #if SYNCLINK_GENERIC_HDLC 8399 #endif 8400 #if SYNCLINK_GENERIC_HDLC 8401 #endif 8402 #ifdef CMSPAR 8403 #endif 8404 #if SYNCLINK_GENERIC_HDLC 8405 #endif 8406 #if SYNCLINK_GENERIC_HDLC 8407 #endif 8408 #if 0 8409 #endif 8410 #if SYNCLINK_GENERIC_HDLC 8411 #endif 8412 #if SYNCLINK_GENERIC_HDLC 8413 #endif 8414 #define TESTFRAMESIZE 20 8415 #if SYNCLINK_GENERIC_HDLC 8416 #endif 8417 #define CALC_REGADDR() \ 8418 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8419 if (info->port_num > 1) \ 8420 RegAddr += 256; \ 8421 if ( info->port_num & 1) { \ 8422 if (Addr > 0x7f) \ 8423 RegAddr += 0x40; \ 8424 else if (Addr > 0x1f && Addr < 0x60) \ 8425 RegAddr += 0x20; \ 8426 } 8427 /* LDV_COMMENT_END_PREP */ 8428 /* content: static int put_char(struct tty_struct *tty, unsigned char ch)*/ 8429 /* LDV_COMMENT_BEGIN_PREP */ 8430 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8431 #if defined(__i386__) 8432 # define BREAKPOINT() asm(" int $3"); 8433 #else 8434 # define BREAKPOINT() { } 8435 #endif 8436 #define MAX_DEVICES 12 8437 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8438 #define SYNCLINK_GENERIC_HDLC 1 8439 #else 8440 #define SYNCLINK_GENERIC_HDLC 0 8441 #endif 8442 #define GET_USER(error,value,addr) error = get_user(value,addr) 8443 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8444 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8445 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8446 #define SCABUFSIZE 1024 8447 #define SCA_MEM_SIZE 0x40000 8448 #define SCA_BASE_SIZE 512 8449 #define SCA_REG_SIZE 16 8450 #define SCA_MAX_PORTS 4 8451 #define SCAMAXDESC 128 8452 #define BUFFERLISTSIZE 4096 8453 #define BH_RECEIVE 1 8454 #define BH_TRANSMIT 2 8455 #define BH_STATUS 4 8456 #define IO_PIN_SHUTDOWN_LIMIT 100 8457 #if SYNCLINK_GENERIC_HDLC 8458 #endif 8459 #define MGSL_MAGIC 0x5401 8460 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8461 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8462 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8463 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8464 #define LPR 0x00 8465 #define PABR0 0x02 8466 #define PABR1 0x03 8467 #define WCRL 0x04 8468 #define WCRM 0x05 8469 #define WCRH 0x06 8470 #define DPCR 0x08 8471 #define DMER 0x09 8472 #define ISR0 0x10 8473 #define ISR1 0x11 8474 #define ISR2 0x12 8475 #define IER0 0x14 8476 #define IER1 0x15 8477 #define IER2 0x16 8478 #define ITCR 0x18 8479 #define INTVR 0x1a 8480 #define IMVR 0x1c 8481 #define TRB 0x20 8482 #define TRBL 0x20 8483 #define TRBH 0x21 8484 #define SR0 0x22 8485 #define SR1 0x23 8486 #define SR2 0x24 8487 #define SR3 0x25 8488 #define FST 0x26 8489 #define IE0 0x28 8490 #define IE1 0x29 8491 #define IE2 0x2a 8492 #define FIE 0x2b 8493 #define CMD 0x2c 8494 #define MD0 0x2e 8495 #define MD1 0x2f 8496 #define MD2 0x30 8497 #define CTL 0x31 8498 #define SA0 0x32 8499 #define SA1 0x33 8500 #define IDL 0x34 8501 #define TMC 0x35 8502 #define RXS 0x36 8503 #define TXS 0x37 8504 #define TRC0 0x38 8505 #define TRC1 0x39 8506 #define RRC 0x3a 8507 #define CST0 0x3c 8508 #define CST1 0x3d 8509 #define TCNT 0x60 8510 #define TCNTL 0x60 8511 #define TCNTH 0x61 8512 #define TCONR 0x62 8513 #define TCONRL 0x62 8514 #define TCONRH 0x63 8515 #define TMCS 0x64 8516 #define TEPR 0x65 8517 #define DARL 0x80 8518 #define DARH 0x81 8519 #define DARB 0x82 8520 #define BAR 0x80 8521 #define BARL 0x80 8522 #define BARH 0x81 8523 #define BARB 0x82 8524 #define SAR 0x84 8525 #define SARL 0x84 8526 #define SARH 0x85 8527 #define SARB 0x86 8528 #define CPB 0x86 8529 #define CDA 0x88 8530 #define CDAL 0x88 8531 #define CDAH 0x89 8532 #define EDA 0x8a 8533 #define EDAL 0x8a 8534 #define EDAH 0x8b 8535 #define BFL 0x8c 8536 #define BFLL 0x8c 8537 #define BFLH 0x8d 8538 #define BCR 0x8e 8539 #define BCRL 0x8e 8540 #define BCRH 0x8f 8541 #define DSR 0x90 8542 #define DMR 0x91 8543 #define FCT 0x93 8544 #define DIR 0x94 8545 #define DCMD 0x95 8546 #define TIMER0 0x00 8547 #define TIMER1 0x08 8548 #define TIMER2 0x10 8549 #define TIMER3 0x18 8550 #define RXDMA 0x00 8551 #define TXDMA 0x20 8552 #define NOOP 0x00 8553 #define TXRESET 0x01 8554 #define TXENABLE 0x02 8555 #define TXDISABLE 0x03 8556 #define TXCRCINIT 0x04 8557 #define TXCRCEXCL 0x05 8558 #define TXEOM 0x06 8559 #define TXABORT 0x07 8560 #define MPON 0x08 8561 #define TXBUFCLR 0x09 8562 #define RXRESET 0x11 8563 #define RXENABLE 0x12 8564 #define RXDISABLE 0x13 8565 #define RXCRCINIT 0x14 8566 #define RXREJECT 0x15 8567 #define SEARCHMP 0x16 8568 #define RXCRCEXCL 0x17 8569 #define RXCRCCALC 0x18 8570 #define CHRESET 0x21 8571 #define HUNT 0x31 8572 #define SWABORT 0x01 8573 #define FEICLEAR 0x02 8574 #define TXINTE BIT7 8575 #define RXINTE BIT6 8576 #define TXRDYE BIT1 8577 #define RXRDYE BIT0 8578 #define UDRN BIT7 8579 #define IDLE BIT6 8580 #define SYNCD BIT4 8581 #define FLGD BIT4 8582 #define CCTS BIT3 8583 #define CDCD BIT2 8584 #define BRKD BIT1 8585 #define ABTD BIT1 8586 #define GAPD BIT1 8587 #define BRKE BIT0 8588 #define IDLD BIT0 8589 #define EOM BIT7 8590 #define PMP BIT6 8591 #define SHRT BIT6 8592 #define PE BIT5 8593 #define ABT BIT5 8594 #define FRME BIT4 8595 #define RBIT BIT4 8596 #define OVRN BIT3 8597 #define CRCE BIT2 8598 #define WAKEUP_CHARS 256 8599 #if SYNCLINK_GENERIC_HDLC 8600 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 8601 #endif 8602 #ifdef SANITY_CHECK 8603 #else 8604 #endif 8605 /* LDV_COMMENT_END_PREP */ 8606 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "put_char" */ 8607 unsigned char var_put_char_9_p1; 8608 /* LDV_COMMENT_BEGIN_PREP */ 8609 #if SYNCLINK_GENERIC_HDLC 8610 #endif 8611 #if SYNCLINK_GENERIC_HDLC 8612 #endif 8613 #if SYNCLINK_GENERIC_HDLC 8614 #endif 8615 #ifdef CMSPAR 8616 #endif 8617 #if SYNCLINK_GENERIC_HDLC 8618 #endif 8619 #if SYNCLINK_GENERIC_HDLC 8620 #endif 8621 #if 0 8622 #endif 8623 #if SYNCLINK_GENERIC_HDLC 8624 #endif 8625 #if SYNCLINK_GENERIC_HDLC 8626 #endif 8627 #define TESTFRAMESIZE 20 8628 #if SYNCLINK_GENERIC_HDLC 8629 #endif 8630 #define CALC_REGADDR() \ 8631 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8632 if (info->port_num > 1) \ 8633 RegAddr += 256; \ 8634 if ( info->port_num & 1) { \ 8635 if (Addr > 0x7f) \ 8636 RegAddr += 0x40; \ 8637 else if (Addr > 0x1f && Addr < 0x60) \ 8638 RegAddr += 0x20; \ 8639 } 8640 /* LDV_COMMENT_END_PREP */ 8641 /* content: static void flush_chars(struct tty_struct *tty)*/ 8642 /* LDV_COMMENT_BEGIN_PREP */ 8643 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8644 #if defined(__i386__) 8645 # define BREAKPOINT() asm(" int $3"); 8646 #else 8647 # define BREAKPOINT() { } 8648 #endif 8649 #define MAX_DEVICES 12 8650 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8651 #define SYNCLINK_GENERIC_HDLC 1 8652 #else 8653 #define SYNCLINK_GENERIC_HDLC 0 8654 #endif 8655 #define GET_USER(error,value,addr) error = get_user(value,addr) 8656 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8657 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8658 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8659 #define SCABUFSIZE 1024 8660 #define SCA_MEM_SIZE 0x40000 8661 #define SCA_BASE_SIZE 512 8662 #define SCA_REG_SIZE 16 8663 #define SCA_MAX_PORTS 4 8664 #define SCAMAXDESC 128 8665 #define BUFFERLISTSIZE 4096 8666 #define BH_RECEIVE 1 8667 #define BH_TRANSMIT 2 8668 #define BH_STATUS 4 8669 #define IO_PIN_SHUTDOWN_LIMIT 100 8670 #if SYNCLINK_GENERIC_HDLC 8671 #endif 8672 #define MGSL_MAGIC 0x5401 8673 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8674 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8675 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8676 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8677 #define LPR 0x00 8678 #define PABR0 0x02 8679 #define PABR1 0x03 8680 #define WCRL 0x04 8681 #define WCRM 0x05 8682 #define WCRH 0x06 8683 #define DPCR 0x08 8684 #define DMER 0x09 8685 #define ISR0 0x10 8686 #define ISR1 0x11 8687 #define ISR2 0x12 8688 #define IER0 0x14 8689 #define IER1 0x15 8690 #define IER2 0x16 8691 #define ITCR 0x18 8692 #define INTVR 0x1a 8693 #define IMVR 0x1c 8694 #define TRB 0x20 8695 #define TRBL 0x20 8696 #define TRBH 0x21 8697 #define SR0 0x22 8698 #define SR1 0x23 8699 #define SR2 0x24 8700 #define SR3 0x25 8701 #define FST 0x26 8702 #define IE0 0x28 8703 #define IE1 0x29 8704 #define IE2 0x2a 8705 #define FIE 0x2b 8706 #define CMD 0x2c 8707 #define MD0 0x2e 8708 #define MD1 0x2f 8709 #define MD2 0x30 8710 #define CTL 0x31 8711 #define SA0 0x32 8712 #define SA1 0x33 8713 #define IDL 0x34 8714 #define TMC 0x35 8715 #define RXS 0x36 8716 #define TXS 0x37 8717 #define TRC0 0x38 8718 #define TRC1 0x39 8719 #define RRC 0x3a 8720 #define CST0 0x3c 8721 #define CST1 0x3d 8722 #define TCNT 0x60 8723 #define TCNTL 0x60 8724 #define TCNTH 0x61 8725 #define TCONR 0x62 8726 #define TCONRL 0x62 8727 #define TCONRH 0x63 8728 #define TMCS 0x64 8729 #define TEPR 0x65 8730 #define DARL 0x80 8731 #define DARH 0x81 8732 #define DARB 0x82 8733 #define BAR 0x80 8734 #define BARL 0x80 8735 #define BARH 0x81 8736 #define BARB 0x82 8737 #define SAR 0x84 8738 #define SARL 0x84 8739 #define SARH 0x85 8740 #define SARB 0x86 8741 #define CPB 0x86 8742 #define CDA 0x88 8743 #define CDAL 0x88 8744 #define CDAH 0x89 8745 #define EDA 0x8a 8746 #define EDAL 0x8a 8747 #define EDAH 0x8b 8748 #define BFL 0x8c 8749 #define BFLL 0x8c 8750 #define BFLH 0x8d 8751 #define BCR 0x8e 8752 #define BCRL 0x8e 8753 #define BCRH 0x8f 8754 #define DSR 0x90 8755 #define DMR 0x91 8756 #define FCT 0x93 8757 #define DIR 0x94 8758 #define DCMD 0x95 8759 #define TIMER0 0x00 8760 #define TIMER1 0x08 8761 #define TIMER2 0x10 8762 #define TIMER3 0x18 8763 #define RXDMA 0x00 8764 #define TXDMA 0x20 8765 #define NOOP 0x00 8766 #define TXRESET 0x01 8767 #define TXENABLE 0x02 8768 #define TXDISABLE 0x03 8769 #define TXCRCINIT 0x04 8770 #define TXCRCEXCL 0x05 8771 #define TXEOM 0x06 8772 #define TXABORT 0x07 8773 #define MPON 0x08 8774 #define TXBUFCLR 0x09 8775 #define RXRESET 0x11 8776 #define RXENABLE 0x12 8777 #define RXDISABLE 0x13 8778 #define RXCRCINIT 0x14 8779 #define RXREJECT 0x15 8780 #define SEARCHMP 0x16 8781 #define RXCRCEXCL 0x17 8782 #define RXCRCCALC 0x18 8783 #define CHRESET 0x21 8784 #define HUNT 0x31 8785 #define SWABORT 0x01 8786 #define FEICLEAR 0x02 8787 #define TXINTE BIT7 8788 #define RXINTE BIT6 8789 #define TXRDYE BIT1 8790 #define RXRDYE BIT0 8791 #define UDRN BIT7 8792 #define IDLE BIT6 8793 #define SYNCD BIT4 8794 #define FLGD BIT4 8795 #define CCTS BIT3 8796 #define CDCD BIT2 8797 #define BRKD BIT1 8798 #define ABTD BIT1 8799 #define GAPD BIT1 8800 #define BRKE BIT0 8801 #define IDLD BIT0 8802 #define EOM BIT7 8803 #define PMP BIT6 8804 #define SHRT BIT6 8805 #define PE BIT5 8806 #define ABT BIT5 8807 #define FRME BIT4 8808 #define RBIT BIT4 8809 #define OVRN BIT3 8810 #define CRCE BIT2 8811 #define WAKEUP_CHARS 256 8812 #if SYNCLINK_GENERIC_HDLC 8813 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 8814 #endif 8815 #ifdef SANITY_CHECK 8816 #else 8817 #endif 8818 /* LDV_COMMENT_END_PREP */ 8819 /* LDV_COMMENT_BEGIN_PREP */ 8820 #if SYNCLINK_GENERIC_HDLC 8821 #endif 8822 #if SYNCLINK_GENERIC_HDLC 8823 #endif 8824 #if SYNCLINK_GENERIC_HDLC 8825 #endif 8826 #ifdef CMSPAR 8827 #endif 8828 #if SYNCLINK_GENERIC_HDLC 8829 #endif 8830 #if SYNCLINK_GENERIC_HDLC 8831 #endif 8832 #if 0 8833 #endif 8834 #if SYNCLINK_GENERIC_HDLC 8835 #endif 8836 #if SYNCLINK_GENERIC_HDLC 8837 #endif 8838 #define TESTFRAMESIZE 20 8839 #if SYNCLINK_GENERIC_HDLC 8840 #endif 8841 #define CALC_REGADDR() \ 8842 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8843 if (info->port_num > 1) \ 8844 RegAddr += 256; \ 8845 if ( info->port_num & 1) { \ 8846 if (Addr > 0x7f) \ 8847 RegAddr += 0x40; \ 8848 else if (Addr > 0x1f && Addr < 0x60) \ 8849 RegAddr += 0x20; \ 8850 } 8851 /* LDV_COMMENT_END_PREP */ 8852 /* content: static int write_room(struct tty_struct *tty)*/ 8853 /* LDV_COMMENT_BEGIN_PREP */ 8854 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8855 #if defined(__i386__) 8856 # define BREAKPOINT() asm(" int $3"); 8857 #else 8858 # define BREAKPOINT() { } 8859 #endif 8860 #define MAX_DEVICES 12 8861 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8862 #define SYNCLINK_GENERIC_HDLC 1 8863 #else 8864 #define SYNCLINK_GENERIC_HDLC 0 8865 #endif 8866 #define GET_USER(error,value,addr) error = get_user(value,addr) 8867 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8868 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8869 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8870 #define SCABUFSIZE 1024 8871 #define SCA_MEM_SIZE 0x40000 8872 #define SCA_BASE_SIZE 512 8873 #define SCA_REG_SIZE 16 8874 #define SCA_MAX_PORTS 4 8875 #define SCAMAXDESC 128 8876 #define BUFFERLISTSIZE 4096 8877 #define BH_RECEIVE 1 8878 #define BH_TRANSMIT 2 8879 #define BH_STATUS 4 8880 #define IO_PIN_SHUTDOWN_LIMIT 100 8881 #if SYNCLINK_GENERIC_HDLC 8882 #endif 8883 #define MGSL_MAGIC 0x5401 8884 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8885 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8886 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8887 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8888 #define LPR 0x00 8889 #define PABR0 0x02 8890 #define PABR1 0x03 8891 #define WCRL 0x04 8892 #define WCRM 0x05 8893 #define WCRH 0x06 8894 #define DPCR 0x08 8895 #define DMER 0x09 8896 #define ISR0 0x10 8897 #define ISR1 0x11 8898 #define ISR2 0x12 8899 #define IER0 0x14 8900 #define IER1 0x15 8901 #define IER2 0x16 8902 #define ITCR 0x18 8903 #define INTVR 0x1a 8904 #define IMVR 0x1c 8905 #define TRB 0x20 8906 #define TRBL 0x20 8907 #define TRBH 0x21 8908 #define SR0 0x22 8909 #define SR1 0x23 8910 #define SR2 0x24 8911 #define SR3 0x25 8912 #define FST 0x26 8913 #define IE0 0x28 8914 #define IE1 0x29 8915 #define IE2 0x2a 8916 #define FIE 0x2b 8917 #define CMD 0x2c 8918 #define MD0 0x2e 8919 #define MD1 0x2f 8920 #define MD2 0x30 8921 #define CTL 0x31 8922 #define SA0 0x32 8923 #define SA1 0x33 8924 #define IDL 0x34 8925 #define TMC 0x35 8926 #define RXS 0x36 8927 #define TXS 0x37 8928 #define TRC0 0x38 8929 #define TRC1 0x39 8930 #define RRC 0x3a 8931 #define CST0 0x3c 8932 #define CST1 0x3d 8933 #define TCNT 0x60 8934 #define TCNTL 0x60 8935 #define TCNTH 0x61 8936 #define TCONR 0x62 8937 #define TCONRL 0x62 8938 #define TCONRH 0x63 8939 #define TMCS 0x64 8940 #define TEPR 0x65 8941 #define DARL 0x80 8942 #define DARH 0x81 8943 #define DARB 0x82 8944 #define BAR 0x80 8945 #define BARL 0x80 8946 #define BARH 0x81 8947 #define BARB 0x82 8948 #define SAR 0x84 8949 #define SARL 0x84 8950 #define SARH 0x85 8951 #define SARB 0x86 8952 #define CPB 0x86 8953 #define CDA 0x88 8954 #define CDAL 0x88 8955 #define CDAH 0x89 8956 #define EDA 0x8a 8957 #define EDAL 0x8a 8958 #define EDAH 0x8b 8959 #define BFL 0x8c 8960 #define BFLL 0x8c 8961 #define BFLH 0x8d 8962 #define BCR 0x8e 8963 #define BCRL 0x8e 8964 #define BCRH 0x8f 8965 #define DSR 0x90 8966 #define DMR 0x91 8967 #define FCT 0x93 8968 #define DIR 0x94 8969 #define DCMD 0x95 8970 #define TIMER0 0x00 8971 #define TIMER1 0x08 8972 #define TIMER2 0x10 8973 #define TIMER3 0x18 8974 #define RXDMA 0x00 8975 #define TXDMA 0x20 8976 #define NOOP 0x00 8977 #define TXRESET 0x01 8978 #define TXENABLE 0x02 8979 #define TXDISABLE 0x03 8980 #define TXCRCINIT 0x04 8981 #define TXCRCEXCL 0x05 8982 #define TXEOM 0x06 8983 #define TXABORT 0x07 8984 #define MPON 0x08 8985 #define TXBUFCLR 0x09 8986 #define RXRESET 0x11 8987 #define RXENABLE 0x12 8988 #define RXDISABLE 0x13 8989 #define RXCRCINIT 0x14 8990 #define RXREJECT 0x15 8991 #define SEARCHMP 0x16 8992 #define RXCRCEXCL 0x17 8993 #define RXCRCCALC 0x18 8994 #define CHRESET 0x21 8995 #define HUNT 0x31 8996 #define SWABORT 0x01 8997 #define FEICLEAR 0x02 8998 #define TXINTE BIT7 8999 #define RXINTE BIT6 9000 #define TXRDYE BIT1 9001 #define RXRDYE BIT0 9002 #define UDRN BIT7 9003 #define IDLE BIT6 9004 #define SYNCD BIT4 9005 #define FLGD BIT4 9006 #define CCTS BIT3 9007 #define CDCD BIT2 9008 #define BRKD BIT1 9009 #define ABTD BIT1 9010 #define GAPD BIT1 9011 #define BRKE BIT0 9012 #define IDLD BIT0 9013 #define EOM BIT7 9014 #define PMP BIT6 9015 #define SHRT BIT6 9016 #define PE BIT5 9017 #define ABT BIT5 9018 #define FRME BIT4 9019 #define RBIT BIT4 9020 #define OVRN BIT3 9021 #define CRCE BIT2 9022 #define WAKEUP_CHARS 256 9023 #if SYNCLINK_GENERIC_HDLC 9024 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9025 #endif 9026 #ifdef SANITY_CHECK 9027 #else 9028 #endif 9029 /* LDV_COMMENT_END_PREP */ 9030 /* LDV_COMMENT_BEGIN_PREP */ 9031 #if SYNCLINK_GENERIC_HDLC 9032 #endif 9033 #if SYNCLINK_GENERIC_HDLC 9034 #endif 9035 #if SYNCLINK_GENERIC_HDLC 9036 #endif 9037 #ifdef CMSPAR 9038 #endif 9039 #if SYNCLINK_GENERIC_HDLC 9040 #endif 9041 #if SYNCLINK_GENERIC_HDLC 9042 #endif 9043 #if 0 9044 #endif 9045 #if SYNCLINK_GENERIC_HDLC 9046 #endif 9047 #if SYNCLINK_GENERIC_HDLC 9048 #endif 9049 #define TESTFRAMESIZE 20 9050 #if SYNCLINK_GENERIC_HDLC 9051 #endif 9052 #define CALC_REGADDR() \ 9053 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9054 if (info->port_num > 1) \ 9055 RegAddr += 256; \ 9056 if ( info->port_num & 1) { \ 9057 if (Addr > 0x7f) \ 9058 RegAddr += 0x40; \ 9059 else if (Addr > 0x1f && Addr < 0x60) \ 9060 RegAddr += 0x20; \ 9061 } 9062 /* LDV_COMMENT_END_PREP */ 9063 /* content: static int chars_in_buffer(struct tty_struct *tty)*/ 9064 /* LDV_COMMENT_BEGIN_PREP */ 9065 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9066 #if defined(__i386__) 9067 # define BREAKPOINT() asm(" int $3"); 9068 #else 9069 # define BREAKPOINT() { } 9070 #endif 9071 #define MAX_DEVICES 12 9072 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9073 #define SYNCLINK_GENERIC_HDLC 1 9074 #else 9075 #define SYNCLINK_GENERIC_HDLC 0 9076 #endif 9077 #define GET_USER(error,value,addr) error = get_user(value,addr) 9078 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9079 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9080 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9081 #define SCABUFSIZE 1024 9082 #define SCA_MEM_SIZE 0x40000 9083 #define SCA_BASE_SIZE 512 9084 #define SCA_REG_SIZE 16 9085 #define SCA_MAX_PORTS 4 9086 #define SCAMAXDESC 128 9087 #define BUFFERLISTSIZE 4096 9088 #define BH_RECEIVE 1 9089 #define BH_TRANSMIT 2 9090 #define BH_STATUS 4 9091 #define IO_PIN_SHUTDOWN_LIMIT 100 9092 #if SYNCLINK_GENERIC_HDLC 9093 #endif 9094 #define MGSL_MAGIC 0x5401 9095 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9096 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9097 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9098 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9099 #define LPR 0x00 9100 #define PABR0 0x02 9101 #define PABR1 0x03 9102 #define WCRL 0x04 9103 #define WCRM 0x05 9104 #define WCRH 0x06 9105 #define DPCR 0x08 9106 #define DMER 0x09 9107 #define ISR0 0x10 9108 #define ISR1 0x11 9109 #define ISR2 0x12 9110 #define IER0 0x14 9111 #define IER1 0x15 9112 #define IER2 0x16 9113 #define ITCR 0x18 9114 #define INTVR 0x1a 9115 #define IMVR 0x1c 9116 #define TRB 0x20 9117 #define TRBL 0x20 9118 #define TRBH 0x21 9119 #define SR0 0x22 9120 #define SR1 0x23 9121 #define SR2 0x24 9122 #define SR3 0x25 9123 #define FST 0x26 9124 #define IE0 0x28 9125 #define IE1 0x29 9126 #define IE2 0x2a 9127 #define FIE 0x2b 9128 #define CMD 0x2c 9129 #define MD0 0x2e 9130 #define MD1 0x2f 9131 #define MD2 0x30 9132 #define CTL 0x31 9133 #define SA0 0x32 9134 #define SA1 0x33 9135 #define IDL 0x34 9136 #define TMC 0x35 9137 #define RXS 0x36 9138 #define TXS 0x37 9139 #define TRC0 0x38 9140 #define TRC1 0x39 9141 #define RRC 0x3a 9142 #define CST0 0x3c 9143 #define CST1 0x3d 9144 #define TCNT 0x60 9145 #define TCNTL 0x60 9146 #define TCNTH 0x61 9147 #define TCONR 0x62 9148 #define TCONRL 0x62 9149 #define TCONRH 0x63 9150 #define TMCS 0x64 9151 #define TEPR 0x65 9152 #define DARL 0x80 9153 #define DARH 0x81 9154 #define DARB 0x82 9155 #define BAR 0x80 9156 #define BARL 0x80 9157 #define BARH 0x81 9158 #define BARB 0x82 9159 #define SAR 0x84 9160 #define SARL 0x84 9161 #define SARH 0x85 9162 #define SARB 0x86 9163 #define CPB 0x86 9164 #define CDA 0x88 9165 #define CDAL 0x88 9166 #define CDAH 0x89 9167 #define EDA 0x8a 9168 #define EDAL 0x8a 9169 #define EDAH 0x8b 9170 #define BFL 0x8c 9171 #define BFLL 0x8c 9172 #define BFLH 0x8d 9173 #define BCR 0x8e 9174 #define BCRL 0x8e 9175 #define BCRH 0x8f 9176 #define DSR 0x90 9177 #define DMR 0x91 9178 #define FCT 0x93 9179 #define DIR 0x94 9180 #define DCMD 0x95 9181 #define TIMER0 0x00 9182 #define TIMER1 0x08 9183 #define TIMER2 0x10 9184 #define TIMER3 0x18 9185 #define RXDMA 0x00 9186 #define TXDMA 0x20 9187 #define NOOP 0x00 9188 #define TXRESET 0x01 9189 #define TXENABLE 0x02 9190 #define TXDISABLE 0x03 9191 #define TXCRCINIT 0x04 9192 #define TXCRCEXCL 0x05 9193 #define TXEOM 0x06 9194 #define TXABORT 0x07 9195 #define MPON 0x08 9196 #define TXBUFCLR 0x09 9197 #define RXRESET 0x11 9198 #define RXENABLE 0x12 9199 #define RXDISABLE 0x13 9200 #define RXCRCINIT 0x14 9201 #define RXREJECT 0x15 9202 #define SEARCHMP 0x16 9203 #define RXCRCEXCL 0x17 9204 #define RXCRCCALC 0x18 9205 #define CHRESET 0x21 9206 #define HUNT 0x31 9207 #define SWABORT 0x01 9208 #define FEICLEAR 0x02 9209 #define TXINTE BIT7 9210 #define RXINTE BIT6 9211 #define TXRDYE BIT1 9212 #define RXRDYE BIT0 9213 #define UDRN BIT7 9214 #define IDLE BIT6 9215 #define SYNCD BIT4 9216 #define FLGD BIT4 9217 #define CCTS BIT3 9218 #define CDCD BIT2 9219 #define BRKD BIT1 9220 #define ABTD BIT1 9221 #define GAPD BIT1 9222 #define BRKE BIT0 9223 #define IDLD BIT0 9224 #define EOM BIT7 9225 #define PMP BIT6 9226 #define SHRT BIT6 9227 #define PE BIT5 9228 #define ABT BIT5 9229 #define FRME BIT4 9230 #define RBIT BIT4 9231 #define OVRN BIT3 9232 #define CRCE BIT2 9233 #define WAKEUP_CHARS 256 9234 #if SYNCLINK_GENERIC_HDLC 9235 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9236 #endif 9237 #ifdef SANITY_CHECK 9238 #else 9239 #endif 9240 /* LDV_COMMENT_END_PREP */ 9241 /* LDV_COMMENT_BEGIN_PREP */ 9242 #if SYNCLINK_GENERIC_HDLC 9243 #endif 9244 #if SYNCLINK_GENERIC_HDLC 9245 #endif 9246 #if SYNCLINK_GENERIC_HDLC 9247 #endif 9248 #ifdef CMSPAR 9249 #endif 9250 #if SYNCLINK_GENERIC_HDLC 9251 #endif 9252 #if SYNCLINK_GENERIC_HDLC 9253 #endif 9254 #if 0 9255 #endif 9256 #if SYNCLINK_GENERIC_HDLC 9257 #endif 9258 #if SYNCLINK_GENERIC_HDLC 9259 #endif 9260 #define TESTFRAMESIZE 20 9261 #if SYNCLINK_GENERIC_HDLC 9262 #endif 9263 #define CALC_REGADDR() \ 9264 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9265 if (info->port_num > 1) \ 9266 RegAddr += 256; \ 9267 if ( info->port_num & 1) { \ 9268 if (Addr > 0x7f) \ 9269 RegAddr += 0x40; \ 9270 else if (Addr > 0x1f && Addr < 0x60) \ 9271 RegAddr += 0x20; \ 9272 } 9273 /* LDV_COMMENT_END_PREP */ 9274 /* content: static void flush_buffer(struct tty_struct *tty)*/ 9275 /* LDV_COMMENT_BEGIN_PREP */ 9276 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9277 #if defined(__i386__) 9278 # define BREAKPOINT() asm(" int $3"); 9279 #else 9280 # define BREAKPOINT() { } 9281 #endif 9282 #define MAX_DEVICES 12 9283 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9284 #define SYNCLINK_GENERIC_HDLC 1 9285 #else 9286 #define SYNCLINK_GENERIC_HDLC 0 9287 #endif 9288 #define GET_USER(error,value,addr) error = get_user(value,addr) 9289 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9290 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9291 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9292 #define SCABUFSIZE 1024 9293 #define SCA_MEM_SIZE 0x40000 9294 #define SCA_BASE_SIZE 512 9295 #define SCA_REG_SIZE 16 9296 #define SCA_MAX_PORTS 4 9297 #define SCAMAXDESC 128 9298 #define BUFFERLISTSIZE 4096 9299 #define BH_RECEIVE 1 9300 #define BH_TRANSMIT 2 9301 #define BH_STATUS 4 9302 #define IO_PIN_SHUTDOWN_LIMIT 100 9303 #if SYNCLINK_GENERIC_HDLC 9304 #endif 9305 #define MGSL_MAGIC 0x5401 9306 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9307 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9308 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9309 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9310 #define LPR 0x00 9311 #define PABR0 0x02 9312 #define PABR1 0x03 9313 #define WCRL 0x04 9314 #define WCRM 0x05 9315 #define WCRH 0x06 9316 #define DPCR 0x08 9317 #define DMER 0x09 9318 #define ISR0 0x10 9319 #define ISR1 0x11 9320 #define ISR2 0x12 9321 #define IER0 0x14 9322 #define IER1 0x15 9323 #define IER2 0x16 9324 #define ITCR 0x18 9325 #define INTVR 0x1a 9326 #define IMVR 0x1c 9327 #define TRB 0x20 9328 #define TRBL 0x20 9329 #define TRBH 0x21 9330 #define SR0 0x22 9331 #define SR1 0x23 9332 #define SR2 0x24 9333 #define SR3 0x25 9334 #define FST 0x26 9335 #define IE0 0x28 9336 #define IE1 0x29 9337 #define IE2 0x2a 9338 #define FIE 0x2b 9339 #define CMD 0x2c 9340 #define MD0 0x2e 9341 #define MD1 0x2f 9342 #define MD2 0x30 9343 #define CTL 0x31 9344 #define SA0 0x32 9345 #define SA1 0x33 9346 #define IDL 0x34 9347 #define TMC 0x35 9348 #define RXS 0x36 9349 #define TXS 0x37 9350 #define TRC0 0x38 9351 #define TRC1 0x39 9352 #define RRC 0x3a 9353 #define CST0 0x3c 9354 #define CST1 0x3d 9355 #define TCNT 0x60 9356 #define TCNTL 0x60 9357 #define TCNTH 0x61 9358 #define TCONR 0x62 9359 #define TCONRL 0x62 9360 #define TCONRH 0x63 9361 #define TMCS 0x64 9362 #define TEPR 0x65 9363 #define DARL 0x80 9364 #define DARH 0x81 9365 #define DARB 0x82 9366 #define BAR 0x80 9367 #define BARL 0x80 9368 #define BARH 0x81 9369 #define BARB 0x82 9370 #define SAR 0x84 9371 #define SARL 0x84 9372 #define SARH 0x85 9373 #define SARB 0x86 9374 #define CPB 0x86 9375 #define CDA 0x88 9376 #define CDAL 0x88 9377 #define CDAH 0x89 9378 #define EDA 0x8a 9379 #define EDAL 0x8a 9380 #define EDAH 0x8b 9381 #define BFL 0x8c 9382 #define BFLL 0x8c 9383 #define BFLH 0x8d 9384 #define BCR 0x8e 9385 #define BCRL 0x8e 9386 #define BCRH 0x8f 9387 #define DSR 0x90 9388 #define DMR 0x91 9389 #define FCT 0x93 9390 #define DIR 0x94 9391 #define DCMD 0x95 9392 #define TIMER0 0x00 9393 #define TIMER1 0x08 9394 #define TIMER2 0x10 9395 #define TIMER3 0x18 9396 #define RXDMA 0x00 9397 #define TXDMA 0x20 9398 #define NOOP 0x00 9399 #define TXRESET 0x01 9400 #define TXENABLE 0x02 9401 #define TXDISABLE 0x03 9402 #define TXCRCINIT 0x04 9403 #define TXCRCEXCL 0x05 9404 #define TXEOM 0x06 9405 #define TXABORT 0x07 9406 #define MPON 0x08 9407 #define TXBUFCLR 0x09 9408 #define RXRESET 0x11 9409 #define RXENABLE 0x12 9410 #define RXDISABLE 0x13 9411 #define RXCRCINIT 0x14 9412 #define RXREJECT 0x15 9413 #define SEARCHMP 0x16 9414 #define RXCRCEXCL 0x17 9415 #define RXCRCCALC 0x18 9416 #define CHRESET 0x21 9417 #define HUNT 0x31 9418 #define SWABORT 0x01 9419 #define FEICLEAR 0x02 9420 #define TXINTE BIT7 9421 #define RXINTE BIT6 9422 #define TXRDYE BIT1 9423 #define RXRDYE BIT0 9424 #define UDRN BIT7 9425 #define IDLE BIT6 9426 #define SYNCD BIT4 9427 #define FLGD BIT4 9428 #define CCTS BIT3 9429 #define CDCD BIT2 9430 #define BRKD BIT1 9431 #define ABTD BIT1 9432 #define GAPD BIT1 9433 #define BRKE BIT0 9434 #define IDLD BIT0 9435 #define EOM BIT7 9436 #define PMP BIT6 9437 #define SHRT BIT6 9438 #define PE BIT5 9439 #define ABT BIT5 9440 #define FRME BIT4 9441 #define RBIT BIT4 9442 #define OVRN BIT3 9443 #define CRCE BIT2 9444 #define WAKEUP_CHARS 256 9445 #if SYNCLINK_GENERIC_HDLC 9446 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9447 #endif 9448 #ifdef SANITY_CHECK 9449 #else 9450 #endif 9451 /* LDV_COMMENT_END_PREP */ 9452 /* LDV_COMMENT_BEGIN_PREP */ 9453 #if SYNCLINK_GENERIC_HDLC 9454 #endif 9455 #if SYNCLINK_GENERIC_HDLC 9456 #endif 9457 #if SYNCLINK_GENERIC_HDLC 9458 #endif 9459 #ifdef CMSPAR 9460 #endif 9461 #if SYNCLINK_GENERIC_HDLC 9462 #endif 9463 #if SYNCLINK_GENERIC_HDLC 9464 #endif 9465 #if 0 9466 #endif 9467 #if SYNCLINK_GENERIC_HDLC 9468 #endif 9469 #if SYNCLINK_GENERIC_HDLC 9470 #endif 9471 #define TESTFRAMESIZE 20 9472 #if SYNCLINK_GENERIC_HDLC 9473 #endif 9474 #define CALC_REGADDR() \ 9475 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9476 if (info->port_num > 1) \ 9477 RegAddr += 256; \ 9478 if ( info->port_num & 1) { \ 9479 if (Addr > 0x7f) \ 9480 RegAddr += 0x40; \ 9481 else if (Addr > 0x1f && Addr < 0x60) \ 9482 RegAddr += 0x20; \ 9483 } 9484 /* LDV_COMMENT_END_PREP */ 9485 /* content: static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg)*/ 9486 /* LDV_COMMENT_BEGIN_PREP */ 9487 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9488 #if defined(__i386__) 9489 # define BREAKPOINT() asm(" int $3"); 9490 #else 9491 # define BREAKPOINT() { } 9492 #endif 9493 #define MAX_DEVICES 12 9494 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9495 #define SYNCLINK_GENERIC_HDLC 1 9496 #else 9497 #define SYNCLINK_GENERIC_HDLC 0 9498 #endif 9499 #define GET_USER(error,value,addr) error = get_user(value,addr) 9500 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9501 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9502 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9503 #define SCABUFSIZE 1024 9504 #define SCA_MEM_SIZE 0x40000 9505 #define SCA_BASE_SIZE 512 9506 #define SCA_REG_SIZE 16 9507 #define SCA_MAX_PORTS 4 9508 #define SCAMAXDESC 128 9509 #define BUFFERLISTSIZE 4096 9510 #define BH_RECEIVE 1 9511 #define BH_TRANSMIT 2 9512 #define BH_STATUS 4 9513 #define IO_PIN_SHUTDOWN_LIMIT 100 9514 #if SYNCLINK_GENERIC_HDLC 9515 #endif 9516 #define MGSL_MAGIC 0x5401 9517 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9518 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9519 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9520 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9521 #define LPR 0x00 9522 #define PABR0 0x02 9523 #define PABR1 0x03 9524 #define WCRL 0x04 9525 #define WCRM 0x05 9526 #define WCRH 0x06 9527 #define DPCR 0x08 9528 #define DMER 0x09 9529 #define ISR0 0x10 9530 #define ISR1 0x11 9531 #define ISR2 0x12 9532 #define IER0 0x14 9533 #define IER1 0x15 9534 #define IER2 0x16 9535 #define ITCR 0x18 9536 #define INTVR 0x1a 9537 #define IMVR 0x1c 9538 #define TRB 0x20 9539 #define TRBL 0x20 9540 #define TRBH 0x21 9541 #define SR0 0x22 9542 #define SR1 0x23 9543 #define SR2 0x24 9544 #define SR3 0x25 9545 #define FST 0x26 9546 #define IE0 0x28 9547 #define IE1 0x29 9548 #define IE2 0x2a 9549 #define FIE 0x2b 9550 #define CMD 0x2c 9551 #define MD0 0x2e 9552 #define MD1 0x2f 9553 #define MD2 0x30 9554 #define CTL 0x31 9555 #define SA0 0x32 9556 #define SA1 0x33 9557 #define IDL 0x34 9558 #define TMC 0x35 9559 #define RXS 0x36 9560 #define TXS 0x37 9561 #define TRC0 0x38 9562 #define TRC1 0x39 9563 #define RRC 0x3a 9564 #define CST0 0x3c 9565 #define CST1 0x3d 9566 #define TCNT 0x60 9567 #define TCNTL 0x60 9568 #define TCNTH 0x61 9569 #define TCONR 0x62 9570 #define TCONRL 0x62 9571 #define TCONRH 0x63 9572 #define TMCS 0x64 9573 #define TEPR 0x65 9574 #define DARL 0x80 9575 #define DARH 0x81 9576 #define DARB 0x82 9577 #define BAR 0x80 9578 #define BARL 0x80 9579 #define BARH 0x81 9580 #define BARB 0x82 9581 #define SAR 0x84 9582 #define SARL 0x84 9583 #define SARH 0x85 9584 #define SARB 0x86 9585 #define CPB 0x86 9586 #define CDA 0x88 9587 #define CDAL 0x88 9588 #define CDAH 0x89 9589 #define EDA 0x8a 9590 #define EDAL 0x8a 9591 #define EDAH 0x8b 9592 #define BFL 0x8c 9593 #define BFLL 0x8c 9594 #define BFLH 0x8d 9595 #define BCR 0x8e 9596 #define BCRL 0x8e 9597 #define BCRH 0x8f 9598 #define DSR 0x90 9599 #define DMR 0x91 9600 #define FCT 0x93 9601 #define DIR 0x94 9602 #define DCMD 0x95 9603 #define TIMER0 0x00 9604 #define TIMER1 0x08 9605 #define TIMER2 0x10 9606 #define TIMER3 0x18 9607 #define RXDMA 0x00 9608 #define TXDMA 0x20 9609 #define NOOP 0x00 9610 #define TXRESET 0x01 9611 #define TXENABLE 0x02 9612 #define TXDISABLE 0x03 9613 #define TXCRCINIT 0x04 9614 #define TXCRCEXCL 0x05 9615 #define TXEOM 0x06 9616 #define TXABORT 0x07 9617 #define MPON 0x08 9618 #define TXBUFCLR 0x09 9619 #define RXRESET 0x11 9620 #define RXENABLE 0x12 9621 #define RXDISABLE 0x13 9622 #define RXCRCINIT 0x14 9623 #define RXREJECT 0x15 9624 #define SEARCHMP 0x16 9625 #define RXCRCEXCL 0x17 9626 #define RXCRCCALC 0x18 9627 #define CHRESET 0x21 9628 #define HUNT 0x31 9629 #define SWABORT 0x01 9630 #define FEICLEAR 0x02 9631 #define TXINTE BIT7 9632 #define RXINTE BIT6 9633 #define TXRDYE BIT1 9634 #define RXRDYE BIT0 9635 #define UDRN BIT7 9636 #define IDLE BIT6 9637 #define SYNCD BIT4 9638 #define FLGD BIT4 9639 #define CCTS BIT3 9640 #define CDCD BIT2 9641 #define BRKD BIT1 9642 #define ABTD BIT1 9643 #define GAPD BIT1 9644 #define BRKE BIT0 9645 #define IDLD BIT0 9646 #define EOM BIT7 9647 #define PMP BIT6 9648 #define SHRT BIT6 9649 #define PE BIT5 9650 #define ABT BIT5 9651 #define FRME BIT4 9652 #define RBIT BIT4 9653 #define OVRN BIT3 9654 #define CRCE BIT2 9655 #define WAKEUP_CHARS 256 9656 #if SYNCLINK_GENERIC_HDLC 9657 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9658 #endif 9659 #ifdef SANITY_CHECK 9660 #else 9661 #endif 9662 /* LDV_COMMENT_END_PREP */ 9663 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "ioctl" */ 9664 unsigned int var_ioctl_17_p1; 9665 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "ioctl" */ 9666 unsigned long var_ioctl_17_p2; 9667 /* LDV_COMMENT_BEGIN_PREP */ 9668 #if SYNCLINK_GENERIC_HDLC 9669 #endif 9670 #if SYNCLINK_GENERIC_HDLC 9671 #endif 9672 #if SYNCLINK_GENERIC_HDLC 9673 #endif 9674 #ifdef CMSPAR 9675 #endif 9676 #if SYNCLINK_GENERIC_HDLC 9677 #endif 9678 #if SYNCLINK_GENERIC_HDLC 9679 #endif 9680 #if 0 9681 #endif 9682 #if SYNCLINK_GENERIC_HDLC 9683 #endif 9684 #if SYNCLINK_GENERIC_HDLC 9685 #endif 9686 #define TESTFRAMESIZE 20 9687 #if SYNCLINK_GENERIC_HDLC 9688 #endif 9689 #define CALC_REGADDR() \ 9690 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9691 if (info->port_num > 1) \ 9692 RegAddr += 256; \ 9693 if ( info->port_num & 1) { \ 9694 if (Addr > 0x7f) \ 9695 RegAddr += 0x40; \ 9696 else if (Addr > 0x1f && Addr < 0x60) \ 9697 RegAddr += 0x20; \ 9698 } 9699 /* LDV_COMMENT_END_PREP */ 9700 /* content: static void throttle(struct tty_struct * tty)*/ 9701 /* LDV_COMMENT_BEGIN_PREP */ 9702 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9703 #if defined(__i386__) 9704 # define BREAKPOINT() asm(" int $3"); 9705 #else 9706 # define BREAKPOINT() { } 9707 #endif 9708 #define MAX_DEVICES 12 9709 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9710 #define SYNCLINK_GENERIC_HDLC 1 9711 #else 9712 #define SYNCLINK_GENERIC_HDLC 0 9713 #endif 9714 #define GET_USER(error,value,addr) error = get_user(value,addr) 9715 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9716 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9717 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9718 #define SCABUFSIZE 1024 9719 #define SCA_MEM_SIZE 0x40000 9720 #define SCA_BASE_SIZE 512 9721 #define SCA_REG_SIZE 16 9722 #define SCA_MAX_PORTS 4 9723 #define SCAMAXDESC 128 9724 #define BUFFERLISTSIZE 4096 9725 #define BH_RECEIVE 1 9726 #define BH_TRANSMIT 2 9727 #define BH_STATUS 4 9728 #define IO_PIN_SHUTDOWN_LIMIT 100 9729 #if SYNCLINK_GENERIC_HDLC 9730 #endif 9731 #define MGSL_MAGIC 0x5401 9732 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9733 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9734 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9735 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9736 #define LPR 0x00 9737 #define PABR0 0x02 9738 #define PABR1 0x03 9739 #define WCRL 0x04 9740 #define WCRM 0x05 9741 #define WCRH 0x06 9742 #define DPCR 0x08 9743 #define DMER 0x09 9744 #define ISR0 0x10 9745 #define ISR1 0x11 9746 #define ISR2 0x12 9747 #define IER0 0x14 9748 #define IER1 0x15 9749 #define IER2 0x16 9750 #define ITCR 0x18 9751 #define INTVR 0x1a 9752 #define IMVR 0x1c 9753 #define TRB 0x20 9754 #define TRBL 0x20 9755 #define TRBH 0x21 9756 #define SR0 0x22 9757 #define SR1 0x23 9758 #define SR2 0x24 9759 #define SR3 0x25 9760 #define FST 0x26 9761 #define IE0 0x28 9762 #define IE1 0x29 9763 #define IE2 0x2a 9764 #define FIE 0x2b 9765 #define CMD 0x2c 9766 #define MD0 0x2e 9767 #define MD1 0x2f 9768 #define MD2 0x30 9769 #define CTL 0x31 9770 #define SA0 0x32 9771 #define SA1 0x33 9772 #define IDL 0x34 9773 #define TMC 0x35 9774 #define RXS 0x36 9775 #define TXS 0x37 9776 #define TRC0 0x38 9777 #define TRC1 0x39 9778 #define RRC 0x3a 9779 #define CST0 0x3c 9780 #define CST1 0x3d 9781 #define TCNT 0x60 9782 #define TCNTL 0x60 9783 #define TCNTH 0x61 9784 #define TCONR 0x62 9785 #define TCONRL 0x62 9786 #define TCONRH 0x63 9787 #define TMCS 0x64 9788 #define TEPR 0x65 9789 #define DARL 0x80 9790 #define DARH 0x81 9791 #define DARB 0x82 9792 #define BAR 0x80 9793 #define BARL 0x80 9794 #define BARH 0x81 9795 #define BARB 0x82 9796 #define SAR 0x84 9797 #define SARL 0x84 9798 #define SARH 0x85 9799 #define SARB 0x86 9800 #define CPB 0x86 9801 #define CDA 0x88 9802 #define CDAL 0x88 9803 #define CDAH 0x89 9804 #define EDA 0x8a 9805 #define EDAL 0x8a 9806 #define EDAH 0x8b 9807 #define BFL 0x8c 9808 #define BFLL 0x8c 9809 #define BFLH 0x8d 9810 #define BCR 0x8e 9811 #define BCRL 0x8e 9812 #define BCRH 0x8f 9813 #define DSR 0x90 9814 #define DMR 0x91 9815 #define FCT 0x93 9816 #define DIR 0x94 9817 #define DCMD 0x95 9818 #define TIMER0 0x00 9819 #define TIMER1 0x08 9820 #define TIMER2 0x10 9821 #define TIMER3 0x18 9822 #define RXDMA 0x00 9823 #define TXDMA 0x20 9824 #define NOOP 0x00 9825 #define TXRESET 0x01 9826 #define TXENABLE 0x02 9827 #define TXDISABLE 0x03 9828 #define TXCRCINIT 0x04 9829 #define TXCRCEXCL 0x05 9830 #define TXEOM 0x06 9831 #define TXABORT 0x07 9832 #define MPON 0x08 9833 #define TXBUFCLR 0x09 9834 #define RXRESET 0x11 9835 #define RXENABLE 0x12 9836 #define RXDISABLE 0x13 9837 #define RXCRCINIT 0x14 9838 #define RXREJECT 0x15 9839 #define SEARCHMP 0x16 9840 #define RXCRCEXCL 0x17 9841 #define RXCRCCALC 0x18 9842 #define CHRESET 0x21 9843 #define HUNT 0x31 9844 #define SWABORT 0x01 9845 #define FEICLEAR 0x02 9846 #define TXINTE BIT7 9847 #define RXINTE BIT6 9848 #define TXRDYE BIT1 9849 #define RXRDYE BIT0 9850 #define UDRN BIT7 9851 #define IDLE BIT6 9852 #define SYNCD BIT4 9853 #define FLGD BIT4 9854 #define CCTS BIT3 9855 #define CDCD BIT2 9856 #define BRKD BIT1 9857 #define ABTD BIT1 9858 #define GAPD BIT1 9859 #define BRKE BIT0 9860 #define IDLD BIT0 9861 #define EOM BIT7 9862 #define PMP BIT6 9863 #define SHRT BIT6 9864 #define PE BIT5 9865 #define ABT BIT5 9866 #define FRME BIT4 9867 #define RBIT BIT4 9868 #define OVRN BIT3 9869 #define CRCE BIT2 9870 #define WAKEUP_CHARS 256 9871 #if SYNCLINK_GENERIC_HDLC 9872 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9873 #endif 9874 #ifdef SANITY_CHECK 9875 #else 9876 #endif 9877 /* LDV_COMMENT_END_PREP */ 9878 /* LDV_COMMENT_BEGIN_PREP */ 9879 #if SYNCLINK_GENERIC_HDLC 9880 #endif 9881 #if SYNCLINK_GENERIC_HDLC 9882 #endif 9883 #if SYNCLINK_GENERIC_HDLC 9884 #endif 9885 #ifdef CMSPAR 9886 #endif 9887 #if SYNCLINK_GENERIC_HDLC 9888 #endif 9889 #if SYNCLINK_GENERIC_HDLC 9890 #endif 9891 #if 0 9892 #endif 9893 #if SYNCLINK_GENERIC_HDLC 9894 #endif 9895 #if SYNCLINK_GENERIC_HDLC 9896 #endif 9897 #define TESTFRAMESIZE 20 9898 #if SYNCLINK_GENERIC_HDLC 9899 #endif 9900 #define CALC_REGADDR() \ 9901 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9902 if (info->port_num > 1) \ 9903 RegAddr += 256; \ 9904 if ( info->port_num & 1) { \ 9905 if (Addr > 0x7f) \ 9906 RegAddr += 0x40; \ 9907 else if (Addr > 0x1f && Addr < 0x60) \ 9908 RegAddr += 0x20; \ 9909 } 9910 /* LDV_COMMENT_END_PREP */ 9911 /* content: static void unthrottle(struct tty_struct * tty)*/ 9912 /* LDV_COMMENT_BEGIN_PREP */ 9913 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9914 #if defined(__i386__) 9915 # define BREAKPOINT() asm(" int $3"); 9916 #else 9917 # define BREAKPOINT() { } 9918 #endif 9919 #define MAX_DEVICES 12 9920 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9921 #define SYNCLINK_GENERIC_HDLC 1 9922 #else 9923 #define SYNCLINK_GENERIC_HDLC 0 9924 #endif 9925 #define GET_USER(error,value,addr) error = get_user(value,addr) 9926 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9927 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9928 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9929 #define SCABUFSIZE 1024 9930 #define SCA_MEM_SIZE 0x40000 9931 #define SCA_BASE_SIZE 512 9932 #define SCA_REG_SIZE 16 9933 #define SCA_MAX_PORTS 4 9934 #define SCAMAXDESC 128 9935 #define BUFFERLISTSIZE 4096 9936 #define BH_RECEIVE 1 9937 #define BH_TRANSMIT 2 9938 #define BH_STATUS 4 9939 #define IO_PIN_SHUTDOWN_LIMIT 100 9940 #if SYNCLINK_GENERIC_HDLC 9941 #endif 9942 #define MGSL_MAGIC 0x5401 9943 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9944 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9945 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9946 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9947 #define LPR 0x00 9948 #define PABR0 0x02 9949 #define PABR1 0x03 9950 #define WCRL 0x04 9951 #define WCRM 0x05 9952 #define WCRH 0x06 9953 #define DPCR 0x08 9954 #define DMER 0x09 9955 #define ISR0 0x10 9956 #define ISR1 0x11 9957 #define ISR2 0x12 9958 #define IER0 0x14 9959 #define IER1 0x15 9960 #define IER2 0x16 9961 #define ITCR 0x18 9962 #define INTVR 0x1a 9963 #define IMVR 0x1c 9964 #define TRB 0x20 9965 #define TRBL 0x20 9966 #define TRBH 0x21 9967 #define SR0 0x22 9968 #define SR1 0x23 9969 #define SR2 0x24 9970 #define SR3 0x25 9971 #define FST 0x26 9972 #define IE0 0x28 9973 #define IE1 0x29 9974 #define IE2 0x2a 9975 #define FIE 0x2b 9976 #define CMD 0x2c 9977 #define MD0 0x2e 9978 #define MD1 0x2f 9979 #define MD2 0x30 9980 #define CTL 0x31 9981 #define SA0 0x32 9982 #define SA1 0x33 9983 #define IDL 0x34 9984 #define TMC 0x35 9985 #define RXS 0x36 9986 #define TXS 0x37 9987 #define TRC0 0x38 9988 #define TRC1 0x39 9989 #define RRC 0x3a 9990 #define CST0 0x3c 9991 #define CST1 0x3d 9992 #define TCNT 0x60 9993 #define TCNTL 0x60 9994 #define TCNTH 0x61 9995 #define TCONR 0x62 9996 #define TCONRL 0x62 9997 #define TCONRH 0x63 9998 #define TMCS 0x64 9999 #define TEPR 0x65 10000 #define DARL 0x80 10001 #define DARH 0x81 10002 #define DARB 0x82 10003 #define BAR 0x80 10004 #define BARL 0x80 10005 #define BARH 0x81 10006 #define BARB 0x82 10007 #define SAR 0x84 10008 #define SARL 0x84 10009 #define SARH 0x85 10010 #define SARB 0x86 10011 #define CPB 0x86 10012 #define CDA 0x88 10013 #define CDAL 0x88 10014 #define CDAH 0x89 10015 #define EDA 0x8a 10016 #define EDAL 0x8a 10017 #define EDAH 0x8b 10018 #define BFL 0x8c 10019 #define BFLL 0x8c 10020 #define BFLH 0x8d 10021 #define BCR 0x8e 10022 #define BCRL 0x8e 10023 #define BCRH 0x8f 10024 #define DSR 0x90 10025 #define DMR 0x91 10026 #define FCT 0x93 10027 #define DIR 0x94 10028 #define DCMD 0x95 10029 #define TIMER0 0x00 10030 #define TIMER1 0x08 10031 #define TIMER2 0x10 10032 #define TIMER3 0x18 10033 #define RXDMA 0x00 10034 #define TXDMA 0x20 10035 #define NOOP 0x00 10036 #define TXRESET 0x01 10037 #define TXENABLE 0x02 10038 #define TXDISABLE 0x03 10039 #define TXCRCINIT 0x04 10040 #define TXCRCEXCL 0x05 10041 #define TXEOM 0x06 10042 #define TXABORT 0x07 10043 #define MPON 0x08 10044 #define TXBUFCLR 0x09 10045 #define RXRESET 0x11 10046 #define RXENABLE 0x12 10047 #define RXDISABLE 0x13 10048 #define RXCRCINIT 0x14 10049 #define RXREJECT 0x15 10050 #define SEARCHMP 0x16 10051 #define RXCRCEXCL 0x17 10052 #define RXCRCCALC 0x18 10053 #define CHRESET 0x21 10054 #define HUNT 0x31 10055 #define SWABORT 0x01 10056 #define FEICLEAR 0x02 10057 #define TXINTE BIT7 10058 #define RXINTE BIT6 10059 #define TXRDYE BIT1 10060 #define RXRDYE BIT0 10061 #define UDRN BIT7 10062 #define IDLE BIT6 10063 #define SYNCD BIT4 10064 #define FLGD BIT4 10065 #define CCTS BIT3 10066 #define CDCD BIT2 10067 #define BRKD BIT1 10068 #define ABTD BIT1 10069 #define GAPD BIT1 10070 #define BRKE BIT0 10071 #define IDLD BIT0 10072 #define EOM BIT7 10073 #define PMP BIT6 10074 #define SHRT BIT6 10075 #define PE BIT5 10076 #define ABT BIT5 10077 #define FRME BIT4 10078 #define RBIT BIT4 10079 #define OVRN BIT3 10080 #define CRCE BIT2 10081 #define WAKEUP_CHARS 256 10082 #if SYNCLINK_GENERIC_HDLC 10083 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10084 #endif 10085 #ifdef SANITY_CHECK 10086 #else 10087 #endif 10088 /* LDV_COMMENT_END_PREP */ 10089 /* LDV_COMMENT_BEGIN_PREP */ 10090 #if SYNCLINK_GENERIC_HDLC 10091 #endif 10092 #if SYNCLINK_GENERIC_HDLC 10093 #endif 10094 #if SYNCLINK_GENERIC_HDLC 10095 #endif 10096 #ifdef CMSPAR 10097 #endif 10098 #if SYNCLINK_GENERIC_HDLC 10099 #endif 10100 #if SYNCLINK_GENERIC_HDLC 10101 #endif 10102 #if 0 10103 #endif 10104 #if SYNCLINK_GENERIC_HDLC 10105 #endif 10106 #if SYNCLINK_GENERIC_HDLC 10107 #endif 10108 #define TESTFRAMESIZE 20 10109 #if SYNCLINK_GENERIC_HDLC 10110 #endif 10111 #define CALC_REGADDR() \ 10112 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10113 if (info->port_num > 1) \ 10114 RegAddr += 256; \ 10115 if ( info->port_num & 1) { \ 10116 if (Addr > 0x7f) \ 10117 RegAddr += 0x40; \ 10118 else if (Addr > 0x1f && Addr < 0x60) \ 10119 RegAddr += 0x20; \ 10120 } 10121 /* LDV_COMMENT_END_PREP */ 10122 /* content: static void send_xchar(struct tty_struct *tty, char ch)*/ 10123 /* LDV_COMMENT_BEGIN_PREP */ 10124 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10125 #if defined(__i386__) 10126 # define BREAKPOINT() asm(" int $3"); 10127 #else 10128 # define BREAKPOINT() { } 10129 #endif 10130 #define MAX_DEVICES 12 10131 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10132 #define SYNCLINK_GENERIC_HDLC 1 10133 #else 10134 #define SYNCLINK_GENERIC_HDLC 0 10135 #endif 10136 #define GET_USER(error,value,addr) error = get_user(value,addr) 10137 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10138 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10139 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10140 #define SCABUFSIZE 1024 10141 #define SCA_MEM_SIZE 0x40000 10142 #define SCA_BASE_SIZE 512 10143 #define SCA_REG_SIZE 16 10144 #define SCA_MAX_PORTS 4 10145 #define SCAMAXDESC 128 10146 #define BUFFERLISTSIZE 4096 10147 #define BH_RECEIVE 1 10148 #define BH_TRANSMIT 2 10149 #define BH_STATUS 4 10150 #define IO_PIN_SHUTDOWN_LIMIT 100 10151 #if SYNCLINK_GENERIC_HDLC 10152 #endif 10153 #define MGSL_MAGIC 0x5401 10154 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 10155 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 10156 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 10157 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 10158 #define LPR 0x00 10159 #define PABR0 0x02 10160 #define PABR1 0x03 10161 #define WCRL 0x04 10162 #define WCRM 0x05 10163 #define WCRH 0x06 10164 #define DPCR 0x08 10165 #define DMER 0x09 10166 #define ISR0 0x10 10167 #define ISR1 0x11 10168 #define ISR2 0x12 10169 #define IER0 0x14 10170 #define IER1 0x15 10171 #define IER2 0x16 10172 #define ITCR 0x18 10173 #define INTVR 0x1a 10174 #define IMVR 0x1c 10175 #define TRB 0x20 10176 #define TRBL 0x20 10177 #define TRBH 0x21 10178 #define SR0 0x22 10179 #define SR1 0x23 10180 #define SR2 0x24 10181 #define SR3 0x25 10182 #define FST 0x26 10183 #define IE0 0x28 10184 #define IE1 0x29 10185 #define IE2 0x2a 10186 #define FIE 0x2b 10187 #define CMD 0x2c 10188 #define MD0 0x2e 10189 #define MD1 0x2f 10190 #define MD2 0x30 10191 #define CTL 0x31 10192 #define SA0 0x32 10193 #define SA1 0x33 10194 #define IDL 0x34 10195 #define TMC 0x35 10196 #define RXS 0x36 10197 #define TXS 0x37 10198 #define TRC0 0x38 10199 #define TRC1 0x39 10200 #define RRC 0x3a 10201 #define CST0 0x3c 10202 #define CST1 0x3d 10203 #define TCNT 0x60 10204 #define TCNTL 0x60 10205 #define TCNTH 0x61 10206 #define TCONR 0x62 10207 #define TCONRL 0x62 10208 #define TCONRH 0x63 10209 #define TMCS 0x64 10210 #define TEPR 0x65 10211 #define DARL 0x80 10212 #define DARH 0x81 10213 #define DARB 0x82 10214 #define BAR 0x80 10215 #define BARL 0x80 10216 #define BARH 0x81 10217 #define BARB 0x82 10218 #define SAR 0x84 10219 #define SARL 0x84 10220 #define SARH 0x85 10221 #define SARB 0x86 10222 #define CPB 0x86 10223 #define CDA 0x88 10224 #define CDAL 0x88 10225 #define CDAH 0x89 10226 #define EDA 0x8a 10227 #define EDAL 0x8a 10228 #define EDAH 0x8b 10229 #define BFL 0x8c 10230 #define BFLL 0x8c 10231 #define BFLH 0x8d 10232 #define BCR 0x8e 10233 #define BCRL 0x8e 10234 #define BCRH 0x8f 10235 #define DSR 0x90 10236 #define DMR 0x91 10237 #define FCT 0x93 10238 #define DIR 0x94 10239 #define DCMD 0x95 10240 #define TIMER0 0x00 10241 #define TIMER1 0x08 10242 #define TIMER2 0x10 10243 #define TIMER3 0x18 10244 #define RXDMA 0x00 10245 #define TXDMA 0x20 10246 #define NOOP 0x00 10247 #define TXRESET 0x01 10248 #define TXENABLE 0x02 10249 #define TXDISABLE 0x03 10250 #define TXCRCINIT 0x04 10251 #define TXCRCEXCL 0x05 10252 #define TXEOM 0x06 10253 #define TXABORT 0x07 10254 #define MPON 0x08 10255 #define TXBUFCLR 0x09 10256 #define RXRESET 0x11 10257 #define RXENABLE 0x12 10258 #define RXDISABLE 0x13 10259 #define RXCRCINIT 0x14 10260 #define RXREJECT 0x15 10261 #define SEARCHMP 0x16 10262 #define RXCRCEXCL 0x17 10263 #define RXCRCCALC 0x18 10264 #define CHRESET 0x21 10265 #define HUNT 0x31 10266 #define SWABORT 0x01 10267 #define FEICLEAR 0x02 10268 #define TXINTE BIT7 10269 #define RXINTE BIT6 10270 #define TXRDYE BIT1 10271 #define RXRDYE BIT0 10272 #define UDRN BIT7 10273 #define IDLE BIT6 10274 #define SYNCD BIT4 10275 #define FLGD BIT4 10276 #define CCTS BIT3 10277 #define CDCD BIT2 10278 #define BRKD BIT1 10279 #define ABTD BIT1 10280 #define GAPD BIT1 10281 #define BRKE BIT0 10282 #define IDLD BIT0 10283 #define EOM BIT7 10284 #define PMP BIT6 10285 #define SHRT BIT6 10286 #define PE BIT5 10287 #define ABT BIT5 10288 #define FRME BIT4 10289 #define RBIT BIT4 10290 #define OVRN BIT3 10291 #define CRCE BIT2 10292 #define WAKEUP_CHARS 256 10293 #if SYNCLINK_GENERIC_HDLC 10294 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10295 #endif 10296 #ifdef SANITY_CHECK 10297 #else 10298 #endif 10299 /* LDV_COMMENT_END_PREP */ 10300 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "send_xchar" */ 10301 char var_send_xchar_10_p1; 10302 /* LDV_COMMENT_BEGIN_PREP */ 10303 #if SYNCLINK_GENERIC_HDLC 10304 #endif 10305 #if SYNCLINK_GENERIC_HDLC 10306 #endif 10307 #if SYNCLINK_GENERIC_HDLC 10308 #endif 10309 #ifdef CMSPAR 10310 #endif 10311 #if SYNCLINK_GENERIC_HDLC 10312 #endif 10313 #if SYNCLINK_GENERIC_HDLC 10314 #endif 10315 #if 0 10316 #endif 10317 #if SYNCLINK_GENERIC_HDLC 10318 #endif 10319 #if SYNCLINK_GENERIC_HDLC 10320 #endif 10321 #define TESTFRAMESIZE 20 10322 #if SYNCLINK_GENERIC_HDLC 10323 #endif 10324 #define CALC_REGADDR() \ 10325 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10326 if (info->port_num > 1) \ 10327 RegAddr += 256; \ 10328 if ( info->port_num & 1) { \ 10329 if (Addr > 0x7f) \ 10330 RegAddr += 0x40; \ 10331 else if (Addr > 0x1f && Addr < 0x60) \ 10332 RegAddr += 0x20; \ 10333 } 10334 /* LDV_COMMENT_END_PREP */ 10335 /* content: static int set_break(struct tty_struct *tty, int break_state)*/ 10336 /* LDV_COMMENT_BEGIN_PREP */ 10337 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10338 #if defined(__i386__) 10339 # define BREAKPOINT() asm(" int $3"); 10340 #else 10341 # define BREAKPOINT() { } 10342 #endif 10343 #define MAX_DEVICES 12 10344 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10345 #define SYNCLINK_GENERIC_HDLC 1 10346 #else 10347 #define SYNCLINK_GENERIC_HDLC 0 10348 #endif 10349 #define GET_USER(error,value,addr) error = get_user(value,addr) 10350 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10351 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10352 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10353 #define SCABUFSIZE 1024 10354 #define SCA_MEM_SIZE 0x40000 10355 #define SCA_BASE_SIZE 512 10356 #define SCA_REG_SIZE 16 10357 #define SCA_MAX_PORTS 4 10358 #define SCAMAXDESC 128 10359 #define BUFFERLISTSIZE 4096 10360 #define BH_RECEIVE 1 10361 #define BH_TRANSMIT 2 10362 #define BH_STATUS 4 10363 #define IO_PIN_SHUTDOWN_LIMIT 100 10364 #if SYNCLINK_GENERIC_HDLC 10365 #endif 10366 #define MGSL_MAGIC 0x5401 10367 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 10368 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 10369 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 10370 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 10371 #define LPR 0x00 10372 #define PABR0 0x02 10373 #define PABR1 0x03 10374 #define WCRL 0x04 10375 #define WCRM 0x05 10376 #define WCRH 0x06 10377 #define DPCR 0x08 10378 #define DMER 0x09 10379 #define ISR0 0x10 10380 #define ISR1 0x11 10381 #define ISR2 0x12 10382 #define IER0 0x14 10383 #define IER1 0x15 10384 #define IER2 0x16 10385 #define ITCR 0x18 10386 #define INTVR 0x1a 10387 #define IMVR 0x1c 10388 #define TRB 0x20 10389 #define TRBL 0x20 10390 #define TRBH 0x21 10391 #define SR0 0x22 10392 #define SR1 0x23 10393 #define SR2 0x24 10394 #define SR3 0x25 10395 #define FST 0x26 10396 #define IE0 0x28 10397 #define IE1 0x29 10398 #define IE2 0x2a 10399 #define FIE 0x2b 10400 #define CMD 0x2c 10401 #define MD0 0x2e 10402 #define MD1 0x2f 10403 #define MD2 0x30 10404 #define CTL 0x31 10405 #define SA0 0x32 10406 #define SA1 0x33 10407 #define IDL 0x34 10408 #define TMC 0x35 10409 #define RXS 0x36 10410 #define TXS 0x37 10411 #define TRC0 0x38 10412 #define TRC1 0x39 10413 #define RRC 0x3a 10414 #define CST0 0x3c 10415 #define CST1 0x3d 10416 #define TCNT 0x60 10417 #define TCNTL 0x60 10418 #define TCNTH 0x61 10419 #define TCONR 0x62 10420 #define TCONRL 0x62 10421 #define TCONRH 0x63 10422 #define TMCS 0x64 10423 #define TEPR 0x65 10424 #define DARL 0x80 10425 #define DARH 0x81 10426 #define DARB 0x82 10427 #define BAR 0x80 10428 #define BARL 0x80 10429 #define BARH 0x81 10430 #define BARB 0x82 10431 #define SAR 0x84 10432 #define SARL 0x84 10433 #define SARH 0x85 10434 #define SARB 0x86 10435 #define CPB 0x86 10436 #define CDA 0x88 10437 #define CDAL 0x88 10438 #define CDAH 0x89 10439 #define EDA 0x8a 10440 #define EDAL 0x8a 10441 #define EDAH 0x8b 10442 #define BFL 0x8c 10443 #define BFLL 0x8c 10444 #define BFLH 0x8d 10445 #define BCR 0x8e 10446 #define BCRL 0x8e 10447 #define BCRH 0x8f 10448 #define DSR 0x90 10449 #define DMR 0x91 10450 #define FCT 0x93 10451 #define DIR 0x94 10452 #define DCMD 0x95 10453 #define TIMER0 0x00 10454 #define TIMER1 0x08 10455 #define TIMER2 0x10 10456 #define TIMER3 0x18 10457 #define RXDMA 0x00 10458 #define TXDMA 0x20 10459 #define NOOP 0x00 10460 #define TXRESET 0x01 10461 #define TXENABLE 0x02 10462 #define TXDISABLE 0x03 10463 #define TXCRCINIT 0x04 10464 #define TXCRCEXCL 0x05 10465 #define TXEOM 0x06 10466 #define TXABORT 0x07 10467 #define MPON 0x08 10468 #define TXBUFCLR 0x09 10469 #define RXRESET 0x11 10470 #define RXENABLE 0x12 10471 #define RXDISABLE 0x13 10472 #define RXCRCINIT 0x14 10473 #define RXREJECT 0x15 10474 #define SEARCHMP 0x16 10475 #define RXCRCEXCL 0x17 10476 #define RXCRCCALC 0x18 10477 #define CHRESET 0x21 10478 #define HUNT 0x31 10479 #define SWABORT 0x01 10480 #define FEICLEAR 0x02 10481 #define TXINTE BIT7 10482 #define RXINTE BIT6 10483 #define TXRDYE BIT1 10484 #define RXRDYE BIT0 10485 #define UDRN BIT7 10486 #define IDLE BIT6 10487 #define SYNCD BIT4 10488 #define FLGD BIT4 10489 #define CCTS BIT3 10490 #define CDCD BIT2 10491 #define BRKD BIT1 10492 #define ABTD BIT1 10493 #define GAPD BIT1 10494 #define BRKE BIT0 10495 #define IDLD BIT0 10496 #define EOM BIT7 10497 #define PMP BIT6 10498 #define SHRT BIT6 10499 #define PE BIT5 10500 #define ABT BIT5 10501 #define FRME BIT4 10502 #define RBIT BIT4 10503 #define OVRN BIT3 10504 #define CRCE BIT2 10505 #define WAKEUP_CHARS 256 10506 #if SYNCLINK_GENERIC_HDLC 10507 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10508 #endif 10509 #ifdef SANITY_CHECK 10510 #else 10511 #endif 10512 /* LDV_COMMENT_END_PREP */ 10513 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "set_break" */ 10514 int var_set_break_25_p1; 10515 /* LDV_COMMENT_BEGIN_PREP */ 10516 #if SYNCLINK_GENERIC_HDLC 10517 #endif 10518 #if SYNCLINK_GENERIC_HDLC 10519 #endif 10520 #if SYNCLINK_GENERIC_HDLC 10521 #endif 10522 #ifdef CMSPAR 10523 #endif 10524 #if SYNCLINK_GENERIC_HDLC 10525 #endif 10526 #if SYNCLINK_GENERIC_HDLC 10527 #endif 10528 #if 0 10529 #endif 10530 #if SYNCLINK_GENERIC_HDLC 10531 #endif 10532 #if SYNCLINK_GENERIC_HDLC 10533 #endif 10534 #define TESTFRAMESIZE 20 10535 #if SYNCLINK_GENERIC_HDLC 10536 #endif 10537 #define CALC_REGADDR() \ 10538 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10539 if (info->port_num > 1) \ 10540 RegAddr += 256; \ 10541 if ( info->port_num & 1) { \ 10542 if (Addr > 0x7f) \ 10543 RegAddr += 0x40; \ 10544 else if (Addr > 0x1f && Addr < 0x60) \ 10545 RegAddr += 0x20; \ 10546 } 10547 /* LDV_COMMENT_END_PREP */ 10548 /* content: static void wait_until_sent(struct tty_struct *tty, int timeout)*/ 10549 /* LDV_COMMENT_BEGIN_PREP */ 10550 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10551 #if defined(__i386__) 10552 # define BREAKPOINT() asm(" int $3"); 10553 #else 10554 # define BREAKPOINT() { } 10555 #endif 10556 #define MAX_DEVICES 12 10557 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10558 #define SYNCLINK_GENERIC_HDLC 1 10559 #else 10560 #define SYNCLINK_GENERIC_HDLC 0 10561 #endif 10562 #define GET_USER(error,value,addr) error = get_user(value,addr) 10563 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10564 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10565 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10566 #define SCABUFSIZE 1024 10567 #define SCA_MEM_SIZE 0x40000 10568 #define SCA_BASE_SIZE 512 10569 #define SCA_REG_SIZE 16 10570 #define SCA_MAX_PORTS 4 10571 #define SCAMAXDESC 128 10572 #define BUFFERLISTSIZE 4096 10573 #define BH_RECEIVE 1 10574 #define BH_TRANSMIT 2 10575 #define BH_STATUS 4 10576 #define IO_PIN_SHUTDOWN_LIMIT 100 10577 #if SYNCLINK_GENERIC_HDLC 10578 #endif 10579 #define MGSL_MAGIC 0x5401 10580 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 10581 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 10582 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 10583 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 10584 #define LPR 0x00 10585 #define PABR0 0x02 10586 #define PABR1 0x03 10587 #define WCRL 0x04 10588 #define WCRM 0x05 10589 #define WCRH 0x06 10590 #define DPCR 0x08 10591 #define DMER 0x09 10592 #define ISR0 0x10 10593 #define ISR1 0x11 10594 #define ISR2 0x12 10595 #define IER0 0x14 10596 #define IER1 0x15 10597 #define IER2 0x16 10598 #define ITCR 0x18 10599 #define INTVR 0x1a 10600 #define IMVR 0x1c 10601 #define TRB 0x20 10602 #define TRBL 0x20 10603 #define TRBH 0x21 10604 #define SR0 0x22 10605 #define SR1 0x23 10606 #define SR2 0x24 10607 #define SR3 0x25 10608 #define FST 0x26 10609 #define IE0 0x28 10610 #define IE1 0x29 10611 #define IE2 0x2a 10612 #define FIE 0x2b 10613 #define CMD 0x2c 10614 #define MD0 0x2e 10615 #define MD1 0x2f 10616 #define MD2 0x30 10617 #define CTL 0x31 10618 #define SA0 0x32 10619 #define SA1 0x33 10620 #define IDL 0x34 10621 #define TMC 0x35 10622 #define RXS 0x36 10623 #define TXS 0x37 10624 #define TRC0 0x38 10625 #define TRC1 0x39 10626 #define RRC 0x3a 10627 #define CST0 0x3c 10628 #define CST1 0x3d 10629 #define TCNT 0x60 10630 #define TCNTL 0x60 10631 #define TCNTH 0x61 10632 #define TCONR 0x62 10633 #define TCONRL 0x62 10634 #define TCONRH 0x63 10635 #define TMCS 0x64 10636 #define TEPR 0x65 10637 #define DARL 0x80 10638 #define DARH 0x81 10639 #define DARB 0x82 10640 #define BAR 0x80 10641 #define BARL 0x80 10642 #define BARH 0x81 10643 #define BARB 0x82 10644 #define SAR 0x84 10645 #define SARL 0x84 10646 #define SARH 0x85 10647 #define SARB 0x86 10648 #define CPB 0x86 10649 #define CDA 0x88 10650 #define CDAL 0x88 10651 #define CDAH 0x89 10652 #define EDA 0x8a 10653 #define EDAL 0x8a 10654 #define EDAH 0x8b 10655 #define BFL 0x8c 10656 #define BFLL 0x8c 10657 #define BFLH 0x8d 10658 #define BCR 0x8e 10659 #define BCRL 0x8e 10660 #define BCRH 0x8f 10661 #define DSR 0x90 10662 #define DMR 0x91 10663 #define FCT 0x93 10664 #define DIR 0x94 10665 #define DCMD 0x95 10666 #define TIMER0 0x00 10667 #define TIMER1 0x08 10668 #define TIMER2 0x10 10669 #define TIMER3 0x18 10670 #define RXDMA 0x00 10671 #define TXDMA 0x20 10672 #define NOOP 0x00 10673 #define TXRESET 0x01 10674 #define TXENABLE 0x02 10675 #define TXDISABLE 0x03 10676 #define TXCRCINIT 0x04 10677 #define TXCRCEXCL 0x05 10678 #define TXEOM 0x06 10679 #define TXABORT 0x07 10680 #define MPON 0x08 10681 #define TXBUFCLR 0x09 10682 #define RXRESET 0x11 10683 #define RXENABLE 0x12 10684 #define RXDISABLE 0x13 10685 #define RXCRCINIT 0x14 10686 #define RXREJECT 0x15 10687 #define SEARCHMP 0x16 10688 #define RXCRCEXCL 0x17 10689 #define RXCRCCALC 0x18 10690 #define CHRESET 0x21 10691 #define HUNT 0x31 10692 #define SWABORT 0x01 10693 #define FEICLEAR 0x02 10694 #define TXINTE BIT7 10695 #define RXINTE BIT6 10696 #define TXRDYE BIT1 10697 #define RXRDYE BIT0 10698 #define UDRN BIT7 10699 #define IDLE BIT6 10700 #define SYNCD BIT4 10701 #define FLGD BIT4 10702 #define CCTS BIT3 10703 #define CDCD BIT2 10704 #define BRKD BIT1 10705 #define ABTD BIT1 10706 #define GAPD BIT1 10707 #define BRKE BIT0 10708 #define IDLD BIT0 10709 #define EOM BIT7 10710 #define PMP BIT6 10711 #define SHRT BIT6 10712 #define PE BIT5 10713 #define ABT BIT5 10714 #define FRME BIT4 10715 #define RBIT BIT4 10716 #define OVRN BIT3 10717 #define CRCE BIT2 10718 #define WAKEUP_CHARS 256 10719 #if SYNCLINK_GENERIC_HDLC 10720 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10721 #endif 10722 #ifdef SANITY_CHECK 10723 #else 10724 #endif 10725 /* LDV_COMMENT_END_PREP */ 10726 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "wait_until_sent" */ 10727 int var_wait_until_sent_11_p1; 10728 /* LDV_COMMENT_BEGIN_PREP */ 10729 #if SYNCLINK_GENERIC_HDLC 10730 #endif 10731 #if SYNCLINK_GENERIC_HDLC 10732 #endif 10733 #if SYNCLINK_GENERIC_HDLC 10734 #endif 10735 #ifdef CMSPAR 10736 #endif 10737 #if SYNCLINK_GENERIC_HDLC 10738 #endif 10739 #if SYNCLINK_GENERIC_HDLC 10740 #endif 10741 #if 0 10742 #endif 10743 #if SYNCLINK_GENERIC_HDLC 10744 #endif 10745 #if SYNCLINK_GENERIC_HDLC 10746 #endif 10747 #define TESTFRAMESIZE 20 10748 #if SYNCLINK_GENERIC_HDLC 10749 #endif 10750 #define CALC_REGADDR() \ 10751 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10752 if (info->port_num > 1) \ 10753 RegAddr += 256; \ 10754 if ( info->port_num & 1) { \ 10755 if (Addr > 0x7f) \ 10756 RegAddr += 0x40; \ 10757 else if (Addr > 0x1f && Addr < 0x60) \ 10758 RegAddr += 0x20; \ 10759 } 10760 /* LDV_COMMENT_END_PREP */ 10761 /* content: static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)*/ 10762 /* LDV_COMMENT_BEGIN_PREP */ 10763 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10764 #if defined(__i386__) 10765 # define BREAKPOINT() asm(" int $3"); 10766 #else 10767 # define BREAKPOINT() { } 10768 #endif 10769 #define MAX_DEVICES 12 10770 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10771 #define SYNCLINK_GENERIC_HDLC 1 10772 #else 10773 #define SYNCLINK_GENERIC_HDLC 0 10774 #endif 10775 #define GET_USER(error,value,addr) error = get_user(value,addr) 10776 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10777 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10778 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10779 #define SCABUFSIZE 1024 10780 #define SCA_MEM_SIZE 0x40000 10781 #define SCA_BASE_SIZE 512 10782 #define SCA_REG_SIZE 16 10783 #define SCA_MAX_PORTS 4 10784 #define SCAMAXDESC 128 10785 #define BUFFERLISTSIZE 4096 10786 #define BH_RECEIVE 1 10787 #define BH_TRANSMIT 2 10788 #define BH_STATUS 4 10789 #define IO_PIN_SHUTDOWN_LIMIT 100 10790 #if SYNCLINK_GENERIC_HDLC 10791 #endif 10792 #define MGSL_MAGIC 0x5401 10793 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 10794 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 10795 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 10796 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 10797 #define LPR 0x00 10798 #define PABR0 0x02 10799 #define PABR1 0x03 10800 #define WCRL 0x04 10801 #define WCRM 0x05 10802 #define WCRH 0x06 10803 #define DPCR 0x08 10804 #define DMER 0x09 10805 #define ISR0 0x10 10806 #define ISR1 0x11 10807 #define ISR2 0x12 10808 #define IER0 0x14 10809 #define IER1 0x15 10810 #define IER2 0x16 10811 #define ITCR 0x18 10812 #define INTVR 0x1a 10813 #define IMVR 0x1c 10814 #define TRB 0x20 10815 #define TRBL 0x20 10816 #define TRBH 0x21 10817 #define SR0 0x22 10818 #define SR1 0x23 10819 #define SR2 0x24 10820 #define SR3 0x25 10821 #define FST 0x26 10822 #define IE0 0x28 10823 #define IE1 0x29 10824 #define IE2 0x2a 10825 #define FIE 0x2b 10826 #define CMD 0x2c 10827 #define MD0 0x2e 10828 #define MD1 0x2f 10829 #define MD2 0x30 10830 #define CTL 0x31 10831 #define SA0 0x32 10832 #define SA1 0x33 10833 #define IDL 0x34 10834 #define TMC 0x35 10835 #define RXS 0x36 10836 #define TXS 0x37 10837 #define TRC0 0x38 10838 #define TRC1 0x39 10839 #define RRC 0x3a 10840 #define CST0 0x3c 10841 #define CST1 0x3d 10842 #define TCNT 0x60 10843 #define TCNTL 0x60 10844 #define TCNTH 0x61 10845 #define TCONR 0x62 10846 #define TCONRL 0x62 10847 #define TCONRH 0x63 10848 #define TMCS 0x64 10849 #define TEPR 0x65 10850 #define DARL 0x80 10851 #define DARH 0x81 10852 #define DARB 0x82 10853 #define BAR 0x80 10854 #define BARL 0x80 10855 #define BARH 0x81 10856 #define BARB 0x82 10857 #define SAR 0x84 10858 #define SARL 0x84 10859 #define SARH 0x85 10860 #define SARB 0x86 10861 #define CPB 0x86 10862 #define CDA 0x88 10863 #define CDAL 0x88 10864 #define CDAH 0x89 10865 #define EDA 0x8a 10866 #define EDAL 0x8a 10867 #define EDAH 0x8b 10868 #define BFL 0x8c 10869 #define BFLL 0x8c 10870 #define BFLH 0x8d 10871 #define BCR 0x8e 10872 #define BCRL 0x8e 10873 #define BCRH 0x8f 10874 #define DSR 0x90 10875 #define DMR 0x91 10876 #define FCT 0x93 10877 #define DIR 0x94 10878 #define DCMD 0x95 10879 #define TIMER0 0x00 10880 #define TIMER1 0x08 10881 #define TIMER2 0x10 10882 #define TIMER3 0x18 10883 #define RXDMA 0x00 10884 #define TXDMA 0x20 10885 #define NOOP 0x00 10886 #define TXRESET 0x01 10887 #define TXENABLE 0x02 10888 #define TXDISABLE 0x03 10889 #define TXCRCINIT 0x04 10890 #define TXCRCEXCL 0x05 10891 #define TXEOM 0x06 10892 #define TXABORT 0x07 10893 #define MPON 0x08 10894 #define TXBUFCLR 0x09 10895 #define RXRESET 0x11 10896 #define RXENABLE 0x12 10897 #define RXDISABLE 0x13 10898 #define RXCRCINIT 0x14 10899 #define RXREJECT 0x15 10900 #define SEARCHMP 0x16 10901 #define RXCRCEXCL 0x17 10902 #define RXCRCCALC 0x18 10903 #define CHRESET 0x21 10904 #define HUNT 0x31 10905 #define SWABORT 0x01 10906 #define FEICLEAR 0x02 10907 #define TXINTE BIT7 10908 #define RXINTE BIT6 10909 #define TXRDYE BIT1 10910 #define RXRDYE BIT0 10911 #define UDRN BIT7 10912 #define IDLE BIT6 10913 #define SYNCD BIT4 10914 #define FLGD BIT4 10915 #define CCTS BIT3 10916 #define CDCD BIT2 10917 #define BRKD BIT1 10918 #define ABTD BIT1 10919 #define GAPD BIT1 10920 #define BRKE BIT0 10921 #define IDLD BIT0 10922 #define EOM BIT7 10923 #define PMP BIT6 10924 #define SHRT BIT6 10925 #define PE BIT5 10926 #define ABT BIT5 10927 #define FRME BIT4 10928 #define RBIT BIT4 10929 #define OVRN BIT3 10930 #define CRCE BIT2 10931 #define WAKEUP_CHARS 256 10932 #if SYNCLINK_GENERIC_HDLC 10933 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10934 #endif 10935 #ifdef SANITY_CHECK 10936 #else 10937 #endif 10938 /* LDV_COMMENT_END_PREP */ 10939 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "set_termios" */ 10940 struct ktermios * var_group9; 10941 /* LDV_COMMENT_BEGIN_PREP */ 10942 #if SYNCLINK_GENERIC_HDLC 10943 #endif 10944 #if SYNCLINK_GENERIC_HDLC 10945 #endif 10946 #if SYNCLINK_GENERIC_HDLC 10947 #endif 10948 #ifdef CMSPAR 10949 #endif 10950 #if SYNCLINK_GENERIC_HDLC 10951 #endif 10952 #if SYNCLINK_GENERIC_HDLC 10953 #endif 10954 #if 0 10955 #endif 10956 #if SYNCLINK_GENERIC_HDLC 10957 #endif 10958 #if SYNCLINK_GENERIC_HDLC 10959 #endif 10960 #define TESTFRAMESIZE 20 10961 #if SYNCLINK_GENERIC_HDLC 10962 #endif 10963 #define CALC_REGADDR() \ 10964 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10965 if (info->port_num > 1) \ 10966 RegAddr += 256; \ 10967 if ( info->port_num & 1) { \ 10968 if (Addr > 0x7f) \ 10969 RegAddr += 0x40; \ 10970 else if (Addr > 0x1f && Addr < 0x60) \ 10971 RegAddr += 0x20; \ 10972 } 10973 /* LDV_COMMENT_END_PREP */ 10974 /* content: static void tx_hold(struct tty_struct *tty)*/ 10975 /* LDV_COMMENT_BEGIN_PREP */ 10976 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10977 #if defined(__i386__) 10978 # define BREAKPOINT() asm(" int $3"); 10979 #else 10980 # define BREAKPOINT() { } 10981 #endif 10982 #define MAX_DEVICES 12 10983 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10984 #define SYNCLINK_GENERIC_HDLC 1 10985 #else 10986 #define SYNCLINK_GENERIC_HDLC 0 10987 #endif 10988 #define GET_USER(error,value,addr) error = get_user(value,addr) 10989 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10990 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10991 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10992 #define SCABUFSIZE 1024 10993 #define SCA_MEM_SIZE 0x40000 10994 #define SCA_BASE_SIZE 512 10995 #define SCA_REG_SIZE 16 10996 #define SCA_MAX_PORTS 4 10997 #define SCAMAXDESC 128 10998 #define BUFFERLISTSIZE 4096 10999 #define BH_RECEIVE 1 11000 #define BH_TRANSMIT 2 11001 #define BH_STATUS 4 11002 #define IO_PIN_SHUTDOWN_LIMIT 100 11003 #if SYNCLINK_GENERIC_HDLC 11004 #endif 11005 #define MGSL_MAGIC 0x5401 11006 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11007 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11008 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11009 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11010 #define LPR 0x00 11011 #define PABR0 0x02 11012 #define PABR1 0x03 11013 #define WCRL 0x04 11014 #define WCRM 0x05 11015 #define WCRH 0x06 11016 #define DPCR 0x08 11017 #define DMER 0x09 11018 #define ISR0 0x10 11019 #define ISR1 0x11 11020 #define ISR2 0x12 11021 #define IER0 0x14 11022 #define IER1 0x15 11023 #define IER2 0x16 11024 #define ITCR 0x18 11025 #define INTVR 0x1a 11026 #define IMVR 0x1c 11027 #define TRB 0x20 11028 #define TRBL 0x20 11029 #define TRBH 0x21 11030 #define SR0 0x22 11031 #define SR1 0x23 11032 #define SR2 0x24 11033 #define SR3 0x25 11034 #define FST 0x26 11035 #define IE0 0x28 11036 #define IE1 0x29 11037 #define IE2 0x2a 11038 #define FIE 0x2b 11039 #define CMD 0x2c 11040 #define MD0 0x2e 11041 #define MD1 0x2f 11042 #define MD2 0x30 11043 #define CTL 0x31 11044 #define SA0 0x32 11045 #define SA1 0x33 11046 #define IDL 0x34 11047 #define TMC 0x35 11048 #define RXS 0x36 11049 #define TXS 0x37 11050 #define TRC0 0x38 11051 #define TRC1 0x39 11052 #define RRC 0x3a 11053 #define CST0 0x3c 11054 #define CST1 0x3d 11055 #define TCNT 0x60 11056 #define TCNTL 0x60 11057 #define TCNTH 0x61 11058 #define TCONR 0x62 11059 #define TCONRL 0x62 11060 #define TCONRH 0x63 11061 #define TMCS 0x64 11062 #define TEPR 0x65 11063 #define DARL 0x80 11064 #define DARH 0x81 11065 #define DARB 0x82 11066 #define BAR 0x80 11067 #define BARL 0x80 11068 #define BARH 0x81 11069 #define BARB 0x82 11070 #define SAR 0x84 11071 #define SARL 0x84 11072 #define SARH 0x85 11073 #define SARB 0x86 11074 #define CPB 0x86 11075 #define CDA 0x88 11076 #define CDAL 0x88 11077 #define CDAH 0x89 11078 #define EDA 0x8a 11079 #define EDAL 0x8a 11080 #define EDAH 0x8b 11081 #define BFL 0x8c 11082 #define BFLL 0x8c 11083 #define BFLH 0x8d 11084 #define BCR 0x8e 11085 #define BCRL 0x8e 11086 #define BCRH 0x8f 11087 #define DSR 0x90 11088 #define DMR 0x91 11089 #define FCT 0x93 11090 #define DIR 0x94 11091 #define DCMD 0x95 11092 #define TIMER0 0x00 11093 #define TIMER1 0x08 11094 #define TIMER2 0x10 11095 #define TIMER3 0x18 11096 #define RXDMA 0x00 11097 #define TXDMA 0x20 11098 #define NOOP 0x00 11099 #define TXRESET 0x01 11100 #define TXENABLE 0x02 11101 #define TXDISABLE 0x03 11102 #define TXCRCINIT 0x04 11103 #define TXCRCEXCL 0x05 11104 #define TXEOM 0x06 11105 #define TXABORT 0x07 11106 #define MPON 0x08 11107 #define TXBUFCLR 0x09 11108 #define RXRESET 0x11 11109 #define RXENABLE 0x12 11110 #define RXDISABLE 0x13 11111 #define RXCRCINIT 0x14 11112 #define RXREJECT 0x15 11113 #define SEARCHMP 0x16 11114 #define RXCRCEXCL 0x17 11115 #define RXCRCCALC 0x18 11116 #define CHRESET 0x21 11117 #define HUNT 0x31 11118 #define SWABORT 0x01 11119 #define FEICLEAR 0x02 11120 #define TXINTE BIT7 11121 #define RXINTE BIT6 11122 #define TXRDYE BIT1 11123 #define RXRDYE BIT0 11124 #define UDRN BIT7 11125 #define IDLE BIT6 11126 #define SYNCD BIT4 11127 #define FLGD BIT4 11128 #define CCTS BIT3 11129 #define CDCD BIT2 11130 #define BRKD BIT1 11131 #define ABTD BIT1 11132 #define GAPD BIT1 11133 #define BRKE BIT0 11134 #define IDLD BIT0 11135 #define EOM BIT7 11136 #define PMP BIT6 11137 #define SHRT BIT6 11138 #define PE BIT5 11139 #define ABT BIT5 11140 #define FRME BIT4 11141 #define RBIT BIT4 11142 #define OVRN BIT3 11143 #define CRCE BIT2 11144 #define WAKEUP_CHARS 256 11145 #if SYNCLINK_GENERIC_HDLC 11146 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11147 #endif 11148 #ifdef SANITY_CHECK 11149 #else 11150 #endif 11151 /* LDV_COMMENT_END_PREP */ 11152 /* LDV_COMMENT_BEGIN_PREP */ 11153 #if SYNCLINK_GENERIC_HDLC 11154 #endif 11155 #if SYNCLINK_GENERIC_HDLC 11156 #endif 11157 #if SYNCLINK_GENERIC_HDLC 11158 #endif 11159 #ifdef CMSPAR 11160 #endif 11161 #if SYNCLINK_GENERIC_HDLC 11162 #endif 11163 #if SYNCLINK_GENERIC_HDLC 11164 #endif 11165 #if 0 11166 #endif 11167 #if SYNCLINK_GENERIC_HDLC 11168 #endif 11169 #if SYNCLINK_GENERIC_HDLC 11170 #endif 11171 #define TESTFRAMESIZE 20 11172 #if SYNCLINK_GENERIC_HDLC 11173 #endif 11174 #define CALC_REGADDR() \ 11175 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 11176 if (info->port_num > 1) \ 11177 RegAddr += 256; \ 11178 if ( info->port_num & 1) { \ 11179 if (Addr > 0x7f) \ 11180 RegAddr += 0x40; \ 11181 else if (Addr > 0x1f && Addr < 0x60) \ 11182 RegAddr += 0x20; \ 11183 } 11184 /* LDV_COMMENT_END_PREP */ 11185 /* content: static void tx_release(struct tty_struct *tty)*/ 11186 /* LDV_COMMENT_BEGIN_PREP */ 11187 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 11188 #if defined(__i386__) 11189 # define BREAKPOINT() asm(" int $3"); 11190 #else 11191 # define BREAKPOINT() { } 11192 #endif 11193 #define MAX_DEVICES 12 11194 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 11195 #define SYNCLINK_GENERIC_HDLC 1 11196 #else 11197 #define SYNCLINK_GENERIC_HDLC 0 11198 #endif 11199 #define GET_USER(error,value,addr) error = get_user(value,addr) 11200 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11201 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11202 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11203 #define SCABUFSIZE 1024 11204 #define SCA_MEM_SIZE 0x40000 11205 #define SCA_BASE_SIZE 512 11206 #define SCA_REG_SIZE 16 11207 #define SCA_MAX_PORTS 4 11208 #define SCAMAXDESC 128 11209 #define BUFFERLISTSIZE 4096 11210 #define BH_RECEIVE 1 11211 #define BH_TRANSMIT 2 11212 #define BH_STATUS 4 11213 #define IO_PIN_SHUTDOWN_LIMIT 100 11214 #if SYNCLINK_GENERIC_HDLC 11215 #endif 11216 #define MGSL_MAGIC 0x5401 11217 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11218 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11219 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11220 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11221 #define LPR 0x00 11222 #define PABR0 0x02 11223 #define PABR1 0x03 11224 #define WCRL 0x04 11225 #define WCRM 0x05 11226 #define WCRH 0x06 11227 #define DPCR 0x08 11228 #define DMER 0x09 11229 #define ISR0 0x10 11230 #define ISR1 0x11 11231 #define ISR2 0x12 11232 #define IER0 0x14 11233 #define IER1 0x15 11234 #define IER2 0x16 11235 #define ITCR 0x18 11236 #define INTVR 0x1a 11237 #define IMVR 0x1c 11238 #define TRB 0x20 11239 #define TRBL 0x20 11240 #define TRBH 0x21 11241 #define SR0 0x22 11242 #define SR1 0x23 11243 #define SR2 0x24 11244 #define SR3 0x25 11245 #define FST 0x26 11246 #define IE0 0x28 11247 #define IE1 0x29 11248 #define IE2 0x2a 11249 #define FIE 0x2b 11250 #define CMD 0x2c 11251 #define MD0 0x2e 11252 #define MD1 0x2f 11253 #define MD2 0x30 11254 #define CTL 0x31 11255 #define SA0 0x32 11256 #define SA1 0x33 11257 #define IDL 0x34 11258 #define TMC 0x35 11259 #define RXS 0x36 11260 #define TXS 0x37 11261 #define TRC0 0x38 11262 #define TRC1 0x39 11263 #define RRC 0x3a 11264 #define CST0 0x3c 11265 #define CST1 0x3d 11266 #define TCNT 0x60 11267 #define TCNTL 0x60 11268 #define TCNTH 0x61 11269 #define TCONR 0x62 11270 #define TCONRL 0x62 11271 #define TCONRH 0x63 11272 #define TMCS 0x64 11273 #define TEPR 0x65 11274 #define DARL 0x80 11275 #define DARH 0x81 11276 #define DARB 0x82 11277 #define BAR 0x80 11278 #define BARL 0x80 11279 #define BARH 0x81 11280 #define BARB 0x82 11281 #define SAR 0x84 11282 #define SARL 0x84 11283 #define SARH 0x85 11284 #define SARB 0x86 11285 #define CPB 0x86 11286 #define CDA 0x88 11287 #define CDAL 0x88 11288 #define CDAH 0x89 11289 #define EDA 0x8a 11290 #define EDAL 0x8a 11291 #define EDAH 0x8b 11292 #define BFL 0x8c 11293 #define BFLL 0x8c 11294 #define BFLH 0x8d 11295 #define BCR 0x8e 11296 #define BCRL 0x8e 11297 #define BCRH 0x8f 11298 #define DSR 0x90 11299 #define DMR 0x91 11300 #define FCT 0x93 11301 #define DIR 0x94 11302 #define DCMD 0x95 11303 #define TIMER0 0x00 11304 #define TIMER1 0x08 11305 #define TIMER2 0x10 11306 #define TIMER3 0x18 11307 #define RXDMA 0x00 11308 #define TXDMA 0x20 11309 #define NOOP 0x00 11310 #define TXRESET 0x01 11311 #define TXENABLE 0x02 11312 #define TXDISABLE 0x03 11313 #define TXCRCINIT 0x04 11314 #define TXCRCEXCL 0x05 11315 #define TXEOM 0x06 11316 #define TXABORT 0x07 11317 #define MPON 0x08 11318 #define TXBUFCLR 0x09 11319 #define RXRESET 0x11 11320 #define RXENABLE 0x12 11321 #define RXDISABLE 0x13 11322 #define RXCRCINIT 0x14 11323 #define RXREJECT 0x15 11324 #define SEARCHMP 0x16 11325 #define RXCRCEXCL 0x17 11326 #define RXCRCCALC 0x18 11327 #define CHRESET 0x21 11328 #define HUNT 0x31 11329 #define SWABORT 0x01 11330 #define FEICLEAR 0x02 11331 #define TXINTE BIT7 11332 #define RXINTE BIT6 11333 #define TXRDYE BIT1 11334 #define RXRDYE BIT0 11335 #define UDRN BIT7 11336 #define IDLE BIT6 11337 #define SYNCD BIT4 11338 #define FLGD BIT4 11339 #define CCTS BIT3 11340 #define CDCD BIT2 11341 #define BRKD BIT1 11342 #define ABTD BIT1 11343 #define GAPD BIT1 11344 #define BRKE BIT0 11345 #define IDLD BIT0 11346 #define EOM BIT7 11347 #define PMP BIT6 11348 #define SHRT BIT6 11349 #define PE BIT5 11350 #define ABT BIT5 11351 #define FRME BIT4 11352 #define RBIT BIT4 11353 #define OVRN BIT3 11354 #define CRCE BIT2 11355 #define WAKEUP_CHARS 256 11356 #if SYNCLINK_GENERIC_HDLC 11357 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11358 #endif 11359 #ifdef SANITY_CHECK 11360 #else 11361 #endif 11362 /* LDV_COMMENT_END_PREP */ 11363 /* LDV_COMMENT_BEGIN_PREP */ 11364 #if SYNCLINK_GENERIC_HDLC 11365 #endif 11366 #if SYNCLINK_GENERIC_HDLC 11367 #endif 11368 #if SYNCLINK_GENERIC_HDLC 11369 #endif 11370 #ifdef CMSPAR 11371 #endif 11372 #if SYNCLINK_GENERIC_HDLC 11373 #endif 11374 #if SYNCLINK_GENERIC_HDLC 11375 #endif 11376 #if 0 11377 #endif 11378 #if SYNCLINK_GENERIC_HDLC 11379 #endif 11380 #if SYNCLINK_GENERIC_HDLC 11381 #endif 11382 #define TESTFRAMESIZE 20 11383 #if SYNCLINK_GENERIC_HDLC 11384 #endif 11385 #define CALC_REGADDR() \ 11386 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 11387 if (info->port_num > 1) \ 11388 RegAddr += 256; \ 11389 if ( info->port_num & 1) { \ 11390 if (Addr > 0x7f) \ 11391 RegAddr += 0x40; \ 11392 else if (Addr > 0x1f && Addr < 0x60) \ 11393 RegAddr += 0x20; \ 11394 } 11395 /* LDV_COMMENT_END_PREP */ 11396 /* content: static void hangup(struct tty_struct *tty)*/ 11397 /* LDV_COMMENT_BEGIN_PREP */ 11398 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 11399 #if defined(__i386__) 11400 # define BREAKPOINT() asm(" int $3"); 11401 #else 11402 # define BREAKPOINT() { } 11403 #endif 11404 #define MAX_DEVICES 12 11405 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 11406 #define SYNCLINK_GENERIC_HDLC 1 11407 #else 11408 #define SYNCLINK_GENERIC_HDLC 0 11409 #endif 11410 #define GET_USER(error,value,addr) error = get_user(value,addr) 11411 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11412 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11413 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11414 #define SCABUFSIZE 1024 11415 #define SCA_MEM_SIZE 0x40000 11416 #define SCA_BASE_SIZE 512 11417 #define SCA_REG_SIZE 16 11418 #define SCA_MAX_PORTS 4 11419 #define SCAMAXDESC 128 11420 #define BUFFERLISTSIZE 4096 11421 #define BH_RECEIVE 1 11422 #define BH_TRANSMIT 2 11423 #define BH_STATUS 4 11424 #define IO_PIN_SHUTDOWN_LIMIT 100 11425 #if SYNCLINK_GENERIC_HDLC 11426 #endif 11427 #define MGSL_MAGIC 0x5401 11428 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11429 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11430 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11431 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11432 #define LPR 0x00 11433 #define PABR0 0x02 11434 #define PABR1 0x03 11435 #define WCRL 0x04 11436 #define WCRM 0x05 11437 #define WCRH 0x06 11438 #define DPCR 0x08 11439 #define DMER 0x09 11440 #define ISR0 0x10 11441 #define ISR1 0x11 11442 #define ISR2 0x12 11443 #define IER0 0x14 11444 #define IER1 0x15 11445 #define IER2 0x16 11446 #define ITCR 0x18 11447 #define INTVR 0x1a 11448 #define IMVR 0x1c 11449 #define TRB 0x20 11450 #define TRBL 0x20 11451 #define TRBH 0x21 11452 #define SR0 0x22 11453 #define SR1 0x23 11454 #define SR2 0x24 11455 #define SR3 0x25 11456 #define FST 0x26 11457 #define IE0 0x28 11458 #define IE1 0x29 11459 #define IE2 0x2a 11460 #define FIE 0x2b 11461 #define CMD 0x2c 11462 #define MD0 0x2e 11463 #define MD1 0x2f 11464 #define MD2 0x30 11465 #define CTL 0x31 11466 #define SA0 0x32 11467 #define SA1 0x33 11468 #define IDL 0x34 11469 #define TMC 0x35 11470 #define RXS 0x36 11471 #define TXS 0x37 11472 #define TRC0 0x38 11473 #define TRC1 0x39 11474 #define RRC 0x3a 11475 #define CST0 0x3c 11476 #define CST1 0x3d 11477 #define TCNT 0x60 11478 #define TCNTL 0x60 11479 #define TCNTH 0x61 11480 #define TCONR 0x62 11481 #define TCONRL 0x62 11482 #define TCONRH 0x63 11483 #define TMCS 0x64 11484 #define TEPR 0x65 11485 #define DARL 0x80 11486 #define DARH 0x81 11487 #define DARB 0x82 11488 #define BAR 0x80 11489 #define BARL 0x80 11490 #define BARH 0x81 11491 #define BARB 0x82 11492 #define SAR 0x84 11493 #define SARL 0x84 11494 #define SARH 0x85 11495 #define SARB 0x86 11496 #define CPB 0x86 11497 #define CDA 0x88 11498 #define CDAL 0x88 11499 #define CDAH 0x89 11500 #define EDA 0x8a 11501 #define EDAL 0x8a 11502 #define EDAH 0x8b 11503 #define BFL 0x8c 11504 #define BFLL 0x8c 11505 #define BFLH 0x8d 11506 #define BCR 0x8e 11507 #define BCRL 0x8e 11508 #define BCRH 0x8f 11509 #define DSR 0x90 11510 #define DMR 0x91 11511 #define FCT 0x93 11512 #define DIR 0x94 11513 #define DCMD 0x95 11514 #define TIMER0 0x00 11515 #define TIMER1 0x08 11516 #define TIMER2 0x10 11517 #define TIMER3 0x18 11518 #define RXDMA 0x00 11519 #define TXDMA 0x20 11520 #define NOOP 0x00 11521 #define TXRESET 0x01 11522 #define TXENABLE 0x02 11523 #define TXDISABLE 0x03 11524 #define TXCRCINIT 0x04 11525 #define TXCRCEXCL 0x05 11526 #define TXEOM 0x06 11527 #define TXABORT 0x07 11528 #define MPON 0x08 11529 #define TXBUFCLR 0x09 11530 #define RXRESET 0x11 11531 #define RXENABLE 0x12 11532 #define RXDISABLE 0x13 11533 #define RXCRCINIT 0x14 11534 #define RXREJECT 0x15 11535 #define SEARCHMP 0x16 11536 #define RXCRCEXCL 0x17 11537 #define RXCRCCALC 0x18 11538 #define CHRESET 0x21 11539 #define HUNT 0x31 11540 #define SWABORT 0x01 11541 #define FEICLEAR 0x02 11542 #define TXINTE BIT7 11543 #define RXINTE BIT6 11544 #define TXRDYE BIT1 11545 #define RXRDYE BIT0 11546 #define UDRN BIT7 11547 #define IDLE BIT6 11548 #define SYNCD BIT4 11549 #define FLGD BIT4 11550 #define CCTS BIT3 11551 #define CDCD BIT2 11552 #define BRKD BIT1 11553 #define ABTD BIT1 11554 #define GAPD BIT1 11555 #define BRKE BIT0 11556 #define IDLD BIT0 11557 #define EOM BIT7 11558 #define PMP BIT6 11559 #define SHRT BIT6 11560 #define PE BIT5 11561 #define ABT BIT5 11562 #define FRME BIT4 11563 #define RBIT BIT4 11564 #define OVRN BIT3 11565 #define CRCE BIT2 11566 #define WAKEUP_CHARS 256 11567 #if SYNCLINK_GENERIC_HDLC 11568 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11569 #endif 11570 #ifdef SANITY_CHECK 11571 #else 11572 #endif 11573 /* LDV_COMMENT_END_PREP */ 11574 /* LDV_COMMENT_BEGIN_PREP */ 11575 #if SYNCLINK_GENERIC_HDLC 11576 #endif 11577 #if SYNCLINK_GENERIC_HDLC 11578 #endif 11579 #if SYNCLINK_GENERIC_HDLC 11580 #endif 11581 #ifdef CMSPAR 11582 #endif 11583 #if SYNCLINK_GENERIC_HDLC 11584 #endif 11585 #if SYNCLINK_GENERIC_HDLC 11586 #endif 11587 #if 0 11588 #endif 11589 #if SYNCLINK_GENERIC_HDLC 11590 #endif 11591 #if SYNCLINK_GENERIC_HDLC 11592 #endif 11593 #define TESTFRAMESIZE 20 11594 #if SYNCLINK_GENERIC_HDLC 11595 #endif 11596 #define CALC_REGADDR() \ 11597 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 11598 if (info->port_num > 1) \ 11599 RegAddr += 256; \ 11600 if ( info->port_num & 1) { \ 11601 if (Addr > 0x7f) \ 11602 RegAddr += 0x40; \ 11603 else if (Addr > 0x1f && Addr < 0x60) \ 11604 RegAddr += 0x20; \ 11605 } 11606 /* LDV_COMMENT_END_PREP */ 11607 /* content: static int tiocmget(struct tty_struct *tty)*/ 11608 /* LDV_COMMENT_BEGIN_PREP */ 11609 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 11610 #if defined(__i386__) 11611 # define BREAKPOINT() asm(" int $3"); 11612 #else 11613 # define BREAKPOINT() { } 11614 #endif 11615 #define MAX_DEVICES 12 11616 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 11617 #define SYNCLINK_GENERIC_HDLC 1 11618 #else 11619 #define SYNCLINK_GENERIC_HDLC 0 11620 #endif 11621 #define GET_USER(error,value,addr) error = get_user(value,addr) 11622 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11623 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11624 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11625 #define SCABUFSIZE 1024 11626 #define SCA_MEM_SIZE 0x40000 11627 #define SCA_BASE_SIZE 512 11628 #define SCA_REG_SIZE 16 11629 #define SCA_MAX_PORTS 4 11630 #define SCAMAXDESC 128 11631 #define BUFFERLISTSIZE 4096 11632 #define BH_RECEIVE 1 11633 #define BH_TRANSMIT 2 11634 #define BH_STATUS 4 11635 #define IO_PIN_SHUTDOWN_LIMIT 100 11636 #if SYNCLINK_GENERIC_HDLC 11637 #endif 11638 #define MGSL_MAGIC 0x5401 11639 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11640 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11641 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11642 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11643 #define LPR 0x00 11644 #define PABR0 0x02 11645 #define PABR1 0x03 11646 #define WCRL 0x04 11647 #define WCRM 0x05 11648 #define WCRH 0x06 11649 #define DPCR 0x08 11650 #define DMER 0x09 11651 #define ISR0 0x10 11652 #define ISR1 0x11 11653 #define ISR2 0x12 11654 #define IER0 0x14 11655 #define IER1 0x15 11656 #define IER2 0x16 11657 #define ITCR 0x18 11658 #define INTVR 0x1a 11659 #define IMVR 0x1c 11660 #define TRB 0x20 11661 #define TRBL 0x20 11662 #define TRBH 0x21 11663 #define SR0 0x22 11664 #define SR1 0x23 11665 #define SR2 0x24 11666 #define SR3 0x25 11667 #define FST 0x26 11668 #define IE0 0x28 11669 #define IE1 0x29 11670 #define IE2 0x2a 11671 #define FIE 0x2b 11672 #define CMD 0x2c 11673 #define MD0 0x2e 11674 #define MD1 0x2f 11675 #define MD2 0x30 11676 #define CTL 0x31 11677 #define SA0 0x32 11678 #define SA1 0x33 11679 #define IDL 0x34 11680 #define TMC 0x35 11681 #define RXS 0x36 11682 #define TXS 0x37 11683 #define TRC0 0x38 11684 #define TRC1 0x39 11685 #define RRC 0x3a 11686 #define CST0 0x3c 11687 #define CST1 0x3d 11688 #define TCNT 0x60 11689 #define TCNTL 0x60 11690 #define TCNTH 0x61 11691 #define TCONR 0x62 11692 #define TCONRL 0x62 11693 #define TCONRH 0x63 11694 #define TMCS 0x64 11695 #define TEPR 0x65 11696 #define DARL 0x80 11697 #define DARH 0x81 11698 #define DARB 0x82 11699 #define BAR 0x80 11700 #define BARL 0x80 11701 #define BARH 0x81 11702 #define BARB 0x82 11703 #define SAR 0x84 11704 #define SARL 0x84 11705 #define SARH 0x85 11706 #define SARB 0x86 11707 #define CPB 0x86 11708 #define CDA 0x88 11709 #define CDAL 0x88 11710 #define CDAH 0x89 11711 #define EDA 0x8a 11712 #define EDAL 0x8a 11713 #define EDAH 0x8b 11714 #define BFL 0x8c 11715 #define BFLL 0x8c 11716 #define BFLH 0x8d 11717 #define BCR 0x8e 11718 #define BCRL 0x8e 11719 #define BCRH 0x8f 11720 #define DSR 0x90 11721 #define DMR 0x91 11722 #define FCT 0x93 11723 #define DIR 0x94 11724 #define DCMD 0x95 11725 #define TIMER0 0x00 11726 #define TIMER1 0x08 11727 #define TIMER2 0x10 11728 #define TIMER3 0x18 11729 #define RXDMA 0x00 11730 #define TXDMA 0x20 11731 #define NOOP 0x00 11732 #define TXRESET 0x01 11733 #define TXENABLE 0x02 11734 #define TXDISABLE 0x03 11735 #define TXCRCINIT 0x04 11736 #define TXCRCEXCL 0x05 11737 #define TXEOM 0x06 11738 #define TXABORT 0x07 11739 #define MPON 0x08 11740 #define TXBUFCLR 0x09 11741 #define RXRESET 0x11 11742 #define RXENABLE 0x12 11743 #define RXDISABLE 0x13 11744 #define RXCRCINIT 0x14 11745 #define RXREJECT 0x15 11746 #define SEARCHMP 0x16 11747 #define RXCRCEXCL 0x17 11748 #define RXCRCCALC 0x18 11749 #define CHRESET 0x21 11750 #define HUNT 0x31 11751 #define SWABORT 0x01 11752 #define FEICLEAR 0x02 11753 #define TXINTE BIT7 11754 #define RXINTE BIT6 11755 #define TXRDYE BIT1 11756 #define RXRDYE BIT0 11757 #define UDRN BIT7 11758 #define IDLE BIT6 11759 #define SYNCD BIT4 11760 #define FLGD BIT4 11761 #define CCTS BIT3 11762 #define CDCD BIT2 11763 #define BRKD BIT1 11764 #define ABTD BIT1 11765 #define GAPD BIT1 11766 #define BRKE BIT0 11767 #define IDLD BIT0 11768 #define EOM BIT7 11769 #define PMP BIT6 11770 #define SHRT BIT6 11771 #define PE BIT5 11772 #define ABT BIT5 11773 #define FRME BIT4 11774 #define RBIT BIT4 11775 #define OVRN BIT3 11776 #define CRCE BIT2 11777 #define WAKEUP_CHARS 256 11778 #if SYNCLINK_GENERIC_HDLC 11779 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11780 #endif 11781 #ifdef SANITY_CHECK 11782 #else 11783 #endif 11784 #if SYNCLINK_GENERIC_HDLC 11785 #endif 11786 #if SYNCLINK_GENERIC_HDLC 11787 #endif 11788 #if SYNCLINK_GENERIC_HDLC 11789 #endif 11790 #ifdef CMSPAR 11791 #endif 11792 /* LDV_COMMENT_END_PREP */ 11793 /* LDV_COMMENT_BEGIN_PREP */ 11794 #if SYNCLINK_GENERIC_HDLC 11795 #endif 11796 #if SYNCLINK_GENERIC_HDLC 11797 #endif 11798 #if 0 11799 #endif 11800 #if SYNCLINK_GENERIC_HDLC 11801 #endif 11802 #if SYNCLINK_GENERIC_HDLC 11803 #endif 11804 #define TESTFRAMESIZE 20 11805 #if SYNCLINK_GENERIC_HDLC 11806 #endif 11807 #define CALC_REGADDR() \ 11808 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 11809 if (info->port_num > 1) \ 11810 RegAddr += 256; \ 11811 if ( info->port_num & 1) { \ 11812 if (Addr > 0x7f) \ 11813 RegAddr += 0x40; \ 11814 else if (Addr > 0x1f && Addr < 0x60) \ 11815 RegAddr += 0x20; \ 11816 } 11817 /* LDV_COMMENT_END_PREP */ 11818 /* content: static int tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)*/ 11819 /* LDV_COMMENT_BEGIN_PREP */ 11820 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 11821 #if defined(__i386__) 11822 # define BREAKPOINT() asm(" int $3"); 11823 #else 11824 # define BREAKPOINT() { } 11825 #endif 11826 #define MAX_DEVICES 12 11827 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 11828 #define SYNCLINK_GENERIC_HDLC 1 11829 #else 11830 #define SYNCLINK_GENERIC_HDLC 0 11831 #endif 11832 #define GET_USER(error,value,addr) error = get_user(value,addr) 11833 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11834 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11835 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11836 #define SCABUFSIZE 1024 11837 #define SCA_MEM_SIZE 0x40000 11838 #define SCA_BASE_SIZE 512 11839 #define SCA_REG_SIZE 16 11840 #define SCA_MAX_PORTS 4 11841 #define SCAMAXDESC 128 11842 #define BUFFERLISTSIZE 4096 11843 #define BH_RECEIVE 1 11844 #define BH_TRANSMIT 2 11845 #define BH_STATUS 4 11846 #define IO_PIN_SHUTDOWN_LIMIT 100 11847 #if SYNCLINK_GENERIC_HDLC 11848 #endif 11849 #define MGSL_MAGIC 0x5401 11850 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11851 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11852 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11853 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11854 #define LPR 0x00 11855 #define PABR0 0x02 11856 #define PABR1 0x03 11857 #define WCRL 0x04 11858 #define WCRM 0x05 11859 #define WCRH 0x06 11860 #define DPCR 0x08 11861 #define DMER 0x09 11862 #define ISR0 0x10 11863 #define ISR1 0x11 11864 #define ISR2 0x12 11865 #define IER0 0x14 11866 #define IER1 0x15 11867 #define IER2 0x16 11868 #define ITCR 0x18 11869 #define INTVR 0x1a 11870 #define IMVR 0x1c 11871 #define TRB 0x20 11872 #define TRBL 0x20 11873 #define TRBH 0x21 11874 #define SR0 0x22 11875 #define SR1 0x23 11876 #define SR2 0x24 11877 #define SR3 0x25 11878 #define FST 0x26 11879 #define IE0 0x28 11880 #define IE1 0x29 11881 #define IE2 0x2a 11882 #define FIE 0x2b 11883 #define CMD 0x2c 11884 #define MD0 0x2e 11885 #define MD1 0x2f 11886 #define MD2 0x30 11887 #define CTL 0x31 11888 #define SA0 0x32 11889 #define SA1 0x33 11890 #define IDL 0x34 11891 #define TMC 0x35 11892 #define RXS 0x36 11893 #define TXS 0x37 11894 #define TRC0 0x38 11895 #define TRC1 0x39 11896 #define RRC 0x3a 11897 #define CST0 0x3c 11898 #define CST1 0x3d 11899 #define TCNT 0x60 11900 #define TCNTL 0x60 11901 #define TCNTH 0x61 11902 #define TCONR 0x62 11903 #define TCONRL 0x62 11904 #define TCONRH 0x63 11905 #define TMCS 0x64 11906 #define TEPR 0x65 11907 #define DARL 0x80 11908 #define DARH 0x81 11909 #define DARB 0x82 11910 #define BAR 0x80 11911 #define BARL 0x80 11912 #define BARH 0x81 11913 #define BARB 0x82 11914 #define SAR 0x84 11915 #define SARL 0x84 11916 #define SARH 0x85 11917 #define SARB 0x86 11918 #define CPB 0x86 11919 #define CDA 0x88 11920 #define CDAL 0x88 11921 #define CDAH 0x89 11922 #define EDA 0x8a 11923 #define EDAL 0x8a 11924 #define EDAH 0x8b 11925 #define BFL 0x8c 11926 #define BFLL 0x8c 11927 #define BFLH 0x8d 11928 #define BCR 0x8e 11929 #define BCRL 0x8e 11930 #define BCRH 0x8f 11931 #define DSR 0x90 11932 #define DMR 0x91 11933 #define FCT 0x93 11934 #define DIR 0x94 11935 #define DCMD 0x95 11936 #define TIMER0 0x00 11937 #define TIMER1 0x08 11938 #define TIMER2 0x10 11939 #define TIMER3 0x18 11940 #define RXDMA 0x00 11941 #define TXDMA 0x20 11942 #define NOOP 0x00 11943 #define TXRESET 0x01 11944 #define TXENABLE 0x02 11945 #define TXDISABLE 0x03 11946 #define TXCRCINIT 0x04 11947 #define TXCRCEXCL 0x05 11948 #define TXEOM 0x06 11949 #define TXABORT 0x07 11950 #define MPON 0x08 11951 #define TXBUFCLR 0x09 11952 #define RXRESET 0x11 11953 #define RXENABLE 0x12 11954 #define RXDISABLE 0x13 11955 #define RXCRCINIT 0x14 11956 #define RXREJECT 0x15 11957 #define SEARCHMP 0x16 11958 #define RXCRCEXCL 0x17 11959 #define RXCRCCALC 0x18 11960 #define CHRESET 0x21 11961 #define HUNT 0x31 11962 #define SWABORT 0x01 11963 #define FEICLEAR 0x02 11964 #define TXINTE BIT7 11965 #define RXINTE BIT6 11966 #define TXRDYE BIT1 11967 #define RXRDYE BIT0 11968 #define UDRN BIT7 11969 #define IDLE BIT6 11970 #define SYNCD BIT4 11971 #define FLGD BIT4 11972 #define CCTS BIT3 11973 #define CDCD BIT2 11974 #define BRKD BIT1 11975 #define ABTD BIT1 11976 #define GAPD BIT1 11977 #define BRKE BIT0 11978 #define IDLD BIT0 11979 #define EOM BIT7 11980 #define PMP BIT6 11981 #define SHRT BIT6 11982 #define PE BIT5 11983 #define ABT BIT5 11984 #define FRME BIT4 11985 #define RBIT BIT4 11986 #define OVRN BIT3 11987 #define CRCE BIT2 11988 #define WAKEUP_CHARS 256 11989 #if SYNCLINK_GENERIC_HDLC 11990 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11991 #endif 11992 #ifdef SANITY_CHECK 11993 #else 11994 #endif 11995 #if SYNCLINK_GENERIC_HDLC 11996 #endif 11997 #if SYNCLINK_GENERIC_HDLC 11998 #endif 11999 #if SYNCLINK_GENERIC_HDLC 12000 #endif 12001 #ifdef CMSPAR 12002 #endif 12003 /* LDV_COMMENT_END_PREP */ 12004 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "tiocmset" */ 12005 unsigned int var_tiocmset_68_p1; 12006 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "tiocmset" */ 12007 unsigned int var_tiocmset_68_p2; 12008 /* LDV_COMMENT_BEGIN_PREP */ 12009 #if SYNCLINK_GENERIC_HDLC 12010 #endif 12011 #if SYNCLINK_GENERIC_HDLC 12012 #endif 12013 #if 0 12014 #endif 12015 #if SYNCLINK_GENERIC_HDLC 12016 #endif 12017 #if SYNCLINK_GENERIC_HDLC 12018 #endif 12019 #define TESTFRAMESIZE 20 12020 #if SYNCLINK_GENERIC_HDLC 12021 #endif 12022 #define CALC_REGADDR() \ 12023 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12024 if (info->port_num > 1) \ 12025 RegAddr += 256; \ 12026 if ( info->port_num & 1) { \ 12027 if (Addr > 0x7f) \ 12028 RegAddr += 0x40; \ 12029 else if (Addr > 0x1f && Addr < 0x60) \ 12030 RegAddr += 0x20; \ 12031 } 12032 /* LDV_COMMENT_END_PREP */ 12033 /* content: static int get_icount(struct tty_struct *tty, struct serial_icounter_struct *icount)*/ 12034 /* LDV_COMMENT_BEGIN_PREP */ 12035 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12036 #if defined(__i386__) 12037 # define BREAKPOINT() asm(" int $3"); 12038 #else 12039 # define BREAKPOINT() { } 12040 #endif 12041 #define MAX_DEVICES 12 12042 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12043 #define SYNCLINK_GENERIC_HDLC 1 12044 #else 12045 #define SYNCLINK_GENERIC_HDLC 0 12046 #endif 12047 #define GET_USER(error,value,addr) error = get_user(value,addr) 12048 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12049 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12050 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12051 #define SCABUFSIZE 1024 12052 #define SCA_MEM_SIZE 0x40000 12053 #define SCA_BASE_SIZE 512 12054 #define SCA_REG_SIZE 16 12055 #define SCA_MAX_PORTS 4 12056 #define SCAMAXDESC 128 12057 #define BUFFERLISTSIZE 4096 12058 #define BH_RECEIVE 1 12059 #define BH_TRANSMIT 2 12060 #define BH_STATUS 4 12061 #define IO_PIN_SHUTDOWN_LIMIT 100 12062 #if SYNCLINK_GENERIC_HDLC 12063 #endif 12064 #define MGSL_MAGIC 0x5401 12065 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12066 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12067 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12068 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12069 #define LPR 0x00 12070 #define PABR0 0x02 12071 #define PABR1 0x03 12072 #define WCRL 0x04 12073 #define WCRM 0x05 12074 #define WCRH 0x06 12075 #define DPCR 0x08 12076 #define DMER 0x09 12077 #define ISR0 0x10 12078 #define ISR1 0x11 12079 #define ISR2 0x12 12080 #define IER0 0x14 12081 #define IER1 0x15 12082 #define IER2 0x16 12083 #define ITCR 0x18 12084 #define INTVR 0x1a 12085 #define IMVR 0x1c 12086 #define TRB 0x20 12087 #define TRBL 0x20 12088 #define TRBH 0x21 12089 #define SR0 0x22 12090 #define SR1 0x23 12091 #define SR2 0x24 12092 #define SR3 0x25 12093 #define FST 0x26 12094 #define IE0 0x28 12095 #define IE1 0x29 12096 #define IE2 0x2a 12097 #define FIE 0x2b 12098 #define CMD 0x2c 12099 #define MD0 0x2e 12100 #define MD1 0x2f 12101 #define MD2 0x30 12102 #define CTL 0x31 12103 #define SA0 0x32 12104 #define SA1 0x33 12105 #define IDL 0x34 12106 #define TMC 0x35 12107 #define RXS 0x36 12108 #define TXS 0x37 12109 #define TRC0 0x38 12110 #define TRC1 0x39 12111 #define RRC 0x3a 12112 #define CST0 0x3c 12113 #define CST1 0x3d 12114 #define TCNT 0x60 12115 #define TCNTL 0x60 12116 #define TCNTH 0x61 12117 #define TCONR 0x62 12118 #define TCONRL 0x62 12119 #define TCONRH 0x63 12120 #define TMCS 0x64 12121 #define TEPR 0x65 12122 #define DARL 0x80 12123 #define DARH 0x81 12124 #define DARB 0x82 12125 #define BAR 0x80 12126 #define BARL 0x80 12127 #define BARH 0x81 12128 #define BARB 0x82 12129 #define SAR 0x84 12130 #define SARL 0x84 12131 #define SARH 0x85 12132 #define SARB 0x86 12133 #define CPB 0x86 12134 #define CDA 0x88 12135 #define CDAL 0x88 12136 #define CDAH 0x89 12137 #define EDA 0x8a 12138 #define EDAL 0x8a 12139 #define EDAH 0x8b 12140 #define BFL 0x8c 12141 #define BFLL 0x8c 12142 #define BFLH 0x8d 12143 #define BCR 0x8e 12144 #define BCRL 0x8e 12145 #define BCRH 0x8f 12146 #define DSR 0x90 12147 #define DMR 0x91 12148 #define FCT 0x93 12149 #define DIR 0x94 12150 #define DCMD 0x95 12151 #define TIMER0 0x00 12152 #define TIMER1 0x08 12153 #define TIMER2 0x10 12154 #define TIMER3 0x18 12155 #define RXDMA 0x00 12156 #define TXDMA 0x20 12157 #define NOOP 0x00 12158 #define TXRESET 0x01 12159 #define TXENABLE 0x02 12160 #define TXDISABLE 0x03 12161 #define TXCRCINIT 0x04 12162 #define TXCRCEXCL 0x05 12163 #define TXEOM 0x06 12164 #define TXABORT 0x07 12165 #define MPON 0x08 12166 #define TXBUFCLR 0x09 12167 #define RXRESET 0x11 12168 #define RXENABLE 0x12 12169 #define RXDISABLE 0x13 12170 #define RXCRCINIT 0x14 12171 #define RXREJECT 0x15 12172 #define SEARCHMP 0x16 12173 #define RXCRCEXCL 0x17 12174 #define RXCRCCALC 0x18 12175 #define CHRESET 0x21 12176 #define HUNT 0x31 12177 #define SWABORT 0x01 12178 #define FEICLEAR 0x02 12179 #define TXINTE BIT7 12180 #define RXINTE BIT6 12181 #define TXRDYE BIT1 12182 #define RXRDYE BIT0 12183 #define UDRN BIT7 12184 #define IDLE BIT6 12185 #define SYNCD BIT4 12186 #define FLGD BIT4 12187 #define CCTS BIT3 12188 #define CDCD BIT2 12189 #define BRKD BIT1 12190 #define ABTD BIT1 12191 #define GAPD BIT1 12192 #define BRKE BIT0 12193 #define IDLD BIT0 12194 #define EOM BIT7 12195 #define PMP BIT6 12196 #define SHRT BIT6 12197 #define PE BIT5 12198 #define ABT BIT5 12199 #define FRME BIT4 12200 #define RBIT BIT4 12201 #define OVRN BIT3 12202 #define CRCE BIT2 12203 #define WAKEUP_CHARS 256 12204 #if SYNCLINK_GENERIC_HDLC 12205 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12206 #endif 12207 #ifdef SANITY_CHECK 12208 #else 12209 #endif 12210 /* LDV_COMMENT_END_PREP */ 12211 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "get_icount" */ 12212 struct serial_icounter_struct * var_group10; 12213 /* LDV_COMMENT_BEGIN_PREP */ 12214 #if SYNCLINK_GENERIC_HDLC 12215 #endif 12216 #if SYNCLINK_GENERIC_HDLC 12217 #endif 12218 #if SYNCLINK_GENERIC_HDLC 12219 #endif 12220 #ifdef CMSPAR 12221 #endif 12222 #if SYNCLINK_GENERIC_HDLC 12223 #endif 12224 #if SYNCLINK_GENERIC_HDLC 12225 #endif 12226 #if 0 12227 #endif 12228 #if SYNCLINK_GENERIC_HDLC 12229 #endif 12230 #if SYNCLINK_GENERIC_HDLC 12231 #endif 12232 #define TESTFRAMESIZE 20 12233 #if SYNCLINK_GENERIC_HDLC 12234 #endif 12235 #define CALC_REGADDR() \ 12236 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12237 if (info->port_num > 1) \ 12238 RegAddr += 256; \ 12239 if ( info->port_num & 1) { \ 12240 if (Addr > 0x7f) \ 12241 RegAddr += 0x40; \ 12242 else if (Addr > 0x1f && Addr < 0x60) \ 12243 RegAddr += 0x20; \ 12244 } 12245 /* LDV_COMMENT_END_PREP */ 12246 12247 /** CALLBACK SECTION request_irq **/ 12248 /* content: static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)*/ 12249 /* LDV_COMMENT_BEGIN_PREP */ 12250 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12251 #if defined(__i386__) 12252 # define BREAKPOINT() asm(" int $3"); 12253 #else 12254 # define BREAKPOINT() { } 12255 #endif 12256 #define MAX_DEVICES 12 12257 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12258 #define SYNCLINK_GENERIC_HDLC 1 12259 #else 12260 #define SYNCLINK_GENERIC_HDLC 0 12261 #endif 12262 #define GET_USER(error,value,addr) error = get_user(value,addr) 12263 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12264 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12265 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12266 #define SCABUFSIZE 1024 12267 #define SCA_MEM_SIZE 0x40000 12268 #define SCA_BASE_SIZE 512 12269 #define SCA_REG_SIZE 16 12270 #define SCA_MAX_PORTS 4 12271 #define SCAMAXDESC 128 12272 #define BUFFERLISTSIZE 4096 12273 #define BH_RECEIVE 1 12274 #define BH_TRANSMIT 2 12275 #define BH_STATUS 4 12276 #define IO_PIN_SHUTDOWN_LIMIT 100 12277 #if SYNCLINK_GENERIC_HDLC 12278 #endif 12279 #define MGSL_MAGIC 0x5401 12280 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12281 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12282 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12283 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12284 #define LPR 0x00 12285 #define PABR0 0x02 12286 #define PABR1 0x03 12287 #define WCRL 0x04 12288 #define WCRM 0x05 12289 #define WCRH 0x06 12290 #define DPCR 0x08 12291 #define DMER 0x09 12292 #define ISR0 0x10 12293 #define ISR1 0x11 12294 #define ISR2 0x12 12295 #define IER0 0x14 12296 #define IER1 0x15 12297 #define IER2 0x16 12298 #define ITCR 0x18 12299 #define INTVR 0x1a 12300 #define IMVR 0x1c 12301 #define TRB 0x20 12302 #define TRBL 0x20 12303 #define TRBH 0x21 12304 #define SR0 0x22 12305 #define SR1 0x23 12306 #define SR2 0x24 12307 #define SR3 0x25 12308 #define FST 0x26 12309 #define IE0 0x28 12310 #define IE1 0x29 12311 #define IE2 0x2a 12312 #define FIE 0x2b 12313 #define CMD 0x2c 12314 #define MD0 0x2e 12315 #define MD1 0x2f 12316 #define MD2 0x30 12317 #define CTL 0x31 12318 #define SA0 0x32 12319 #define SA1 0x33 12320 #define IDL 0x34 12321 #define TMC 0x35 12322 #define RXS 0x36 12323 #define TXS 0x37 12324 #define TRC0 0x38 12325 #define TRC1 0x39 12326 #define RRC 0x3a 12327 #define CST0 0x3c 12328 #define CST1 0x3d 12329 #define TCNT 0x60 12330 #define TCNTL 0x60 12331 #define TCNTH 0x61 12332 #define TCONR 0x62 12333 #define TCONRL 0x62 12334 #define TCONRH 0x63 12335 #define TMCS 0x64 12336 #define TEPR 0x65 12337 #define DARL 0x80 12338 #define DARH 0x81 12339 #define DARB 0x82 12340 #define BAR 0x80 12341 #define BARL 0x80 12342 #define BARH 0x81 12343 #define BARB 0x82 12344 #define SAR 0x84 12345 #define SARL 0x84 12346 #define SARH 0x85 12347 #define SARB 0x86 12348 #define CPB 0x86 12349 #define CDA 0x88 12350 #define CDAL 0x88 12351 #define CDAH 0x89 12352 #define EDA 0x8a 12353 #define EDAL 0x8a 12354 #define EDAH 0x8b 12355 #define BFL 0x8c 12356 #define BFLL 0x8c 12357 #define BFLH 0x8d 12358 #define BCR 0x8e 12359 #define BCRL 0x8e 12360 #define BCRH 0x8f 12361 #define DSR 0x90 12362 #define DMR 0x91 12363 #define FCT 0x93 12364 #define DIR 0x94 12365 #define DCMD 0x95 12366 #define TIMER0 0x00 12367 #define TIMER1 0x08 12368 #define TIMER2 0x10 12369 #define TIMER3 0x18 12370 #define RXDMA 0x00 12371 #define TXDMA 0x20 12372 #define NOOP 0x00 12373 #define TXRESET 0x01 12374 #define TXENABLE 0x02 12375 #define TXDISABLE 0x03 12376 #define TXCRCINIT 0x04 12377 #define TXCRCEXCL 0x05 12378 #define TXEOM 0x06 12379 #define TXABORT 0x07 12380 #define MPON 0x08 12381 #define TXBUFCLR 0x09 12382 #define RXRESET 0x11 12383 #define RXENABLE 0x12 12384 #define RXDISABLE 0x13 12385 #define RXCRCINIT 0x14 12386 #define RXREJECT 0x15 12387 #define SEARCHMP 0x16 12388 #define RXCRCEXCL 0x17 12389 #define RXCRCCALC 0x18 12390 #define CHRESET 0x21 12391 #define HUNT 0x31 12392 #define SWABORT 0x01 12393 #define FEICLEAR 0x02 12394 #define TXINTE BIT7 12395 #define RXINTE BIT6 12396 #define TXRDYE BIT1 12397 #define RXRDYE BIT0 12398 #define UDRN BIT7 12399 #define IDLE BIT6 12400 #define SYNCD BIT4 12401 #define FLGD BIT4 12402 #define CCTS BIT3 12403 #define CDCD BIT2 12404 #define BRKD BIT1 12405 #define ABTD BIT1 12406 #define GAPD BIT1 12407 #define BRKE BIT0 12408 #define IDLD BIT0 12409 #define EOM BIT7 12410 #define PMP BIT6 12411 #define SHRT BIT6 12412 #define PE BIT5 12413 #define ABT BIT5 12414 #define FRME BIT4 12415 #define RBIT BIT4 12416 #define OVRN BIT3 12417 #define CRCE BIT2 12418 #define WAKEUP_CHARS 256 12419 #if SYNCLINK_GENERIC_HDLC 12420 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12421 #endif 12422 #ifdef SANITY_CHECK 12423 #else 12424 #endif 12425 #if SYNCLINK_GENERIC_HDLC 12426 #endif 12427 #if SYNCLINK_GENERIC_HDLC 12428 #endif 12429 #if SYNCLINK_GENERIC_HDLC 12430 #endif 12431 /* LDV_COMMENT_END_PREP */ 12432 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_interrupt" */ 12433 int var_synclinkmp_interrupt_52_p0; 12434 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_interrupt" */ 12435 void * var_synclinkmp_interrupt_52_p1; 12436 /* LDV_COMMENT_BEGIN_PREP */ 12437 #ifdef CMSPAR 12438 #endif 12439 #if SYNCLINK_GENERIC_HDLC 12440 #endif 12441 #if SYNCLINK_GENERIC_HDLC 12442 #endif 12443 #if 0 12444 #endif 12445 #if SYNCLINK_GENERIC_HDLC 12446 #endif 12447 #if SYNCLINK_GENERIC_HDLC 12448 #endif 12449 #define TESTFRAMESIZE 20 12450 #if SYNCLINK_GENERIC_HDLC 12451 #endif 12452 #define CALC_REGADDR() \ 12453 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12454 if (info->port_num > 1) \ 12455 RegAddr += 256; \ 12456 if ( info->port_num & 1) { \ 12457 if (Addr > 0x7f) \ 12458 RegAddr += 0x40; \ 12459 else if (Addr > 0x1f && Addr < 0x60) \ 12460 RegAddr += 0x20; \ 12461 } 12462 /* LDV_COMMENT_END_PREP */ 12463 12464 12465 12466 12467 /* LDV_COMMENT_END_VARIABLE_DECLARATION_PART */ 12468 /* LDV_COMMENT_BEGIN_VARIABLE_INITIALIZING_PART */ 12469 /*============================= VARIABLE INITIALIZING PART =============================*/ 12470 LDV_IN_INTERRUPT=1; 12471 12472 12473 12474 12475 /* LDV_COMMENT_END_VARIABLE_INITIALIZING_PART */ 12476 /* LDV_COMMENT_BEGIN_FUNCTION_CALL_SECTION */ 12477 /*============================= FUNCTION CALL SECTION =============================*/ 12478 /* LDV_COMMENT_FUNCTION_CALL Initialize LDV model. */ 12479 ldv_initialize(); 12480 12481 /** INIT: init_type: ST_MODULE_INIT **/ 12482 /* content: static int __init synclinkmp_init(void)*/ 12483 /* LDV_COMMENT_BEGIN_PREP */ 12484 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12485 #if defined(__i386__) 12486 # define BREAKPOINT() asm(" int $3"); 12487 #else 12488 # define BREAKPOINT() { } 12489 #endif 12490 #define MAX_DEVICES 12 12491 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12492 #define SYNCLINK_GENERIC_HDLC 1 12493 #else 12494 #define SYNCLINK_GENERIC_HDLC 0 12495 #endif 12496 #define GET_USER(error,value,addr) error = get_user(value,addr) 12497 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12498 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12499 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12500 #define SCABUFSIZE 1024 12501 #define SCA_MEM_SIZE 0x40000 12502 #define SCA_BASE_SIZE 512 12503 #define SCA_REG_SIZE 16 12504 #define SCA_MAX_PORTS 4 12505 #define SCAMAXDESC 128 12506 #define BUFFERLISTSIZE 4096 12507 #define BH_RECEIVE 1 12508 #define BH_TRANSMIT 2 12509 #define BH_STATUS 4 12510 #define IO_PIN_SHUTDOWN_LIMIT 100 12511 #if SYNCLINK_GENERIC_HDLC 12512 #endif 12513 #define MGSL_MAGIC 0x5401 12514 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12515 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12516 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12517 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12518 #define LPR 0x00 12519 #define PABR0 0x02 12520 #define PABR1 0x03 12521 #define WCRL 0x04 12522 #define WCRM 0x05 12523 #define WCRH 0x06 12524 #define DPCR 0x08 12525 #define DMER 0x09 12526 #define ISR0 0x10 12527 #define ISR1 0x11 12528 #define ISR2 0x12 12529 #define IER0 0x14 12530 #define IER1 0x15 12531 #define IER2 0x16 12532 #define ITCR 0x18 12533 #define INTVR 0x1a 12534 #define IMVR 0x1c 12535 #define TRB 0x20 12536 #define TRBL 0x20 12537 #define TRBH 0x21 12538 #define SR0 0x22 12539 #define SR1 0x23 12540 #define SR2 0x24 12541 #define SR3 0x25 12542 #define FST 0x26 12543 #define IE0 0x28 12544 #define IE1 0x29 12545 #define IE2 0x2a 12546 #define FIE 0x2b 12547 #define CMD 0x2c 12548 #define MD0 0x2e 12549 #define MD1 0x2f 12550 #define MD2 0x30 12551 #define CTL 0x31 12552 #define SA0 0x32 12553 #define SA1 0x33 12554 #define IDL 0x34 12555 #define TMC 0x35 12556 #define RXS 0x36 12557 #define TXS 0x37 12558 #define TRC0 0x38 12559 #define TRC1 0x39 12560 #define RRC 0x3a 12561 #define CST0 0x3c 12562 #define CST1 0x3d 12563 #define TCNT 0x60 12564 #define TCNTL 0x60 12565 #define TCNTH 0x61 12566 #define TCONR 0x62 12567 #define TCONRL 0x62 12568 #define TCONRH 0x63 12569 #define TMCS 0x64 12570 #define TEPR 0x65 12571 #define DARL 0x80 12572 #define DARH 0x81 12573 #define DARB 0x82 12574 #define BAR 0x80 12575 #define BARL 0x80 12576 #define BARH 0x81 12577 #define BARB 0x82 12578 #define SAR 0x84 12579 #define SARL 0x84 12580 #define SARH 0x85 12581 #define SARB 0x86 12582 #define CPB 0x86 12583 #define CDA 0x88 12584 #define CDAL 0x88 12585 #define CDAH 0x89 12586 #define EDA 0x8a 12587 #define EDAL 0x8a 12588 #define EDAH 0x8b 12589 #define BFL 0x8c 12590 #define BFLL 0x8c 12591 #define BFLH 0x8d 12592 #define BCR 0x8e 12593 #define BCRL 0x8e 12594 #define BCRH 0x8f 12595 #define DSR 0x90 12596 #define DMR 0x91 12597 #define FCT 0x93 12598 #define DIR 0x94 12599 #define DCMD 0x95 12600 #define TIMER0 0x00 12601 #define TIMER1 0x08 12602 #define TIMER2 0x10 12603 #define TIMER3 0x18 12604 #define RXDMA 0x00 12605 #define TXDMA 0x20 12606 #define NOOP 0x00 12607 #define TXRESET 0x01 12608 #define TXENABLE 0x02 12609 #define TXDISABLE 0x03 12610 #define TXCRCINIT 0x04 12611 #define TXCRCEXCL 0x05 12612 #define TXEOM 0x06 12613 #define TXABORT 0x07 12614 #define MPON 0x08 12615 #define TXBUFCLR 0x09 12616 #define RXRESET 0x11 12617 #define RXENABLE 0x12 12618 #define RXDISABLE 0x13 12619 #define RXCRCINIT 0x14 12620 #define RXREJECT 0x15 12621 #define SEARCHMP 0x16 12622 #define RXCRCEXCL 0x17 12623 #define RXCRCCALC 0x18 12624 #define CHRESET 0x21 12625 #define HUNT 0x31 12626 #define SWABORT 0x01 12627 #define FEICLEAR 0x02 12628 #define TXINTE BIT7 12629 #define RXINTE BIT6 12630 #define TXRDYE BIT1 12631 #define RXRDYE BIT0 12632 #define UDRN BIT7 12633 #define IDLE BIT6 12634 #define SYNCD BIT4 12635 #define FLGD BIT4 12636 #define CCTS BIT3 12637 #define CDCD BIT2 12638 #define BRKD BIT1 12639 #define ABTD BIT1 12640 #define GAPD BIT1 12641 #define BRKE BIT0 12642 #define IDLD BIT0 12643 #define EOM BIT7 12644 #define PMP BIT6 12645 #define SHRT BIT6 12646 #define PE BIT5 12647 #define ABT BIT5 12648 #define FRME BIT4 12649 #define RBIT BIT4 12650 #define OVRN BIT3 12651 #define CRCE BIT2 12652 #define WAKEUP_CHARS 256 12653 #if SYNCLINK_GENERIC_HDLC 12654 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12655 #endif 12656 #ifdef SANITY_CHECK 12657 #else 12658 #endif 12659 #if SYNCLINK_GENERIC_HDLC 12660 #endif 12661 #if SYNCLINK_GENERIC_HDLC 12662 #endif 12663 #if SYNCLINK_GENERIC_HDLC 12664 #endif 12665 #ifdef CMSPAR 12666 #endif 12667 #if SYNCLINK_GENERIC_HDLC 12668 #endif 12669 #if SYNCLINK_GENERIC_HDLC 12670 #endif 12671 /* LDV_COMMENT_END_PREP */ 12672 /* LDV_COMMENT_FUNCTION_CALL Kernel calls driver init function after driver loading to kernel. This function declared as "MODULE_INIT(function name)". */ 12673 ldv_handler_precall(); 12674 if(synclinkmp_init()) 12675 goto ldv_final; 12676 /* LDV_COMMENT_BEGIN_PREP */ 12677 #if 0 12678 #endif 12679 #if SYNCLINK_GENERIC_HDLC 12680 #endif 12681 #if SYNCLINK_GENERIC_HDLC 12682 #endif 12683 #define TESTFRAMESIZE 20 12684 #if SYNCLINK_GENERIC_HDLC 12685 #endif 12686 #define CALC_REGADDR() \ 12687 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12688 if (info->port_num > 1) \ 12689 RegAddr += 256; \ 12690 if ( info->port_num & 1) { \ 12691 if (Addr > 0x7f) \ 12692 RegAddr += 0x40; \ 12693 else if (Addr > 0x1f && Addr < 0x60) \ 12694 RegAddr += 0x20; \ 12695 } 12696 /* LDV_COMMENT_END_PREP */ 12697 int ldv_s_synclinkmp_pci_driver_pci_driver = 0; 12698 12699 int ldv_s_synclinkmp_proc_fops_file_operations = 0; 12700 12701 int ldv_s_hdlcdev_ops_net_device_ops = 0; 12702 12703 12704 12705 12706 int ldv_s_ops_tty_operations = 0; 12707 12708 12709 12710 12711 12712 while( nondet_int() 12713 || !(ldv_s_synclinkmp_pci_driver_pci_driver == 0) 12714 || !(ldv_s_synclinkmp_proc_fops_file_operations == 0) 12715 || !(ldv_s_hdlcdev_ops_net_device_ops == 0) 12716 || !(ldv_s_ops_tty_operations == 0) 12717 ) { 12718 12719 switch(nondet_int()) { 12720 12721 case 0: { 12722 12723 /** STRUCT: struct type: pci_driver, struct name: synclinkmp_pci_driver **/ 12724 if(ldv_s_synclinkmp_pci_driver_pci_driver==0) { 12725 12726 /* content: static int synclinkmp_init_one (struct pci_dev *dev, const struct pci_device_id *ent)*/ 12727 /* LDV_COMMENT_BEGIN_PREP */ 12728 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12729 #if defined(__i386__) 12730 # define BREAKPOINT() asm(" int $3"); 12731 #else 12732 # define BREAKPOINT() { } 12733 #endif 12734 #define MAX_DEVICES 12 12735 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12736 #define SYNCLINK_GENERIC_HDLC 1 12737 #else 12738 #define SYNCLINK_GENERIC_HDLC 0 12739 #endif 12740 #define GET_USER(error,value,addr) error = get_user(value,addr) 12741 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12742 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12743 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12744 #define SCABUFSIZE 1024 12745 #define SCA_MEM_SIZE 0x40000 12746 #define SCA_BASE_SIZE 512 12747 #define SCA_REG_SIZE 16 12748 #define SCA_MAX_PORTS 4 12749 #define SCAMAXDESC 128 12750 #define BUFFERLISTSIZE 4096 12751 #define BH_RECEIVE 1 12752 #define BH_TRANSMIT 2 12753 #define BH_STATUS 4 12754 #define IO_PIN_SHUTDOWN_LIMIT 100 12755 #if SYNCLINK_GENERIC_HDLC 12756 #endif 12757 #define MGSL_MAGIC 0x5401 12758 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12759 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12760 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12761 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12762 #define LPR 0x00 12763 #define PABR0 0x02 12764 #define PABR1 0x03 12765 #define WCRL 0x04 12766 #define WCRM 0x05 12767 #define WCRH 0x06 12768 #define DPCR 0x08 12769 #define DMER 0x09 12770 #define ISR0 0x10 12771 #define ISR1 0x11 12772 #define ISR2 0x12 12773 #define IER0 0x14 12774 #define IER1 0x15 12775 #define IER2 0x16 12776 #define ITCR 0x18 12777 #define INTVR 0x1a 12778 #define IMVR 0x1c 12779 #define TRB 0x20 12780 #define TRBL 0x20 12781 #define TRBH 0x21 12782 #define SR0 0x22 12783 #define SR1 0x23 12784 #define SR2 0x24 12785 #define SR3 0x25 12786 #define FST 0x26 12787 #define IE0 0x28 12788 #define IE1 0x29 12789 #define IE2 0x2a 12790 #define FIE 0x2b 12791 #define CMD 0x2c 12792 #define MD0 0x2e 12793 #define MD1 0x2f 12794 #define MD2 0x30 12795 #define CTL 0x31 12796 #define SA0 0x32 12797 #define SA1 0x33 12798 #define IDL 0x34 12799 #define TMC 0x35 12800 #define RXS 0x36 12801 #define TXS 0x37 12802 #define TRC0 0x38 12803 #define TRC1 0x39 12804 #define RRC 0x3a 12805 #define CST0 0x3c 12806 #define CST1 0x3d 12807 #define TCNT 0x60 12808 #define TCNTL 0x60 12809 #define TCNTH 0x61 12810 #define TCONR 0x62 12811 #define TCONRL 0x62 12812 #define TCONRH 0x63 12813 #define TMCS 0x64 12814 #define TEPR 0x65 12815 #define DARL 0x80 12816 #define DARH 0x81 12817 #define DARB 0x82 12818 #define BAR 0x80 12819 #define BARL 0x80 12820 #define BARH 0x81 12821 #define BARB 0x82 12822 #define SAR 0x84 12823 #define SARL 0x84 12824 #define SARH 0x85 12825 #define SARB 0x86 12826 #define CPB 0x86 12827 #define CDA 0x88 12828 #define CDAL 0x88 12829 #define CDAH 0x89 12830 #define EDA 0x8a 12831 #define EDAL 0x8a 12832 #define EDAH 0x8b 12833 #define BFL 0x8c 12834 #define BFLL 0x8c 12835 #define BFLH 0x8d 12836 #define BCR 0x8e 12837 #define BCRL 0x8e 12838 #define BCRH 0x8f 12839 #define DSR 0x90 12840 #define DMR 0x91 12841 #define FCT 0x93 12842 #define DIR 0x94 12843 #define DCMD 0x95 12844 #define TIMER0 0x00 12845 #define TIMER1 0x08 12846 #define TIMER2 0x10 12847 #define TIMER3 0x18 12848 #define RXDMA 0x00 12849 #define TXDMA 0x20 12850 #define NOOP 0x00 12851 #define TXRESET 0x01 12852 #define TXENABLE 0x02 12853 #define TXDISABLE 0x03 12854 #define TXCRCINIT 0x04 12855 #define TXCRCEXCL 0x05 12856 #define TXEOM 0x06 12857 #define TXABORT 0x07 12858 #define MPON 0x08 12859 #define TXBUFCLR 0x09 12860 #define RXRESET 0x11 12861 #define RXENABLE 0x12 12862 #define RXDISABLE 0x13 12863 #define RXCRCINIT 0x14 12864 #define RXREJECT 0x15 12865 #define SEARCHMP 0x16 12866 #define RXCRCEXCL 0x17 12867 #define RXCRCCALC 0x18 12868 #define CHRESET 0x21 12869 #define HUNT 0x31 12870 #define SWABORT 0x01 12871 #define FEICLEAR 0x02 12872 #define TXINTE BIT7 12873 #define RXINTE BIT6 12874 #define TXRDYE BIT1 12875 #define RXRDYE BIT0 12876 #define UDRN BIT7 12877 #define IDLE BIT6 12878 #define SYNCD BIT4 12879 #define FLGD BIT4 12880 #define CCTS BIT3 12881 #define CDCD BIT2 12882 #define BRKD BIT1 12883 #define ABTD BIT1 12884 #define GAPD BIT1 12885 #define BRKE BIT0 12886 #define IDLD BIT0 12887 #define EOM BIT7 12888 #define PMP BIT6 12889 #define SHRT BIT6 12890 #define PE BIT5 12891 #define ABT BIT5 12892 #define FRME BIT4 12893 #define RBIT BIT4 12894 #define OVRN BIT3 12895 #define CRCE BIT2 12896 #define WAKEUP_CHARS 256 12897 #if SYNCLINK_GENERIC_HDLC 12898 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12899 #endif 12900 #ifdef SANITY_CHECK 12901 #else 12902 #endif 12903 #if SYNCLINK_GENERIC_HDLC 12904 #endif 12905 #if SYNCLINK_GENERIC_HDLC 12906 #endif 12907 #if SYNCLINK_GENERIC_HDLC 12908 #endif 12909 #ifdef CMSPAR 12910 #endif 12911 #if SYNCLINK_GENERIC_HDLC 12912 #endif 12913 #if SYNCLINK_GENERIC_HDLC 12914 #endif 12915 #if 0 12916 #endif 12917 #if SYNCLINK_GENERIC_HDLC 12918 #endif 12919 #if SYNCLINK_GENERIC_HDLC 12920 #endif 12921 #define TESTFRAMESIZE 20 12922 #if SYNCLINK_GENERIC_HDLC 12923 #endif 12924 #define CALC_REGADDR() \ 12925 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12926 if (info->port_num > 1) \ 12927 RegAddr += 256; \ 12928 if ( info->port_num & 1) { \ 12929 if (Addr > 0x7f) \ 12930 RegAddr += 0x40; \ 12931 else if (Addr > 0x1f && Addr < 0x60) \ 12932 RegAddr += 0x20; \ 12933 } 12934 /* LDV_COMMENT_END_PREP */ 12935 /* LDV_COMMENT_FUNCTION_CALL Function from field "probe" from driver structure with callbacks "synclinkmp_pci_driver". Standart function test for correct return result. */ 12936 res_synclinkmp_init_one_121 = synclinkmp_init_one( var_group1, var_synclinkmp_init_one_121_p1); 12937 ldv_check_return_value(res_synclinkmp_init_one_121); 12938 ldv_check_return_value_probe(res_synclinkmp_init_one_121); 12939 if(res_synclinkmp_init_one_121) 12940 goto ldv_module_exit; 12941 ldv_s_synclinkmp_pci_driver_pci_driver++; 12942 12943 } 12944 12945 } 12946 12947 break; 12948 case 1: { 12949 12950 /** STRUCT: struct type: pci_driver, struct name: synclinkmp_pci_driver **/ 12951 if(ldv_s_synclinkmp_pci_driver_pci_driver==1) { 12952 12953 /* content: static void synclinkmp_remove_one (struct pci_dev *dev)*/ 12954 /* LDV_COMMENT_BEGIN_PREP */ 12955 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12956 #if defined(__i386__) 12957 # define BREAKPOINT() asm(" int $3"); 12958 #else 12959 # define BREAKPOINT() { } 12960 #endif 12961 #define MAX_DEVICES 12 12962 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12963 #define SYNCLINK_GENERIC_HDLC 1 12964 #else 12965 #define SYNCLINK_GENERIC_HDLC 0 12966 #endif 12967 #define GET_USER(error,value,addr) error = get_user(value,addr) 12968 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12969 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12970 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12971 #define SCABUFSIZE 1024 12972 #define SCA_MEM_SIZE 0x40000 12973 #define SCA_BASE_SIZE 512 12974 #define SCA_REG_SIZE 16 12975 #define SCA_MAX_PORTS 4 12976 #define SCAMAXDESC 128 12977 #define BUFFERLISTSIZE 4096 12978 #define BH_RECEIVE 1 12979 #define BH_TRANSMIT 2 12980 #define BH_STATUS 4 12981 #define IO_PIN_SHUTDOWN_LIMIT 100 12982 #if SYNCLINK_GENERIC_HDLC 12983 #endif 12984 #define MGSL_MAGIC 0x5401 12985 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12986 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12987 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12988 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12989 #define LPR 0x00 12990 #define PABR0 0x02 12991 #define PABR1 0x03 12992 #define WCRL 0x04 12993 #define WCRM 0x05 12994 #define WCRH 0x06 12995 #define DPCR 0x08 12996 #define DMER 0x09 12997 #define ISR0 0x10 12998 #define ISR1 0x11 12999 #define ISR2 0x12 13000 #define IER0 0x14 13001 #define IER1 0x15 13002 #define IER2 0x16 13003 #define ITCR 0x18 13004 #define INTVR 0x1a 13005 #define IMVR 0x1c 13006 #define TRB 0x20 13007 #define TRBL 0x20 13008 #define TRBH 0x21 13009 #define SR0 0x22 13010 #define SR1 0x23 13011 #define SR2 0x24 13012 #define SR3 0x25 13013 #define FST 0x26 13014 #define IE0 0x28 13015 #define IE1 0x29 13016 #define IE2 0x2a 13017 #define FIE 0x2b 13018 #define CMD 0x2c 13019 #define MD0 0x2e 13020 #define MD1 0x2f 13021 #define MD2 0x30 13022 #define CTL 0x31 13023 #define SA0 0x32 13024 #define SA1 0x33 13025 #define IDL 0x34 13026 #define TMC 0x35 13027 #define RXS 0x36 13028 #define TXS 0x37 13029 #define TRC0 0x38 13030 #define TRC1 0x39 13031 #define RRC 0x3a 13032 #define CST0 0x3c 13033 #define CST1 0x3d 13034 #define TCNT 0x60 13035 #define TCNTL 0x60 13036 #define TCNTH 0x61 13037 #define TCONR 0x62 13038 #define TCONRL 0x62 13039 #define TCONRH 0x63 13040 #define TMCS 0x64 13041 #define TEPR 0x65 13042 #define DARL 0x80 13043 #define DARH 0x81 13044 #define DARB 0x82 13045 #define BAR 0x80 13046 #define BARL 0x80 13047 #define BARH 0x81 13048 #define BARB 0x82 13049 #define SAR 0x84 13050 #define SARL 0x84 13051 #define SARH 0x85 13052 #define SARB 0x86 13053 #define CPB 0x86 13054 #define CDA 0x88 13055 #define CDAL 0x88 13056 #define CDAH 0x89 13057 #define EDA 0x8a 13058 #define EDAL 0x8a 13059 #define EDAH 0x8b 13060 #define BFL 0x8c 13061 #define BFLL 0x8c 13062 #define BFLH 0x8d 13063 #define BCR 0x8e 13064 #define BCRL 0x8e 13065 #define BCRH 0x8f 13066 #define DSR 0x90 13067 #define DMR 0x91 13068 #define FCT 0x93 13069 #define DIR 0x94 13070 #define DCMD 0x95 13071 #define TIMER0 0x00 13072 #define TIMER1 0x08 13073 #define TIMER2 0x10 13074 #define TIMER3 0x18 13075 #define RXDMA 0x00 13076 #define TXDMA 0x20 13077 #define NOOP 0x00 13078 #define TXRESET 0x01 13079 #define TXENABLE 0x02 13080 #define TXDISABLE 0x03 13081 #define TXCRCINIT 0x04 13082 #define TXCRCEXCL 0x05 13083 #define TXEOM 0x06 13084 #define TXABORT 0x07 13085 #define MPON 0x08 13086 #define TXBUFCLR 0x09 13087 #define RXRESET 0x11 13088 #define RXENABLE 0x12 13089 #define RXDISABLE 0x13 13090 #define RXCRCINIT 0x14 13091 #define RXREJECT 0x15 13092 #define SEARCHMP 0x16 13093 #define RXCRCEXCL 0x17 13094 #define RXCRCCALC 0x18 13095 #define CHRESET 0x21 13096 #define HUNT 0x31 13097 #define SWABORT 0x01 13098 #define FEICLEAR 0x02 13099 #define TXINTE BIT7 13100 #define RXINTE BIT6 13101 #define TXRDYE BIT1 13102 #define RXRDYE BIT0 13103 #define UDRN BIT7 13104 #define IDLE BIT6 13105 #define SYNCD BIT4 13106 #define FLGD BIT4 13107 #define CCTS BIT3 13108 #define CDCD BIT2 13109 #define BRKD BIT1 13110 #define ABTD BIT1 13111 #define GAPD BIT1 13112 #define BRKE BIT0 13113 #define IDLD BIT0 13114 #define EOM BIT7 13115 #define PMP BIT6 13116 #define SHRT BIT6 13117 #define PE BIT5 13118 #define ABT BIT5 13119 #define FRME BIT4 13120 #define RBIT BIT4 13121 #define OVRN BIT3 13122 #define CRCE BIT2 13123 #define WAKEUP_CHARS 256 13124 #if SYNCLINK_GENERIC_HDLC 13125 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 13126 #endif 13127 #ifdef SANITY_CHECK 13128 #else 13129 #endif 13130 #if SYNCLINK_GENERIC_HDLC 13131 #endif 13132 #if SYNCLINK_GENERIC_HDLC 13133 #endif 13134 #if SYNCLINK_GENERIC_HDLC 13135 #endif 13136 #ifdef CMSPAR 13137 #endif 13138 #if SYNCLINK_GENERIC_HDLC 13139 #endif 13140 #if SYNCLINK_GENERIC_HDLC 13141 #endif 13142 #if 0 13143 #endif 13144 #if SYNCLINK_GENERIC_HDLC 13145 #endif 13146 #if SYNCLINK_GENERIC_HDLC 13147 #endif 13148 #define TESTFRAMESIZE 20 13149 #if SYNCLINK_GENERIC_HDLC 13150 #endif 13151 #define CALC_REGADDR() \ 13152 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 13153 if (info->port_num > 1) \ 13154 RegAddr += 256; \ 13155 if ( info->port_num & 1) { \ 13156 if (Addr > 0x7f) \ 13157 RegAddr += 0x40; \ 13158 else if (Addr > 0x1f && Addr < 0x60) \ 13159 RegAddr += 0x20; \ 13160 } 13161 /* LDV_COMMENT_END_PREP */ 13162 /* LDV_COMMENT_FUNCTION_CALL Function from field "remove" from driver structure with callbacks "synclinkmp_pci_driver" */ 13163 ldv_handler_precall(); 13164 synclinkmp_remove_one( var_group1); 13165 ldv_s_synclinkmp_pci_driver_pci_driver=0; 13166 13167 } 13168 13169 } 13170 13171 break; 13172 case 2: { 13173 13174 /** STRUCT: struct type: file_operations, struct name: synclinkmp_proc_fops **/ 13175 if(ldv_s_synclinkmp_proc_fops_file_operations==0) { 13176 13177 /* content: static int synclinkmp_proc_open(struct inode *inode, struct file *file)*/ 13178 /* LDV_COMMENT_BEGIN_PREP */ 13179 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 13180 #if defined(__i386__) 13181 # define BREAKPOINT() asm(" int $3"); 13182 #else 13183 # define BREAKPOINT() { } 13184 #endif 13185 #define MAX_DEVICES 12 13186 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 13187 #define SYNCLINK_GENERIC_HDLC 1 13188 #else 13189 #define SYNCLINK_GENERIC_HDLC 0 13190 #endif 13191 #define GET_USER(error,value,addr) error = get_user(value,addr) 13192 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 13193 #define PUT_USER(error,value,addr) error = put_user(value,addr) 13194 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 13195 #define SCABUFSIZE 1024 13196 #define SCA_MEM_SIZE 0x40000 13197 #define SCA_BASE_SIZE 512 13198 #define SCA_REG_SIZE 16 13199 #define SCA_MAX_PORTS 4 13200 #define SCAMAXDESC 128 13201 #define BUFFERLISTSIZE 4096 13202 #define BH_RECEIVE 1 13203 #define BH_TRANSMIT 2 13204 #define BH_STATUS 4 13205 #define IO_PIN_SHUTDOWN_LIMIT 100 13206 #if SYNCLINK_GENERIC_HDLC 13207 #endif 13208 #define MGSL_MAGIC 0x5401 13209 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13210 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13211 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13212 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13213 #define LPR 0x00 13214 #define PABR0 0x02 13215 #define PABR1 0x03 13216 #define WCRL 0x04 13217 #define WCRM 0x05 13218 #define WCRH 0x06 13219 #define DPCR 0x08 13220 #define DMER 0x09 13221 #define ISR0 0x10 13222 #define ISR1 0x11 13223 #define ISR2 0x12 13224 #define IER0 0x14 13225 #define IER1 0x15 13226 #define IER2 0x16 13227 #define ITCR 0x18 13228 #define INTVR 0x1a 13229 #define IMVR 0x1c 13230 #define TRB 0x20 13231 #define TRBL 0x20 13232 #define TRBH 0x21 13233 #define SR0 0x22 13234 #define SR1 0x23 13235 #define SR2 0x24 13236 #define SR3 0x25 13237 #define FST 0x26 13238 #define IE0 0x28 13239 #define IE1 0x29 13240 #define IE2 0x2a 13241 #define FIE 0x2b 13242 #define CMD 0x2c 13243 #define MD0 0x2e 13244 #define MD1 0x2f 13245 #define MD2 0x30 13246 #define CTL 0x31 13247 #define SA0 0x32 13248 #define SA1 0x33 13249 #define IDL 0x34 13250 #define TMC 0x35 13251 #define RXS 0x36 13252 #define TXS 0x37 13253 #define TRC0 0x38 13254 #define TRC1 0x39 13255 #define RRC 0x3a 13256 #define CST0 0x3c 13257 #define CST1 0x3d 13258 #define TCNT 0x60 13259 #define TCNTL 0x60 13260 #define TCNTH 0x61 13261 #define TCONR 0x62 13262 #define TCONRL 0x62 13263 #define TCONRH 0x63 13264 #define TMCS 0x64 13265 #define TEPR 0x65 13266 #define DARL 0x80 13267 #define DARH 0x81 13268 #define DARB 0x82 13269 #define BAR 0x80 13270 #define BARL 0x80 13271 #define BARH 0x81 13272 #define BARB 0x82 13273 #define SAR 0x84 13274 #define SARL 0x84 13275 #define SARH 0x85 13276 #define SARB 0x86 13277 #define CPB 0x86 13278 #define CDA 0x88 13279 #define CDAL 0x88 13280 #define CDAH 0x89 13281 #define EDA 0x8a 13282 #define EDAL 0x8a 13283 #define EDAH 0x8b 13284 #define BFL 0x8c 13285 #define BFLL 0x8c 13286 #define BFLH 0x8d 13287 #define BCR 0x8e 13288 #define BCRL 0x8e 13289 #define BCRH 0x8f 13290 #define DSR 0x90 13291 #define DMR 0x91 13292 #define FCT 0x93 13293 #define DIR 0x94 13294 #define DCMD 0x95 13295 #define TIMER0 0x00 13296 #define TIMER1 0x08 13297 #define TIMER2 0x10 13298 #define TIMER3 0x18 13299 #define RXDMA 0x00 13300 #define TXDMA 0x20 13301 #define NOOP 0x00 13302 #define TXRESET 0x01 13303 #define TXENABLE 0x02 13304 #define TXDISABLE 0x03 13305 #define TXCRCINIT 0x04 13306 #define TXCRCEXCL 0x05 13307 #define TXEOM 0x06 13308 #define TXABORT 0x07 13309 #define MPON 0x08 13310 #define TXBUFCLR 0x09 13311 #define RXRESET 0x11 13312 #define RXENABLE 0x12 13313 #define RXDISABLE 0x13 13314 #define RXCRCINIT 0x14 13315 #define RXREJECT 0x15 13316 #define SEARCHMP 0x16 13317 #define RXCRCEXCL 0x17 13318 #define RXCRCCALC 0x18 13319 #define CHRESET 0x21 13320 #define HUNT 0x31 13321 #define SWABORT 0x01 13322 #define FEICLEAR 0x02 13323 #define TXINTE BIT7 13324 #define RXINTE BIT6 13325 #define TXRDYE BIT1 13326 #define RXRDYE BIT0 13327 #define UDRN BIT7 13328 #define IDLE BIT6 13329 #define SYNCD BIT4 13330 #define FLGD BIT4 13331 #define CCTS BIT3 13332 #define CDCD BIT2 13333 #define BRKD BIT1 13334 #define ABTD BIT1 13335 #define GAPD BIT1 13336 #define BRKE BIT0 13337 #define IDLD BIT0 13338 #define EOM BIT7 13339 #define PMP BIT6 13340 #define SHRT BIT6 13341 #define PE BIT5 13342 #define ABT BIT5 13343 #define FRME BIT4 13344 #define RBIT BIT4 13345 #define OVRN BIT3 13346 #define CRCE BIT2 13347 #define WAKEUP_CHARS 256 13348 #if SYNCLINK_GENERIC_HDLC 13349 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 13350 #endif 13351 #ifdef SANITY_CHECK 13352 #else 13353 #endif 13354 /* LDV_COMMENT_END_PREP */ 13355 /* LDV_COMMENT_FUNCTION_CALL Function from field "open" from driver structure with callbacks "synclinkmp_proc_fops". Standart function test for correct return result. */ 13356 ldv_handler_precall(); 13357 res_synclinkmp_proc_open_21 = synclinkmp_proc_open( var_group2, var_group3); 13358 ldv_check_return_value(res_synclinkmp_proc_open_21); 13359 if(res_synclinkmp_proc_open_21) 13360 goto ldv_module_exit; 13361 /* LDV_COMMENT_BEGIN_PREP */ 13362 #if SYNCLINK_GENERIC_HDLC 13363 #endif 13364 #if SYNCLINK_GENERIC_HDLC 13365 #endif 13366 #if SYNCLINK_GENERIC_HDLC 13367 #endif 13368 #ifdef CMSPAR 13369 #endif 13370 #if SYNCLINK_GENERIC_HDLC 13371 #endif 13372 #if SYNCLINK_GENERIC_HDLC 13373 #endif 13374 #if 0 13375 #endif 13376 #if SYNCLINK_GENERIC_HDLC 13377 #endif 13378 #if SYNCLINK_GENERIC_HDLC 13379 #endif 13380 #define TESTFRAMESIZE 20 13381 #if SYNCLINK_GENERIC_HDLC 13382 #endif 13383 #define CALC_REGADDR() \ 13384 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 13385 if (info->port_num > 1) \ 13386 RegAddr += 256; \ 13387 if ( info->port_num & 1) { \ 13388 if (Addr > 0x7f) \ 13389 RegAddr += 0x40; \ 13390 else if (Addr > 0x1f && Addr < 0x60) \ 13391 RegAddr += 0x20; \ 13392 } 13393 /* LDV_COMMENT_END_PREP */ 13394 ldv_s_synclinkmp_proc_fops_file_operations=0; 13395 13396 } 13397 13398 } 13399 13400 break; 13401 case 3: { 13402 13403 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 13404 if(ldv_s_hdlcdev_ops_net_device_ops==0) { 13405 13406 /* content: static int hdlcdev_open(struct net_device *dev)*/ 13407 /* LDV_COMMENT_BEGIN_PREP */ 13408 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 13409 #if defined(__i386__) 13410 # define BREAKPOINT() asm(" int $3"); 13411 #else 13412 # define BREAKPOINT() { } 13413 #endif 13414 #define MAX_DEVICES 12 13415 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 13416 #define SYNCLINK_GENERIC_HDLC 1 13417 #else 13418 #define SYNCLINK_GENERIC_HDLC 0 13419 #endif 13420 #define GET_USER(error,value,addr) error = get_user(value,addr) 13421 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 13422 #define PUT_USER(error,value,addr) error = put_user(value,addr) 13423 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 13424 #define SCABUFSIZE 1024 13425 #define SCA_MEM_SIZE 0x40000 13426 #define SCA_BASE_SIZE 512 13427 #define SCA_REG_SIZE 16 13428 #define SCA_MAX_PORTS 4 13429 #define SCAMAXDESC 128 13430 #define BUFFERLISTSIZE 4096 13431 #define BH_RECEIVE 1 13432 #define BH_TRANSMIT 2 13433 #define BH_STATUS 4 13434 #define IO_PIN_SHUTDOWN_LIMIT 100 13435 #if SYNCLINK_GENERIC_HDLC 13436 #endif 13437 #define MGSL_MAGIC 0x5401 13438 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13439 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13440 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13441 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13442 #define LPR 0x00 13443 #define PABR0 0x02 13444 #define PABR1 0x03 13445 #define WCRL 0x04 13446 #define WCRM 0x05 13447 #define WCRH 0x06 13448 #define DPCR 0x08 13449 #define DMER 0x09 13450 #define ISR0 0x10 13451 #define ISR1 0x11 13452 #define ISR2 0x12 13453 #define IER0 0x14 13454 #define IER1 0x15 13455 #define IER2 0x16 13456 #define ITCR 0x18 13457 #define INTVR 0x1a 13458 #define IMVR 0x1c 13459 #define TRB 0x20 13460 #define TRBL 0x20 13461 #define TRBH 0x21 13462 #define SR0 0x22 13463 #define SR1 0x23 13464 #define SR2 0x24 13465 #define SR3 0x25 13466 #define FST 0x26 13467 #define IE0 0x28 13468 #define IE1 0x29 13469 #define IE2 0x2a 13470 #define FIE 0x2b 13471 #define CMD 0x2c 13472 #define MD0 0x2e 13473 #define MD1 0x2f 13474 #define MD2 0x30 13475 #define CTL 0x31 13476 #define SA0 0x32 13477 #define SA1 0x33 13478 #define IDL 0x34 13479 #define TMC 0x35 13480 #define RXS 0x36 13481 #define TXS 0x37 13482 #define TRC0 0x38 13483 #define TRC1 0x39 13484 #define RRC 0x3a 13485 #define CST0 0x3c 13486 #define CST1 0x3d 13487 #define TCNT 0x60 13488 #define TCNTL 0x60 13489 #define TCNTH 0x61 13490 #define TCONR 0x62 13491 #define TCONRL 0x62 13492 #define TCONRH 0x63 13493 #define TMCS 0x64 13494 #define TEPR 0x65 13495 #define DARL 0x80 13496 #define DARH 0x81 13497 #define DARB 0x82 13498 #define BAR 0x80 13499 #define BARL 0x80 13500 #define BARH 0x81 13501 #define BARB 0x82 13502 #define SAR 0x84 13503 #define SARL 0x84 13504 #define SARH 0x85 13505 #define SARB 0x86 13506 #define CPB 0x86 13507 #define CDA 0x88 13508 #define CDAL 0x88 13509 #define CDAH 0x89 13510 #define EDA 0x8a 13511 #define EDAL 0x8a 13512 #define EDAH 0x8b 13513 #define BFL 0x8c 13514 #define BFLL 0x8c 13515 #define BFLH 0x8d 13516 #define BCR 0x8e 13517 #define BCRL 0x8e 13518 #define BCRH 0x8f 13519 #define DSR 0x90 13520 #define DMR 0x91 13521 #define FCT 0x93 13522 #define DIR 0x94 13523 #define DCMD 0x95 13524 #define TIMER0 0x00 13525 #define TIMER1 0x08 13526 #define TIMER2 0x10 13527 #define TIMER3 0x18 13528 #define RXDMA 0x00 13529 #define TXDMA 0x20 13530 #define NOOP 0x00 13531 #define TXRESET 0x01 13532 #define TXENABLE 0x02 13533 #define TXDISABLE 0x03 13534 #define TXCRCINIT 0x04 13535 #define TXCRCEXCL 0x05 13536 #define TXEOM 0x06 13537 #define TXABORT 0x07 13538 #define MPON 0x08 13539 #define TXBUFCLR 0x09 13540 #define RXRESET 0x11 13541 #define RXENABLE 0x12 13542 #define RXDISABLE 0x13 13543 #define RXCRCINIT 0x14 13544 #define RXREJECT 0x15 13545 #define SEARCHMP 0x16 13546 #define RXCRCEXCL 0x17 13547 #define RXCRCCALC 0x18 13548 #define CHRESET 0x21 13549 #define HUNT 0x31 13550 #define SWABORT 0x01 13551 #define FEICLEAR 0x02 13552 #define TXINTE BIT7 13553 #define RXINTE BIT6 13554 #define TXRDYE BIT1 13555 #define RXRDYE BIT0 13556 #define UDRN BIT7 13557 #define IDLE BIT6 13558 #define SYNCD BIT4 13559 #define FLGD BIT4 13560 #define CCTS BIT3 13561 #define CDCD BIT2 13562 #define BRKD BIT1 13563 #define ABTD BIT1 13564 #define GAPD BIT1 13565 #define BRKE BIT0 13566 #define IDLD BIT0 13567 #define EOM BIT7 13568 #define PMP BIT6 13569 #define SHRT BIT6 13570 #define PE BIT5 13571 #define ABT BIT5 13572 #define FRME BIT4 13573 #define RBIT BIT4 13574 #define OVRN BIT3 13575 #define CRCE BIT2 13576 #define WAKEUP_CHARS 256 13577 #if SYNCLINK_GENERIC_HDLC 13578 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 13579 #endif 13580 #ifdef SANITY_CHECK 13581 #else 13582 #endif 13583 #if SYNCLINK_GENERIC_HDLC 13584 /* LDV_COMMENT_END_PREP */ 13585 /* LDV_COMMENT_FUNCTION_CALL Function from field "ndo_open" from driver structure with callbacks "hdlcdev_ops". Standart function test for correct return result. */ 13586 ldv_handler_precall(); 13587 res_hdlcdev_open_28 = hdlcdev_open( var_group4); 13588 ldv_check_return_value(res_hdlcdev_open_28); 13589 if(res_hdlcdev_open_28 < 0) 13590 goto ldv_module_exit; 13591 /* LDV_COMMENT_BEGIN_PREP */ 13592 #endif 13593 #if SYNCLINK_GENERIC_HDLC 13594 #endif 13595 #if SYNCLINK_GENERIC_HDLC 13596 #endif 13597 #ifdef CMSPAR 13598 #endif 13599 #if SYNCLINK_GENERIC_HDLC 13600 #endif 13601 #if SYNCLINK_GENERIC_HDLC 13602 #endif 13603 #if 0 13604 #endif 13605 #if SYNCLINK_GENERIC_HDLC 13606 #endif 13607 #if SYNCLINK_GENERIC_HDLC 13608 #endif 13609 #define TESTFRAMESIZE 20 13610 #if SYNCLINK_GENERIC_HDLC 13611 #endif 13612 #define CALC_REGADDR() \ 13613 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 13614 if (info->port_num > 1) \ 13615 RegAddr += 256; \ 13616 if ( info->port_num & 1) { \ 13617 if (Addr > 0x7f) \ 13618 RegAddr += 0x40; \ 13619 else if (Addr > 0x1f && Addr < 0x60) \ 13620 RegAddr += 0x20; \ 13621 } 13622 /* LDV_COMMENT_END_PREP */ 13623 ldv_s_hdlcdev_ops_net_device_ops++; 13624 13625 } 13626 13627 } 13628 13629 break; 13630 case 4: { 13631 13632 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 13633 if(ldv_s_hdlcdev_ops_net_device_ops==1) { 13634 13635 /* content: static int hdlcdev_close(struct net_device *dev)*/ 13636 /* LDV_COMMENT_BEGIN_PREP */ 13637 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 13638 #if defined(__i386__) 13639 # define BREAKPOINT() asm(" int $3"); 13640 #else 13641 # define BREAKPOINT() { } 13642 #endif 13643 #define MAX_DEVICES 12 13644 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 13645 #define SYNCLINK_GENERIC_HDLC 1 13646 #else 13647 #define SYNCLINK_GENERIC_HDLC 0 13648 #endif 13649 #define GET_USER(error,value,addr) error = get_user(value,addr) 13650 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 13651 #define PUT_USER(error,value,addr) error = put_user(value,addr) 13652 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 13653 #define SCABUFSIZE 1024 13654 #define SCA_MEM_SIZE 0x40000 13655 #define SCA_BASE_SIZE 512 13656 #define SCA_REG_SIZE 16 13657 #define SCA_MAX_PORTS 4 13658 #define SCAMAXDESC 128 13659 #define BUFFERLISTSIZE 4096 13660 #define BH_RECEIVE 1 13661 #define BH_TRANSMIT 2 13662 #define BH_STATUS 4 13663 #define IO_PIN_SHUTDOWN_LIMIT 100 13664 #if SYNCLINK_GENERIC_HDLC 13665 #endif 13666 #define MGSL_MAGIC 0x5401 13667 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13668 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13669 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13670 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13671 #define LPR 0x00 13672 #define PABR0 0x02 13673 #define PABR1 0x03 13674 #define WCRL 0x04 13675 #define WCRM 0x05 13676 #define WCRH 0x06 13677 #define DPCR 0x08 13678 #define DMER 0x09 13679 #define ISR0 0x10 13680 #define ISR1 0x11 13681 #define ISR2 0x12 13682 #define IER0 0x14 13683 #define IER1 0x15 13684 #define IER2 0x16 13685 #define ITCR 0x18 13686 #define INTVR 0x1a 13687 #define IMVR 0x1c 13688 #define TRB 0x20 13689 #define TRBL 0x20 13690 #define TRBH 0x21 13691 #define SR0 0x22 13692 #define SR1 0x23 13693 #define SR2 0x24 13694 #define SR3 0x25 13695 #define FST 0x26 13696 #define IE0 0x28 13697 #define IE1 0x29 13698 #define IE2 0x2a 13699 #define FIE 0x2b 13700 #define CMD 0x2c 13701 #define MD0 0x2e 13702 #define MD1 0x2f 13703 #define MD2 0x30 13704 #define CTL 0x31 13705 #define SA0 0x32 13706 #define SA1 0x33 13707 #define IDL 0x34 13708 #define TMC 0x35 13709 #define RXS 0x36 13710 #define TXS 0x37 13711 #define TRC0 0x38 13712 #define TRC1 0x39 13713 #define RRC 0x3a 13714 #define CST0 0x3c 13715 #define CST1 0x3d 13716 #define TCNT 0x60 13717 #define TCNTL 0x60 13718 #define TCNTH 0x61 13719 #define TCONR 0x62 13720 #define TCONRL 0x62 13721 #define TCONRH 0x63 13722 #define TMCS 0x64 13723 #define TEPR 0x65 13724 #define DARL 0x80 13725 #define DARH 0x81 13726 #define DARB 0x82 13727 #define BAR 0x80 13728 #define BARL 0x80 13729 #define BARH 0x81 13730 #define BARB 0x82 13731 #define SAR 0x84 13732 #define SARL 0x84 13733 #define SARH 0x85 13734 #define SARB 0x86 13735 #define CPB 0x86 13736 #define CDA 0x88 13737 #define CDAL 0x88 13738 #define CDAH 0x89 13739 #define EDA 0x8a 13740 #define EDAL 0x8a 13741 #define EDAH 0x8b 13742 #define BFL 0x8c 13743 #define BFLL 0x8c 13744 #define BFLH 0x8d 13745 #define BCR 0x8e 13746 #define BCRL 0x8e 13747 #define BCRH 0x8f 13748 #define DSR 0x90 13749 #define DMR 0x91 13750 #define FCT 0x93 13751 #define DIR 0x94 13752 #define DCMD 0x95 13753 #define TIMER0 0x00 13754 #define TIMER1 0x08 13755 #define TIMER2 0x10 13756 #define TIMER3 0x18 13757 #define RXDMA 0x00 13758 #define TXDMA 0x20 13759 #define NOOP 0x00 13760 #define TXRESET 0x01 13761 #define TXENABLE 0x02 13762 #define TXDISABLE 0x03 13763 #define TXCRCINIT 0x04 13764 #define TXCRCEXCL 0x05 13765 #define TXEOM 0x06 13766 #define TXABORT 0x07 13767 #define MPON 0x08 13768 #define TXBUFCLR 0x09 13769 #define RXRESET 0x11 13770 #define RXENABLE 0x12 13771 #define RXDISABLE 0x13 13772 #define RXCRCINIT 0x14 13773 #define RXREJECT 0x15 13774 #define SEARCHMP 0x16 13775 #define RXCRCEXCL 0x17 13776 #define RXCRCCALC 0x18 13777 #define CHRESET 0x21 13778 #define HUNT 0x31 13779 #define SWABORT 0x01 13780 #define FEICLEAR 0x02 13781 #define TXINTE BIT7 13782 #define RXINTE BIT6 13783 #define TXRDYE BIT1 13784 #define RXRDYE BIT0 13785 #define UDRN BIT7 13786 #define IDLE BIT6 13787 #define SYNCD BIT4 13788 #define FLGD BIT4 13789 #define CCTS BIT3 13790 #define CDCD BIT2 13791 #define BRKD BIT1 13792 #define ABTD BIT1 13793 #define GAPD BIT1 13794 #define BRKE BIT0 13795 #define IDLD BIT0 13796 #define EOM BIT7 13797 #define PMP BIT6 13798 #define SHRT BIT6 13799 #define PE BIT5 13800 #define ABT BIT5 13801 #define FRME BIT4 13802 #define RBIT BIT4 13803 #define OVRN BIT3 13804 #define CRCE BIT2 13805 #define WAKEUP_CHARS 256 13806 #if SYNCLINK_GENERIC_HDLC 13807 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 13808 #endif 13809 #ifdef SANITY_CHECK 13810 #else 13811 #endif 13812 #if SYNCLINK_GENERIC_HDLC 13813 /* LDV_COMMENT_END_PREP */ 13814 /* LDV_COMMENT_FUNCTION_CALL Function from field "ndo_stop" from driver structure with callbacks "hdlcdev_ops". Standart function test for correct return result. */ 13815 ldv_handler_precall(); 13816 res_hdlcdev_close_29 = hdlcdev_close( var_group4); 13817 ldv_check_return_value(res_hdlcdev_close_29); 13818 if(res_hdlcdev_close_29) 13819 goto ldv_module_exit; 13820 /* LDV_COMMENT_BEGIN_PREP */ 13821 #endif 13822 #if SYNCLINK_GENERIC_HDLC 13823 #endif 13824 #if SYNCLINK_GENERIC_HDLC 13825 #endif 13826 #ifdef CMSPAR 13827 #endif 13828 #if SYNCLINK_GENERIC_HDLC 13829 #endif 13830 #if SYNCLINK_GENERIC_HDLC 13831 #endif 13832 #if 0 13833 #endif 13834 #if SYNCLINK_GENERIC_HDLC 13835 #endif 13836 #if SYNCLINK_GENERIC_HDLC 13837 #endif 13838 #define TESTFRAMESIZE 20 13839 #if SYNCLINK_GENERIC_HDLC 13840 #endif 13841 #define CALC_REGADDR() \ 13842 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 13843 if (info->port_num > 1) \ 13844 RegAddr += 256; \ 13845 if ( info->port_num & 1) { \ 13846 if (Addr > 0x7f) \ 13847 RegAddr += 0x40; \ 13848 else if (Addr > 0x1f && Addr < 0x60) \ 13849 RegAddr += 0x20; \ 13850 } 13851 /* LDV_COMMENT_END_PREP */ 13852 ldv_s_hdlcdev_ops_net_device_ops=0; 13853 13854 } 13855 13856 } 13857 13858 break; 13859 case 5: { 13860 13861 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 13862 13863 13864 /* content: static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)*/ 13865 /* LDV_COMMENT_BEGIN_PREP */ 13866 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 13867 #if defined(__i386__) 13868 # define BREAKPOINT() asm(" int $3"); 13869 #else 13870 # define BREAKPOINT() { } 13871 #endif 13872 #define MAX_DEVICES 12 13873 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 13874 #define SYNCLINK_GENERIC_HDLC 1 13875 #else 13876 #define SYNCLINK_GENERIC_HDLC 0 13877 #endif 13878 #define GET_USER(error,value,addr) error = get_user(value,addr) 13879 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 13880 #define PUT_USER(error,value,addr) error = put_user(value,addr) 13881 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 13882 #define SCABUFSIZE 1024 13883 #define SCA_MEM_SIZE 0x40000 13884 #define SCA_BASE_SIZE 512 13885 #define SCA_REG_SIZE 16 13886 #define SCA_MAX_PORTS 4 13887 #define SCAMAXDESC 128 13888 #define BUFFERLISTSIZE 4096 13889 #define BH_RECEIVE 1 13890 #define BH_TRANSMIT 2 13891 #define BH_STATUS 4 13892 #define IO_PIN_SHUTDOWN_LIMIT 100 13893 #if SYNCLINK_GENERIC_HDLC 13894 #endif 13895 #define MGSL_MAGIC 0x5401 13896 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13897 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13898 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13899 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13900 #define LPR 0x00 13901 #define PABR0 0x02 13902 #define PABR1 0x03 13903 #define WCRL 0x04 13904 #define WCRM 0x05 13905 #define WCRH 0x06 13906 #define DPCR 0x08 13907 #define DMER 0x09 13908 #define ISR0 0x10 13909 #define ISR1 0x11 13910 #define ISR2 0x12 13911 #define IER0 0x14 13912 #define IER1 0x15 13913 #define IER2 0x16 13914 #define ITCR 0x18 13915 #define INTVR 0x1a 13916 #define IMVR 0x1c 13917 #define TRB 0x20 13918 #define TRBL 0x20 13919 #define TRBH 0x21 13920 #define SR0 0x22 13921 #define SR1 0x23 13922 #define SR2 0x24 13923 #define SR3 0x25 13924 #define FST 0x26 13925 #define IE0 0x28 13926 #define IE1 0x29 13927 #define IE2 0x2a 13928 #define FIE 0x2b 13929 #define CMD 0x2c 13930 #define MD0 0x2e 13931 #define MD1 0x2f 13932 #define MD2 0x30 13933 #define CTL 0x31 13934 #define SA0 0x32 13935 #define SA1 0x33 13936 #define IDL 0x34 13937 #define TMC 0x35 13938 #define RXS 0x36 13939 #define TXS 0x37 13940 #define TRC0 0x38 13941 #define TRC1 0x39 13942 #define RRC 0x3a 13943 #define CST0 0x3c 13944 #define CST1 0x3d 13945 #define TCNT 0x60 13946 #define TCNTL 0x60 13947 #define TCNTH 0x61 13948 #define TCONR 0x62 13949 #define TCONRL 0x62 13950 #define TCONRH 0x63 13951 #define TMCS 0x64 13952 #define TEPR 0x65 13953 #define DARL 0x80 13954 #define DARH 0x81 13955 #define DARB 0x82 13956 #define BAR 0x80 13957 #define BARL 0x80 13958 #define BARH 0x81 13959 #define BARB 0x82 13960 #define SAR 0x84 13961 #define SARL 0x84 13962 #define SARH 0x85 13963 #define SARB 0x86 13964 #define CPB 0x86 13965 #define CDA 0x88 13966 #define CDAL 0x88 13967 #define CDAH 0x89 13968 #define EDA 0x8a 13969 #define EDAL 0x8a 13970 #define EDAH 0x8b 13971 #define BFL 0x8c 13972 #define BFLL 0x8c 13973 #define BFLH 0x8d 13974 #define BCR 0x8e 13975 #define BCRL 0x8e 13976 #define BCRH 0x8f 13977 #define DSR 0x90 13978 #define DMR 0x91 13979 #define FCT 0x93 13980 #define DIR 0x94 13981 #define DCMD 0x95 13982 #define TIMER0 0x00 13983 #define TIMER1 0x08 13984 #define TIMER2 0x10 13985 #define TIMER3 0x18 13986 #define RXDMA 0x00 13987 #define TXDMA 0x20 13988 #define NOOP 0x00 13989 #define TXRESET 0x01 13990 #define TXENABLE 0x02 13991 #define TXDISABLE 0x03 13992 #define TXCRCINIT 0x04 13993 #define TXCRCEXCL 0x05 13994 #define TXEOM 0x06 13995 #define TXABORT 0x07 13996 #define MPON 0x08 13997 #define TXBUFCLR 0x09 13998 #define RXRESET 0x11 13999 #define RXENABLE 0x12 14000 #define RXDISABLE 0x13 14001 #define RXCRCINIT 0x14 14002 #define RXREJECT 0x15 14003 #define SEARCHMP 0x16 14004 #define RXCRCEXCL 0x17 14005 #define RXCRCCALC 0x18 14006 #define CHRESET 0x21 14007 #define HUNT 0x31 14008 #define SWABORT 0x01 14009 #define FEICLEAR 0x02 14010 #define TXINTE BIT7 14011 #define RXINTE BIT6 14012 #define TXRDYE BIT1 14013 #define RXRDYE BIT0 14014 #define UDRN BIT7 14015 #define IDLE BIT6 14016 #define SYNCD BIT4 14017 #define FLGD BIT4 14018 #define CCTS BIT3 14019 #define CDCD BIT2 14020 #define BRKD BIT1 14021 #define ABTD BIT1 14022 #define GAPD BIT1 14023 #define BRKE BIT0 14024 #define IDLD BIT0 14025 #define EOM BIT7 14026 #define PMP BIT6 14027 #define SHRT BIT6 14028 #define PE BIT5 14029 #define ABT BIT5 14030 #define FRME BIT4 14031 #define RBIT BIT4 14032 #define OVRN BIT3 14033 #define CRCE BIT2 14034 #define WAKEUP_CHARS 256 14035 #if SYNCLINK_GENERIC_HDLC 14036 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14037 #endif 14038 #ifdef SANITY_CHECK 14039 #else 14040 #endif 14041 #if SYNCLINK_GENERIC_HDLC 14042 /* LDV_COMMENT_END_PREP */ 14043 /* LDV_COMMENT_FUNCTION_CALL Function from field "ndo_do_ioctl" from driver structure with callbacks "hdlcdev_ops" */ 14044 ldv_handler_precall(); 14045 hdlcdev_ioctl( var_group4, var_group5, var_hdlcdev_ioctl_30_p2); 14046 /* LDV_COMMENT_BEGIN_PREP */ 14047 #endif 14048 #if SYNCLINK_GENERIC_HDLC 14049 #endif 14050 #if SYNCLINK_GENERIC_HDLC 14051 #endif 14052 #ifdef CMSPAR 14053 #endif 14054 #if SYNCLINK_GENERIC_HDLC 14055 #endif 14056 #if SYNCLINK_GENERIC_HDLC 14057 #endif 14058 #if 0 14059 #endif 14060 #if SYNCLINK_GENERIC_HDLC 14061 #endif 14062 #if SYNCLINK_GENERIC_HDLC 14063 #endif 14064 #define TESTFRAMESIZE 20 14065 #if SYNCLINK_GENERIC_HDLC 14066 #endif 14067 #define CALC_REGADDR() \ 14068 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14069 if (info->port_num > 1) \ 14070 RegAddr += 256; \ 14071 if ( info->port_num & 1) { \ 14072 if (Addr > 0x7f) \ 14073 RegAddr += 0x40; \ 14074 else if (Addr > 0x1f && Addr < 0x60) \ 14075 RegAddr += 0x20; \ 14076 } 14077 /* LDV_COMMENT_END_PREP */ 14078 14079 14080 14081 14082 } 14083 14084 break; 14085 case 6: { 14086 14087 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 14088 14089 14090 /* content: static void hdlcdev_tx_timeout(struct net_device *dev)*/ 14091 /* LDV_COMMENT_BEGIN_PREP */ 14092 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 14093 #if defined(__i386__) 14094 # define BREAKPOINT() asm(" int $3"); 14095 #else 14096 # define BREAKPOINT() { } 14097 #endif 14098 #define MAX_DEVICES 12 14099 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 14100 #define SYNCLINK_GENERIC_HDLC 1 14101 #else 14102 #define SYNCLINK_GENERIC_HDLC 0 14103 #endif 14104 #define GET_USER(error,value,addr) error = get_user(value,addr) 14105 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 14106 #define PUT_USER(error,value,addr) error = put_user(value,addr) 14107 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 14108 #define SCABUFSIZE 1024 14109 #define SCA_MEM_SIZE 0x40000 14110 #define SCA_BASE_SIZE 512 14111 #define SCA_REG_SIZE 16 14112 #define SCA_MAX_PORTS 4 14113 #define SCAMAXDESC 128 14114 #define BUFFERLISTSIZE 4096 14115 #define BH_RECEIVE 1 14116 #define BH_TRANSMIT 2 14117 #define BH_STATUS 4 14118 #define IO_PIN_SHUTDOWN_LIMIT 100 14119 #if SYNCLINK_GENERIC_HDLC 14120 #endif 14121 #define MGSL_MAGIC 0x5401 14122 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 14123 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 14124 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 14125 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 14126 #define LPR 0x00 14127 #define PABR0 0x02 14128 #define PABR1 0x03 14129 #define WCRL 0x04 14130 #define WCRM 0x05 14131 #define WCRH 0x06 14132 #define DPCR 0x08 14133 #define DMER 0x09 14134 #define ISR0 0x10 14135 #define ISR1 0x11 14136 #define ISR2 0x12 14137 #define IER0 0x14 14138 #define IER1 0x15 14139 #define IER2 0x16 14140 #define ITCR 0x18 14141 #define INTVR 0x1a 14142 #define IMVR 0x1c 14143 #define TRB 0x20 14144 #define TRBL 0x20 14145 #define TRBH 0x21 14146 #define SR0 0x22 14147 #define SR1 0x23 14148 #define SR2 0x24 14149 #define SR3 0x25 14150 #define FST 0x26 14151 #define IE0 0x28 14152 #define IE1 0x29 14153 #define IE2 0x2a 14154 #define FIE 0x2b 14155 #define CMD 0x2c 14156 #define MD0 0x2e 14157 #define MD1 0x2f 14158 #define MD2 0x30 14159 #define CTL 0x31 14160 #define SA0 0x32 14161 #define SA1 0x33 14162 #define IDL 0x34 14163 #define TMC 0x35 14164 #define RXS 0x36 14165 #define TXS 0x37 14166 #define TRC0 0x38 14167 #define TRC1 0x39 14168 #define RRC 0x3a 14169 #define CST0 0x3c 14170 #define CST1 0x3d 14171 #define TCNT 0x60 14172 #define TCNTL 0x60 14173 #define TCNTH 0x61 14174 #define TCONR 0x62 14175 #define TCONRL 0x62 14176 #define TCONRH 0x63 14177 #define TMCS 0x64 14178 #define TEPR 0x65 14179 #define DARL 0x80 14180 #define DARH 0x81 14181 #define DARB 0x82 14182 #define BAR 0x80 14183 #define BARL 0x80 14184 #define BARH 0x81 14185 #define BARB 0x82 14186 #define SAR 0x84 14187 #define SARL 0x84 14188 #define SARH 0x85 14189 #define SARB 0x86 14190 #define CPB 0x86 14191 #define CDA 0x88 14192 #define CDAL 0x88 14193 #define CDAH 0x89 14194 #define EDA 0x8a 14195 #define EDAL 0x8a 14196 #define EDAH 0x8b 14197 #define BFL 0x8c 14198 #define BFLL 0x8c 14199 #define BFLH 0x8d 14200 #define BCR 0x8e 14201 #define BCRL 0x8e 14202 #define BCRH 0x8f 14203 #define DSR 0x90 14204 #define DMR 0x91 14205 #define FCT 0x93 14206 #define DIR 0x94 14207 #define DCMD 0x95 14208 #define TIMER0 0x00 14209 #define TIMER1 0x08 14210 #define TIMER2 0x10 14211 #define TIMER3 0x18 14212 #define RXDMA 0x00 14213 #define TXDMA 0x20 14214 #define NOOP 0x00 14215 #define TXRESET 0x01 14216 #define TXENABLE 0x02 14217 #define TXDISABLE 0x03 14218 #define TXCRCINIT 0x04 14219 #define TXCRCEXCL 0x05 14220 #define TXEOM 0x06 14221 #define TXABORT 0x07 14222 #define MPON 0x08 14223 #define TXBUFCLR 0x09 14224 #define RXRESET 0x11 14225 #define RXENABLE 0x12 14226 #define RXDISABLE 0x13 14227 #define RXCRCINIT 0x14 14228 #define RXREJECT 0x15 14229 #define SEARCHMP 0x16 14230 #define RXCRCEXCL 0x17 14231 #define RXCRCCALC 0x18 14232 #define CHRESET 0x21 14233 #define HUNT 0x31 14234 #define SWABORT 0x01 14235 #define FEICLEAR 0x02 14236 #define TXINTE BIT7 14237 #define RXINTE BIT6 14238 #define TXRDYE BIT1 14239 #define RXRDYE BIT0 14240 #define UDRN BIT7 14241 #define IDLE BIT6 14242 #define SYNCD BIT4 14243 #define FLGD BIT4 14244 #define CCTS BIT3 14245 #define CDCD BIT2 14246 #define BRKD BIT1 14247 #define ABTD BIT1 14248 #define GAPD BIT1 14249 #define BRKE BIT0 14250 #define IDLD BIT0 14251 #define EOM BIT7 14252 #define PMP BIT6 14253 #define SHRT BIT6 14254 #define PE BIT5 14255 #define ABT BIT5 14256 #define FRME BIT4 14257 #define RBIT BIT4 14258 #define OVRN BIT3 14259 #define CRCE BIT2 14260 #define WAKEUP_CHARS 256 14261 #if SYNCLINK_GENERIC_HDLC 14262 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14263 #endif 14264 #ifdef SANITY_CHECK 14265 #else 14266 #endif 14267 #if SYNCLINK_GENERIC_HDLC 14268 /* LDV_COMMENT_END_PREP */ 14269 /* LDV_COMMENT_FUNCTION_CALL Function from field "ndo_tx_timeout" from driver structure with callbacks "hdlcdev_ops" */ 14270 ldv_handler_precall(); 14271 hdlcdev_tx_timeout( var_group4); 14272 /* LDV_COMMENT_BEGIN_PREP */ 14273 #endif 14274 #if SYNCLINK_GENERIC_HDLC 14275 #endif 14276 #if SYNCLINK_GENERIC_HDLC 14277 #endif 14278 #ifdef CMSPAR 14279 #endif 14280 #if SYNCLINK_GENERIC_HDLC 14281 #endif 14282 #if SYNCLINK_GENERIC_HDLC 14283 #endif 14284 #if 0 14285 #endif 14286 #if SYNCLINK_GENERIC_HDLC 14287 #endif 14288 #if SYNCLINK_GENERIC_HDLC 14289 #endif 14290 #define TESTFRAMESIZE 20 14291 #if SYNCLINK_GENERIC_HDLC 14292 #endif 14293 #define CALC_REGADDR() \ 14294 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14295 if (info->port_num > 1) \ 14296 RegAddr += 256; \ 14297 if ( info->port_num & 1) { \ 14298 if (Addr > 0x7f) \ 14299 RegAddr += 0x40; \ 14300 else if (Addr > 0x1f && Addr < 0x60) \ 14301 RegAddr += 0x20; \ 14302 } 14303 /* LDV_COMMENT_END_PREP */ 14304 14305 14306 14307 14308 } 14309 14310 break; 14311 case 7: { 14312 14313 /** STRUCT: struct type: tty_port_operations, struct name: port_ops **/ 14314 14315 14316 /* content: static int carrier_raised(struct tty_port *port)*/ 14317 /* LDV_COMMENT_BEGIN_PREP */ 14318 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 14319 #if defined(__i386__) 14320 # define BREAKPOINT() asm(" int $3"); 14321 #else 14322 # define BREAKPOINT() { } 14323 #endif 14324 #define MAX_DEVICES 12 14325 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 14326 #define SYNCLINK_GENERIC_HDLC 1 14327 #else 14328 #define SYNCLINK_GENERIC_HDLC 0 14329 #endif 14330 #define GET_USER(error,value,addr) error = get_user(value,addr) 14331 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 14332 #define PUT_USER(error,value,addr) error = put_user(value,addr) 14333 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 14334 #define SCABUFSIZE 1024 14335 #define SCA_MEM_SIZE 0x40000 14336 #define SCA_BASE_SIZE 512 14337 #define SCA_REG_SIZE 16 14338 #define SCA_MAX_PORTS 4 14339 #define SCAMAXDESC 128 14340 #define BUFFERLISTSIZE 4096 14341 #define BH_RECEIVE 1 14342 #define BH_TRANSMIT 2 14343 #define BH_STATUS 4 14344 #define IO_PIN_SHUTDOWN_LIMIT 100 14345 #if SYNCLINK_GENERIC_HDLC 14346 #endif 14347 #define MGSL_MAGIC 0x5401 14348 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 14349 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 14350 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 14351 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 14352 #define LPR 0x00 14353 #define PABR0 0x02 14354 #define PABR1 0x03 14355 #define WCRL 0x04 14356 #define WCRM 0x05 14357 #define WCRH 0x06 14358 #define DPCR 0x08 14359 #define DMER 0x09 14360 #define ISR0 0x10 14361 #define ISR1 0x11 14362 #define ISR2 0x12 14363 #define IER0 0x14 14364 #define IER1 0x15 14365 #define IER2 0x16 14366 #define ITCR 0x18 14367 #define INTVR 0x1a 14368 #define IMVR 0x1c 14369 #define TRB 0x20 14370 #define TRBL 0x20 14371 #define TRBH 0x21 14372 #define SR0 0x22 14373 #define SR1 0x23 14374 #define SR2 0x24 14375 #define SR3 0x25 14376 #define FST 0x26 14377 #define IE0 0x28 14378 #define IE1 0x29 14379 #define IE2 0x2a 14380 #define FIE 0x2b 14381 #define CMD 0x2c 14382 #define MD0 0x2e 14383 #define MD1 0x2f 14384 #define MD2 0x30 14385 #define CTL 0x31 14386 #define SA0 0x32 14387 #define SA1 0x33 14388 #define IDL 0x34 14389 #define TMC 0x35 14390 #define RXS 0x36 14391 #define TXS 0x37 14392 #define TRC0 0x38 14393 #define TRC1 0x39 14394 #define RRC 0x3a 14395 #define CST0 0x3c 14396 #define CST1 0x3d 14397 #define TCNT 0x60 14398 #define TCNTL 0x60 14399 #define TCNTH 0x61 14400 #define TCONR 0x62 14401 #define TCONRL 0x62 14402 #define TCONRH 0x63 14403 #define TMCS 0x64 14404 #define TEPR 0x65 14405 #define DARL 0x80 14406 #define DARH 0x81 14407 #define DARB 0x82 14408 #define BAR 0x80 14409 #define BARL 0x80 14410 #define BARH 0x81 14411 #define BARB 0x82 14412 #define SAR 0x84 14413 #define SARL 0x84 14414 #define SARH 0x85 14415 #define SARB 0x86 14416 #define CPB 0x86 14417 #define CDA 0x88 14418 #define CDAL 0x88 14419 #define CDAH 0x89 14420 #define EDA 0x8a 14421 #define EDAL 0x8a 14422 #define EDAH 0x8b 14423 #define BFL 0x8c 14424 #define BFLL 0x8c 14425 #define BFLH 0x8d 14426 #define BCR 0x8e 14427 #define BCRL 0x8e 14428 #define BCRH 0x8f 14429 #define DSR 0x90 14430 #define DMR 0x91 14431 #define FCT 0x93 14432 #define DIR 0x94 14433 #define DCMD 0x95 14434 #define TIMER0 0x00 14435 #define TIMER1 0x08 14436 #define TIMER2 0x10 14437 #define TIMER3 0x18 14438 #define RXDMA 0x00 14439 #define TXDMA 0x20 14440 #define NOOP 0x00 14441 #define TXRESET 0x01 14442 #define TXENABLE 0x02 14443 #define TXDISABLE 0x03 14444 #define TXCRCINIT 0x04 14445 #define TXCRCEXCL 0x05 14446 #define TXEOM 0x06 14447 #define TXABORT 0x07 14448 #define MPON 0x08 14449 #define TXBUFCLR 0x09 14450 #define RXRESET 0x11 14451 #define RXENABLE 0x12 14452 #define RXDISABLE 0x13 14453 #define RXCRCINIT 0x14 14454 #define RXREJECT 0x15 14455 #define SEARCHMP 0x16 14456 #define RXCRCEXCL 0x17 14457 #define RXCRCCALC 0x18 14458 #define CHRESET 0x21 14459 #define HUNT 0x31 14460 #define SWABORT 0x01 14461 #define FEICLEAR 0x02 14462 #define TXINTE BIT7 14463 #define RXINTE BIT6 14464 #define TXRDYE BIT1 14465 #define RXRDYE BIT0 14466 #define UDRN BIT7 14467 #define IDLE BIT6 14468 #define SYNCD BIT4 14469 #define FLGD BIT4 14470 #define CCTS BIT3 14471 #define CDCD BIT2 14472 #define BRKD BIT1 14473 #define ABTD BIT1 14474 #define GAPD BIT1 14475 #define BRKE BIT0 14476 #define IDLD BIT0 14477 #define EOM BIT7 14478 #define PMP BIT6 14479 #define SHRT BIT6 14480 #define PE BIT5 14481 #define ABT BIT5 14482 #define FRME BIT4 14483 #define RBIT BIT4 14484 #define OVRN BIT3 14485 #define CRCE BIT2 14486 #define WAKEUP_CHARS 256 14487 #if SYNCLINK_GENERIC_HDLC 14488 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14489 #endif 14490 #ifdef SANITY_CHECK 14491 #else 14492 #endif 14493 #if SYNCLINK_GENERIC_HDLC 14494 #endif 14495 #if SYNCLINK_GENERIC_HDLC 14496 #endif 14497 #if SYNCLINK_GENERIC_HDLC 14498 #endif 14499 #ifdef CMSPAR 14500 #endif 14501 /* LDV_COMMENT_END_PREP */ 14502 /* LDV_COMMENT_FUNCTION_CALL Function from field "carrier_raised" from driver structure with callbacks "port_ops" */ 14503 ldv_handler_precall(); 14504 carrier_raised( var_group6); 14505 /* LDV_COMMENT_BEGIN_PREP */ 14506 #if SYNCLINK_GENERIC_HDLC 14507 #endif 14508 #if SYNCLINK_GENERIC_HDLC 14509 #endif 14510 #if 0 14511 #endif 14512 #if SYNCLINK_GENERIC_HDLC 14513 #endif 14514 #if SYNCLINK_GENERIC_HDLC 14515 #endif 14516 #define TESTFRAMESIZE 20 14517 #if SYNCLINK_GENERIC_HDLC 14518 #endif 14519 #define CALC_REGADDR() \ 14520 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14521 if (info->port_num > 1) \ 14522 RegAddr += 256; \ 14523 if ( info->port_num & 1) { \ 14524 if (Addr > 0x7f) \ 14525 RegAddr += 0x40; \ 14526 else if (Addr > 0x1f && Addr < 0x60) \ 14527 RegAddr += 0x20; \ 14528 } 14529 /* LDV_COMMENT_END_PREP */ 14530 14531 14532 14533 14534 } 14535 14536 break; 14537 case 8: { 14538 14539 /** STRUCT: struct type: tty_port_operations, struct name: port_ops **/ 14540 14541 14542 /* content: static void dtr_rts(struct tty_port *port, int on)*/ 14543 /* LDV_COMMENT_BEGIN_PREP */ 14544 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 14545 #if defined(__i386__) 14546 # define BREAKPOINT() asm(" int $3"); 14547 #else 14548 # define BREAKPOINT() { } 14549 #endif 14550 #define MAX_DEVICES 12 14551 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 14552 #define SYNCLINK_GENERIC_HDLC 1 14553 #else 14554 #define SYNCLINK_GENERIC_HDLC 0 14555 #endif 14556 #define GET_USER(error,value,addr) error = get_user(value,addr) 14557 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 14558 #define PUT_USER(error,value,addr) error = put_user(value,addr) 14559 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 14560 #define SCABUFSIZE 1024 14561 #define SCA_MEM_SIZE 0x40000 14562 #define SCA_BASE_SIZE 512 14563 #define SCA_REG_SIZE 16 14564 #define SCA_MAX_PORTS 4 14565 #define SCAMAXDESC 128 14566 #define BUFFERLISTSIZE 4096 14567 #define BH_RECEIVE 1 14568 #define BH_TRANSMIT 2 14569 #define BH_STATUS 4 14570 #define IO_PIN_SHUTDOWN_LIMIT 100 14571 #if SYNCLINK_GENERIC_HDLC 14572 #endif 14573 #define MGSL_MAGIC 0x5401 14574 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 14575 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 14576 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 14577 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 14578 #define LPR 0x00 14579 #define PABR0 0x02 14580 #define PABR1 0x03 14581 #define WCRL 0x04 14582 #define WCRM 0x05 14583 #define WCRH 0x06 14584 #define DPCR 0x08 14585 #define DMER 0x09 14586 #define ISR0 0x10 14587 #define ISR1 0x11 14588 #define ISR2 0x12 14589 #define IER0 0x14 14590 #define IER1 0x15 14591 #define IER2 0x16 14592 #define ITCR 0x18 14593 #define INTVR 0x1a 14594 #define IMVR 0x1c 14595 #define TRB 0x20 14596 #define TRBL 0x20 14597 #define TRBH 0x21 14598 #define SR0 0x22 14599 #define SR1 0x23 14600 #define SR2 0x24 14601 #define SR3 0x25 14602 #define FST 0x26 14603 #define IE0 0x28 14604 #define IE1 0x29 14605 #define IE2 0x2a 14606 #define FIE 0x2b 14607 #define CMD 0x2c 14608 #define MD0 0x2e 14609 #define MD1 0x2f 14610 #define MD2 0x30 14611 #define CTL 0x31 14612 #define SA0 0x32 14613 #define SA1 0x33 14614 #define IDL 0x34 14615 #define TMC 0x35 14616 #define RXS 0x36 14617 #define TXS 0x37 14618 #define TRC0 0x38 14619 #define TRC1 0x39 14620 #define RRC 0x3a 14621 #define CST0 0x3c 14622 #define CST1 0x3d 14623 #define TCNT 0x60 14624 #define TCNTL 0x60 14625 #define TCNTH 0x61 14626 #define TCONR 0x62 14627 #define TCONRL 0x62 14628 #define TCONRH 0x63 14629 #define TMCS 0x64 14630 #define TEPR 0x65 14631 #define DARL 0x80 14632 #define DARH 0x81 14633 #define DARB 0x82 14634 #define BAR 0x80 14635 #define BARL 0x80 14636 #define BARH 0x81 14637 #define BARB 0x82 14638 #define SAR 0x84 14639 #define SARL 0x84 14640 #define SARH 0x85 14641 #define SARB 0x86 14642 #define CPB 0x86 14643 #define CDA 0x88 14644 #define CDAL 0x88 14645 #define CDAH 0x89 14646 #define EDA 0x8a 14647 #define EDAL 0x8a 14648 #define EDAH 0x8b 14649 #define BFL 0x8c 14650 #define BFLL 0x8c 14651 #define BFLH 0x8d 14652 #define BCR 0x8e 14653 #define BCRL 0x8e 14654 #define BCRH 0x8f 14655 #define DSR 0x90 14656 #define DMR 0x91 14657 #define FCT 0x93 14658 #define DIR 0x94 14659 #define DCMD 0x95 14660 #define TIMER0 0x00 14661 #define TIMER1 0x08 14662 #define TIMER2 0x10 14663 #define TIMER3 0x18 14664 #define RXDMA 0x00 14665 #define TXDMA 0x20 14666 #define NOOP 0x00 14667 #define TXRESET 0x01 14668 #define TXENABLE 0x02 14669 #define TXDISABLE 0x03 14670 #define TXCRCINIT 0x04 14671 #define TXCRCEXCL 0x05 14672 #define TXEOM 0x06 14673 #define TXABORT 0x07 14674 #define MPON 0x08 14675 #define TXBUFCLR 0x09 14676 #define RXRESET 0x11 14677 #define RXENABLE 0x12 14678 #define RXDISABLE 0x13 14679 #define RXCRCINIT 0x14 14680 #define RXREJECT 0x15 14681 #define SEARCHMP 0x16 14682 #define RXCRCEXCL 0x17 14683 #define RXCRCCALC 0x18 14684 #define CHRESET 0x21 14685 #define HUNT 0x31 14686 #define SWABORT 0x01 14687 #define FEICLEAR 0x02 14688 #define TXINTE BIT7 14689 #define RXINTE BIT6 14690 #define TXRDYE BIT1 14691 #define RXRDYE BIT0 14692 #define UDRN BIT7 14693 #define IDLE BIT6 14694 #define SYNCD BIT4 14695 #define FLGD BIT4 14696 #define CCTS BIT3 14697 #define CDCD BIT2 14698 #define BRKD BIT1 14699 #define ABTD BIT1 14700 #define GAPD BIT1 14701 #define BRKE BIT0 14702 #define IDLD BIT0 14703 #define EOM BIT7 14704 #define PMP BIT6 14705 #define SHRT BIT6 14706 #define PE BIT5 14707 #define ABT BIT5 14708 #define FRME BIT4 14709 #define RBIT BIT4 14710 #define OVRN BIT3 14711 #define CRCE BIT2 14712 #define WAKEUP_CHARS 256 14713 #if SYNCLINK_GENERIC_HDLC 14714 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14715 #endif 14716 #ifdef SANITY_CHECK 14717 #else 14718 #endif 14719 #if SYNCLINK_GENERIC_HDLC 14720 #endif 14721 #if SYNCLINK_GENERIC_HDLC 14722 #endif 14723 #if SYNCLINK_GENERIC_HDLC 14724 #endif 14725 #ifdef CMSPAR 14726 #endif 14727 /* LDV_COMMENT_END_PREP */ 14728 /* LDV_COMMENT_FUNCTION_CALL Function from field "dtr_rts" from driver structure with callbacks "port_ops" */ 14729 ldv_handler_precall(); 14730 dtr_rts( var_group6, var_dtr_rts_70_p1); 14731 /* LDV_COMMENT_BEGIN_PREP */ 14732 #if SYNCLINK_GENERIC_HDLC 14733 #endif 14734 #if SYNCLINK_GENERIC_HDLC 14735 #endif 14736 #if 0 14737 #endif 14738 #if SYNCLINK_GENERIC_HDLC 14739 #endif 14740 #if SYNCLINK_GENERIC_HDLC 14741 #endif 14742 #define TESTFRAMESIZE 20 14743 #if SYNCLINK_GENERIC_HDLC 14744 #endif 14745 #define CALC_REGADDR() \ 14746 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14747 if (info->port_num > 1) \ 14748 RegAddr += 256; \ 14749 if ( info->port_num & 1) { \ 14750 if (Addr > 0x7f) \ 14751 RegAddr += 0x40; \ 14752 else if (Addr > 0x1f && Addr < 0x60) \ 14753 RegAddr += 0x20; \ 14754 } 14755 /* LDV_COMMENT_END_PREP */ 14756 14757 14758 14759 14760 } 14761 14762 break; 14763 case 9: { 14764 14765 /** STRUCT: struct type: tty_operations, struct name: ops **/ 14766 if(ldv_s_ops_tty_operations==0) { 14767 14768 /* content: static int open(struct tty_struct *tty, struct file *filp)*/ 14769 /* LDV_COMMENT_BEGIN_PREP */ 14770 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 14771 #if defined(__i386__) 14772 # define BREAKPOINT() asm(" int $3"); 14773 #else 14774 # define BREAKPOINT() { } 14775 #endif 14776 #define MAX_DEVICES 12 14777 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 14778 #define SYNCLINK_GENERIC_HDLC 1 14779 #else 14780 #define SYNCLINK_GENERIC_HDLC 0 14781 #endif 14782 #define GET_USER(error,value,addr) error = get_user(value,addr) 14783 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 14784 #define PUT_USER(error,value,addr) error = put_user(value,addr) 14785 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 14786 #define SCABUFSIZE 1024 14787 #define SCA_MEM_SIZE 0x40000 14788 #define SCA_BASE_SIZE 512 14789 #define SCA_REG_SIZE 16 14790 #define SCA_MAX_PORTS 4 14791 #define SCAMAXDESC 128 14792 #define BUFFERLISTSIZE 4096 14793 #define BH_RECEIVE 1 14794 #define BH_TRANSMIT 2 14795 #define BH_STATUS 4 14796 #define IO_PIN_SHUTDOWN_LIMIT 100 14797 #if SYNCLINK_GENERIC_HDLC 14798 #endif 14799 #define MGSL_MAGIC 0x5401 14800 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 14801 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 14802 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 14803 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 14804 #define LPR 0x00 14805 #define PABR0 0x02 14806 #define PABR1 0x03 14807 #define WCRL 0x04 14808 #define WCRM 0x05 14809 #define WCRH 0x06 14810 #define DPCR 0x08 14811 #define DMER 0x09 14812 #define ISR0 0x10 14813 #define ISR1 0x11 14814 #define ISR2 0x12 14815 #define IER0 0x14 14816 #define IER1 0x15 14817 #define IER2 0x16 14818 #define ITCR 0x18 14819 #define INTVR 0x1a 14820 #define IMVR 0x1c 14821 #define TRB 0x20 14822 #define TRBL 0x20 14823 #define TRBH 0x21 14824 #define SR0 0x22 14825 #define SR1 0x23 14826 #define SR2 0x24 14827 #define SR3 0x25 14828 #define FST 0x26 14829 #define IE0 0x28 14830 #define IE1 0x29 14831 #define IE2 0x2a 14832 #define FIE 0x2b 14833 #define CMD 0x2c 14834 #define MD0 0x2e 14835 #define MD1 0x2f 14836 #define MD2 0x30 14837 #define CTL 0x31 14838 #define SA0 0x32 14839 #define SA1 0x33 14840 #define IDL 0x34 14841 #define TMC 0x35 14842 #define RXS 0x36 14843 #define TXS 0x37 14844 #define TRC0 0x38 14845 #define TRC1 0x39 14846 #define RRC 0x3a 14847 #define CST0 0x3c 14848 #define CST1 0x3d 14849 #define TCNT 0x60 14850 #define TCNTL 0x60 14851 #define TCNTH 0x61 14852 #define TCONR 0x62 14853 #define TCONRL 0x62 14854 #define TCONRH 0x63 14855 #define TMCS 0x64 14856 #define TEPR 0x65 14857 #define DARL 0x80 14858 #define DARH 0x81 14859 #define DARB 0x82 14860 #define BAR 0x80 14861 #define BARL 0x80 14862 #define BARH 0x81 14863 #define BARB 0x82 14864 #define SAR 0x84 14865 #define SARL 0x84 14866 #define SARH 0x85 14867 #define SARB 0x86 14868 #define CPB 0x86 14869 #define CDA 0x88 14870 #define CDAL 0x88 14871 #define CDAH 0x89 14872 #define EDA 0x8a 14873 #define EDAL 0x8a 14874 #define EDAH 0x8b 14875 #define BFL 0x8c 14876 #define BFLL 0x8c 14877 #define BFLH 0x8d 14878 #define BCR 0x8e 14879 #define BCRL 0x8e 14880 #define BCRH 0x8f 14881 #define DSR 0x90 14882 #define DMR 0x91 14883 #define FCT 0x93 14884 #define DIR 0x94 14885 #define DCMD 0x95 14886 #define TIMER0 0x00 14887 #define TIMER1 0x08 14888 #define TIMER2 0x10 14889 #define TIMER3 0x18 14890 #define RXDMA 0x00 14891 #define TXDMA 0x20 14892 #define NOOP 0x00 14893 #define TXRESET 0x01 14894 #define TXENABLE 0x02 14895 #define TXDISABLE 0x03 14896 #define TXCRCINIT 0x04 14897 #define TXCRCEXCL 0x05 14898 #define TXEOM 0x06 14899 #define TXABORT 0x07 14900 #define MPON 0x08 14901 #define TXBUFCLR 0x09 14902 #define RXRESET 0x11 14903 #define RXENABLE 0x12 14904 #define RXDISABLE 0x13 14905 #define RXCRCINIT 0x14 14906 #define RXREJECT 0x15 14907 #define SEARCHMP 0x16 14908 #define RXCRCEXCL 0x17 14909 #define RXCRCCALC 0x18 14910 #define CHRESET 0x21 14911 #define HUNT 0x31 14912 #define SWABORT 0x01 14913 #define FEICLEAR 0x02 14914 #define TXINTE BIT7 14915 #define RXINTE BIT6 14916 #define TXRDYE BIT1 14917 #define RXRDYE BIT0 14918 #define UDRN BIT7 14919 #define IDLE BIT6 14920 #define SYNCD BIT4 14921 #define FLGD BIT4 14922 #define CCTS BIT3 14923 #define CDCD BIT2 14924 #define BRKD BIT1 14925 #define ABTD BIT1 14926 #define GAPD BIT1 14927 #define BRKE BIT0 14928 #define IDLD BIT0 14929 #define EOM BIT7 14930 #define PMP BIT6 14931 #define SHRT BIT6 14932 #define PE BIT5 14933 #define ABT BIT5 14934 #define FRME BIT4 14935 #define RBIT BIT4 14936 #define OVRN BIT3 14937 #define CRCE BIT2 14938 #define WAKEUP_CHARS 256 14939 #if SYNCLINK_GENERIC_HDLC 14940 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14941 #endif 14942 #ifdef SANITY_CHECK 14943 #else 14944 #endif 14945 /* LDV_COMMENT_END_PREP */ 14946 /* LDV_COMMENT_FUNCTION_CALL Function from field "open" from driver structure with callbacks "ops". Standart function test for correct return result. */ 14947 ldv_handler_precall(); 14948 res_open_4 = open( var_group8, var_group3); 14949 ldv_check_return_value(res_open_4); 14950 if(res_open_4) 14951 goto ldv_module_exit; 14952 /* LDV_COMMENT_BEGIN_PREP */ 14953 #if SYNCLINK_GENERIC_HDLC 14954 #endif 14955 #if SYNCLINK_GENERIC_HDLC 14956 #endif 14957 #if SYNCLINK_GENERIC_HDLC 14958 #endif 14959 #ifdef CMSPAR 14960 #endif 14961 #if SYNCLINK_GENERIC_HDLC 14962 #endif 14963 #if SYNCLINK_GENERIC_HDLC 14964 #endif 14965 #if 0 14966 #endif 14967 #if SYNCLINK_GENERIC_HDLC 14968 #endif 14969 #if SYNCLINK_GENERIC_HDLC 14970 #endif 14971 #define TESTFRAMESIZE 20 14972 #if SYNCLINK_GENERIC_HDLC 14973 #endif 14974 #define CALC_REGADDR() \ 14975 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14976 if (info->port_num > 1) \ 14977 RegAddr += 256; \ 14978 if ( info->port_num & 1) { \ 14979 if (Addr > 0x7f) \ 14980 RegAddr += 0x40; \ 14981 else if (Addr > 0x1f && Addr < 0x60) \ 14982 RegAddr += 0x20; \ 14983 } 14984 /* LDV_COMMENT_END_PREP */ 14985 ldv_s_ops_tty_operations++; 14986 14987 } 14988 14989 } 14990 14991 break; 14992 case 10: { 14993 14994 /** STRUCT: struct type: tty_operations, struct name: ops **/ 14995 if(ldv_s_ops_tty_operations==1) { 14996 14997 /* content: static void close(struct tty_struct *tty, struct file *filp)*/ 14998 /* LDV_COMMENT_BEGIN_PREP */ 14999 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15000 #if defined(__i386__) 15001 # define BREAKPOINT() asm(" int $3"); 15002 #else 15003 # define BREAKPOINT() { } 15004 #endif 15005 #define MAX_DEVICES 12 15006 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15007 #define SYNCLINK_GENERIC_HDLC 1 15008 #else 15009 #define SYNCLINK_GENERIC_HDLC 0 15010 #endif 15011 #define GET_USER(error,value,addr) error = get_user(value,addr) 15012 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15013 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15014 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15015 #define SCABUFSIZE 1024 15016 #define SCA_MEM_SIZE 0x40000 15017 #define SCA_BASE_SIZE 512 15018 #define SCA_REG_SIZE 16 15019 #define SCA_MAX_PORTS 4 15020 #define SCAMAXDESC 128 15021 #define BUFFERLISTSIZE 4096 15022 #define BH_RECEIVE 1 15023 #define BH_TRANSMIT 2 15024 #define BH_STATUS 4 15025 #define IO_PIN_SHUTDOWN_LIMIT 100 15026 #if SYNCLINK_GENERIC_HDLC 15027 #endif 15028 #define MGSL_MAGIC 0x5401 15029 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15030 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15031 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15032 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15033 #define LPR 0x00 15034 #define PABR0 0x02 15035 #define PABR1 0x03 15036 #define WCRL 0x04 15037 #define WCRM 0x05 15038 #define WCRH 0x06 15039 #define DPCR 0x08 15040 #define DMER 0x09 15041 #define ISR0 0x10 15042 #define ISR1 0x11 15043 #define ISR2 0x12 15044 #define IER0 0x14 15045 #define IER1 0x15 15046 #define IER2 0x16 15047 #define ITCR 0x18 15048 #define INTVR 0x1a 15049 #define IMVR 0x1c 15050 #define TRB 0x20 15051 #define TRBL 0x20 15052 #define TRBH 0x21 15053 #define SR0 0x22 15054 #define SR1 0x23 15055 #define SR2 0x24 15056 #define SR3 0x25 15057 #define FST 0x26 15058 #define IE0 0x28 15059 #define IE1 0x29 15060 #define IE2 0x2a 15061 #define FIE 0x2b 15062 #define CMD 0x2c 15063 #define MD0 0x2e 15064 #define MD1 0x2f 15065 #define MD2 0x30 15066 #define CTL 0x31 15067 #define SA0 0x32 15068 #define SA1 0x33 15069 #define IDL 0x34 15070 #define TMC 0x35 15071 #define RXS 0x36 15072 #define TXS 0x37 15073 #define TRC0 0x38 15074 #define TRC1 0x39 15075 #define RRC 0x3a 15076 #define CST0 0x3c 15077 #define CST1 0x3d 15078 #define TCNT 0x60 15079 #define TCNTL 0x60 15080 #define TCNTH 0x61 15081 #define TCONR 0x62 15082 #define TCONRL 0x62 15083 #define TCONRH 0x63 15084 #define TMCS 0x64 15085 #define TEPR 0x65 15086 #define DARL 0x80 15087 #define DARH 0x81 15088 #define DARB 0x82 15089 #define BAR 0x80 15090 #define BARL 0x80 15091 #define BARH 0x81 15092 #define BARB 0x82 15093 #define SAR 0x84 15094 #define SARL 0x84 15095 #define SARH 0x85 15096 #define SARB 0x86 15097 #define CPB 0x86 15098 #define CDA 0x88 15099 #define CDAL 0x88 15100 #define CDAH 0x89 15101 #define EDA 0x8a 15102 #define EDAL 0x8a 15103 #define EDAH 0x8b 15104 #define BFL 0x8c 15105 #define BFLL 0x8c 15106 #define BFLH 0x8d 15107 #define BCR 0x8e 15108 #define BCRL 0x8e 15109 #define BCRH 0x8f 15110 #define DSR 0x90 15111 #define DMR 0x91 15112 #define FCT 0x93 15113 #define DIR 0x94 15114 #define DCMD 0x95 15115 #define TIMER0 0x00 15116 #define TIMER1 0x08 15117 #define TIMER2 0x10 15118 #define TIMER3 0x18 15119 #define RXDMA 0x00 15120 #define TXDMA 0x20 15121 #define NOOP 0x00 15122 #define TXRESET 0x01 15123 #define TXENABLE 0x02 15124 #define TXDISABLE 0x03 15125 #define TXCRCINIT 0x04 15126 #define TXCRCEXCL 0x05 15127 #define TXEOM 0x06 15128 #define TXABORT 0x07 15129 #define MPON 0x08 15130 #define TXBUFCLR 0x09 15131 #define RXRESET 0x11 15132 #define RXENABLE 0x12 15133 #define RXDISABLE 0x13 15134 #define RXCRCINIT 0x14 15135 #define RXREJECT 0x15 15136 #define SEARCHMP 0x16 15137 #define RXCRCEXCL 0x17 15138 #define RXCRCCALC 0x18 15139 #define CHRESET 0x21 15140 #define HUNT 0x31 15141 #define SWABORT 0x01 15142 #define FEICLEAR 0x02 15143 #define TXINTE BIT7 15144 #define RXINTE BIT6 15145 #define TXRDYE BIT1 15146 #define RXRDYE BIT0 15147 #define UDRN BIT7 15148 #define IDLE BIT6 15149 #define SYNCD BIT4 15150 #define FLGD BIT4 15151 #define CCTS BIT3 15152 #define CDCD BIT2 15153 #define BRKD BIT1 15154 #define ABTD BIT1 15155 #define GAPD BIT1 15156 #define BRKE BIT0 15157 #define IDLD BIT0 15158 #define EOM BIT7 15159 #define PMP BIT6 15160 #define SHRT BIT6 15161 #define PE BIT5 15162 #define ABT BIT5 15163 #define FRME BIT4 15164 #define RBIT BIT4 15165 #define OVRN BIT3 15166 #define CRCE BIT2 15167 #define WAKEUP_CHARS 256 15168 #if SYNCLINK_GENERIC_HDLC 15169 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 15170 #endif 15171 #ifdef SANITY_CHECK 15172 #else 15173 #endif 15174 /* LDV_COMMENT_END_PREP */ 15175 /* LDV_COMMENT_FUNCTION_CALL Function from field "close" from driver structure with callbacks "ops" */ 15176 ldv_handler_precall(); 15177 close( var_group8, var_group3); 15178 /* LDV_COMMENT_BEGIN_PREP */ 15179 #if SYNCLINK_GENERIC_HDLC 15180 #endif 15181 #if SYNCLINK_GENERIC_HDLC 15182 #endif 15183 #if SYNCLINK_GENERIC_HDLC 15184 #endif 15185 #ifdef CMSPAR 15186 #endif 15187 #if SYNCLINK_GENERIC_HDLC 15188 #endif 15189 #if SYNCLINK_GENERIC_HDLC 15190 #endif 15191 #if 0 15192 #endif 15193 #if SYNCLINK_GENERIC_HDLC 15194 #endif 15195 #if SYNCLINK_GENERIC_HDLC 15196 #endif 15197 #define TESTFRAMESIZE 20 15198 #if SYNCLINK_GENERIC_HDLC 15199 #endif 15200 #define CALC_REGADDR() \ 15201 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 15202 if (info->port_num > 1) \ 15203 RegAddr += 256; \ 15204 if ( info->port_num & 1) { \ 15205 if (Addr > 0x7f) \ 15206 RegAddr += 0x40; \ 15207 else if (Addr > 0x1f && Addr < 0x60) \ 15208 RegAddr += 0x20; \ 15209 } 15210 /* LDV_COMMENT_END_PREP */ 15211 ldv_s_ops_tty_operations=0; 15212 15213 } 15214 15215 } 15216 15217 break; 15218 case 11: { 15219 15220 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15221 15222 15223 /* content: static int install(struct tty_driver *driver, struct tty_struct *tty)*/ 15224 /* LDV_COMMENT_BEGIN_PREP */ 15225 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15226 #if defined(__i386__) 15227 # define BREAKPOINT() asm(" int $3"); 15228 #else 15229 # define BREAKPOINT() { } 15230 #endif 15231 #define MAX_DEVICES 12 15232 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15233 #define SYNCLINK_GENERIC_HDLC 1 15234 #else 15235 #define SYNCLINK_GENERIC_HDLC 0 15236 #endif 15237 #define GET_USER(error,value,addr) error = get_user(value,addr) 15238 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15239 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15240 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15241 #define SCABUFSIZE 1024 15242 #define SCA_MEM_SIZE 0x40000 15243 #define SCA_BASE_SIZE 512 15244 #define SCA_REG_SIZE 16 15245 #define SCA_MAX_PORTS 4 15246 #define SCAMAXDESC 128 15247 #define BUFFERLISTSIZE 4096 15248 #define BH_RECEIVE 1 15249 #define BH_TRANSMIT 2 15250 #define BH_STATUS 4 15251 #define IO_PIN_SHUTDOWN_LIMIT 100 15252 #if SYNCLINK_GENERIC_HDLC 15253 #endif 15254 #define MGSL_MAGIC 0x5401 15255 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15256 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15257 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15258 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15259 #define LPR 0x00 15260 #define PABR0 0x02 15261 #define PABR1 0x03 15262 #define WCRL 0x04 15263 #define WCRM 0x05 15264 #define WCRH 0x06 15265 #define DPCR 0x08 15266 #define DMER 0x09 15267 #define ISR0 0x10 15268 #define ISR1 0x11 15269 #define ISR2 0x12 15270 #define IER0 0x14 15271 #define IER1 0x15 15272 #define IER2 0x16 15273 #define ITCR 0x18 15274 #define INTVR 0x1a 15275 #define IMVR 0x1c 15276 #define TRB 0x20 15277 #define TRBL 0x20 15278 #define TRBH 0x21 15279 #define SR0 0x22 15280 #define SR1 0x23 15281 #define SR2 0x24 15282 #define SR3 0x25 15283 #define FST 0x26 15284 #define IE0 0x28 15285 #define IE1 0x29 15286 #define IE2 0x2a 15287 #define FIE 0x2b 15288 #define CMD 0x2c 15289 #define MD0 0x2e 15290 #define MD1 0x2f 15291 #define MD2 0x30 15292 #define CTL 0x31 15293 #define SA0 0x32 15294 #define SA1 0x33 15295 #define IDL 0x34 15296 #define TMC 0x35 15297 #define RXS 0x36 15298 #define TXS 0x37 15299 #define TRC0 0x38 15300 #define TRC1 0x39 15301 #define RRC 0x3a 15302 #define CST0 0x3c 15303 #define CST1 0x3d 15304 #define TCNT 0x60 15305 #define TCNTL 0x60 15306 #define TCNTH 0x61 15307 #define TCONR 0x62 15308 #define TCONRL 0x62 15309 #define TCONRH 0x63 15310 #define TMCS 0x64 15311 #define TEPR 0x65 15312 #define DARL 0x80 15313 #define DARH 0x81 15314 #define DARB 0x82 15315 #define BAR 0x80 15316 #define BARL 0x80 15317 #define BARH 0x81 15318 #define BARB 0x82 15319 #define SAR 0x84 15320 #define SARL 0x84 15321 #define SARH 0x85 15322 #define SARB 0x86 15323 #define CPB 0x86 15324 #define CDA 0x88 15325 #define CDAL 0x88 15326 #define CDAH 0x89 15327 #define EDA 0x8a 15328 #define EDAL 0x8a 15329 #define EDAH 0x8b 15330 #define BFL 0x8c 15331 #define BFLL 0x8c 15332 #define BFLH 0x8d 15333 #define BCR 0x8e 15334 #define BCRL 0x8e 15335 #define BCRH 0x8f 15336 #define DSR 0x90 15337 #define DMR 0x91 15338 #define FCT 0x93 15339 #define DIR 0x94 15340 #define DCMD 0x95 15341 #define TIMER0 0x00 15342 #define TIMER1 0x08 15343 #define TIMER2 0x10 15344 #define TIMER3 0x18 15345 #define RXDMA 0x00 15346 #define TXDMA 0x20 15347 #define NOOP 0x00 15348 #define TXRESET 0x01 15349 #define TXENABLE 0x02 15350 #define TXDISABLE 0x03 15351 #define TXCRCINIT 0x04 15352 #define TXCRCEXCL 0x05 15353 #define TXEOM 0x06 15354 #define TXABORT 0x07 15355 #define MPON 0x08 15356 #define TXBUFCLR 0x09 15357 #define RXRESET 0x11 15358 #define RXENABLE 0x12 15359 #define RXDISABLE 0x13 15360 #define RXCRCINIT 0x14 15361 #define RXREJECT 0x15 15362 #define SEARCHMP 0x16 15363 #define RXCRCEXCL 0x17 15364 #define RXCRCCALC 0x18 15365 #define CHRESET 0x21 15366 #define HUNT 0x31 15367 #define SWABORT 0x01 15368 #define FEICLEAR 0x02 15369 #define TXINTE BIT7 15370 #define RXINTE BIT6 15371 #define TXRDYE BIT1 15372 #define RXRDYE BIT0 15373 #define UDRN BIT7 15374 #define IDLE BIT6 15375 #define SYNCD BIT4 15376 #define FLGD BIT4 15377 #define CCTS BIT3 15378 #define CDCD BIT2 15379 #define BRKD BIT1 15380 #define ABTD BIT1 15381 #define GAPD BIT1 15382 #define BRKE BIT0 15383 #define IDLD BIT0 15384 #define EOM BIT7 15385 #define PMP BIT6 15386 #define SHRT BIT6 15387 #define PE BIT5 15388 #define ABT BIT5 15389 #define FRME BIT4 15390 #define RBIT BIT4 15391 #define OVRN BIT3 15392 #define CRCE BIT2 15393 #define WAKEUP_CHARS 256 15394 #if SYNCLINK_GENERIC_HDLC 15395 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 15396 #endif 15397 #ifdef SANITY_CHECK 15398 #else 15399 #endif 15400 /* LDV_COMMENT_END_PREP */ 15401 /* LDV_COMMENT_FUNCTION_CALL Function from field "install" from driver structure with callbacks "ops" */ 15402 ldv_handler_precall(); 15403 install( var_group7, var_group8); 15404 /* LDV_COMMENT_BEGIN_PREP */ 15405 #if SYNCLINK_GENERIC_HDLC 15406 #endif 15407 #if SYNCLINK_GENERIC_HDLC 15408 #endif 15409 #if SYNCLINK_GENERIC_HDLC 15410 #endif 15411 #ifdef CMSPAR 15412 #endif 15413 #if SYNCLINK_GENERIC_HDLC 15414 #endif 15415 #if SYNCLINK_GENERIC_HDLC 15416 #endif 15417 #if 0 15418 #endif 15419 #if SYNCLINK_GENERIC_HDLC 15420 #endif 15421 #if SYNCLINK_GENERIC_HDLC 15422 #endif 15423 #define TESTFRAMESIZE 20 15424 #if SYNCLINK_GENERIC_HDLC 15425 #endif 15426 #define CALC_REGADDR() \ 15427 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 15428 if (info->port_num > 1) \ 15429 RegAddr += 256; \ 15430 if ( info->port_num & 1) { \ 15431 if (Addr > 0x7f) \ 15432 RegAddr += 0x40; \ 15433 else if (Addr > 0x1f && Addr < 0x60) \ 15434 RegAddr += 0x20; \ 15435 } 15436 /* LDV_COMMENT_END_PREP */ 15437 15438 15439 15440 15441 } 15442 15443 break; 15444 case 12: { 15445 15446 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15447 15448 15449 /* content: static int write(struct tty_struct *tty, const unsigned char *buf, int count)*/ 15450 /* LDV_COMMENT_BEGIN_PREP */ 15451 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15452 #if defined(__i386__) 15453 # define BREAKPOINT() asm(" int $3"); 15454 #else 15455 # define BREAKPOINT() { } 15456 #endif 15457 #define MAX_DEVICES 12 15458 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15459 #define SYNCLINK_GENERIC_HDLC 1 15460 #else 15461 #define SYNCLINK_GENERIC_HDLC 0 15462 #endif 15463 #define GET_USER(error,value,addr) error = get_user(value,addr) 15464 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15465 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15466 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15467 #define SCABUFSIZE 1024 15468 #define SCA_MEM_SIZE 0x40000 15469 #define SCA_BASE_SIZE 512 15470 #define SCA_REG_SIZE 16 15471 #define SCA_MAX_PORTS 4 15472 #define SCAMAXDESC 128 15473 #define BUFFERLISTSIZE 4096 15474 #define BH_RECEIVE 1 15475 #define BH_TRANSMIT 2 15476 #define BH_STATUS 4 15477 #define IO_PIN_SHUTDOWN_LIMIT 100 15478 #if SYNCLINK_GENERIC_HDLC 15479 #endif 15480 #define MGSL_MAGIC 0x5401 15481 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15482 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15483 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15484 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15485 #define LPR 0x00 15486 #define PABR0 0x02 15487 #define PABR1 0x03 15488 #define WCRL 0x04 15489 #define WCRM 0x05 15490 #define WCRH 0x06 15491 #define DPCR 0x08 15492 #define DMER 0x09 15493 #define ISR0 0x10 15494 #define ISR1 0x11 15495 #define ISR2 0x12 15496 #define IER0 0x14 15497 #define IER1 0x15 15498 #define IER2 0x16 15499 #define ITCR 0x18 15500 #define INTVR 0x1a 15501 #define IMVR 0x1c 15502 #define TRB 0x20 15503 #define TRBL 0x20 15504 #define TRBH 0x21 15505 #define SR0 0x22 15506 #define SR1 0x23 15507 #define SR2 0x24 15508 #define SR3 0x25 15509 #define FST 0x26 15510 #define IE0 0x28 15511 #define IE1 0x29 15512 #define IE2 0x2a 15513 #define FIE 0x2b 15514 #define CMD 0x2c 15515 #define MD0 0x2e 15516 #define MD1 0x2f 15517 #define MD2 0x30 15518 #define CTL 0x31 15519 #define SA0 0x32 15520 #define SA1 0x33 15521 #define IDL 0x34 15522 #define TMC 0x35 15523 #define RXS 0x36 15524 #define TXS 0x37 15525 #define TRC0 0x38 15526 #define TRC1 0x39 15527 #define RRC 0x3a 15528 #define CST0 0x3c 15529 #define CST1 0x3d 15530 #define TCNT 0x60 15531 #define TCNTL 0x60 15532 #define TCNTH 0x61 15533 #define TCONR 0x62 15534 #define TCONRL 0x62 15535 #define TCONRH 0x63 15536 #define TMCS 0x64 15537 #define TEPR 0x65 15538 #define DARL 0x80 15539 #define DARH 0x81 15540 #define DARB 0x82 15541 #define BAR 0x80 15542 #define BARL 0x80 15543 #define BARH 0x81 15544 #define BARB 0x82 15545 #define SAR 0x84 15546 #define SARL 0x84 15547 #define SARH 0x85 15548 #define SARB 0x86 15549 #define CPB 0x86 15550 #define CDA 0x88 15551 #define CDAL 0x88 15552 #define CDAH 0x89 15553 #define EDA 0x8a 15554 #define EDAL 0x8a 15555 #define EDAH 0x8b 15556 #define BFL 0x8c 15557 #define BFLL 0x8c 15558 #define BFLH 0x8d 15559 #define BCR 0x8e 15560 #define BCRL 0x8e 15561 #define BCRH 0x8f 15562 #define DSR 0x90 15563 #define DMR 0x91 15564 #define FCT 0x93 15565 #define DIR 0x94 15566 #define DCMD 0x95 15567 #define TIMER0 0x00 15568 #define TIMER1 0x08 15569 #define TIMER2 0x10 15570 #define TIMER3 0x18 15571 #define RXDMA 0x00 15572 #define TXDMA 0x20 15573 #define NOOP 0x00 15574 #define TXRESET 0x01 15575 #define TXENABLE 0x02 15576 #define TXDISABLE 0x03 15577 #define TXCRCINIT 0x04 15578 #define TXCRCEXCL 0x05 15579 #define TXEOM 0x06 15580 #define TXABORT 0x07 15581 #define MPON 0x08 15582 #define TXBUFCLR 0x09 15583 #define RXRESET 0x11 15584 #define RXENABLE 0x12 15585 #define RXDISABLE 0x13 15586 #define RXCRCINIT 0x14 15587 #define RXREJECT 0x15 15588 #define SEARCHMP 0x16 15589 #define RXCRCEXCL 0x17 15590 #define RXCRCCALC 0x18 15591 #define CHRESET 0x21 15592 #define HUNT 0x31 15593 #define SWABORT 0x01 15594 #define FEICLEAR 0x02 15595 #define TXINTE BIT7 15596 #define RXINTE BIT6 15597 #define TXRDYE BIT1 15598 #define RXRDYE BIT0 15599 #define UDRN BIT7 15600 #define IDLE BIT6 15601 #define SYNCD BIT4 15602 #define FLGD BIT4 15603 #define CCTS BIT3 15604 #define CDCD BIT2 15605 #define BRKD BIT1 15606 #define ABTD BIT1 15607 #define GAPD BIT1 15608 #define BRKE BIT0 15609 #define IDLD BIT0 15610 #define EOM BIT7 15611 #define PMP BIT6 15612 #define SHRT BIT6 15613 #define PE BIT5 15614 #define ABT BIT5 15615 #define FRME BIT4 15616 #define RBIT BIT4 15617 #define OVRN BIT3 15618 #define CRCE BIT2 15619 #define WAKEUP_CHARS 256 15620 #if SYNCLINK_GENERIC_HDLC 15621 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 15622 #endif 15623 #ifdef SANITY_CHECK 15624 #else 15625 #endif 15626 /* LDV_COMMENT_END_PREP */ 15627 /* LDV_COMMENT_FUNCTION_CALL Function from field "write" from driver structure with callbacks "ops" */ 15628 ldv_handler_precall(); 15629 write( var_group8, var_write_8_p1, var_write_8_p2); 15630 /* LDV_COMMENT_BEGIN_PREP */ 15631 #if SYNCLINK_GENERIC_HDLC 15632 #endif 15633 #if SYNCLINK_GENERIC_HDLC 15634 #endif 15635 #if SYNCLINK_GENERIC_HDLC 15636 #endif 15637 #ifdef CMSPAR 15638 #endif 15639 #if SYNCLINK_GENERIC_HDLC 15640 #endif 15641 #if SYNCLINK_GENERIC_HDLC 15642 #endif 15643 #if 0 15644 #endif 15645 #if SYNCLINK_GENERIC_HDLC 15646 #endif 15647 #if SYNCLINK_GENERIC_HDLC 15648 #endif 15649 #define TESTFRAMESIZE 20 15650 #if SYNCLINK_GENERIC_HDLC 15651 #endif 15652 #define CALC_REGADDR() \ 15653 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 15654 if (info->port_num > 1) \ 15655 RegAddr += 256; \ 15656 if ( info->port_num & 1) { \ 15657 if (Addr > 0x7f) \ 15658 RegAddr += 0x40; \ 15659 else if (Addr > 0x1f && Addr < 0x60) \ 15660 RegAddr += 0x20; \ 15661 } 15662 /* LDV_COMMENT_END_PREP */ 15663 15664 15665 15666 15667 } 15668 15669 break; 15670 case 13: { 15671 15672 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15673 15674 15675 /* content: static int put_char(struct tty_struct *tty, unsigned char ch)*/ 15676 /* LDV_COMMENT_BEGIN_PREP */ 15677 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15678 #if defined(__i386__) 15679 # define BREAKPOINT() asm(" int $3"); 15680 #else 15681 # define BREAKPOINT() { } 15682 #endif 15683 #define MAX_DEVICES 12 15684 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15685 #define SYNCLINK_GENERIC_HDLC 1 15686 #else 15687 #define SYNCLINK_GENERIC_HDLC 0 15688 #endif 15689 #define GET_USER(error,value,addr) error = get_user(value,addr) 15690 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15691 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15692 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15693 #define SCABUFSIZE 1024 15694 #define SCA_MEM_SIZE 0x40000 15695 #define SCA_BASE_SIZE 512 15696 #define SCA_REG_SIZE 16 15697 #define SCA_MAX_PORTS 4 15698 #define SCAMAXDESC 128 15699 #define BUFFERLISTSIZE 4096 15700 #define BH_RECEIVE 1 15701 #define BH_TRANSMIT 2 15702 #define BH_STATUS 4 15703 #define IO_PIN_SHUTDOWN_LIMIT 100 15704 #if SYNCLINK_GENERIC_HDLC 15705 #endif 15706 #define MGSL_MAGIC 0x5401 15707 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15708 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15709 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15710 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15711 #define LPR 0x00 15712 #define PABR0 0x02 15713 #define PABR1 0x03 15714 #define WCRL 0x04 15715 #define WCRM 0x05 15716 #define WCRH 0x06 15717 #define DPCR 0x08 15718 #define DMER 0x09 15719 #define ISR0 0x10 15720 #define ISR1 0x11 15721 #define ISR2 0x12 15722 #define IER0 0x14 15723 #define IER1 0x15 15724 #define IER2 0x16 15725 #define ITCR 0x18 15726 #define INTVR 0x1a 15727 #define IMVR 0x1c 15728 #define TRB 0x20 15729 #define TRBL 0x20 15730 #define TRBH 0x21 15731 #define SR0 0x22 15732 #define SR1 0x23 15733 #define SR2 0x24 15734 #define SR3 0x25 15735 #define FST 0x26 15736 #define IE0 0x28 15737 #define IE1 0x29 15738 #define IE2 0x2a 15739 #define FIE 0x2b 15740 #define CMD 0x2c 15741 #define MD0 0x2e 15742 #define MD1 0x2f 15743 #define MD2 0x30 15744 #define CTL 0x31 15745 #define SA0 0x32 15746 #define SA1 0x33 15747 #define IDL 0x34 15748 #define TMC 0x35 15749 #define RXS 0x36 15750 #define TXS 0x37 15751 #define TRC0 0x38 15752 #define TRC1 0x39 15753 #define RRC 0x3a 15754 #define CST0 0x3c 15755 #define CST1 0x3d 15756 #define TCNT 0x60 15757 #define TCNTL 0x60 15758 #define TCNTH 0x61 15759 #define TCONR 0x62 15760 #define TCONRL 0x62 15761 #define TCONRH 0x63 15762 #define TMCS 0x64 15763 #define TEPR 0x65 15764 #define DARL 0x80 15765 #define DARH 0x81 15766 #define DARB 0x82 15767 #define BAR 0x80 15768 #define BARL 0x80 15769 #define BARH 0x81 15770 #define BARB 0x82 15771 #define SAR 0x84 15772 #define SARL 0x84 15773 #define SARH 0x85 15774 #define SARB 0x86 15775 #define CPB 0x86 15776 #define CDA 0x88 15777 #define CDAL 0x88 15778 #define CDAH 0x89 15779 #define EDA 0x8a 15780 #define EDAL 0x8a 15781 #define EDAH 0x8b 15782 #define BFL 0x8c 15783 #define BFLL 0x8c 15784 #define BFLH 0x8d 15785 #define BCR 0x8e 15786 #define BCRL 0x8e 15787 #define BCRH 0x8f 15788 #define DSR 0x90 15789 #define DMR 0x91 15790 #define FCT 0x93 15791 #define DIR 0x94 15792 #define DCMD 0x95 15793 #define TIMER0 0x00 15794 #define TIMER1 0x08 15795 #define TIMER2 0x10 15796 #define TIMER3 0x18 15797 #define RXDMA 0x00 15798 #define TXDMA 0x20 15799 #define NOOP 0x00 15800 #define TXRESET 0x01 15801 #define TXENABLE 0x02 15802 #define TXDISABLE 0x03 15803 #define TXCRCINIT 0x04 15804 #define TXCRCEXCL 0x05 15805 #define TXEOM 0x06 15806 #define TXABORT 0x07 15807 #define MPON 0x08 15808 #define TXBUFCLR 0x09 15809 #define RXRESET 0x11 15810 #define RXENABLE 0x12 15811 #define RXDISABLE 0x13 15812 #define RXCRCINIT 0x14 15813 #define RXREJECT 0x15 15814 #define SEARCHMP 0x16 15815 #define RXCRCEXCL 0x17 15816 #define RXCRCCALC 0x18 15817 #define CHRESET 0x21 15818 #define HUNT 0x31 15819 #define SWABORT 0x01 15820 #define FEICLEAR 0x02 15821 #define TXINTE BIT7 15822 #define RXINTE BIT6 15823 #define TXRDYE BIT1 15824 #define RXRDYE BIT0 15825 #define UDRN BIT7 15826 #define IDLE BIT6 15827 #define SYNCD BIT4 15828 #define FLGD BIT4 15829 #define CCTS BIT3 15830 #define CDCD BIT2 15831 #define BRKD BIT1 15832 #define ABTD BIT1 15833 #define GAPD BIT1 15834 #define BRKE BIT0 15835 #define IDLD BIT0 15836 #define EOM BIT7 15837 #define PMP BIT6 15838 #define SHRT BIT6 15839 #define PE BIT5 15840 #define ABT BIT5 15841 #define FRME BIT4 15842 #define RBIT BIT4 15843 #define OVRN BIT3 15844 #define CRCE BIT2 15845 #define WAKEUP_CHARS 256 15846 #if SYNCLINK_GENERIC_HDLC 15847 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 15848 #endif 15849 #ifdef SANITY_CHECK 15850 #else 15851 #endif 15852 /* LDV_COMMENT_END_PREP */ 15853 /* LDV_COMMENT_FUNCTION_CALL Function from field "put_char" from driver structure with callbacks "ops" */ 15854 ldv_handler_precall(); 15855 put_char( var_group8, var_put_char_9_p1); 15856 /* LDV_COMMENT_BEGIN_PREP */ 15857 #if SYNCLINK_GENERIC_HDLC 15858 #endif 15859 #if SYNCLINK_GENERIC_HDLC 15860 #endif 15861 #if SYNCLINK_GENERIC_HDLC 15862 #endif 15863 #ifdef CMSPAR 15864 #endif 15865 #if SYNCLINK_GENERIC_HDLC 15866 #endif 15867 #if SYNCLINK_GENERIC_HDLC 15868 #endif 15869 #if 0 15870 #endif 15871 #if SYNCLINK_GENERIC_HDLC 15872 #endif 15873 #if SYNCLINK_GENERIC_HDLC 15874 #endif 15875 #define TESTFRAMESIZE 20 15876 #if SYNCLINK_GENERIC_HDLC 15877 #endif 15878 #define CALC_REGADDR() \ 15879 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 15880 if (info->port_num > 1) \ 15881 RegAddr += 256; \ 15882 if ( info->port_num & 1) { \ 15883 if (Addr > 0x7f) \ 15884 RegAddr += 0x40; \ 15885 else if (Addr > 0x1f && Addr < 0x60) \ 15886 RegAddr += 0x20; \ 15887 } 15888 /* LDV_COMMENT_END_PREP */ 15889 15890 15891 15892 15893 } 15894 15895 break; 15896 case 14: { 15897 15898 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15899 15900 15901 /* content: static void flush_chars(struct tty_struct *tty)*/ 15902 /* LDV_COMMENT_BEGIN_PREP */ 15903 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15904 #if defined(__i386__) 15905 # define BREAKPOINT() asm(" int $3"); 15906 #else 15907 # define BREAKPOINT() { } 15908 #endif 15909 #define MAX_DEVICES 12 15910 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15911 #define SYNCLINK_GENERIC_HDLC 1 15912 #else 15913 #define SYNCLINK_GENERIC_HDLC 0 15914 #endif 15915 #define GET_USER(error,value,addr) error = get_user(value,addr) 15916 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15917 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15918 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15919 #define SCABUFSIZE 1024 15920 #define SCA_MEM_SIZE 0x40000 15921 #define SCA_BASE_SIZE 512 15922 #define SCA_REG_SIZE 16 15923 #define SCA_MAX_PORTS 4 15924 #define SCAMAXDESC 128 15925 #define BUFFERLISTSIZE 4096 15926 #define BH_RECEIVE 1 15927 #define BH_TRANSMIT 2 15928 #define BH_STATUS 4 15929 #define IO_PIN_SHUTDOWN_LIMIT 100 15930 #if SYNCLINK_GENERIC_HDLC 15931 #endif 15932 #define MGSL_MAGIC 0x5401 15933 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15934 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15935 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15936 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15937 #define LPR 0x00 15938 #define PABR0 0x02 15939 #define PABR1 0x03 15940 #define WCRL 0x04 15941 #define WCRM 0x05 15942 #define WCRH 0x06 15943 #define DPCR 0x08 15944 #define DMER 0x09 15945 #define ISR0 0x10 15946 #define ISR1 0x11 15947 #define ISR2 0x12 15948 #define IER0 0x14 15949 #define IER1 0x15 15950 #define IER2 0x16 15951 #define ITCR 0x18 15952 #define INTVR 0x1a 15953 #define IMVR 0x1c 15954 #define TRB 0x20 15955 #define TRBL 0x20 15956 #define TRBH 0x21 15957 #define SR0 0x22 15958 #define SR1 0x23 15959 #define SR2 0x24 15960 #define SR3 0x25 15961 #define FST 0x26 15962 #define IE0 0x28 15963 #define IE1 0x29 15964 #define IE2 0x2a 15965 #define FIE 0x2b 15966 #define CMD 0x2c 15967 #define MD0 0x2e 15968 #define MD1 0x2f 15969 #define MD2 0x30 15970 #define CTL 0x31 15971 #define SA0 0x32 15972 #define SA1 0x33 15973 #define IDL 0x34 15974 #define TMC 0x35 15975 #define RXS 0x36 15976 #define TXS 0x37 15977 #define TRC0 0x38 15978 #define TRC1 0x39 15979 #define RRC 0x3a 15980 #define CST0 0x3c 15981 #define CST1 0x3d 15982 #define TCNT 0x60 15983 #define TCNTL 0x60 15984 #define TCNTH 0x61 15985 #define TCONR 0x62 15986 #define TCONRL 0x62 15987 #define TCONRH 0x63 15988 #define TMCS 0x64 15989 #define TEPR 0x65 15990 #define DARL 0x80 15991 #define DARH 0x81 15992 #define DARB 0x82 15993 #define BAR 0x80 15994 #define BARL 0x80 15995 #define BARH 0x81 15996 #define BARB 0x82 15997 #define SAR 0x84 15998 #define SARL 0x84 15999 #define SARH 0x85 16000 #define SARB 0x86 16001 #define CPB 0x86 16002 #define CDA 0x88 16003 #define CDAL 0x88 16004 #define CDAH 0x89 16005 #define EDA 0x8a 16006 #define EDAL 0x8a 16007 #define EDAH 0x8b 16008 #define BFL 0x8c 16009 #define BFLL 0x8c 16010 #define BFLH 0x8d 16011 #define BCR 0x8e 16012 #define BCRL 0x8e 16013 #define BCRH 0x8f 16014 #define DSR 0x90 16015 #define DMR 0x91 16016 #define FCT 0x93 16017 #define DIR 0x94 16018 #define DCMD 0x95 16019 #define TIMER0 0x00 16020 #define TIMER1 0x08 16021 #define TIMER2 0x10 16022 #define TIMER3 0x18 16023 #define RXDMA 0x00 16024 #define TXDMA 0x20 16025 #define NOOP 0x00 16026 #define TXRESET 0x01 16027 #define TXENABLE 0x02 16028 #define TXDISABLE 0x03 16029 #define TXCRCINIT 0x04 16030 #define TXCRCEXCL 0x05 16031 #define TXEOM 0x06 16032 #define TXABORT 0x07 16033 #define MPON 0x08 16034 #define TXBUFCLR 0x09 16035 #define RXRESET 0x11 16036 #define RXENABLE 0x12 16037 #define RXDISABLE 0x13 16038 #define RXCRCINIT 0x14 16039 #define RXREJECT 0x15 16040 #define SEARCHMP 0x16 16041 #define RXCRCEXCL 0x17 16042 #define RXCRCCALC 0x18 16043 #define CHRESET 0x21 16044 #define HUNT 0x31 16045 #define SWABORT 0x01 16046 #define FEICLEAR 0x02 16047 #define TXINTE BIT7 16048 #define RXINTE BIT6 16049 #define TXRDYE BIT1 16050 #define RXRDYE BIT0 16051 #define UDRN BIT7 16052 #define IDLE BIT6 16053 #define SYNCD BIT4 16054 #define FLGD BIT4 16055 #define CCTS BIT3 16056 #define CDCD BIT2 16057 #define BRKD BIT1 16058 #define ABTD BIT1 16059 #define GAPD BIT1 16060 #define BRKE BIT0 16061 #define IDLD BIT0 16062 #define EOM BIT7 16063 #define PMP BIT6 16064 #define SHRT BIT6 16065 #define PE BIT5 16066 #define ABT BIT5 16067 #define FRME BIT4 16068 #define RBIT BIT4 16069 #define OVRN BIT3 16070 #define CRCE BIT2 16071 #define WAKEUP_CHARS 256 16072 #if SYNCLINK_GENERIC_HDLC 16073 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16074 #endif 16075 #ifdef SANITY_CHECK 16076 #else 16077 #endif 16078 /* LDV_COMMENT_END_PREP */ 16079 /* LDV_COMMENT_FUNCTION_CALL Function from field "flush_chars" from driver structure with callbacks "ops" */ 16080 ldv_handler_precall(); 16081 flush_chars( var_group8); 16082 /* LDV_COMMENT_BEGIN_PREP */ 16083 #if SYNCLINK_GENERIC_HDLC 16084 #endif 16085 #if SYNCLINK_GENERIC_HDLC 16086 #endif 16087 #if SYNCLINK_GENERIC_HDLC 16088 #endif 16089 #ifdef CMSPAR 16090 #endif 16091 #if SYNCLINK_GENERIC_HDLC 16092 #endif 16093 #if SYNCLINK_GENERIC_HDLC 16094 #endif 16095 #if 0 16096 #endif 16097 #if SYNCLINK_GENERIC_HDLC 16098 #endif 16099 #if SYNCLINK_GENERIC_HDLC 16100 #endif 16101 #define TESTFRAMESIZE 20 16102 #if SYNCLINK_GENERIC_HDLC 16103 #endif 16104 #define CALC_REGADDR() \ 16105 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 16106 if (info->port_num > 1) \ 16107 RegAddr += 256; \ 16108 if ( info->port_num & 1) { \ 16109 if (Addr > 0x7f) \ 16110 RegAddr += 0x40; \ 16111 else if (Addr > 0x1f && Addr < 0x60) \ 16112 RegAddr += 0x20; \ 16113 } 16114 /* LDV_COMMENT_END_PREP */ 16115 16116 16117 16118 16119 } 16120 16121 break; 16122 case 15: { 16123 16124 /** STRUCT: struct type: tty_operations, struct name: ops **/ 16125 16126 16127 /* content: static int write_room(struct tty_struct *tty)*/ 16128 /* LDV_COMMENT_BEGIN_PREP */ 16129 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 16130 #if defined(__i386__) 16131 # define BREAKPOINT() asm(" int $3"); 16132 #else 16133 # define BREAKPOINT() { } 16134 #endif 16135 #define MAX_DEVICES 12 16136 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 16137 #define SYNCLINK_GENERIC_HDLC 1 16138 #else 16139 #define SYNCLINK_GENERIC_HDLC 0 16140 #endif 16141 #define GET_USER(error,value,addr) error = get_user(value,addr) 16142 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 16143 #define PUT_USER(error,value,addr) error = put_user(value,addr) 16144 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 16145 #define SCABUFSIZE 1024 16146 #define SCA_MEM_SIZE 0x40000 16147 #define SCA_BASE_SIZE 512 16148 #define SCA_REG_SIZE 16 16149 #define SCA_MAX_PORTS 4 16150 #define SCAMAXDESC 128 16151 #define BUFFERLISTSIZE 4096 16152 #define BH_RECEIVE 1 16153 #define BH_TRANSMIT 2 16154 #define BH_STATUS 4 16155 #define IO_PIN_SHUTDOWN_LIMIT 100 16156 #if SYNCLINK_GENERIC_HDLC 16157 #endif 16158 #define MGSL_MAGIC 0x5401 16159 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 16160 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 16161 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 16162 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 16163 #define LPR 0x00 16164 #define PABR0 0x02 16165 #define PABR1 0x03 16166 #define WCRL 0x04 16167 #define WCRM 0x05 16168 #define WCRH 0x06 16169 #define DPCR 0x08 16170 #define DMER 0x09 16171 #define ISR0 0x10 16172 #define ISR1 0x11 16173 #define ISR2 0x12 16174 #define IER0 0x14 16175 #define IER1 0x15 16176 #define IER2 0x16 16177 #define ITCR 0x18 16178 #define INTVR 0x1a 16179 #define IMVR 0x1c 16180 #define TRB 0x20 16181 #define TRBL 0x20 16182 #define TRBH 0x21 16183 #define SR0 0x22 16184 #define SR1 0x23 16185 #define SR2 0x24 16186 #define SR3 0x25 16187 #define FST 0x26 16188 #define IE0 0x28 16189 #define IE1 0x29 16190 #define IE2 0x2a 16191 #define FIE 0x2b 16192 #define CMD 0x2c 16193 #define MD0 0x2e 16194 #define MD1 0x2f 16195 #define MD2 0x30 16196 #define CTL 0x31 16197 #define SA0 0x32 16198 #define SA1 0x33 16199 #define IDL 0x34 16200 #define TMC 0x35 16201 #define RXS 0x36 16202 #define TXS 0x37 16203 #define TRC0 0x38 16204 #define TRC1 0x39 16205 #define RRC 0x3a 16206 #define CST0 0x3c 16207 #define CST1 0x3d 16208 #define TCNT 0x60 16209 #define TCNTL 0x60 16210 #define TCNTH 0x61 16211 #define TCONR 0x62 16212 #define TCONRL 0x62 16213 #define TCONRH 0x63 16214 #define TMCS 0x64 16215 #define TEPR 0x65 16216 #define DARL 0x80 16217 #define DARH 0x81 16218 #define DARB 0x82 16219 #define BAR 0x80 16220 #define BARL 0x80 16221 #define BARH 0x81 16222 #define BARB 0x82 16223 #define SAR 0x84 16224 #define SARL 0x84 16225 #define SARH 0x85 16226 #define SARB 0x86 16227 #define CPB 0x86 16228 #define CDA 0x88 16229 #define CDAL 0x88 16230 #define CDAH 0x89 16231 #define EDA 0x8a 16232 #define EDAL 0x8a 16233 #define EDAH 0x8b 16234 #define BFL 0x8c 16235 #define BFLL 0x8c 16236 #define BFLH 0x8d 16237 #define BCR 0x8e 16238 #define BCRL 0x8e 16239 #define BCRH 0x8f 16240 #define DSR 0x90 16241 #define DMR 0x91 16242 #define FCT 0x93 16243 #define DIR 0x94 16244 #define DCMD 0x95 16245 #define TIMER0 0x00 16246 #define TIMER1 0x08 16247 #define TIMER2 0x10 16248 #define TIMER3 0x18 16249 #define RXDMA 0x00 16250 #define TXDMA 0x20 16251 #define NOOP 0x00 16252 #define TXRESET 0x01 16253 #define TXENABLE 0x02 16254 #define TXDISABLE 0x03 16255 #define TXCRCINIT 0x04 16256 #define TXCRCEXCL 0x05 16257 #define TXEOM 0x06 16258 #define TXABORT 0x07 16259 #define MPON 0x08 16260 #define TXBUFCLR 0x09 16261 #define RXRESET 0x11 16262 #define RXENABLE 0x12 16263 #define RXDISABLE 0x13 16264 #define RXCRCINIT 0x14 16265 #define RXREJECT 0x15 16266 #define SEARCHMP 0x16 16267 #define RXCRCEXCL 0x17 16268 #define RXCRCCALC 0x18 16269 #define CHRESET 0x21 16270 #define HUNT 0x31 16271 #define SWABORT 0x01 16272 #define FEICLEAR 0x02 16273 #define TXINTE BIT7 16274 #define RXINTE BIT6 16275 #define TXRDYE BIT1 16276 #define RXRDYE BIT0 16277 #define UDRN BIT7 16278 #define IDLE BIT6 16279 #define SYNCD BIT4 16280 #define FLGD BIT4 16281 #define CCTS BIT3 16282 #define CDCD BIT2 16283 #define BRKD BIT1 16284 #define ABTD BIT1 16285 #define GAPD BIT1 16286 #define BRKE BIT0 16287 #define IDLD BIT0 16288 #define EOM BIT7 16289 #define PMP BIT6 16290 #define SHRT BIT6 16291 #define PE BIT5 16292 #define ABT BIT5 16293 #define FRME BIT4 16294 #define RBIT BIT4 16295 #define OVRN BIT3 16296 #define CRCE BIT2 16297 #define WAKEUP_CHARS 256 16298 #if SYNCLINK_GENERIC_HDLC 16299 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16300 #endif 16301 #ifdef SANITY_CHECK 16302 #else 16303 #endif 16304 /* LDV_COMMENT_END_PREP */ 16305 /* LDV_COMMENT_FUNCTION_CALL Function from field "write_room" from driver structure with callbacks "ops" */ 16306 ldv_handler_precall(); 16307 write_room( var_group8); 16308 /* LDV_COMMENT_BEGIN_PREP */ 16309 #if SYNCLINK_GENERIC_HDLC 16310 #endif 16311 #if SYNCLINK_GENERIC_HDLC 16312 #endif 16313 #if SYNCLINK_GENERIC_HDLC 16314 #endif 16315 #ifdef CMSPAR 16316 #endif 16317 #if SYNCLINK_GENERIC_HDLC 16318 #endif 16319 #if SYNCLINK_GENERIC_HDLC 16320 #endif 16321 #if 0 16322 #endif 16323 #if SYNCLINK_GENERIC_HDLC 16324 #endif 16325 #if SYNCLINK_GENERIC_HDLC 16326 #endif 16327 #define TESTFRAMESIZE 20 16328 #if SYNCLINK_GENERIC_HDLC 16329 #endif 16330 #define CALC_REGADDR() \ 16331 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 16332 if (info->port_num > 1) \ 16333 RegAddr += 256; \ 16334 if ( info->port_num & 1) { \ 16335 if (Addr > 0x7f) \ 16336 RegAddr += 0x40; \ 16337 else if (Addr > 0x1f && Addr < 0x60) \ 16338 RegAddr += 0x20; \ 16339 } 16340 /* LDV_COMMENT_END_PREP */ 16341 16342 16343 16344 16345 } 16346 16347 break; 16348 case 16: { 16349 16350 /** STRUCT: struct type: tty_operations, struct name: ops **/ 16351 16352 16353 /* content: static int chars_in_buffer(struct tty_struct *tty)*/ 16354 /* LDV_COMMENT_BEGIN_PREP */ 16355 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 16356 #if defined(__i386__) 16357 # define BREAKPOINT() asm(" int $3"); 16358 #else 16359 # define BREAKPOINT() { } 16360 #endif 16361 #define MAX_DEVICES 12 16362 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 16363 #define SYNCLINK_GENERIC_HDLC 1 16364 #else 16365 #define SYNCLINK_GENERIC_HDLC 0 16366 #endif 16367 #define GET_USER(error,value,addr) error = get_user(value,addr) 16368 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 16369 #define PUT_USER(error,value,addr) error = put_user(value,addr) 16370 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 16371 #define SCABUFSIZE 1024 16372 #define SCA_MEM_SIZE 0x40000 16373 #define SCA_BASE_SIZE 512 16374 #define SCA_REG_SIZE 16 16375 #define SCA_MAX_PORTS 4 16376 #define SCAMAXDESC 128 16377 #define BUFFERLISTSIZE 4096 16378 #define BH_RECEIVE 1 16379 #define BH_TRANSMIT 2 16380 #define BH_STATUS 4 16381 #define IO_PIN_SHUTDOWN_LIMIT 100 16382 #if SYNCLINK_GENERIC_HDLC 16383 #endif 16384 #define MGSL_MAGIC 0x5401 16385 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 16386 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 16387 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 16388 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 16389 #define LPR 0x00 16390 #define PABR0 0x02 16391 #define PABR1 0x03 16392 #define WCRL 0x04 16393 #define WCRM 0x05 16394 #define WCRH 0x06 16395 #define DPCR 0x08 16396 #define DMER 0x09 16397 #define ISR0 0x10 16398 #define ISR1 0x11 16399 #define ISR2 0x12 16400 #define IER0 0x14 16401 #define IER1 0x15 16402 #define IER2 0x16 16403 #define ITCR 0x18 16404 #define INTVR 0x1a 16405 #define IMVR 0x1c 16406 #define TRB 0x20 16407 #define TRBL 0x20 16408 #define TRBH 0x21 16409 #define SR0 0x22 16410 #define SR1 0x23 16411 #define SR2 0x24 16412 #define SR3 0x25 16413 #define FST 0x26 16414 #define IE0 0x28 16415 #define IE1 0x29 16416 #define IE2 0x2a 16417 #define FIE 0x2b 16418 #define CMD 0x2c 16419 #define MD0 0x2e 16420 #define MD1 0x2f 16421 #define MD2 0x30 16422 #define CTL 0x31 16423 #define SA0 0x32 16424 #define SA1 0x33 16425 #define IDL 0x34 16426 #define TMC 0x35 16427 #define RXS 0x36 16428 #define TXS 0x37 16429 #define TRC0 0x38 16430 #define TRC1 0x39 16431 #define RRC 0x3a 16432 #define CST0 0x3c 16433 #define CST1 0x3d 16434 #define TCNT 0x60 16435 #define TCNTL 0x60 16436 #define TCNTH 0x61 16437 #define TCONR 0x62 16438 #define TCONRL 0x62 16439 #define TCONRH 0x63 16440 #define TMCS 0x64 16441 #define TEPR 0x65 16442 #define DARL 0x80 16443 #define DARH 0x81 16444 #define DARB 0x82 16445 #define BAR 0x80 16446 #define BARL 0x80 16447 #define BARH 0x81 16448 #define BARB 0x82 16449 #define SAR 0x84 16450 #define SARL 0x84 16451 #define SARH 0x85 16452 #define SARB 0x86 16453 #define CPB 0x86 16454 #define CDA 0x88 16455 #define CDAL 0x88 16456 #define CDAH 0x89 16457 #define EDA 0x8a 16458 #define EDAL 0x8a 16459 #define EDAH 0x8b 16460 #define BFL 0x8c 16461 #define BFLL 0x8c 16462 #define BFLH 0x8d 16463 #define BCR 0x8e 16464 #define BCRL 0x8e 16465 #define BCRH 0x8f 16466 #define DSR 0x90 16467 #define DMR 0x91 16468 #define FCT 0x93 16469 #define DIR 0x94 16470 #define DCMD 0x95 16471 #define TIMER0 0x00 16472 #define TIMER1 0x08 16473 #define TIMER2 0x10 16474 #define TIMER3 0x18 16475 #define RXDMA 0x00 16476 #define TXDMA 0x20 16477 #define NOOP 0x00 16478 #define TXRESET 0x01 16479 #define TXENABLE 0x02 16480 #define TXDISABLE 0x03 16481 #define TXCRCINIT 0x04 16482 #define TXCRCEXCL 0x05 16483 #define TXEOM 0x06 16484 #define TXABORT 0x07 16485 #define MPON 0x08 16486 #define TXBUFCLR 0x09 16487 #define RXRESET 0x11 16488 #define RXENABLE 0x12 16489 #define RXDISABLE 0x13 16490 #define RXCRCINIT 0x14 16491 #define RXREJECT 0x15 16492 #define SEARCHMP 0x16 16493 #define RXCRCEXCL 0x17 16494 #define RXCRCCALC 0x18 16495 #define CHRESET 0x21 16496 #define HUNT 0x31 16497 #define SWABORT 0x01 16498 #define FEICLEAR 0x02 16499 #define TXINTE BIT7 16500 #define RXINTE BIT6 16501 #define TXRDYE BIT1 16502 #define RXRDYE BIT0 16503 #define UDRN BIT7 16504 #define IDLE BIT6 16505 #define SYNCD BIT4 16506 #define FLGD BIT4 16507 #define CCTS BIT3 16508 #define CDCD BIT2 16509 #define BRKD BIT1 16510 #define ABTD BIT1 16511 #define GAPD BIT1 16512 #define BRKE BIT0 16513 #define IDLD BIT0 16514 #define EOM BIT7 16515 #define PMP BIT6 16516 #define SHRT BIT6 16517 #define PE BIT5 16518 #define ABT BIT5 16519 #define FRME BIT4 16520 #define RBIT BIT4 16521 #define OVRN BIT3 16522 #define CRCE BIT2 16523 #define WAKEUP_CHARS 256 16524 #if SYNCLINK_GENERIC_HDLC 16525 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16526 #endif 16527 #ifdef SANITY_CHECK 16528 #else 16529 #endif 16530 /* LDV_COMMENT_END_PREP */ 16531 /* LDV_COMMENT_FUNCTION_CALL Function from field "chars_in_buffer" from driver structure with callbacks "ops" */ 16532 ldv_handler_precall(); 16533 chars_in_buffer( var_group8); 16534 /* LDV_COMMENT_BEGIN_PREP */ 16535 #if SYNCLINK_GENERIC_HDLC 16536 #endif 16537 #if SYNCLINK_GENERIC_HDLC 16538 #endif 16539 #if SYNCLINK_GENERIC_HDLC 16540 #endif 16541 #ifdef CMSPAR 16542 #endif 16543 #if SYNCLINK_GENERIC_HDLC 16544 #endif 16545 #if SYNCLINK_GENERIC_HDLC 16546 #endif 16547 #if 0 16548 #endif 16549 #if SYNCLINK_GENERIC_HDLC 16550 #endif 16551 #if SYNCLINK_GENERIC_HDLC 16552 #endif 16553 #define TESTFRAMESIZE 20 16554 #if SYNCLINK_GENERIC_HDLC 16555 #endif 16556 #define CALC_REGADDR() \ 16557 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 16558 if (info->port_num > 1) \ 16559 RegAddr += 256; \ 16560 if ( info->port_num & 1) { \ 16561 if (Addr > 0x7f) \ 16562 RegAddr += 0x40; \ 16563 else if (Addr > 0x1f && Addr < 0x60) \ 16564 RegAddr += 0x20; \ 16565 } 16566 /* LDV_COMMENT_END_PREP */ 16567 16568 16569 16570 16571 } 16572 16573 break; 16574 case 17: { 16575 16576 /** STRUCT: struct type: tty_operations, struct name: ops **/ 16577 16578 16579 /* content: static void flush_buffer(struct tty_struct *tty)*/ 16580 /* LDV_COMMENT_BEGIN_PREP */ 16581 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 16582 #if defined(__i386__) 16583 # define BREAKPOINT() asm(" int $3"); 16584 #else 16585 # define BREAKPOINT() { } 16586 #endif 16587 #define MAX_DEVICES 12 16588 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 16589 #define SYNCLINK_GENERIC_HDLC 1 16590 #else 16591 #define SYNCLINK_GENERIC_HDLC 0 16592 #endif 16593 #define GET_USER(error,value,addr) error = get_user(value,addr) 16594 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 16595 #define PUT_USER(error,value,addr) error = put_user(value,addr) 16596 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 16597 #define SCABUFSIZE 1024 16598 #define SCA_MEM_SIZE 0x40000 16599 #define SCA_BASE_SIZE 512 16600 #define SCA_REG_SIZE 16 16601 #define SCA_MAX_PORTS 4 16602 #define SCAMAXDESC 128 16603 #define BUFFERLISTSIZE 4096 16604 #define BH_RECEIVE 1 16605 #define BH_TRANSMIT 2 16606 #define BH_STATUS 4 16607 #define IO_PIN_SHUTDOWN_LIMIT 100 16608 #if SYNCLINK_GENERIC_HDLC 16609 #endif 16610 #define MGSL_MAGIC 0x5401 16611 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 16612 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 16613 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 16614 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 16615 #define LPR 0x00 16616 #define PABR0 0x02 16617 #define PABR1 0x03 16618 #define WCRL 0x04 16619 #define WCRM 0x05 16620 #define WCRH 0x06 16621 #define DPCR 0x08 16622 #define DMER 0x09 16623 #define ISR0 0x10 16624 #define ISR1 0x11 16625 #define ISR2 0x12 16626 #define IER0 0x14 16627 #define IER1 0x15 16628 #define IER2 0x16 16629 #define ITCR 0x18 16630 #define INTVR 0x1a 16631 #define IMVR 0x1c 16632 #define TRB 0x20 16633 #define TRBL 0x20 16634 #define TRBH 0x21 16635 #define SR0 0x22 16636 #define SR1 0x23 16637 #define SR2 0x24 16638 #define SR3 0x25 16639 #define FST 0x26 16640 #define IE0 0x28 16641 #define IE1 0x29 16642 #define IE2 0x2a 16643 #define FIE 0x2b 16644 #define CMD 0x2c 16645 #define MD0 0x2e 16646 #define MD1 0x2f 16647 #define MD2 0x30 16648 #define CTL 0x31 16649 #define SA0 0x32 16650 #define SA1 0x33 16651 #define IDL 0x34 16652 #define TMC 0x35 16653 #define RXS 0x36 16654 #define TXS 0x37 16655 #define TRC0 0x38 16656 #define TRC1 0x39 16657 #define RRC 0x3a 16658 #define CST0 0x3c 16659 #define CST1 0x3d 16660 #define TCNT 0x60 16661 #define TCNTL 0x60 16662 #define TCNTH 0x61 16663 #define TCONR 0x62 16664 #define TCONRL 0x62 16665 #define TCONRH 0x63 16666 #define TMCS 0x64 16667 #define TEPR 0x65 16668 #define DARL 0x80 16669 #define DARH 0x81 16670 #define DARB 0x82 16671 #define BAR 0x80 16672 #define BARL 0x80 16673 #define BARH 0x81 16674 #define BARB 0x82 16675 #define SAR 0x84 16676 #define SARL 0x84 16677 #define SARH 0x85 16678 #define SARB 0x86 16679 #define CPB 0x86 16680 #define CDA 0x88 16681 #define CDAL 0x88 16682 #define CDAH 0x89 16683 #define EDA 0x8a 16684 #define EDAL 0x8a 16685 #define EDAH 0x8b 16686 #define BFL 0x8c 16687 #define BFLL 0x8c 16688 #define BFLH 0x8d 16689 #define BCR 0x8e 16690 #define BCRL 0x8e 16691 #define BCRH 0x8f 16692 #define DSR 0x90 16693 #define DMR 0x91 16694 #define FCT 0x93 16695 #define DIR 0x94 16696 #define DCMD 0x95 16697 #define TIMER0 0x00 16698 #define TIMER1 0x08 16699 #define TIMER2 0x10 16700 #define TIMER3 0x18 16701 #define RXDMA 0x00 16702 #define TXDMA 0x20 16703 #define NOOP 0x00 16704 #define TXRESET 0x01 16705 #define TXENABLE 0x02 16706 #define TXDISABLE 0x03 16707 #define TXCRCINIT 0x04 16708 #define TXCRCEXCL 0x05 16709 #define TXEOM 0x06 16710 #define TXABORT 0x07 16711 #define MPON 0x08 16712 #define TXBUFCLR 0x09 16713 #define RXRESET 0x11 16714 #define RXENABLE 0x12 16715 #define RXDISABLE 0x13 16716 #define RXCRCINIT 0x14 16717 #define RXREJECT 0x15 16718 #define SEARCHMP 0x16 16719 #define RXCRCEXCL 0x17 16720 #define RXCRCCALC 0x18 16721 #define CHRESET 0x21 16722 #define HUNT 0x31 16723 #define SWABORT 0x01 16724 #define FEICLEAR 0x02 16725 #define TXINTE BIT7 16726 #define RXINTE BIT6 16727 #define TXRDYE BIT1 16728 #define RXRDYE BIT0 16729 #define UDRN BIT7 16730 #define IDLE BIT6 16731 #define SYNCD BIT4 16732 #define FLGD BIT4 16733 #define CCTS BIT3 16734 #define CDCD BIT2 16735 #define BRKD BIT1 16736 #define ABTD BIT1 16737 #define GAPD BIT1 16738 #define BRKE BIT0 16739 #define IDLD BIT0 16740 #define EOM BIT7 16741 #define PMP BIT6 16742 #define SHRT BIT6 16743 #define PE BIT5 16744 #define ABT BIT5 16745 #define FRME BIT4 16746 #define RBIT BIT4 16747 #define OVRN BIT3 16748 #define CRCE BIT2 16749 #define WAKEUP_CHARS 256 16750 #if SYNCLINK_GENERIC_HDLC 16751 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16752 #endif 16753 #ifdef SANITY_CHECK 16754 #else 16755 #endif 16756 /* LDV_COMMENT_END_PREP */ 16757 /* LDV_COMMENT_FUNCTION_CALL Function from field "flush_buffer" from driver structure with callbacks "ops" */ 16758 ldv_handler_precall(); 16759 flush_buffer( var_group8); 16760 /* LDV_COMMENT_BEGIN_PREP */ 16761 #if SYNCLINK_GENERIC_HDLC 16762 #endif 16763 #if SYNCLINK_GENERIC_HDLC 16764 #endif 16765 #if SYNCLINK_GENERIC_HDLC 16766 #endif 16767 #ifdef CMSPAR 16768 #endif 16769 #if SYNCLINK_GENERIC_HDLC 16770 #endif 16771 #if SYNCLINK_GENERIC_HDLC 16772 #endif 16773 #if 0 16774 #endif 16775 #if SYNCLINK_GENERIC_HDLC 16776 #endif 16777 #if SYNCLINK_GENERIC_HDLC 16778 #endif 16779 #define TESTFRAMESIZE 20 16780 #if SYNCLINK_GENERIC_HDLC 16781 #endif 16782 #define CALC_REGADDR() \ 16783 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 16784 if (info->port_num > 1) \ 16785 RegAddr += 256; \ 16786 if ( info->port_num & 1) { \ 16787 if (Addr > 0x7f) \ 16788 RegAddr += 0x40; \ 16789 else if (Addr > 0x1f && Addr < 0x60) \ 16790 RegAddr += 0x20; \ 16791 } 16792 /* LDV_COMMENT_END_PREP */ 16793 16794 16795 16796 16797 } 16798 16799 break; 16800 case 18: { 16801 16802 /** STRUCT: struct type: tty_operations, struct name: ops **/ 16803 16804 16805 /* content: static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg)*/ 16806 /* LDV_COMMENT_BEGIN_PREP */ 16807 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 16808 #if defined(__i386__) 16809 # define BREAKPOINT() asm(" int $3"); 16810 #else 16811 # define BREAKPOINT() { } 16812 #endif 16813 #define MAX_DEVICES 12 16814 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 16815 #define SYNCLINK_GENERIC_HDLC 1 16816 #else 16817 #define SYNCLINK_GENERIC_HDLC 0 16818 #endif 16819 #define GET_USER(error,value,addr) error = get_user(value,addr) 16820 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 16821 #define PUT_USER(error,value,addr) error = put_user(value,addr) 16822 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 16823 #define SCABUFSIZE 1024 16824 #define SCA_MEM_SIZE 0x40000 16825 #define SCA_BASE_SIZE 512 16826 #define SCA_REG_SIZE 16 16827 #define SCA_MAX_PORTS 4 16828 #define SCAMAXDESC 128 16829 #define BUFFERLISTSIZE 4096 16830 #define BH_RECEIVE 1 16831 #define BH_TRANSMIT 2 16832 #define BH_STATUS 4 16833 #define IO_PIN_SHUTDOWN_LIMIT 100 16834 #if SYNCLINK_GENERIC_HDLC 16835 #endif 16836 #define MGSL_MAGIC 0x5401 16837 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 16838 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 16839 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 16840 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 16841 #define LPR 0x00 16842 #define PABR0 0x02 16843 #define PABR1 0x03 16844 #define WCRL 0x04 16845 #define WCRM 0x05 16846 #define WCRH 0x06 16847 #define DPCR 0x08 16848 #define DMER 0x09 16849 #define ISR0 0x10 16850 #define ISR1 0x11 16851 #define ISR2 0x12 16852 #define IER0 0x14 16853 #define IER1 0x15 16854 #define IER2 0x16 16855 #define ITCR 0x18 16856 #define INTVR 0x1a 16857 #define IMVR 0x1c 16858 #define TRB 0x20 16859 #define TRBL 0x20 16860 #define TRBH 0x21 16861 #define SR0 0x22 16862 #define SR1 0x23 16863 #define SR2 0x24 16864 #define SR3 0x25 16865 #define FST 0x26 16866 #define IE0 0x28 16867 #define IE1 0x29 16868 #define IE2 0x2a 16869 #define FIE 0x2b 16870 #define CMD 0x2c 16871 #define MD0 0x2e 16872 #define MD1 0x2f 16873 #define MD2 0x30 16874 #define CTL 0x31 16875 #define SA0 0x32 16876 #define SA1 0x33 16877 #define IDL 0x34 16878 #define TMC 0x35 16879 #define RXS 0x36 16880 #define TXS 0x37 16881 #define TRC0 0x38 16882 #define TRC1 0x39 16883 #define RRC 0x3a 16884 #define CST0 0x3c 16885 #define CST1 0x3d 16886 #define TCNT 0x60 16887 #define TCNTL 0x60 16888 #define TCNTH 0x61 16889 #define TCONR 0x62 16890 #define TCONRL 0x62 16891 #define TCONRH 0x63 16892 #define TMCS 0x64 16893 #define TEPR 0x65 16894 #define DARL 0x80 16895 #define DARH 0x81 16896 #define DARB 0x82 16897 #define BAR 0x80 16898 #define BARL 0x80 16899 #define BARH 0x81 16900 #define BARB 0x82 16901 #define SAR 0x84 16902 #define SARL 0x84 16903 #define SARH 0x85 16904 #define SARB 0x86 16905 #define CPB 0x86 16906 #define CDA 0x88 16907 #define CDAL 0x88 16908 #define CDAH 0x89 16909 #define EDA 0x8a 16910 #define EDAL 0x8a 16911 #define EDAH 0x8b 16912 #define BFL 0x8c 16913 #define BFLL 0x8c 16914 #define BFLH 0x8d 16915 #define BCR 0x8e 16916 #define BCRL 0x8e 16917 #define BCRH 0x8f 16918 #define DSR 0x90 16919 #define DMR 0x91 16920 #define FCT 0x93 16921 #define DIR 0x94 16922 #define DCMD 0x95 16923 #define TIMER0 0x00 16924 #define TIMER1 0x08 16925 #define TIMER2 0x10 16926 #define TIMER3 0x18 16927 #define RXDMA 0x00 16928 #define TXDMA 0x20 16929 #define NOOP 0x00 16930 #define TXRESET 0x01 16931 #define TXENABLE 0x02 16932 #define TXDISABLE 0x03 16933 #define TXCRCINIT 0x04 16934 #define TXCRCEXCL 0x05 16935 #define TXEOM 0x06 16936 #define TXABORT 0x07 16937 #define MPON 0x08 16938 #define TXBUFCLR 0x09 16939 #define RXRESET 0x11 16940 #define RXENABLE 0x12 16941 #define RXDISABLE 0x13 16942 #define RXCRCINIT 0x14 16943 #define RXREJECT 0x15 16944 #define SEARCHMP 0x16 16945 #define RXCRCEXCL 0x17 16946 #define RXCRCCALC 0x18 16947 #define CHRESET 0x21 16948 #define HUNT 0x31 16949 #define SWABORT 0x01 16950 #define FEICLEAR 0x02 16951 #define TXINTE BIT7 16952 #define RXINTE BIT6 16953 #define TXRDYE BIT1 16954 #define RXRDYE BIT0 16955 #define UDRN BIT7 16956 #define IDLE BIT6 16957 #define SYNCD BIT4 16958 #define FLGD BIT4 16959 #define CCTS BIT3 16960 #define CDCD BIT2 16961 #define BRKD BIT1 16962 #define ABTD BIT1 16963 #define GAPD BIT1 16964 #define BRKE BIT0 16965 #define IDLD BIT0 16966 #define EOM BIT7 16967 #define PMP BIT6 16968 #define SHRT BIT6 16969 #define PE BIT5 16970 #define ABT BIT5 16971 #define FRME BIT4 16972 #define RBIT BIT4 16973 #define OVRN BIT3 16974 #define CRCE BIT2 16975 #define WAKEUP_CHARS 256 16976 #if SYNCLINK_GENERIC_HDLC 16977 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16978 #endif 16979 #ifdef SANITY_CHECK 16980 #else 16981 #endif 16982 /* LDV_COMMENT_END_PREP */ 16983 /* LDV_COMMENT_FUNCTION_CALL Function from field "ioctl" from driver structure with callbacks "ops" */ 16984 ldv_handler_precall(); 16985 ioctl( var_group8, var_ioctl_17_p1, var_ioctl_17_p2); 16986 /* LDV_COMMENT_BEGIN_PREP */ 16987 #if SYNCLINK_GENERIC_HDLC 16988 #endif 16989 #if SYNCLINK_GENERIC_HDLC 16990 #endif 16991 #if SYNCLINK_GENERIC_HDLC 16992 #endif 16993 #ifdef CMSPAR 16994 #endif 16995 #if SYNCLINK_GENERIC_HDLC 16996 #endif 16997 #if SYNCLINK_GENERIC_HDLC 16998 #endif 16999 #if 0 17000 #endif 17001 #if SYNCLINK_GENERIC_HDLC 17002 #endif 17003 #if SYNCLINK_GENERIC_HDLC 17004 #endif 17005 #define TESTFRAMESIZE 20 17006 #if SYNCLINK_GENERIC_HDLC 17007 #endif 17008 #define CALC_REGADDR() \ 17009 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17010 if (info->port_num > 1) \ 17011 RegAddr += 256; \ 17012 if ( info->port_num & 1) { \ 17013 if (Addr > 0x7f) \ 17014 RegAddr += 0x40; \ 17015 else if (Addr > 0x1f && Addr < 0x60) \ 17016 RegAddr += 0x20; \ 17017 } 17018 /* LDV_COMMENT_END_PREP */ 17019 17020 17021 17022 17023 } 17024 17025 break; 17026 case 19: { 17027 17028 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17029 17030 17031 /* content: static void throttle(struct tty_struct * tty)*/ 17032 /* LDV_COMMENT_BEGIN_PREP */ 17033 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17034 #if defined(__i386__) 17035 # define BREAKPOINT() asm(" int $3"); 17036 #else 17037 # define BREAKPOINT() { } 17038 #endif 17039 #define MAX_DEVICES 12 17040 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17041 #define SYNCLINK_GENERIC_HDLC 1 17042 #else 17043 #define SYNCLINK_GENERIC_HDLC 0 17044 #endif 17045 #define GET_USER(error,value,addr) error = get_user(value,addr) 17046 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17047 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17048 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17049 #define SCABUFSIZE 1024 17050 #define SCA_MEM_SIZE 0x40000 17051 #define SCA_BASE_SIZE 512 17052 #define SCA_REG_SIZE 16 17053 #define SCA_MAX_PORTS 4 17054 #define SCAMAXDESC 128 17055 #define BUFFERLISTSIZE 4096 17056 #define BH_RECEIVE 1 17057 #define BH_TRANSMIT 2 17058 #define BH_STATUS 4 17059 #define IO_PIN_SHUTDOWN_LIMIT 100 17060 #if SYNCLINK_GENERIC_HDLC 17061 #endif 17062 #define MGSL_MAGIC 0x5401 17063 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17064 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17065 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17066 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17067 #define LPR 0x00 17068 #define PABR0 0x02 17069 #define PABR1 0x03 17070 #define WCRL 0x04 17071 #define WCRM 0x05 17072 #define WCRH 0x06 17073 #define DPCR 0x08 17074 #define DMER 0x09 17075 #define ISR0 0x10 17076 #define ISR1 0x11 17077 #define ISR2 0x12 17078 #define IER0 0x14 17079 #define IER1 0x15 17080 #define IER2 0x16 17081 #define ITCR 0x18 17082 #define INTVR 0x1a 17083 #define IMVR 0x1c 17084 #define TRB 0x20 17085 #define TRBL 0x20 17086 #define TRBH 0x21 17087 #define SR0 0x22 17088 #define SR1 0x23 17089 #define SR2 0x24 17090 #define SR3 0x25 17091 #define FST 0x26 17092 #define IE0 0x28 17093 #define IE1 0x29 17094 #define IE2 0x2a 17095 #define FIE 0x2b 17096 #define CMD 0x2c 17097 #define MD0 0x2e 17098 #define MD1 0x2f 17099 #define MD2 0x30 17100 #define CTL 0x31 17101 #define SA0 0x32 17102 #define SA1 0x33 17103 #define IDL 0x34 17104 #define TMC 0x35 17105 #define RXS 0x36 17106 #define TXS 0x37 17107 #define TRC0 0x38 17108 #define TRC1 0x39 17109 #define RRC 0x3a 17110 #define CST0 0x3c 17111 #define CST1 0x3d 17112 #define TCNT 0x60 17113 #define TCNTL 0x60 17114 #define TCNTH 0x61 17115 #define TCONR 0x62 17116 #define TCONRL 0x62 17117 #define TCONRH 0x63 17118 #define TMCS 0x64 17119 #define TEPR 0x65 17120 #define DARL 0x80 17121 #define DARH 0x81 17122 #define DARB 0x82 17123 #define BAR 0x80 17124 #define BARL 0x80 17125 #define BARH 0x81 17126 #define BARB 0x82 17127 #define SAR 0x84 17128 #define SARL 0x84 17129 #define SARH 0x85 17130 #define SARB 0x86 17131 #define CPB 0x86 17132 #define CDA 0x88 17133 #define CDAL 0x88 17134 #define CDAH 0x89 17135 #define EDA 0x8a 17136 #define EDAL 0x8a 17137 #define EDAH 0x8b 17138 #define BFL 0x8c 17139 #define BFLL 0x8c 17140 #define BFLH 0x8d 17141 #define BCR 0x8e 17142 #define BCRL 0x8e 17143 #define BCRH 0x8f 17144 #define DSR 0x90 17145 #define DMR 0x91 17146 #define FCT 0x93 17147 #define DIR 0x94 17148 #define DCMD 0x95 17149 #define TIMER0 0x00 17150 #define TIMER1 0x08 17151 #define TIMER2 0x10 17152 #define TIMER3 0x18 17153 #define RXDMA 0x00 17154 #define TXDMA 0x20 17155 #define NOOP 0x00 17156 #define TXRESET 0x01 17157 #define TXENABLE 0x02 17158 #define TXDISABLE 0x03 17159 #define TXCRCINIT 0x04 17160 #define TXCRCEXCL 0x05 17161 #define TXEOM 0x06 17162 #define TXABORT 0x07 17163 #define MPON 0x08 17164 #define TXBUFCLR 0x09 17165 #define RXRESET 0x11 17166 #define RXENABLE 0x12 17167 #define RXDISABLE 0x13 17168 #define RXCRCINIT 0x14 17169 #define RXREJECT 0x15 17170 #define SEARCHMP 0x16 17171 #define RXCRCEXCL 0x17 17172 #define RXCRCCALC 0x18 17173 #define CHRESET 0x21 17174 #define HUNT 0x31 17175 #define SWABORT 0x01 17176 #define FEICLEAR 0x02 17177 #define TXINTE BIT7 17178 #define RXINTE BIT6 17179 #define TXRDYE BIT1 17180 #define RXRDYE BIT0 17181 #define UDRN BIT7 17182 #define IDLE BIT6 17183 #define SYNCD BIT4 17184 #define FLGD BIT4 17185 #define CCTS BIT3 17186 #define CDCD BIT2 17187 #define BRKD BIT1 17188 #define ABTD BIT1 17189 #define GAPD BIT1 17190 #define BRKE BIT0 17191 #define IDLD BIT0 17192 #define EOM BIT7 17193 #define PMP BIT6 17194 #define SHRT BIT6 17195 #define PE BIT5 17196 #define ABT BIT5 17197 #define FRME BIT4 17198 #define RBIT BIT4 17199 #define OVRN BIT3 17200 #define CRCE BIT2 17201 #define WAKEUP_CHARS 256 17202 #if SYNCLINK_GENERIC_HDLC 17203 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 17204 #endif 17205 #ifdef SANITY_CHECK 17206 #else 17207 #endif 17208 /* LDV_COMMENT_END_PREP */ 17209 /* LDV_COMMENT_FUNCTION_CALL Function from field "throttle" from driver structure with callbacks "ops" */ 17210 ldv_handler_precall(); 17211 throttle( var_group8); 17212 /* LDV_COMMENT_BEGIN_PREP */ 17213 #if SYNCLINK_GENERIC_HDLC 17214 #endif 17215 #if SYNCLINK_GENERIC_HDLC 17216 #endif 17217 #if SYNCLINK_GENERIC_HDLC 17218 #endif 17219 #ifdef CMSPAR 17220 #endif 17221 #if SYNCLINK_GENERIC_HDLC 17222 #endif 17223 #if SYNCLINK_GENERIC_HDLC 17224 #endif 17225 #if 0 17226 #endif 17227 #if SYNCLINK_GENERIC_HDLC 17228 #endif 17229 #if SYNCLINK_GENERIC_HDLC 17230 #endif 17231 #define TESTFRAMESIZE 20 17232 #if SYNCLINK_GENERIC_HDLC 17233 #endif 17234 #define CALC_REGADDR() \ 17235 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17236 if (info->port_num > 1) \ 17237 RegAddr += 256; \ 17238 if ( info->port_num & 1) { \ 17239 if (Addr > 0x7f) \ 17240 RegAddr += 0x40; \ 17241 else if (Addr > 0x1f && Addr < 0x60) \ 17242 RegAddr += 0x20; \ 17243 } 17244 /* LDV_COMMENT_END_PREP */ 17245 17246 17247 17248 17249 } 17250 17251 break; 17252 case 20: { 17253 17254 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17255 17256 17257 /* content: static void unthrottle(struct tty_struct * tty)*/ 17258 /* LDV_COMMENT_BEGIN_PREP */ 17259 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17260 #if defined(__i386__) 17261 # define BREAKPOINT() asm(" int $3"); 17262 #else 17263 # define BREAKPOINT() { } 17264 #endif 17265 #define MAX_DEVICES 12 17266 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17267 #define SYNCLINK_GENERIC_HDLC 1 17268 #else 17269 #define SYNCLINK_GENERIC_HDLC 0 17270 #endif 17271 #define GET_USER(error,value,addr) error = get_user(value,addr) 17272 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17273 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17274 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17275 #define SCABUFSIZE 1024 17276 #define SCA_MEM_SIZE 0x40000 17277 #define SCA_BASE_SIZE 512 17278 #define SCA_REG_SIZE 16 17279 #define SCA_MAX_PORTS 4 17280 #define SCAMAXDESC 128 17281 #define BUFFERLISTSIZE 4096 17282 #define BH_RECEIVE 1 17283 #define BH_TRANSMIT 2 17284 #define BH_STATUS 4 17285 #define IO_PIN_SHUTDOWN_LIMIT 100 17286 #if SYNCLINK_GENERIC_HDLC 17287 #endif 17288 #define MGSL_MAGIC 0x5401 17289 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17290 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17291 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17292 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17293 #define LPR 0x00 17294 #define PABR0 0x02 17295 #define PABR1 0x03 17296 #define WCRL 0x04 17297 #define WCRM 0x05 17298 #define WCRH 0x06 17299 #define DPCR 0x08 17300 #define DMER 0x09 17301 #define ISR0 0x10 17302 #define ISR1 0x11 17303 #define ISR2 0x12 17304 #define IER0 0x14 17305 #define IER1 0x15 17306 #define IER2 0x16 17307 #define ITCR 0x18 17308 #define INTVR 0x1a 17309 #define IMVR 0x1c 17310 #define TRB 0x20 17311 #define TRBL 0x20 17312 #define TRBH 0x21 17313 #define SR0 0x22 17314 #define SR1 0x23 17315 #define SR2 0x24 17316 #define SR3 0x25 17317 #define FST 0x26 17318 #define IE0 0x28 17319 #define IE1 0x29 17320 #define IE2 0x2a 17321 #define FIE 0x2b 17322 #define CMD 0x2c 17323 #define MD0 0x2e 17324 #define MD1 0x2f 17325 #define MD2 0x30 17326 #define CTL 0x31 17327 #define SA0 0x32 17328 #define SA1 0x33 17329 #define IDL 0x34 17330 #define TMC 0x35 17331 #define RXS 0x36 17332 #define TXS 0x37 17333 #define TRC0 0x38 17334 #define TRC1 0x39 17335 #define RRC 0x3a 17336 #define CST0 0x3c 17337 #define CST1 0x3d 17338 #define TCNT 0x60 17339 #define TCNTL 0x60 17340 #define TCNTH 0x61 17341 #define TCONR 0x62 17342 #define TCONRL 0x62 17343 #define TCONRH 0x63 17344 #define TMCS 0x64 17345 #define TEPR 0x65 17346 #define DARL 0x80 17347 #define DARH 0x81 17348 #define DARB 0x82 17349 #define BAR 0x80 17350 #define BARL 0x80 17351 #define BARH 0x81 17352 #define BARB 0x82 17353 #define SAR 0x84 17354 #define SARL 0x84 17355 #define SARH 0x85 17356 #define SARB 0x86 17357 #define CPB 0x86 17358 #define CDA 0x88 17359 #define CDAL 0x88 17360 #define CDAH 0x89 17361 #define EDA 0x8a 17362 #define EDAL 0x8a 17363 #define EDAH 0x8b 17364 #define BFL 0x8c 17365 #define BFLL 0x8c 17366 #define BFLH 0x8d 17367 #define BCR 0x8e 17368 #define BCRL 0x8e 17369 #define BCRH 0x8f 17370 #define DSR 0x90 17371 #define DMR 0x91 17372 #define FCT 0x93 17373 #define DIR 0x94 17374 #define DCMD 0x95 17375 #define TIMER0 0x00 17376 #define TIMER1 0x08 17377 #define TIMER2 0x10 17378 #define TIMER3 0x18 17379 #define RXDMA 0x00 17380 #define TXDMA 0x20 17381 #define NOOP 0x00 17382 #define TXRESET 0x01 17383 #define TXENABLE 0x02 17384 #define TXDISABLE 0x03 17385 #define TXCRCINIT 0x04 17386 #define TXCRCEXCL 0x05 17387 #define TXEOM 0x06 17388 #define TXABORT 0x07 17389 #define MPON 0x08 17390 #define TXBUFCLR 0x09 17391 #define RXRESET 0x11 17392 #define RXENABLE 0x12 17393 #define RXDISABLE 0x13 17394 #define RXCRCINIT 0x14 17395 #define RXREJECT 0x15 17396 #define SEARCHMP 0x16 17397 #define RXCRCEXCL 0x17 17398 #define RXCRCCALC 0x18 17399 #define CHRESET 0x21 17400 #define HUNT 0x31 17401 #define SWABORT 0x01 17402 #define FEICLEAR 0x02 17403 #define TXINTE BIT7 17404 #define RXINTE BIT6 17405 #define TXRDYE BIT1 17406 #define RXRDYE BIT0 17407 #define UDRN BIT7 17408 #define IDLE BIT6 17409 #define SYNCD BIT4 17410 #define FLGD BIT4 17411 #define CCTS BIT3 17412 #define CDCD BIT2 17413 #define BRKD BIT1 17414 #define ABTD BIT1 17415 #define GAPD BIT1 17416 #define BRKE BIT0 17417 #define IDLD BIT0 17418 #define EOM BIT7 17419 #define PMP BIT6 17420 #define SHRT BIT6 17421 #define PE BIT5 17422 #define ABT BIT5 17423 #define FRME BIT4 17424 #define RBIT BIT4 17425 #define OVRN BIT3 17426 #define CRCE BIT2 17427 #define WAKEUP_CHARS 256 17428 #if SYNCLINK_GENERIC_HDLC 17429 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 17430 #endif 17431 #ifdef SANITY_CHECK 17432 #else 17433 #endif 17434 /* LDV_COMMENT_END_PREP */ 17435 /* LDV_COMMENT_FUNCTION_CALL Function from field "unthrottle" from driver structure with callbacks "ops" */ 17436 ldv_handler_precall(); 17437 unthrottle( var_group8); 17438 /* LDV_COMMENT_BEGIN_PREP */ 17439 #if SYNCLINK_GENERIC_HDLC 17440 #endif 17441 #if SYNCLINK_GENERIC_HDLC 17442 #endif 17443 #if SYNCLINK_GENERIC_HDLC 17444 #endif 17445 #ifdef CMSPAR 17446 #endif 17447 #if SYNCLINK_GENERIC_HDLC 17448 #endif 17449 #if SYNCLINK_GENERIC_HDLC 17450 #endif 17451 #if 0 17452 #endif 17453 #if SYNCLINK_GENERIC_HDLC 17454 #endif 17455 #if SYNCLINK_GENERIC_HDLC 17456 #endif 17457 #define TESTFRAMESIZE 20 17458 #if SYNCLINK_GENERIC_HDLC 17459 #endif 17460 #define CALC_REGADDR() \ 17461 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17462 if (info->port_num > 1) \ 17463 RegAddr += 256; \ 17464 if ( info->port_num & 1) { \ 17465 if (Addr > 0x7f) \ 17466 RegAddr += 0x40; \ 17467 else if (Addr > 0x1f && Addr < 0x60) \ 17468 RegAddr += 0x20; \ 17469 } 17470 /* LDV_COMMENT_END_PREP */ 17471 17472 17473 17474 17475 } 17476 17477 break; 17478 case 21: { 17479 17480 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17481 17482 17483 /* content: static void send_xchar(struct tty_struct *tty, char ch)*/ 17484 /* LDV_COMMENT_BEGIN_PREP */ 17485 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17486 #if defined(__i386__) 17487 # define BREAKPOINT() asm(" int $3"); 17488 #else 17489 # define BREAKPOINT() { } 17490 #endif 17491 #define MAX_DEVICES 12 17492 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17493 #define SYNCLINK_GENERIC_HDLC 1 17494 #else 17495 #define SYNCLINK_GENERIC_HDLC 0 17496 #endif 17497 #define GET_USER(error,value,addr) error = get_user(value,addr) 17498 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17499 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17500 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17501 #define SCABUFSIZE 1024 17502 #define SCA_MEM_SIZE 0x40000 17503 #define SCA_BASE_SIZE 512 17504 #define SCA_REG_SIZE 16 17505 #define SCA_MAX_PORTS 4 17506 #define SCAMAXDESC 128 17507 #define BUFFERLISTSIZE 4096 17508 #define BH_RECEIVE 1 17509 #define BH_TRANSMIT 2 17510 #define BH_STATUS 4 17511 #define IO_PIN_SHUTDOWN_LIMIT 100 17512 #if SYNCLINK_GENERIC_HDLC 17513 #endif 17514 #define MGSL_MAGIC 0x5401 17515 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17516 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17517 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17518 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17519 #define LPR 0x00 17520 #define PABR0 0x02 17521 #define PABR1 0x03 17522 #define WCRL 0x04 17523 #define WCRM 0x05 17524 #define WCRH 0x06 17525 #define DPCR 0x08 17526 #define DMER 0x09 17527 #define ISR0 0x10 17528 #define ISR1 0x11 17529 #define ISR2 0x12 17530 #define IER0 0x14 17531 #define IER1 0x15 17532 #define IER2 0x16 17533 #define ITCR 0x18 17534 #define INTVR 0x1a 17535 #define IMVR 0x1c 17536 #define TRB 0x20 17537 #define TRBL 0x20 17538 #define TRBH 0x21 17539 #define SR0 0x22 17540 #define SR1 0x23 17541 #define SR2 0x24 17542 #define SR3 0x25 17543 #define FST 0x26 17544 #define IE0 0x28 17545 #define IE1 0x29 17546 #define IE2 0x2a 17547 #define FIE 0x2b 17548 #define CMD 0x2c 17549 #define MD0 0x2e 17550 #define MD1 0x2f 17551 #define MD2 0x30 17552 #define CTL 0x31 17553 #define SA0 0x32 17554 #define SA1 0x33 17555 #define IDL 0x34 17556 #define TMC 0x35 17557 #define RXS 0x36 17558 #define TXS 0x37 17559 #define TRC0 0x38 17560 #define TRC1 0x39 17561 #define RRC 0x3a 17562 #define CST0 0x3c 17563 #define CST1 0x3d 17564 #define TCNT 0x60 17565 #define TCNTL 0x60 17566 #define TCNTH 0x61 17567 #define TCONR 0x62 17568 #define TCONRL 0x62 17569 #define TCONRH 0x63 17570 #define TMCS 0x64 17571 #define TEPR 0x65 17572 #define DARL 0x80 17573 #define DARH 0x81 17574 #define DARB 0x82 17575 #define BAR 0x80 17576 #define BARL 0x80 17577 #define BARH 0x81 17578 #define BARB 0x82 17579 #define SAR 0x84 17580 #define SARL 0x84 17581 #define SARH 0x85 17582 #define SARB 0x86 17583 #define CPB 0x86 17584 #define CDA 0x88 17585 #define CDAL 0x88 17586 #define CDAH 0x89 17587 #define EDA 0x8a 17588 #define EDAL 0x8a 17589 #define EDAH 0x8b 17590 #define BFL 0x8c 17591 #define BFLL 0x8c 17592 #define BFLH 0x8d 17593 #define BCR 0x8e 17594 #define BCRL 0x8e 17595 #define BCRH 0x8f 17596 #define DSR 0x90 17597 #define DMR 0x91 17598 #define FCT 0x93 17599 #define DIR 0x94 17600 #define DCMD 0x95 17601 #define TIMER0 0x00 17602 #define TIMER1 0x08 17603 #define TIMER2 0x10 17604 #define TIMER3 0x18 17605 #define RXDMA 0x00 17606 #define TXDMA 0x20 17607 #define NOOP 0x00 17608 #define TXRESET 0x01 17609 #define TXENABLE 0x02 17610 #define TXDISABLE 0x03 17611 #define TXCRCINIT 0x04 17612 #define TXCRCEXCL 0x05 17613 #define TXEOM 0x06 17614 #define TXABORT 0x07 17615 #define MPON 0x08 17616 #define TXBUFCLR 0x09 17617 #define RXRESET 0x11 17618 #define RXENABLE 0x12 17619 #define RXDISABLE 0x13 17620 #define RXCRCINIT 0x14 17621 #define RXREJECT 0x15 17622 #define SEARCHMP 0x16 17623 #define RXCRCEXCL 0x17 17624 #define RXCRCCALC 0x18 17625 #define CHRESET 0x21 17626 #define HUNT 0x31 17627 #define SWABORT 0x01 17628 #define FEICLEAR 0x02 17629 #define TXINTE BIT7 17630 #define RXINTE BIT6 17631 #define TXRDYE BIT1 17632 #define RXRDYE BIT0 17633 #define UDRN BIT7 17634 #define IDLE BIT6 17635 #define SYNCD BIT4 17636 #define FLGD BIT4 17637 #define CCTS BIT3 17638 #define CDCD BIT2 17639 #define BRKD BIT1 17640 #define ABTD BIT1 17641 #define GAPD BIT1 17642 #define BRKE BIT0 17643 #define IDLD BIT0 17644 #define EOM BIT7 17645 #define PMP BIT6 17646 #define SHRT BIT6 17647 #define PE BIT5 17648 #define ABT BIT5 17649 #define FRME BIT4 17650 #define RBIT BIT4 17651 #define OVRN BIT3 17652 #define CRCE BIT2 17653 #define WAKEUP_CHARS 256 17654 #if SYNCLINK_GENERIC_HDLC 17655 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 17656 #endif 17657 #ifdef SANITY_CHECK 17658 #else 17659 #endif 17660 /* LDV_COMMENT_END_PREP */ 17661 /* LDV_COMMENT_FUNCTION_CALL Function from field "send_xchar" from driver structure with callbacks "ops" */ 17662 ldv_handler_precall(); 17663 send_xchar( var_group8, var_send_xchar_10_p1); 17664 /* LDV_COMMENT_BEGIN_PREP */ 17665 #if SYNCLINK_GENERIC_HDLC 17666 #endif 17667 #if SYNCLINK_GENERIC_HDLC 17668 #endif 17669 #if SYNCLINK_GENERIC_HDLC 17670 #endif 17671 #ifdef CMSPAR 17672 #endif 17673 #if SYNCLINK_GENERIC_HDLC 17674 #endif 17675 #if SYNCLINK_GENERIC_HDLC 17676 #endif 17677 #if 0 17678 #endif 17679 #if SYNCLINK_GENERIC_HDLC 17680 #endif 17681 #if SYNCLINK_GENERIC_HDLC 17682 #endif 17683 #define TESTFRAMESIZE 20 17684 #if SYNCLINK_GENERIC_HDLC 17685 #endif 17686 #define CALC_REGADDR() \ 17687 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17688 if (info->port_num > 1) \ 17689 RegAddr += 256; \ 17690 if ( info->port_num & 1) { \ 17691 if (Addr > 0x7f) \ 17692 RegAddr += 0x40; \ 17693 else if (Addr > 0x1f && Addr < 0x60) \ 17694 RegAddr += 0x20; \ 17695 } 17696 /* LDV_COMMENT_END_PREP */ 17697 17698 17699 17700 17701 } 17702 17703 break; 17704 case 22: { 17705 17706 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17707 17708 17709 /* content: static int set_break(struct tty_struct *tty, int break_state)*/ 17710 /* LDV_COMMENT_BEGIN_PREP */ 17711 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17712 #if defined(__i386__) 17713 # define BREAKPOINT() asm(" int $3"); 17714 #else 17715 # define BREAKPOINT() { } 17716 #endif 17717 #define MAX_DEVICES 12 17718 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17719 #define SYNCLINK_GENERIC_HDLC 1 17720 #else 17721 #define SYNCLINK_GENERIC_HDLC 0 17722 #endif 17723 #define GET_USER(error,value,addr) error = get_user(value,addr) 17724 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17725 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17726 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17727 #define SCABUFSIZE 1024 17728 #define SCA_MEM_SIZE 0x40000 17729 #define SCA_BASE_SIZE 512 17730 #define SCA_REG_SIZE 16 17731 #define SCA_MAX_PORTS 4 17732 #define SCAMAXDESC 128 17733 #define BUFFERLISTSIZE 4096 17734 #define BH_RECEIVE 1 17735 #define BH_TRANSMIT 2 17736 #define BH_STATUS 4 17737 #define IO_PIN_SHUTDOWN_LIMIT 100 17738 #if SYNCLINK_GENERIC_HDLC 17739 #endif 17740 #define MGSL_MAGIC 0x5401 17741 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17742 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17743 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17744 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17745 #define LPR 0x00 17746 #define PABR0 0x02 17747 #define PABR1 0x03 17748 #define WCRL 0x04 17749 #define WCRM 0x05 17750 #define WCRH 0x06 17751 #define DPCR 0x08 17752 #define DMER 0x09 17753 #define ISR0 0x10 17754 #define ISR1 0x11 17755 #define ISR2 0x12 17756 #define IER0 0x14 17757 #define IER1 0x15 17758 #define IER2 0x16 17759 #define ITCR 0x18 17760 #define INTVR 0x1a 17761 #define IMVR 0x1c 17762 #define TRB 0x20 17763 #define TRBL 0x20 17764 #define TRBH 0x21 17765 #define SR0 0x22 17766 #define SR1 0x23 17767 #define SR2 0x24 17768 #define SR3 0x25 17769 #define FST 0x26 17770 #define IE0 0x28 17771 #define IE1 0x29 17772 #define IE2 0x2a 17773 #define FIE 0x2b 17774 #define CMD 0x2c 17775 #define MD0 0x2e 17776 #define MD1 0x2f 17777 #define MD2 0x30 17778 #define CTL 0x31 17779 #define SA0 0x32 17780 #define SA1 0x33 17781 #define IDL 0x34 17782 #define TMC 0x35 17783 #define RXS 0x36 17784 #define TXS 0x37 17785 #define TRC0 0x38 17786 #define TRC1 0x39 17787 #define RRC 0x3a 17788 #define CST0 0x3c 17789 #define CST1 0x3d 17790 #define TCNT 0x60 17791 #define TCNTL 0x60 17792 #define TCNTH 0x61 17793 #define TCONR 0x62 17794 #define TCONRL 0x62 17795 #define TCONRH 0x63 17796 #define TMCS 0x64 17797 #define TEPR 0x65 17798 #define DARL 0x80 17799 #define DARH 0x81 17800 #define DARB 0x82 17801 #define BAR 0x80 17802 #define BARL 0x80 17803 #define BARH 0x81 17804 #define BARB 0x82 17805 #define SAR 0x84 17806 #define SARL 0x84 17807 #define SARH 0x85 17808 #define SARB 0x86 17809 #define CPB 0x86 17810 #define CDA 0x88 17811 #define CDAL 0x88 17812 #define CDAH 0x89 17813 #define EDA 0x8a 17814 #define EDAL 0x8a 17815 #define EDAH 0x8b 17816 #define BFL 0x8c 17817 #define BFLL 0x8c 17818 #define BFLH 0x8d 17819 #define BCR 0x8e 17820 #define BCRL 0x8e 17821 #define BCRH 0x8f 17822 #define DSR 0x90 17823 #define DMR 0x91 17824 #define FCT 0x93 17825 #define DIR 0x94 17826 #define DCMD 0x95 17827 #define TIMER0 0x00 17828 #define TIMER1 0x08 17829 #define TIMER2 0x10 17830 #define TIMER3 0x18 17831 #define RXDMA 0x00 17832 #define TXDMA 0x20 17833 #define NOOP 0x00 17834 #define TXRESET 0x01 17835 #define TXENABLE 0x02 17836 #define TXDISABLE 0x03 17837 #define TXCRCINIT 0x04 17838 #define TXCRCEXCL 0x05 17839 #define TXEOM 0x06 17840 #define TXABORT 0x07 17841 #define MPON 0x08 17842 #define TXBUFCLR 0x09 17843 #define RXRESET 0x11 17844 #define RXENABLE 0x12 17845 #define RXDISABLE 0x13 17846 #define RXCRCINIT 0x14 17847 #define RXREJECT 0x15 17848 #define SEARCHMP 0x16 17849 #define RXCRCEXCL 0x17 17850 #define RXCRCCALC 0x18 17851 #define CHRESET 0x21 17852 #define HUNT 0x31 17853 #define SWABORT 0x01 17854 #define FEICLEAR 0x02 17855 #define TXINTE BIT7 17856 #define RXINTE BIT6 17857 #define TXRDYE BIT1 17858 #define RXRDYE BIT0 17859 #define UDRN BIT7 17860 #define IDLE BIT6 17861 #define SYNCD BIT4 17862 #define FLGD BIT4 17863 #define CCTS BIT3 17864 #define CDCD BIT2 17865 #define BRKD BIT1 17866 #define ABTD BIT1 17867 #define GAPD BIT1 17868 #define BRKE BIT0 17869 #define IDLD BIT0 17870 #define EOM BIT7 17871 #define PMP BIT6 17872 #define SHRT BIT6 17873 #define PE BIT5 17874 #define ABT BIT5 17875 #define FRME BIT4 17876 #define RBIT BIT4 17877 #define OVRN BIT3 17878 #define CRCE BIT2 17879 #define WAKEUP_CHARS 256 17880 #if SYNCLINK_GENERIC_HDLC 17881 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 17882 #endif 17883 #ifdef SANITY_CHECK 17884 #else 17885 #endif 17886 /* LDV_COMMENT_END_PREP */ 17887 /* LDV_COMMENT_FUNCTION_CALL Function from field "break_ctl" from driver structure with callbacks "ops" */ 17888 ldv_handler_precall(); 17889 set_break( var_group8, var_set_break_25_p1); 17890 /* LDV_COMMENT_BEGIN_PREP */ 17891 #if SYNCLINK_GENERIC_HDLC 17892 #endif 17893 #if SYNCLINK_GENERIC_HDLC 17894 #endif 17895 #if SYNCLINK_GENERIC_HDLC 17896 #endif 17897 #ifdef CMSPAR 17898 #endif 17899 #if SYNCLINK_GENERIC_HDLC 17900 #endif 17901 #if SYNCLINK_GENERIC_HDLC 17902 #endif 17903 #if 0 17904 #endif 17905 #if SYNCLINK_GENERIC_HDLC 17906 #endif 17907 #if SYNCLINK_GENERIC_HDLC 17908 #endif 17909 #define TESTFRAMESIZE 20 17910 #if SYNCLINK_GENERIC_HDLC 17911 #endif 17912 #define CALC_REGADDR() \ 17913 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17914 if (info->port_num > 1) \ 17915 RegAddr += 256; \ 17916 if ( info->port_num & 1) { \ 17917 if (Addr > 0x7f) \ 17918 RegAddr += 0x40; \ 17919 else if (Addr > 0x1f && Addr < 0x60) \ 17920 RegAddr += 0x20; \ 17921 } 17922 /* LDV_COMMENT_END_PREP */ 17923 17924 17925 17926 17927 } 17928 17929 break; 17930 case 23: { 17931 17932 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17933 17934 17935 /* content: static void wait_until_sent(struct tty_struct *tty, int timeout)*/ 17936 /* LDV_COMMENT_BEGIN_PREP */ 17937 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17938 #if defined(__i386__) 17939 # define BREAKPOINT() asm(" int $3"); 17940 #else 17941 # define BREAKPOINT() { } 17942 #endif 17943 #define MAX_DEVICES 12 17944 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17945 #define SYNCLINK_GENERIC_HDLC 1 17946 #else 17947 #define SYNCLINK_GENERIC_HDLC 0 17948 #endif 17949 #define GET_USER(error,value,addr) error = get_user(value,addr) 17950 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17951 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17952 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17953 #define SCABUFSIZE 1024 17954 #define SCA_MEM_SIZE 0x40000 17955 #define SCA_BASE_SIZE 512 17956 #define SCA_REG_SIZE 16 17957 #define SCA_MAX_PORTS 4 17958 #define SCAMAXDESC 128 17959 #define BUFFERLISTSIZE 4096 17960 #define BH_RECEIVE 1 17961 #define BH_TRANSMIT 2 17962 #define BH_STATUS 4 17963 #define IO_PIN_SHUTDOWN_LIMIT 100 17964 #if SYNCLINK_GENERIC_HDLC 17965 #endif 17966 #define MGSL_MAGIC 0x5401 17967 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17968 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17969 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17970 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17971 #define LPR 0x00 17972 #define PABR0 0x02 17973 #define PABR1 0x03 17974 #define WCRL 0x04 17975 #define WCRM 0x05 17976 #define WCRH 0x06 17977 #define DPCR 0x08 17978 #define DMER 0x09 17979 #define ISR0 0x10 17980 #define ISR1 0x11 17981 #define ISR2 0x12 17982 #define IER0 0x14 17983 #define IER1 0x15 17984 #define IER2 0x16 17985 #define ITCR 0x18 17986 #define INTVR 0x1a 17987 #define IMVR 0x1c 17988 #define TRB 0x20 17989 #define TRBL 0x20 17990 #define TRBH 0x21 17991 #define SR0 0x22 17992 #define SR1 0x23 17993 #define SR2 0x24 17994 #define SR3 0x25 17995 #define FST 0x26 17996 #define IE0 0x28 17997 #define IE1 0x29 17998 #define IE2 0x2a 17999 #define FIE 0x2b 18000 #define CMD 0x2c 18001 #define MD0 0x2e 18002 #define MD1 0x2f 18003 #define MD2 0x30 18004 #define CTL 0x31 18005 #define SA0 0x32 18006 #define SA1 0x33 18007 #define IDL 0x34 18008 #define TMC 0x35 18009 #define RXS 0x36 18010 #define TXS 0x37 18011 #define TRC0 0x38 18012 #define TRC1 0x39 18013 #define RRC 0x3a 18014 #define CST0 0x3c 18015 #define CST1 0x3d 18016 #define TCNT 0x60 18017 #define TCNTL 0x60 18018 #define TCNTH 0x61 18019 #define TCONR 0x62 18020 #define TCONRL 0x62 18021 #define TCONRH 0x63 18022 #define TMCS 0x64 18023 #define TEPR 0x65 18024 #define DARL 0x80 18025 #define DARH 0x81 18026 #define DARB 0x82 18027 #define BAR 0x80 18028 #define BARL 0x80 18029 #define BARH 0x81 18030 #define BARB 0x82 18031 #define SAR 0x84 18032 #define SARL 0x84 18033 #define SARH 0x85 18034 #define SARB 0x86 18035 #define CPB 0x86 18036 #define CDA 0x88 18037 #define CDAL 0x88 18038 #define CDAH 0x89 18039 #define EDA 0x8a 18040 #define EDAL 0x8a 18041 #define EDAH 0x8b 18042 #define BFL 0x8c 18043 #define BFLL 0x8c 18044 #define BFLH 0x8d 18045 #define BCR 0x8e 18046 #define BCRL 0x8e 18047 #define BCRH 0x8f 18048 #define DSR 0x90 18049 #define DMR 0x91 18050 #define FCT 0x93 18051 #define DIR 0x94 18052 #define DCMD 0x95 18053 #define TIMER0 0x00 18054 #define TIMER1 0x08 18055 #define TIMER2 0x10 18056 #define TIMER3 0x18 18057 #define RXDMA 0x00 18058 #define TXDMA 0x20 18059 #define NOOP 0x00 18060 #define TXRESET 0x01 18061 #define TXENABLE 0x02 18062 #define TXDISABLE 0x03 18063 #define TXCRCINIT 0x04 18064 #define TXCRCEXCL 0x05 18065 #define TXEOM 0x06 18066 #define TXABORT 0x07 18067 #define MPON 0x08 18068 #define TXBUFCLR 0x09 18069 #define RXRESET 0x11 18070 #define RXENABLE 0x12 18071 #define RXDISABLE 0x13 18072 #define RXCRCINIT 0x14 18073 #define RXREJECT 0x15 18074 #define SEARCHMP 0x16 18075 #define RXCRCEXCL 0x17 18076 #define RXCRCCALC 0x18 18077 #define CHRESET 0x21 18078 #define HUNT 0x31 18079 #define SWABORT 0x01 18080 #define FEICLEAR 0x02 18081 #define TXINTE BIT7 18082 #define RXINTE BIT6 18083 #define TXRDYE BIT1 18084 #define RXRDYE BIT0 18085 #define UDRN BIT7 18086 #define IDLE BIT6 18087 #define SYNCD BIT4 18088 #define FLGD BIT4 18089 #define CCTS BIT3 18090 #define CDCD BIT2 18091 #define BRKD BIT1 18092 #define ABTD BIT1 18093 #define GAPD BIT1 18094 #define BRKE BIT0 18095 #define IDLD BIT0 18096 #define EOM BIT7 18097 #define PMP BIT6 18098 #define SHRT BIT6 18099 #define PE BIT5 18100 #define ABT BIT5 18101 #define FRME BIT4 18102 #define RBIT BIT4 18103 #define OVRN BIT3 18104 #define CRCE BIT2 18105 #define WAKEUP_CHARS 256 18106 #if SYNCLINK_GENERIC_HDLC 18107 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 18108 #endif 18109 #ifdef SANITY_CHECK 18110 #else 18111 #endif 18112 /* LDV_COMMENT_END_PREP */ 18113 /* LDV_COMMENT_FUNCTION_CALL Function from field "wait_until_sent" from driver structure with callbacks "ops" */ 18114 ldv_handler_precall(); 18115 wait_until_sent( var_group8, var_wait_until_sent_11_p1); 18116 /* LDV_COMMENT_BEGIN_PREP */ 18117 #if SYNCLINK_GENERIC_HDLC 18118 #endif 18119 #if SYNCLINK_GENERIC_HDLC 18120 #endif 18121 #if SYNCLINK_GENERIC_HDLC 18122 #endif 18123 #ifdef CMSPAR 18124 #endif 18125 #if SYNCLINK_GENERIC_HDLC 18126 #endif 18127 #if SYNCLINK_GENERIC_HDLC 18128 #endif 18129 #if 0 18130 #endif 18131 #if SYNCLINK_GENERIC_HDLC 18132 #endif 18133 #if SYNCLINK_GENERIC_HDLC 18134 #endif 18135 #define TESTFRAMESIZE 20 18136 #if SYNCLINK_GENERIC_HDLC 18137 #endif 18138 #define CALC_REGADDR() \ 18139 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 18140 if (info->port_num > 1) \ 18141 RegAddr += 256; \ 18142 if ( info->port_num & 1) { \ 18143 if (Addr > 0x7f) \ 18144 RegAddr += 0x40; \ 18145 else if (Addr > 0x1f && Addr < 0x60) \ 18146 RegAddr += 0x20; \ 18147 } 18148 /* LDV_COMMENT_END_PREP */ 18149 18150 18151 18152 18153 } 18154 18155 break; 18156 case 24: { 18157 18158 /** STRUCT: struct type: tty_operations, struct name: ops **/ 18159 18160 18161 /* content: static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)*/ 18162 /* LDV_COMMENT_BEGIN_PREP */ 18163 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 18164 #if defined(__i386__) 18165 # define BREAKPOINT() asm(" int $3"); 18166 #else 18167 # define BREAKPOINT() { } 18168 #endif 18169 #define MAX_DEVICES 12 18170 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 18171 #define SYNCLINK_GENERIC_HDLC 1 18172 #else 18173 #define SYNCLINK_GENERIC_HDLC 0 18174 #endif 18175 #define GET_USER(error,value,addr) error = get_user(value,addr) 18176 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 18177 #define PUT_USER(error,value,addr) error = put_user(value,addr) 18178 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 18179 #define SCABUFSIZE 1024 18180 #define SCA_MEM_SIZE 0x40000 18181 #define SCA_BASE_SIZE 512 18182 #define SCA_REG_SIZE 16 18183 #define SCA_MAX_PORTS 4 18184 #define SCAMAXDESC 128 18185 #define BUFFERLISTSIZE 4096 18186 #define BH_RECEIVE 1 18187 #define BH_TRANSMIT 2 18188 #define BH_STATUS 4 18189 #define IO_PIN_SHUTDOWN_LIMIT 100 18190 #if SYNCLINK_GENERIC_HDLC 18191 #endif 18192 #define MGSL_MAGIC 0x5401 18193 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 18194 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 18195 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 18196 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 18197 #define LPR 0x00 18198 #define PABR0 0x02 18199 #define PABR1 0x03 18200 #define WCRL 0x04 18201 #define WCRM 0x05 18202 #define WCRH 0x06 18203 #define DPCR 0x08 18204 #define DMER 0x09 18205 #define ISR0 0x10 18206 #define ISR1 0x11 18207 #define ISR2 0x12 18208 #define IER0 0x14 18209 #define IER1 0x15 18210 #define IER2 0x16 18211 #define ITCR 0x18 18212 #define INTVR 0x1a 18213 #define IMVR 0x1c 18214 #define TRB 0x20 18215 #define TRBL 0x20 18216 #define TRBH 0x21 18217 #define SR0 0x22 18218 #define SR1 0x23 18219 #define SR2 0x24 18220 #define SR3 0x25 18221 #define FST 0x26 18222 #define IE0 0x28 18223 #define IE1 0x29 18224 #define IE2 0x2a 18225 #define FIE 0x2b 18226 #define CMD 0x2c 18227 #define MD0 0x2e 18228 #define MD1 0x2f 18229 #define MD2 0x30 18230 #define CTL 0x31 18231 #define SA0 0x32 18232 #define SA1 0x33 18233 #define IDL 0x34 18234 #define TMC 0x35 18235 #define RXS 0x36 18236 #define TXS 0x37 18237 #define TRC0 0x38 18238 #define TRC1 0x39 18239 #define RRC 0x3a 18240 #define CST0 0x3c 18241 #define CST1 0x3d 18242 #define TCNT 0x60 18243 #define TCNTL 0x60 18244 #define TCNTH 0x61 18245 #define TCONR 0x62 18246 #define TCONRL 0x62 18247 #define TCONRH 0x63 18248 #define TMCS 0x64 18249 #define TEPR 0x65 18250 #define DARL 0x80 18251 #define DARH 0x81 18252 #define DARB 0x82 18253 #define BAR 0x80 18254 #define BARL 0x80 18255 #define BARH 0x81 18256 #define BARB 0x82 18257 #define SAR 0x84 18258 #define SARL 0x84 18259 #define SARH 0x85 18260 #define SARB 0x86 18261 #define CPB 0x86 18262 #define CDA 0x88 18263 #define CDAL 0x88 18264 #define CDAH 0x89 18265 #define EDA 0x8a 18266 #define EDAL 0x8a 18267 #define EDAH 0x8b 18268 #define BFL 0x8c 18269 #define BFLL 0x8c 18270 #define BFLH 0x8d 18271 #define BCR 0x8e 18272 #define BCRL 0x8e 18273 #define BCRH 0x8f 18274 #define DSR 0x90 18275 #define DMR 0x91 18276 #define FCT 0x93 18277 #define DIR 0x94 18278 #define DCMD 0x95 18279 #define TIMER0 0x00 18280 #define TIMER1 0x08 18281 #define TIMER2 0x10 18282 #define TIMER3 0x18 18283 #define RXDMA 0x00 18284 #define TXDMA 0x20 18285 #define NOOP 0x00 18286 #define TXRESET 0x01 18287 #define TXENABLE 0x02 18288 #define TXDISABLE 0x03 18289 #define TXCRCINIT 0x04 18290 #define TXCRCEXCL 0x05 18291 #define TXEOM 0x06 18292 #define TXABORT 0x07 18293 #define MPON 0x08 18294 #define TXBUFCLR 0x09 18295 #define RXRESET 0x11 18296 #define RXENABLE 0x12 18297 #define RXDISABLE 0x13 18298 #define RXCRCINIT 0x14 18299 #define RXREJECT 0x15 18300 #define SEARCHMP 0x16 18301 #define RXCRCEXCL 0x17 18302 #define RXCRCCALC 0x18 18303 #define CHRESET 0x21 18304 #define HUNT 0x31 18305 #define SWABORT 0x01 18306 #define FEICLEAR 0x02 18307 #define TXINTE BIT7 18308 #define RXINTE BIT6 18309 #define TXRDYE BIT1 18310 #define RXRDYE BIT0 18311 #define UDRN BIT7 18312 #define IDLE BIT6 18313 #define SYNCD BIT4 18314 #define FLGD BIT4 18315 #define CCTS BIT3 18316 #define CDCD BIT2 18317 #define BRKD BIT1 18318 #define ABTD BIT1 18319 #define GAPD BIT1 18320 #define BRKE BIT0 18321 #define IDLD BIT0 18322 #define EOM BIT7 18323 #define PMP BIT6 18324 #define SHRT BIT6 18325 #define PE BIT5 18326 #define ABT BIT5 18327 #define FRME BIT4 18328 #define RBIT BIT4 18329 #define OVRN BIT3 18330 #define CRCE BIT2 18331 #define WAKEUP_CHARS 256 18332 #if SYNCLINK_GENERIC_HDLC 18333 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 18334 #endif 18335 #ifdef SANITY_CHECK 18336 #else 18337 #endif 18338 /* LDV_COMMENT_END_PREP */ 18339 /* LDV_COMMENT_FUNCTION_CALL Function from field "set_termios" from driver structure with callbacks "ops" */ 18340 ldv_handler_precall(); 18341 set_termios( var_group8, var_group9); 18342 /* LDV_COMMENT_BEGIN_PREP */ 18343 #if SYNCLINK_GENERIC_HDLC 18344 #endif 18345 #if SYNCLINK_GENERIC_HDLC 18346 #endif 18347 #if SYNCLINK_GENERIC_HDLC 18348 #endif 18349 #ifdef CMSPAR 18350 #endif 18351 #if SYNCLINK_GENERIC_HDLC 18352 #endif 18353 #if SYNCLINK_GENERIC_HDLC 18354 #endif 18355 #if 0 18356 #endif 18357 #if SYNCLINK_GENERIC_HDLC 18358 #endif 18359 #if SYNCLINK_GENERIC_HDLC 18360 #endif 18361 #define TESTFRAMESIZE 20 18362 #if SYNCLINK_GENERIC_HDLC 18363 #endif 18364 #define CALC_REGADDR() \ 18365 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 18366 if (info->port_num > 1) \ 18367 RegAddr += 256; \ 18368 if ( info->port_num & 1) { \ 18369 if (Addr > 0x7f) \ 18370 RegAddr += 0x40; \ 18371 else if (Addr > 0x1f && Addr < 0x60) \ 18372 RegAddr += 0x20; \ 18373 } 18374 /* LDV_COMMENT_END_PREP */ 18375 18376 18377 18378 18379 } 18380 18381 break; 18382 case 25: { 18383 18384 /** STRUCT: struct type: tty_operations, struct name: ops **/ 18385 18386 18387 /* content: static void tx_hold(struct tty_struct *tty)*/ 18388 /* LDV_COMMENT_BEGIN_PREP */ 18389 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 18390 #if defined(__i386__) 18391 # define BREAKPOINT() asm(" int $3"); 18392 #else 18393 # define BREAKPOINT() { } 18394 #endif 18395 #define MAX_DEVICES 12 18396 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 18397 #define SYNCLINK_GENERIC_HDLC 1 18398 #else 18399 #define SYNCLINK_GENERIC_HDLC 0 18400 #endif 18401 #define GET_USER(error,value,addr) error = get_user(value,addr) 18402 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 18403 #define PUT_USER(error,value,addr) error = put_user(value,addr) 18404 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 18405 #define SCABUFSIZE 1024 18406 #define SCA_MEM_SIZE 0x40000 18407 #define SCA_BASE_SIZE 512 18408 #define SCA_REG_SIZE 16 18409 #define SCA_MAX_PORTS 4 18410 #define SCAMAXDESC 128 18411 #define BUFFERLISTSIZE 4096 18412 #define BH_RECEIVE 1 18413 #define BH_TRANSMIT 2 18414 #define BH_STATUS 4 18415 #define IO_PIN_SHUTDOWN_LIMIT 100 18416 #if SYNCLINK_GENERIC_HDLC 18417 #endif 18418 #define MGSL_MAGIC 0x5401 18419 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 18420 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 18421 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 18422 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 18423 #define LPR 0x00 18424 #define PABR0 0x02 18425 #define PABR1 0x03 18426 #define WCRL 0x04 18427 #define WCRM 0x05 18428 #define WCRH 0x06 18429 #define DPCR 0x08 18430 #define DMER 0x09 18431 #define ISR0 0x10 18432 #define ISR1 0x11 18433 #define ISR2 0x12 18434 #define IER0 0x14 18435 #define IER1 0x15 18436 #define IER2 0x16 18437 #define ITCR 0x18 18438 #define INTVR 0x1a 18439 #define IMVR 0x1c 18440 #define TRB 0x20 18441 #define TRBL 0x20 18442 #define TRBH 0x21 18443 #define SR0 0x22 18444 #define SR1 0x23 18445 #define SR2 0x24 18446 #define SR3 0x25 18447 #define FST 0x26 18448 #define IE0 0x28 18449 #define IE1 0x29 18450 #define IE2 0x2a 18451 #define FIE 0x2b 18452 #define CMD 0x2c 18453 #define MD0 0x2e 18454 #define MD1 0x2f 18455 #define MD2 0x30 18456 #define CTL 0x31 18457 #define SA0 0x32 18458 #define SA1 0x33 18459 #define IDL 0x34 18460 #define TMC 0x35 18461 #define RXS 0x36 18462 #define TXS 0x37 18463 #define TRC0 0x38 18464 #define TRC1 0x39 18465 #define RRC 0x3a 18466 #define CST0 0x3c 18467 #define CST1 0x3d 18468 #define TCNT 0x60 18469 #define TCNTL 0x60 18470 #define TCNTH 0x61 18471 #define TCONR 0x62 18472 #define TCONRL 0x62 18473 #define TCONRH 0x63 18474 #define TMCS 0x64 18475 #define TEPR 0x65 18476 #define DARL 0x80 18477 #define DARH 0x81 18478 #define DARB 0x82 18479 #define BAR 0x80 18480 #define BARL 0x80 18481 #define BARH 0x81 18482 #define BARB 0x82 18483 #define SAR 0x84 18484 #define SARL 0x84 18485 #define SARH 0x85 18486 #define SARB 0x86 18487 #define CPB 0x86 18488 #define CDA 0x88 18489 #define CDAL 0x88 18490 #define CDAH 0x89 18491 #define EDA 0x8a 18492 #define EDAL 0x8a 18493 #define EDAH 0x8b 18494 #define BFL 0x8c 18495 #define BFLL 0x8c 18496 #define BFLH 0x8d 18497 #define BCR 0x8e 18498 #define BCRL 0x8e 18499 #define BCRH 0x8f 18500 #define DSR 0x90 18501 #define DMR 0x91 18502 #define FCT 0x93 18503 #define DIR 0x94 18504 #define DCMD 0x95 18505 #define TIMER0 0x00 18506 #define TIMER1 0x08 18507 #define TIMER2 0x10 18508 #define TIMER3 0x18 18509 #define RXDMA 0x00 18510 #define TXDMA 0x20 18511 #define NOOP 0x00 18512 #define TXRESET 0x01 18513 #define TXENABLE 0x02 18514 #define TXDISABLE 0x03 18515 #define TXCRCINIT 0x04 18516 #define TXCRCEXCL 0x05 18517 #define TXEOM 0x06 18518 #define TXABORT 0x07 18519 #define MPON 0x08 18520 #define TXBUFCLR 0x09 18521 #define RXRESET 0x11 18522 #define RXENABLE 0x12 18523 #define RXDISABLE 0x13 18524 #define RXCRCINIT 0x14 18525 #define RXREJECT 0x15 18526 #define SEARCHMP 0x16 18527 #define RXCRCEXCL 0x17 18528 #define RXCRCCALC 0x18 18529 #define CHRESET 0x21 18530 #define HUNT 0x31 18531 #define SWABORT 0x01 18532 #define FEICLEAR 0x02 18533 #define TXINTE BIT7 18534 #define RXINTE BIT6 18535 #define TXRDYE BIT1 18536 #define RXRDYE BIT0 18537 #define UDRN BIT7 18538 #define IDLE BIT6 18539 #define SYNCD BIT4 18540 #define FLGD BIT4 18541 #define CCTS BIT3 18542 #define CDCD BIT2 18543 #define BRKD BIT1 18544 #define ABTD BIT1 18545 #define GAPD BIT1 18546 #define BRKE BIT0 18547 #define IDLD BIT0 18548 #define EOM BIT7 18549 #define PMP BIT6 18550 #define SHRT BIT6 18551 #define PE BIT5 18552 #define ABT BIT5 18553 #define FRME BIT4 18554 #define RBIT BIT4 18555 #define OVRN BIT3 18556 #define CRCE BIT2 18557 #define WAKEUP_CHARS 256 18558 #if SYNCLINK_GENERIC_HDLC 18559 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 18560 #endif 18561 #ifdef SANITY_CHECK 18562 #else 18563 #endif 18564 /* LDV_COMMENT_END_PREP */ 18565 /* LDV_COMMENT_FUNCTION_CALL Function from field "stop" from driver structure with callbacks "ops" */ 18566 ldv_handler_precall(); 18567 tx_hold( var_group8); 18568 /* LDV_COMMENT_BEGIN_PREP */ 18569 #if SYNCLINK_GENERIC_HDLC 18570 #endif 18571 #if SYNCLINK_GENERIC_HDLC 18572 #endif 18573 #if SYNCLINK_GENERIC_HDLC 18574 #endif 18575 #ifdef CMSPAR 18576 #endif 18577 #if SYNCLINK_GENERIC_HDLC 18578 #endif 18579 #if SYNCLINK_GENERIC_HDLC 18580 #endif 18581 #if 0 18582 #endif 18583 #if SYNCLINK_GENERIC_HDLC 18584 #endif 18585 #if SYNCLINK_GENERIC_HDLC 18586 #endif 18587 #define TESTFRAMESIZE 20 18588 #if SYNCLINK_GENERIC_HDLC 18589 #endif 18590 #define CALC_REGADDR() \ 18591 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 18592 if (info->port_num > 1) \ 18593 RegAddr += 256; \ 18594 if ( info->port_num & 1) { \ 18595 if (Addr > 0x7f) \ 18596 RegAddr += 0x40; \ 18597 else if (Addr > 0x1f && Addr < 0x60) \ 18598 RegAddr += 0x20; \ 18599 } 18600 /* LDV_COMMENT_END_PREP */ 18601 18602 18603 18604 18605 } 18606 18607 break; 18608 case 26: { 18609 18610 /** STRUCT: struct type: tty_operations, struct name: ops **/ 18611 18612 18613 /* content: static void tx_release(struct tty_struct *tty)*/ 18614 /* LDV_COMMENT_BEGIN_PREP */ 18615 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 18616 #if defined(__i386__) 18617 # define BREAKPOINT() asm(" int $3"); 18618 #else 18619 # define BREAKPOINT() { } 18620 #endif 18621 #define MAX_DEVICES 12 18622 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 18623 #define SYNCLINK_GENERIC_HDLC 1 18624 #else 18625 #define SYNCLINK_GENERIC_HDLC 0 18626 #endif 18627 #define GET_USER(error,value,addr) error = get_user(value,addr) 18628 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 18629 #define PUT_USER(error,value,addr) error = put_user(value,addr) 18630 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 18631 #define SCABUFSIZE 1024 18632 #define SCA_MEM_SIZE 0x40000 18633 #define SCA_BASE_SIZE 512 18634 #define SCA_REG_SIZE 16 18635 #define SCA_MAX_PORTS 4 18636 #define SCAMAXDESC 128 18637 #define BUFFERLISTSIZE 4096 18638 #define BH_RECEIVE 1 18639 #define BH_TRANSMIT 2 18640 #define BH_STATUS 4 18641 #define IO_PIN_SHUTDOWN_LIMIT 100 18642 #if SYNCLINK_GENERIC_HDLC 18643 #endif 18644 #define MGSL_MAGIC 0x5401 18645 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 18646 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 18647 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 18648 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 18649 #define LPR 0x00 18650 #define PABR0 0x02 18651 #define PABR1 0x03 18652 #define WCRL 0x04 18653 #define WCRM 0x05 18654 #define WCRH 0x06 18655 #define DPCR 0x08 18656 #define DMER 0x09 18657 #define ISR0 0x10 18658 #define ISR1 0x11 18659 #define ISR2 0x12 18660 #define IER0 0x14 18661 #define IER1 0x15 18662 #define IER2 0x16 18663 #define ITCR 0x18 18664 #define INTVR 0x1a 18665 #define IMVR 0x1c 18666 #define TRB 0x20 18667 #define TRBL 0x20 18668 #define TRBH 0x21 18669 #define SR0 0x22 18670 #define SR1 0x23 18671 #define SR2 0x24 18672 #define SR3 0x25 18673 #define FST 0x26 18674 #define IE0 0x28 18675 #define IE1 0x29 18676 #define IE2 0x2a 18677 #define FIE 0x2b 18678 #define CMD 0x2c 18679 #define MD0 0x2e 18680 #define MD1 0x2f 18681 #define MD2 0x30 18682 #define CTL 0x31 18683 #define SA0 0x32 18684 #define SA1 0x33 18685 #define IDL 0x34 18686 #define TMC 0x35 18687 #define RXS 0x36 18688 #define TXS 0x37 18689 #define TRC0 0x38 18690 #define TRC1 0x39 18691 #define RRC 0x3a 18692 #define CST0 0x3c 18693 #define CST1 0x3d 18694 #define TCNT 0x60 18695 #define TCNTL 0x60 18696 #define TCNTH 0x61 18697 #define TCONR 0x62 18698 #define TCONRL 0x62 18699 #define TCONRH 0x63 18700 #define TMCS 0x64 18701 #define TEPR 0x65 18702 #define DARL 0x80 18703 #define DARH 0x81 18704 #define DARB 0x82 18705 #define BAR 0x80 18706 #define BARL 0x80 18707 #define BARH 0x81 18708 #define BARB 0x82 18709 #define SAR 0x84 18710 #define SARL 0x84 18711 #define SARH 0x85 18712 #define SARB 0x86 18713 #define CPB 0x86 18714 #define CDA 0x88 18715 #define CDAL 0x88 18716 #define CDAH 0x89 18717 #define EDA 0x8a 18718 #define EDAL 0x8a 18719 #define EDAH 0x8b 18720 #define BFL 0x8c 18721 #define BFLL 0x8c 18722 #define BFLH 0x8d 18723 #define BCR 0x8e 18724 #define BCRL 0x8e 18725 #define BCRH 0x8f 18726 #define DSR 0x90 18727 #define DMR 0x91 18728 #define FCT 0x93 18729 #define DIR 0x94 18730 #define DCMD 0x95 18731 #define TIMER0 0x00 18732 #define TIMER1 0x08 18733 #define TIMER2 0x10 18734 #define TIMER3 0x18 18735 #define RXDMA 0x00 18736 #define TXDMA 0x20 18737 #define NOOP 0x00 18738 #define TXRESET 0x01 18739 #define TXENABLE 0x02 18740 #define TXDISABLE 0x03 18741 #define TXCRCINIT 0x04 18742 #define TXCRCEXCL 0x05 18743 #define TXEOM 0x06 18744 #define TXABORT 0x07 18745 #define MPON 0x08 18746 #define TXBUFCLR 0x09 18747 #define RXRESET 0x11 18748 #define RXENABLE 0x12 18749 #define RXDISABLE 0x13 18750 #define RXCRCINIT 0x14 18751 #define RXREJECT 0x15 18752 #define SEARCHMP 0x16 18753 #define RXCRCEXCL 0x17 18754 #define RXCRCCALC 0x18 18755 #define CHRESET 0x21 18756 #define HUNT 0x31 18757 #define SWABORT 0x01 18758 #define FEICLEAR 0x02 18759 #define TXINTE BIT7 18760 #define RXINTE BIT6 18761 #define TXRDYE BIT1 18762 #define RXRDYE BIT0 18763 #define UDRN BIT7 18764 #define IDLE BIT6 18765 #define SYNCD BIT4 18766 #define FLGD BIT4 18767 #define CCTS BIT3 18768 #define CDCD BIT2 18769 #define BRKD BIT1 18770 #define ABTD BIT1 18771 #define GAPD BIT1 18772 #define BRKE BIT0 18773 #define IDLD BIT0 18774 #define EOM BIT7 18775 #define PMP BIT6 18776 #define SHRT BIT6 18777 #define PE BIT5 18778 #define ABT BIT5 18779 #define FRME BIT4 18780 #define RBIT BIT4 18781 #define OVRN BIT3 18782 #define CRCE BIT2 18783 #define WAKEUP_CHARS 256 18784 #if SYNCLINK_GENERIC_HDLC 18785 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 18786 #endif 18787 #ifdef SANITY_CHECK 18788 #else 18789 #endif 18790 /* LDV_COMMENT_END_PREP */ 18791 /* LDV_COMMENT_FUNCTION_CALL Function from field "start" from driver structure with callbacks "ops" */ 18792 ldv_handler_precall(); 18793 tx_release( var_group8); 18794 /* LDV_COMMENT_BEGIN_PREP */ 18795 #if SYNCLINK_GENERIC_HDLC 18796 #endif 18797 #if SYNCLINK_GENERIC_HDLC 18798 #endif 18799 #if SYNCLINK_GENERIC_HDLC 18800 #endif 18801 #ifdef CMSPAR 18802 #endif 18803 #if SYNCLINK_GENERIC_HDLC 18804 #endif 18805 #if SYNCLINK_GENERIC_HDLC 18806 #endif 18807 #if 0 18808 #endif 18809 #if SYNCLINK_GENERIC_HDLC 18810 #endif 18811 #if SYNCLINK_GENERIC_HDLC 18812 #endif 18813 #define TESTFRAMESIZE 20 18814 #if SYNCLINK_GENERIC_HDLC 18815 #endif 18816 #define CALC_REGADDR() \ 18817 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 18818 if (info->port_num > 1) \ 18819 RegAddr += 256; \ 18820 if ( info->port_num & 1) { \ 18821 if (Addr > 0x7f) \ 18822 RegAddr += 0x40; \ 18823 else if (Addr > 0x1f && Addr < 0x60) \ 18824 RegAddr += 0x20; \ 18825 } 18826 /* LDV_COMMENT_END_PREP */ 18827 18828 18829 18830 18831 } 18832 18833 break; 18834 case 27: { 18835 18836 /** STRUCT: struct type: tty_operations, struct name: ops **/ 18837 18838 18839 /* content: static void hangup(struct tty_struct *tty)*/ 18840 /* LDV_COMMENT_BEGIN_PREP */ 18841 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 18842 #if defined(__i386__) 18843 # define BREAKPOINT() asm(" int $3"); 18844 #else 18845 # define BREAKPOINT() { } 18846 #endif 18847 #define MAX_DEVICES 12 18848 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 18849 #define SYNCLINK_GENERIC_HDLC 1 18850 #else 18851 #define SYNCLINK_GENERIC_HDLC 0 18852 #endif 18853 #define GET_USER(error,value,addr) error = get_user(value,addr) 18854 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 18855 #define PUT_USER(error,value,addr) error = put_user(value,addr) 18856 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 18857 #define SCABUFSIZE 1024 18858 #define SCA_MEM_SIZE 0x40000 18859 #define SCA_BASE_SIZE 512 18860 #define SCA_REG_SIZE 16 18861 #define SCA_MAX_PORTS 4 18862 #define SCAMAXDESC 128 18863 #define BUFFERLISTSIZE 4096 18864 #define BH_RECEIVE 1 18865 #define BH_TRANSMIT 2 18866 #define BH_STATUS 4 18867 #define IO_PIN_SHUTDOWN_LIMIT 100 18868 #if SYNCLINK_GENERIC_HDLC 18869 #endif 18870 #define MGSL_MAGIC 0x5401 18871 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 18872 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 18873 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 18874 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 18875 #define LPR 0x00 18876 #define PABR0 0x02 18877 #define PABR1 0x03 18878 #define WCRL 0x04 18879 #define WCRM 0x05 18880 #define WCRH 0x06 18881 #define DPCR 0x08 18882 #define DMER 0x09 18883 #define ISR0 0x10 18884 #define ISR1 0x11 18885 #define ISR2 0x12 18886 #define IER0 0x14 18887 #define IER1 0x15 18888 #define IER2 0x16 18889 #define ITCR 0x18 18890 #define INTVR 0x1a 18891 #define IMVR 0x1c 18892 #define TRB 0x20 18893 #define TRBL 0x20 18894 #define TRBH 0x21 18895 #define SR0 0x22 18896 #define SR1 0x23 18897 #define SR2 0x24 18898 #define SR3 0x25 18899 #define FST 0x26 18900 #define IE0 0x28 18901 #define IE1 0x29 18902 #define IE2 0x2a 18903 #define FIE 0x2b 18904 #define CMD 0x2c 18905 #define MD0 0x2e 18906 #define MD1 0x2f 18907 #define MD2 0x30 18908 #define CTL 0x31 18909 #define SA0 0x32 18910 #define SA1 0x33 18911 #define IDL 0x34 18912 #define TMC 0x35 18913 #define RXS 0x36 18914 #define TXS 0x37 18915 #define TRC0 0x38 18916 #define TRC1 0x39 18917 #define RRC 0x3a 18918 #define CST0 0x3c 18919 #define CST1 0x3d 18920 #define TCNT 0x60 18921 #define TCNTL 0x60 18922 #define TCNTH 0x61 18923 #define TCONR 0x62 18924 #define TCONRL 0x62 18925 #define TCONRH 0x63 18926 #define TMCS 0x64 18927 #define TEPR 0x65 18928 #define DARL 0x80 18929 #define DARH 0x81 18930 #define DARB 0x82 18931 #define BAR 0x80 18932 #define BARL 0x80 18933 #define BARH 0x81 18934 #define BARB 0x82 18935 #define SAR 0x84 18936 #define SARL 0x84 18937 #define SARH 0x85 18938 #define SARB 0x86 18939 #define CPB 0x86 18940 #define CDA 0x88 18941 #define CDAL 0x88 18942 #define CDAH 0x89 18943 #define EDA 0x8a 18944 #define EDAL 0x8a 18945 #define EDAH 0x8b 18946 #define BFL 0x8c 18947 #define BFLL 0x8c 18948 #define BFLH 0x8d 18949 #define BCR 0x8e 18950 #define BCRL 0x8e 18951 #define BCRH 0x8f 18952 #define DSR 0x90 18953 #define DMR 0x91 18954 #define FCT 0x93 18955 #define DIR 0x94 18956 #define DCMD 0x95 18957 #define TIMER0 0x00 18958 #define TIMER1 0x08 18959 #define TIMER2 0x10 18960 #define TIMER3 0x18 18961 #define RXDMA 0x00 18962 #define TXDMA 0x20 18963 #define NOOP 0x00 18964 #define TXRESET 0x01 18965 #define TXENABLE 0x02 18966 #define TXDISABLE 0x03 18967 #define TXCRCINIT 0x04 18968 #define TXCRCEXCL 0x05 18969 #define TXEOM 0x06 18970 #define TXABORT 0x07 18971 #define MPON 0x08 18972 #define TXBUFCLR 0x09 18973 #define RXRESET 0x11 18974 #define RXENABLE 0x12 18975 #define RXDISABLE 0x13 18976 #define RXCRCINIT 0x14 18977 #define RXREJECT 0x15 18978 #define SEARCHMP 0x16 18979 #define RXCRCEXCL 0x17 18980 #define RXCRCCALC 0x18 18981 #define CHRESET 0x21 18982 #define HUNT 0x31 18983 #define SWABORT 0x01 18984 #define FEICLEAR 0x02 18985 #define TXINTE BIT7 18986 #define RXINTE BIT6 18987 #define TXRDYE BIT1 18988 #define RXRDYE BIT0 18989 #define UDRN BIT7 18990 #define IDLE BIT6 18991 #define SYNCD BIT4 18992 #define FLGD BIT4 18993 #define CCTS BIT3 18994 #define CDCD BIT2 18995 #define BRKD BIT1 18996 #define ABTD BIT1 18997 #define GAPD BIT1 18998 #define BRKE BIT0 18999 #define IDLD BIT0 19000 #define EOM BIT7 19001 #define PMP BIT6 19002 #define SHRT BIT6 19003 #define PE BIT5 19004 #define ABT BIT5 19005 #define FRME BIT4 19006 #define RBIT BIT4 19007 #define OVRN BIT3 19008 #define CRCE BIT2 19009 #define WAKEUP_CHARS 256 19010 #if SYNCLINK_GENERIC_HDLC 19011 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19012 #endif 19013 #ifdef SANITY_CHECK 19014 #else 19015 #endif 19016 /* LDV_COMMENT_END_PREP */ 19017 /* LDV_COMMENT_FUNCTION_CALL Function from field "hangup" from driver structure with callbacks "ops" */ 19018 ldv_handler_precall(); 19019 hangup( var_group8); 19020 /* LDV_COMMENT_BEGIN_PREP */ 19021 #if SYNCLINK_GENERIC_HDLC 19022 #endif 19023 #if SYNCLINK_GENERIC_HDLC 19024 #endif 19025 #if SYNCLINK_GENERIC_HDLC 19026 #endif 19027 #ifdef CMSPAR 19028 #endif 19029 #if SYNCLINK_GENERIC_HDLC 19030 #endif 19031 #if SYNCLINK_GENERIC_HDLC 19032 #endif 19033 #if 0 19034 #endif 19035 #if SYNCLINK_GENERIC_HDLC 19036 #endif 19037 #if SYNCLINK_GENERIC_HDLC 19038 #endif 19039 #define TESTFRAMESIZE 20 19040 #if SYNCLINK_GENERIC_HDLC 19041 #endif 19042 #define CALC_REGADDR() \ 19043 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19044 if (info->port_num > 1) \ 19045 RegAddr += 256; \ 19046 if ( info->port_num & 1) { \ 19047 if (Addr > 0x7f) \ 19048 RegAddr += 0x40; \ 19049 else if (Addr > 0x1f && Addr < 0x60) \ 19050 RegAddr += 0x20; \ 19051 } 19052 /* LDV_COMMENT_END_PREP */ 19053 19054 19055 19056 19057 } 19058 19059 break; 19060 case 28: { 19061 19062 /** STRUCT: struct type: tty_operations, struct name: ops **/ 19063 19064 19065 /* content: static int tiocmget(struct tty_struct *tty)*/ 19066 /* LDV_COMMENT_BEGIN_PREP */ 19067 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19068 #if defined(__i386__) 19069 # define BREAKPOINT() asm(" int $3"); 19070 #else 19071 # define BREAKPOINT() { } 19072 #endif 19073 #define MAX_DEVICES 12 19074 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19075 #define SYNCLINK_GENERIC_HDLC 1 19076 #else 19077 #define SYNCLINK_GENERIC_HDLC 0 19078 #endif 19079 #define GET_USER(error,value,addr) error = get_user(value,addr) 19080 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19081 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19082 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19083 #define SCABUFSIZE 1024 19084 #define SCA_MEM_SIZE 0x40000 19085 #define SCA_BASE_SIZE 512 19086 #define SCA_REG_SIZE 16 19087 #define SCA_MAX_PORTS 4 19088 #define SCAMAXDESC 128 19089 #define BUFFERLISTSIZE 4096 19090 #define BH_RECEIVE 1 19091 #define BH_TRANSMIT 2 19092 #define BH_STATUS 4 19093 #define IO_PIN_SHUTDOWN_LIMIT 100 19094 #if SYNCLINK_GENERIC_HDLC 19095 #endif 19096 #define MGSL_MAGIC 0x5401 19097 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 19098 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 19099 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 19100 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 19101 #define LPR 0x00 19102 #define PABR0 0x02 19103 #define PABR1 0x03 19104 #define WCRL 0x04 19105 #define WCRM 0x05 19106 #define WCRH 0x06 19107 #define DPCR 0x08 19108 #define DMER 0x09 19109 #define ISR0 0x10 19110 #define ISR1 0x11 19111 #define ISR2 0x12 19112 #define IER0 0x14 19113 #define IER1 0x15 19114 #define IER2 0x16 19115 #define ITCR 0x18 19116 #define INTVR 0x1a 19117 #define IMVR 0x1c 19118 #define TRB 0x20 19119 #define TRBL 0x20 19120 #define TRBH 0x21 19121 #define SR0 0x22 19122 #define SR1 0x23 19123 #define SR2 0x24 19124 #define SR3 0x25 19125 #define FST 0x26 19126 #define IE0 0x28 19127 #define IE1 0x29 19128 #define IE2 0x2a 19129 #define FIE 0x2b 19130 #define CMD 0x2c 19131 #define MD0 0x2e 19132 #define MD1 0x2f 19133 #define MD2 0x30 19134 #define CTL 0x31 19135 #define SA0 0x32 19136 #define SA1 0x33 19137 #define IDL 0x34 19138 #define TMC 0x35 19139 #define RXS 0x36 19140 #define TXS 0x37 19141 #define TRC0 0x38 19142 #define TRC1 0x39 19143 #define RRC 0x3a 19144 #define CST0 0x3c 19145 #define CST1 0x3d 19146 #define TCNT 0x60 19147 #define TCNTL 0x60 19148 #define TCNTH 0x61 19149 #define TCONR 0x62 19150 #define TCONRL 0x62 19151 #define TCONRH 0x63 19152 #define TMCS 0x64 19153 #define TEPR 0x65 19154 #define DARL 0x80 19155 #define DARH 0x81 19156 #define DARB 0x82 19157 #define BAR 0x80 19158 #define BARL 0x80 19159 #define BARH 0x81 19160 #define BARB 0x82 19161 #define SAR 0x84 19162 #define SARL 0x84 19163 #define SARH 0x85 19164 #define SARB 0x86 19165 #define CPB 0x86 19166 #define CDA 0x88 19167 #define CDAL 0x88 19168 #define CDAH 0x89 19169 #define EDA 0x8a 19170 #define EDAL 0x8a 19171 #define EDAH 0x8b 19172 #define BFL 0x8c 19173 #define BFLL 0x8c 19174 #define BFLH 0x8d 19175 #define BCR 0x8e 19176 #define BCRL 0x8e 19177 #define BCRH 0x8f 19178 #define DSR 0x90 19179 #define DMR 0x91 19180 #define FCT 0x93 19181 #define DIR 0x94 19182 #define DCMD 0x95 19183 #define TIMER0 0x00 19184 #define TIMER1 0x08 19185 #define TIMER2 0x10 19186 #define TIMER3 0x18 19187 #define RXDMA 0x00 19188 #define TXDMA 0x20 19189 #define NOOP 0x00 19190 #define TXRESET 0x01 19191 #define TXENABLE 0x02 19192 #define TXDISABLE 0x03 19193 #define TXCRCINIT 0x04 19194 #define TXCRCEXCL 0x05 19195 #define TXEOM 0x06 19196 #define TXABORT 0x07 19197 #define MPON 0x08 19198 #define TXBUFCLR 0x09 19199 #define RXRESET 0x11 19200 #define RXENABLE 0x12 19201 #define RXDISABLE 0x13 19202 #define RXCRCINIT 0x14 19203 #define RXREJECT 0x15 19204 #define SEARCHMP 0x16 19205 #define RXCRCEXCL 0x17 19206 #define RXCRCCALC 0x18 19207 #define CHRESET 0x21 19208 #define HUNT 0x31 19209 #define SWABORT 0x01 19210 #define FEICLEAR 0x02 19211 #define TXINTE BIT7 19212 #define RXINTE BIT6 19213 #define TXRDYE BIT1 19214 #define RXRDYE BIT0 19215 #define UDRN BIT7 19216 #define IDLE BIT6 19217 #define SYNCD BIT4 19218 #define FLGD BIT4 19219 #define CCTS BIT3 19220 #define CDCD BIT2 19221 #define BRKD BIT1 19222 #define ABTD BIT1 19223 #define GAPD BIT1 19224 #define BRKE BIT0 19225 #define IDLD BIT0 19226 #define EOM BIT7 19227 #define PMP BIT6 19228 #define SHRT BIT6 19229 #define PE BIT5 19230 #define ABT BIT5 19231 #define FRME BIT4 19232 #define RBIT BIT4 19233 #define OVRN BIT3 19234 #define CRCE BIT2 19235 #define WAKEUP_CHARS 256 19236 #if SYNCLINK_GENERIC_HDLC 19237 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19238 #endif 19239 #ifdef SANITY_CHECK 19240 #else 19241 #endif 19242 #if SYNCLINK_GENERIC_HDLC 19243 #endif 19244 #if SYNCLINK_GENERIC_HDLC 19245 #endif 19246 #if SYNCLINK_GENERIC_HDLC 19247 #endif 19248 #ifdef CMSPAR 19249 #endif 19250 /* LDV_COMMENT_END_PREP */ 19251 /* LDV_COMMENT_FUNCTION_CALL Function from field "tiocmget" from driver structure with callbacks "ops" */ 19252 ldv_handler_precall(); 19253 tiocmget( var_group8); 19254 /* LDV_COMMENT_BEGIN_PREP */ 19255 #if SYNCLINK_GENERIC_HDLC 19256 #endif 19257 #if SYNCLINK_GENERIC_HDLC 19258 #endif 19259 #if 0 19260 #endif 19261 #if SYNCLINK_GENERIC_HDLC 19262 #endif 19263 #if SYNCLINK_GENERIC_HDLC 19264 #endif 19265 #define TESTFRAMESIZE 20 19266 #if SYNCLINK_GENERIC_HDLC 19267 #endif 19268 #define CALC_REGADDR() \ 19269 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19270 if (info->port_num > 1) \ 19271 RegAddr += 256; \ 19272 if ( info->port_num & 1) { \ 19273 if (Addr > 0x7f) \ 19274 RegAddr += 0x40; \ 19275 else if (Addr > 0x1f && Addr < 0x60) \ 19276 RegAddr += 0x20; \ 19277 } 19278 /* LDV_COMMENT_END_PREP */ 19279 19280 19281 19282 19283 } 19284 19285 break; 19286 case 29: { 19287 19288 /** STRUCT: struct type: tty_operations, struct name: ops **/ 19289 19290 19291 /* content: static int tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)*/ 19292 /* LDV_COMMENT_BEGIN_PREP */ 19293 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19294 #if defined(__i386__) 19295 # define BREAKPOINT() asm(" int $3"); 19296 #else 19297 # define BREAKPOINT() { } 19298 #endif 19299 #define MAX_DEVICES 12 19300 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19301 #define SYNCLINK_GENERIC_HDLC 1 19302 #else 19303 #define SYNCLINK_GENERIC_HDLC 0 19304 #endif 19305 #define GET_USER(error,value,addr) error = get_user(value,addr) 19306 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19307 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19308 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19309 #define SCABUFSIZE 1024 19310 #define SCA_MEM_SIZE 0x40000 19311 #define SCA_BASE_SIZE 512 19312 #define SCA_REG_SIZE 16 19313 #define SCA_MAX_PORTS 4 19314 #define SCAMAXDESC 128 19315 #define BUFFERLISTSIZE 4096 19316 #define BH_RECEIVE 1 19317 #define BH_TRANSMIT 2 19318 #define BH_STATUS 4 19319 #define IO_PIN_SHUTDOWN_LIMIT 100 19320 #if SYNCLINK_GENERIC_HDLC 19321 #endif 19322 #define MGSL_MAGIC 0x5401 19323 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 19324 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 19325 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 19326 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 19327 #define LPR 0x00 19328 #define PABR0 0x02 19329 #define PABR1 0x03 19330 #define WCRL 0x04 19331 #define WCRM 0x05 19332 #define WCRH 0x06 19333 #define DPCR 0x08 19334 #define DMER 0x09 19335 #define ISR0 0x10 19336 #define ISR1 0x11 19337 #define ISR2 0x12 19338 #define IER0 0x14 19339 #define IER1 0x15 19340 #define IER2 0x16 19341 #define ITCR 0x18 19342 #define INTVR 0x1a 19343 #define IMVR 0x1c 19344 #define TRB 0x20 19345 #define TRBL 0x20 19346 #define TRBH 0x21 19347 #define SR0 0x22 19348 #define SR1 0x23 19349 #define SR2 0x24 19350 #define SR3 0x25 19351 #define FST 0x26 19352 #define IE0 0x28 19353 #define IE1 0x29 19354 #define IE2 0x2a 19355 #define FIE 0x2b 19356 #define CMD 0x2c 19357 #define MD0 0x2e 19358 #define MD1 0x2f 19359 #define MD2 0x30 19360 #define CTL 0x31 19361 #define SA0 0x32 19362 #define SA1 0x33 19363 #define IDL 0x34 19364 #define TMC 0x35 19365 #define RXS 0x36 19366 #define TXS 0x37 19367 #define TRC0 0x38 19368 #define TRC1 0x39 19369 #define RRC 0x3a 19370 #define CST0 0x3c 19371 #define CST1 0x3d 19372 #define TCNT 0x60 19373 #define TCNTL 0x60 19374 #define TCNTH 0x61 19375 #define TCONR 0x62 19376 #define TCONRL 0x62 19377 #define TCONRH 0x63 19378 #define TMCS 0x64 19379 #define TEPR 0x65 19380 #define DARL 0x80 19381 #define DARH 0x81 19382 #define DARB 0x82 19383 #define BAR 0x80 19384 #define BARL 0x80 19385 #define BARH 0x81 19386 #define BARB 0x82 19387 #define SAR 0x84 19388 #define SARL 0x84 19389 #define SARH 0x85 19390 #define SARB 0x86 19391 #define CPB 0x86 19392 #define CDA 0x88 19393 #define CDAL 0x88 19394 #define CDAH 0x89 19395 #define EDA 0x8a 19396 #define EDAL 0x8a 19397 #define EDAH 0x8b 19398 #define BFL 0x8c 19399 #define BFLL 0x8c 19400 #define BFLH 0x8d 19401 #define BCR 0x8e 19402 #define BCRL 0x8e 19403 #define BCRH 0x8f 19404 #define DSR 0x90 19405 #define DMR 0x91 19406 #define FCT 0x93 19407 #define DIR 0x94 19408 #define DCMD 0x95 19409 #define TIMER0 0x00 19410 #define TIMER1 0x08 19411 #define TIMER2 0x10 19412 #define TIMER3 0x18 19413 #define RXDMA 0x00 19414 #define TXDMA 0x20 19415 #define NOOP 0x00 19416 #define TXRESET 0x01 19417 #define TXENABLE 0x02 19418 #define TXDISABLE 0x03 19419 #define TXCRCINIT 0x04 19420 #define TXCRCEXCL 0x05 19421 #define TXEOM 0x06 19422 #define TXABORT 0x07 19423 #define MPON 0x08 19424 #define TXBUFCLR 0x09 19425 #define RXRESET 0x11 19426 #define RXENABLE 0x12 19427 #define RXDISABLE 0x13 19428 #define RXCRCINIT 0x14 19429 #define RXREJECT 0x15 19430 #define SEARCHMP 0x16 19431 #define RXCRCEXCL 0x17 19432 #define RXCRCCALC 0x18 19433 #define CHRESET 0x21 19434 #define HUNT 0x31 19435 #define SWABORT 0x01 19436 #define FEICLEAR 0x02 19437 #define TXINTE BIT7 19438 #define RXINTE BIT6 19439 #define TXRDYE BIT1 19440 #define RXRDYE BIT0 19441 #define UDRN BIT7 19442 #define IDLE BIT6 19443 #define SYNCD BIT4 19444 #define FLGD BIT4 19445 #define CCTS BIT3 19446 #define CDCD BIT2 19447 #define BRKD BIT1 19448 #define ABTD BIT1 19449 #define GAPD BIT1 19450 #define BRKE BIT0 19451 #define IDLD BIT0 19452 #define EOM BIT7 19453 #define PMP BIT6 19454 #define SHRT BIT6 19455 #define PE BIT5 19456 #define ABT BIT5 19457 #define FRME BIT4 19458 #define RBIT BIT4 19459 #define OVRN BIT3 19460 #define CRCE BIT2 19461 #define WAKEUP_CHARS 256 19462 #if SYNCLINK_GENERIC_HDLC 19463 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19464 #endif 19465 #ifdef SANITY_CHECK 19466 #else 19467 #endif 19468 #if SYNCLINK_GENERIC_HDLC 19469 #endif 19470 #if SYNCLINK_GENERIC_HDLC 19471 #endif 19472 #if SYNCLINK_GENERIC_HDLC 19473 #endif 19474 #ifdef CMSPAR 19475 #endif 19476 /* LDV_COMMENT_END_PREP */ 19477 /* LDV_COMMENT_FUNCTION_CALL Function from field "tiocmset" from driver structure with callbacks "ops" */ 19478 ldv_handler_precall(); 19479 tiocmset( var_group8, var_tiocmset_68_p1, var_tiocmset_68_p2); 19480 /* LDV_COMMENT_BEGIN_PREP */ 19481 #if SYNCLINK_GENERIC_HDLC 19482 #endif 19483 #if SYNCLINK_GENERIC_HDLC 19484 #endif 19485 #if 0 19486 #endif 19487 #if SYNCLINK_GENERIC_HDLC 19488 #endif 19489 #if SYNCLINK_GENERIC_HDLC 19490 #endif 19491 #define TESTFRAMESIZE 20 19492 #if SYNCLINK_GENERIC_HDLC 19493 #endif 19494 #define CALC_REGADDR() \ 19495 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19496 if (info->port_num > 1) \ 19497 RegAddr += 256; \ 19498 if ( info->port_num & 1) { \ 19499 if (Addr > 0x7f) \ 19500 RegAddr += 0x40; \ 19501 else if (Addr > 0x1f && Addr < 0x60) \ 19502 RegAddr += 0x20; \ 19503 } 19504 /* LDV_COMMENT_END_PREP */ 19505 19506 19507 19508 19509 } 19510 19511 break; 19512 case 30: { 19513 19514 /** STRUCT: struct type: tty_operations, struct name: ops **/ 19515 19516 19517 /* content: static int get_icount(struct tty_struct *tty, struct serial_icounter_struct *icount)*/ 19518 /* LDV_COMMENT_BEGIN_PREP */ 19519 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19520 #if defined(__i386__) 19521 # define BREAKPOINT() asm(" int $3"); 19522 #else 19523 # define BREAKPOINT() { } 19524 #endif 19525 #define MAX_DEVICES 12 19526 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19527 #define SYNCLINK_GENERIC_HDLC 1 19528 #else 19529 #define SYNCLINK_GENERIC_HDLC 0 19530 #endif 19531 #define GET_USER(error,value,addr) error = get_user(value,addr) 19532 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19533 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19534 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19535 #define SCABUFSIZE 1024 19536 #define SCA_MEM_SIZE 0x40000 19537 #define SCA_BASE_SIZE 512 19538 #define SCA_REG_SIZE 16 19539 #define SCA_MAX_PORTS 4 19540 #define SCAMAXDESC 128 19541 #define BUFFERLISTSIZE 4096 19542 #define BH_RECEIVE 1 19543 #define BH_TRANSMIT 2 19544 #define BH_STATUS 4 19545 #define IO_PIN_SHUTDOWN_LIMIT 100 19546 #if SYNCLINK_GENERIC_HDLC 19547 #endif 19548 #define MGSL_MAGIC 0x5401 19549 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 19550 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 19551 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 19552 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 19553 #define LPR 0x00 19554 #define PABR0 0x02 19555 #define PABR1 0x03 19556 #define WCRL 0x04 19557 #define WCRM 0x05 19558 #define WCRH 0x06 19559 #define DPCR 0x08 19560 #define DMER 0x09 19561 #define ISR0 0x10 19562 #define ISR1 0x11 19563 #define ISR2 0x12 19564 #define IER0 0x14 19565 #define IER1 0x15 19566 #define IER2 0x16 19567 #define ITCR 0x18 19568 #define INTVR 0x1a 19569 #define IMVR 0x1c 19570 #define TRB 0x20 19571 #define TRBL 0x20 19572 #define TRBH 0x21 19573 #define SR0 0x22 19574 #define SR1 0x23 19575 #define SR2 0x24 19576 #define SR3 0x25 19577 #define FST 0x26 19578 #define IE0 0x28 19579 #define IE1 0x29 19580 #define IE2 0x2a 19581 #define FIE 0x2b 19582 #define CMD 0x2c 19583 #define MD0 0x2e 19584 #define MD1 0x2f 19585 #define MD2 0x30 19586 #define CTL 0x31 19587 #define SA0 0x32 19588 #define SA1 0x33 19589 #define IDL 0x34 19590 #define TMC 0x35 19591 #define RXS 0x36 19592 #define TXS 0x37 19593 #define TRC0 0x38 19594 #define TRC1 0x39 19595 #define RRC 0x3a 19596 #define CST0 0x3c 19597 #define CST1 0x3d 19598 #define TCNT 0x60 19599 #define TCNTL 0x60 19600 #define TCNTH 0x61 19601 #define TCONR 0x62 19602 #define TCONRL 0x62 19603 #define TCONRH 0x63 19604 #define TMCS 0x64 19605 #define TEPR 0x65 19606 #define DARL 0x80 19607 #define DARH 0x81 19608 #define DARB 0x82 19609 #define BAR 0x80 19610 #define BARL 0x80 19611 #define BARH 0x81 19612 #define BARB 0x82 19613 #define SAR 0x84 19614 #define SARL 0x84 19615 #define SARH 0x85 19616 #define SARB 0x86 19617 #define CPB 0x86 19618 #define CDA 0x88 19619 #define CDAL 0x88 19620 #define CDAH 0x89 19621 #define EDA 0x8a 19622 #define EDAL 0x8a 19623 #define EDAH 0x8b 19624 #define BFL 0x8c 19625 #define BFLL 0x8c 19626 #define BFLH 0x8d 19627 #define BCR 0x8e 19628 #define BCRL 0x8e 19629 #define BCRH 0x8f 19630 #define DSR 0x90 19631 #define DMR 0x91 19632 #define FCT 0x93 19633 #define DIR 0x94 19634 #define DCMD 0x95 19635 #define TIMER0 0x00 19636 #define TIMER1 0x08 19637 #define TIMER2 0x10 19638 #define TIMER3 0x18 19639 #define RXDMA 0x00 19640 #define TXDMA 0x20 19641 #define NOOP 0x00 19642 #define TXRESET 0x01 19643 #define TXENABLE 0x02 19644 #define TXDISABLE 0x03 19645 #define TXCRCINIT 0x04 19646 #define TXCRCEXCL 0x05 19647 #define TXEOM 0x06 19648 #define TXABORT 0x07 19649 #define MPON 0x08 19650 #define TXBUFCLR 0x09 19651 #define RXRESET 0x11 19652 #define RXENABLE 0x12 19653 #define RXDISABLE 0x13 19654 #define RXCRCINIT 0x14 19655 #define RXREJECT 0x15 19656 #define SEARCHMP 0x16 19657 #define RXCRCEXCL 0x17 19658 #define RXCRCCALC 0x18 19659 #define CHRESET 0x21 19660 #define HUNT 0x31 19661 #define SWABORT 0x01 19662 #define FEICLEAR 0x02 19663 #define TXINTE BIT7 19664 #define RXINTE BIT6 19665 #define TXRDYE BIT1 19666 #define RXRDYE BIT0 19667 #define UDRN BIT7 19668 #define IDLE BIT6 19669 #define SYNCD BIT4 19670 #define FLGD BIT4 19671 #define CCTS BIT3 19672 #define CDCD BIT2 19673 #define BRKD BIT1 19674 #define ABTD BIT1 19675 #define GAPD BIT1 19676 #define BRKE BIT0 19677 #define IDLD BIT0 19678 #define EOM BIT7 19679 #define PMP BIT6 19680 #define SHRT BIT6 19681 #define PE BIT5 19682 #define ABT BIT5 19683 #define FRME BIT4 19684 #define RBIT BIT4 19685 #define OVRN BIT3 19686 #define CRCE BIT2 19687 #define WAKEUP_CHARS 256 19688 #if SYNCLINK_GENERIC_HDLC 19689 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19690 #endif 19691 #ifdef SANITY_CHECK 19692 #else 19693 #endif 19694 /* LDV_COMMENT_END_PREP */ 19695 /* LDV_COMMENT_FUNCTION_CALL Function from field "get_icount" from driver structure with callbacks "ops" */ 19696 ldv_handler_precall(); 19697 get_icount( var_group8, var_group10); 19698 /* LDV_COMMENT_BEGIN_PREP */ 19699 #if SYNCLINK_GENERIC_HDLC 19700 #endif 19701 #if SYNCLINK_GENERIC_HDLC 19702 #endif 19703 #if SYNCLINK_GENERIC_HDLC 19704 #endif 19705 #ifdef CMSPAR 19706 #endif 19707 #if SYNCLINK_GENERIC_HDLC 19708 #endif 19709 #if SYNCLINK_GENERIC_HDLC 19710 #endif 19711 #if 0 19712 #endif 19713 #if SYNCLINK_GENERIC_HDLC 19714 #endif 19715 #if SYNCLINK_GENERIC_HDLC 19716 #endif 19717 #define TESTFRAMESIZE 20 19718 #if SYNCLINK_GENERIC_HDLC 19719 #endif 19720 #define CALC_REGADDR() \ 19721 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19722 if (info->port_num > 1) \ 19723 RegAddr += 256; \ 19724 if ( info->port_num & 1) { \ 19725 if (Addr > 0x7f) \ 19726 RegAddr += 0x40; \ 19727 else if (Addr > 0x1f && Addr < 0x60) \ 19728 RegAddr += 0x20; \ 19729 } 19730 /* LDV_COMMENT_END_PREP */ 19731 19732 19733 19734 19735 } 19736 19737 break; 19738 case 31: { 19739 19740 /** CALLBACK SECTION request_irq **/ 19741 LDV_IN_INTERRUPT=2; 19742 19743 /* content: static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)*/ 19744 /* LDV_COMMENT_BEGIN_PREP */ 19745 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19746 #if defined(__i386__) 19747 # define BREAKPOINT() asm(" int $3"); 19748 #else 19749 # define BREAKPOINT() { } 19750 #endif 19751 #define MAX_DEVICES 12 19752 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19753 #define SYNCLINK_GENERIC_HDLC 1 19754 #else 19755 #define SYNCLINK_GENERIC_HDLC 0 19756 #endif 19757 #define GET_USER(error,value,addr) error = get_user(value,addr) 19758 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19759 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19760 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19761 #define SCABUFSIZE 1024 19762 #define SCA_MEM_SIZE 0x40000 19763 #define SCA_BASE_SIZE 512 19764 #define SCA_REG_SIZE 16 19765 #define SCA_MAX_PORTS 4 19766 #define SCAMAXDESC 128 19767 #define BUFFERLISTSIZE 4096 19768 #define BH_RECEIVE 1 19769 #define BH_TRANSMIT 2 19770 #define BH_STATUS 4 19771 #define IO_PIN_SHUTDOWN_LIMIT 100 19772 #if SYNCLINK_GENERIC_HDLC 19773 #endif 19774 #define MGSL_MAGIC 0x5401 19775 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 19776 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 19777 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 19778 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 19779 #define LPR 0x00 19780 #define PABR0 0x02 19781 #define PABR1 0x03 19782 #define WCRL 0x04 19783 #define WCRM 0x05 19784 #define WCRH 0x06 19785 #define DPCR 0x08 19786 #define DMER 0x09 19787 #define ISR0 0x10 19788 #define ISR1 0x11 19789 #define ISR2 0x12 19790 #define IER0 0x14 19791 #define IER1 0x15 19792 #define IER2 0x16 19793 #define ITCR 0x18 19794 #define INTVR 0x1a 19795 #define IMVR 0x1c 19796 #define TRB 0x20 19797 #define TRBL 0x20 19798 #define TRBH 0x21 19799 #define SR0 0x22 19800 #define SR1 0x23 19801 #define SR2 0x24 19802 #define SR3 0x25 19803 #define FST 0x26 19804 #define IE0 0x28 19805 #define IE1 0x29 19806 #define IE2 0x2a 19807 #define FIE 0x2b 19808 #define CMD 0x2c 19809 #define MD0 0x2e 19810 #define MD1 0x2f 19811 #define MD2 0x30 19812 #define CTL 0x31 19813 #define SA0 0x32 19814 #define SA1 0x33 19815 #define IDL 0x34 19816 #define TMC 0x35 19817 #define RXS 0x36 19818 #define TXS 0x37 19819 #define TRC0 0x38 19820 #define TRC1 0x39 19821 #define RRC 0x3a 19822 #define CST0 0x3c 19823 #define CST1 0x3d 19824 #define TCNT 0x60 19825 #define TCNTL 0x60 19826 #define TCNTH 0x61 19827 #define TCONR 0x62 19828 #define TCONRL 0x62 19829 #define TCONRH 0x63 19830 #define TMCS 0x64 19831 #define TEPR 0x65 19832 #define DARL 0x80 19833 #define DARH 0x81 19834 #define DARB 0x82 19835 #define BAR 0x80 19836 #define BARL 0x80 19837 #define BARH 0x81 19838 #define BARB 0x82 19839 #define SAR 0x84 19840 #define SARL 0x84 19841 #define SARH 0x85 19842 #define SARB 0x86 19843 #define CPB 0x86 19844 #define CDA 0x88 19845 #define CDAL 0x88 19846 #define CDAH 0x89 19847 #define EDA 0x8a 19848 #define EDAL 0x8a 19849 #define EDAH 0x8b 19850 #define BFL 0x8c 19851 #define BFLL 0x8c 19852 #define BFLH 0x8d 19853 #define BCR 0x8e 19854 #define BCRL 0x8e 19855 #define BCRH 0x8f 19856 #define DSR 0x90 19857 #define DMR 0x91 19858 #define FCT 0x93 19859 #define DIR 0x94 19860 #define DCMD 0x95 19861 #define TIMER0 0x00 19862 #define TIMER1 0x08 19863 #define TIMER2 0x10 19864 #define TIMER3 0x18 19865 #define RXDMA 0x00 19866 #define TXDMA 0x20 19867 #define NOOP 0x00 19868 #define TXRESET 0x01 19869 #define TXENABLE 0x02 19870 #define TXDISABLE 0x03 19871 #define TXCRCINIT 0x04 19872 #define TXCRCEXCL 0x05 19873 #define TXEOM 0x06 19874 #define TXABORT 0x07 19875 #define MPON 0x08 19876 #define TXBUFCLR 0x09 19877 #define RXRESET 0x11 19878 #define RXENABLE 0x12 19879 #define RXDISABLE 0x13 19880 #define RXCRCINIT 0x14 19881 #define RXREJECT 0x15 19882 #define SEARCHMP 0x16 19883 #define RXCRCEXCL 0x17 19884 #define RXCRCCALC 0x18 19885 #define CHRESET 0x21 19886 #define HUNT 0x31 19887 #define SWABORT 0x01 19888 #define FEICLEAR 0x02 19889 #define TXINTE BIT7 19890 #define RXINTE BIT6 19891 #define TXRDYE BIT1 19892 #define RXRDYE BIT0 19893 #define UDRN BIT7 19894 #define IDLE BIT6 19895 #define SYNCD BIT4 19896 #define FLGD BIT4 19897 #define CCTS BIT3 19898 #define CDCD BIT2 19899 #define BRKD BIT1 19900 #define ABTD BIT1 19901 #define GAPD BIT1 19902 #define BRKE BIT0 19903 #define IDLD BIT0 19904 #define EOM BIT7 19905 #define PMP BIT6 19906 #define SHRT BIT6 19907 #define PE BIT5 19908 #define ABT BIT5 19909 #define FRME BIT4 19910 #define RBIT BIT4 19911 #define OVRN BIT3 19912 #define CRCE BIT2 19913 #define WAKEUP_CHARS 256 19914 #if SYNCLINK_GENERIC_HDLC 19915 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19916 #endif 19917 #ifdef SANITY_CHECK 19918 #else 19919 #endif 19920 #if SYNCLINK_GENERIC_HDLC 19921 #endif 19922 #if SYNCLINK_GENERIC_HDLC 19923 #endif 19924 #if SYNCLINK_GENERIC_HDLC 19925 #endif 19926 /* LDV_COMMENT_END_PREP */ 19927 /* LDV_COMMENT_FUNCTION_CALL */ 19928 ldv_handler_precall(); 19929 synclinkmp_interrupt( var_synclinkmp_interrupt_52_p0, var_synclinkmp_interrupt_52_p1); 19930 /* LDV_COMMENT_BEGIN_PREP */ 19931 #ifdef CMSPAR 19932 #endif 19933 #if SYNCLINK_GENERIC_HDLC 19934 #endif 19935 #if SYNCLINK_GENERIC_HDLC 19936 #endif 19937 #if 0 19938 #endif 19939 #if SYNCLINK_GENERIC_HDLC 19940 #endif 19941 #if SYNCLINK_GENERIC_HDLC 19942 #endif 19943 #define TESTFRAMESIZE 20 19944 #if SYNCLINK_GENERIC_HDLC 19945 #endif 19946 #define CALC_REGADDR() \ 19947 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19948 if (info->port_num > 1) \ 19949 RegAddr += 256; \ 19950 if ( info->port_num & 1) { \ 19951 if (Addr > 0x7f) \ 19952 RegAddr += 0x40; \ 19953 else if (Addr > 0x1f && Addr < 0x60) \ 19954 RegAddr += 0x20; \ 19955 } 19956 /* LDV_COMMENT_END_PREP */ 19957 LDV_IN_INTERRUPT=1; 19958 19959 19960 19961 } 19962 19963 break; 19964 default: break; 19965 19966 } 19967 19968 } 19969 19970 ldv_module_exit: 19971 19972 /** INIT: init_type: ST_MODULE_EXIT **/ 19973 /* content: static void __exit synclinkmp_exit(void)*/ 19974 /* LDV_COMMENT_BEGIN_PREP */ 19975 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19976 #if defined(__i386__) 19977 # define BREAKPOINT() asm(" int $3"); 19978 #else 19979 # define BREAKPOINT() { } 19980 #endif 19981 #define MAX_DEVICES 12 19982 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19983 #define SYNCLINK_GENERIC_HDLC 1 19984 #else 19985 #define SYNCLINK_GENERIC_HDLC 0 19986 #endif 19987 #define GET_USER(error,value,addr) error = get_user(value,addr) 19988 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19989 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19990 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19991 #define SCABUFSIZE 1024 19992 #define SCA_MEM_SIZE 0x40000 19993 #define SCA_BASE_SIZE 512 19994 #define SCA_REG_SIZE 16 19995 #define SCA_MAX_PORTS 4 19996 #define SCAMAXDESC 128 19997 #define BUFFERLISTSIZE 4096 19998 #define BH_RECEIVE 1 19999 #define BH_TRANSMIT 2 20000 #define BH_STATUS 4 20001 #define IO_PIN_SHUTDOWN_LIMIT 100 20002 #if SYNCLINK_GENERIC_HDLC 20003 #endif 20004 #define MGSL_MAGIC 0x5401 20005 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 20006 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 20007 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 20008 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 20009 #define LPR 0x00 20010 #define PABR0 0x02 20011 #define PABR1 0x03 20012 #define WCRL 0x04 20013 #define WCRM 0x05 20014 #define WCRH 0x06 20015 #define DPCR 0x08 20016 #define DMER 0x09 20017 #define ISR0 0x10 20018 #define ISR1 0x11 20019 #define ISR2 0x12 20020 #define IER0 0x14 20021 #define IER1 0x15 20022 #define IER2 0x16 20023 #define ITCR 0x18 20024 #define INTVR 0x1a 20025 #define IMVR 0x1c 20026 #define TRB 0x20 20027 #define TRBL 0x20 20028 #define TRBH 0x21 20029 #define SR0 0x22 20030 #define SR1 0x23 20031 #define SR2 0x24 20032 #define SR3 0x25 20033 #define FST 0x26 20034 #define IE0 0x28 20035 #define IE1 0x29 20036 #define IE2 0x2a 20037 #define FIE 0x2b 20038 #define CMD 0x2c 20039 #define MD0 0x2e 20040 #define MD1 0x2f 20041 #define MD2 0x30 20042 #define CTL 0x31 20043 #define SA0 0x32 20044 #define SA1 0x33 20045 #define IDL 0x34 20046 #define TMC 0x35 20047 #define RXS 0x36 20048 #define TXS 0x37 20049 #define TRC0 0x38 20050 #define TRC1 0x39 20051 #define RRC 0x3a 20052 #define CST0 0x3c 20053 #define CST1 0x3d 20054 #define TCNT 0x60 20055 #define TCNTL 0x60 20056 #define TCNTH 0x61 20057 #define TCONR 0x62 20058 #define TCONRL 0x62 20059 #define TCONRH 0x63 20060 #define TMCS 0x64 20061 #define TEPR 0x65 20062 #define DARL 0x80 20063 #define DARH 0x81 20064 #define DARB 0x82 20065 #define BAR 0x80 20066 #define BARL 0x80 20067 #define BARH 0x81 20068 #define BARB 0x82 20069 #define SAR 0x84 20070 #define SARL 0x84 20071 #define SARH 0x85 20072 #define SARB 0x86 20073 #define CPB 0x86 20074 #define CDA 0x88 20075 #define CDAL 0x88 20076 #define CDAH 0x89 20077 #define EDA 0x8a 20078 #define EDAL 0x8a 20079 #define EDAH 0x8b 20080 #define BFL 0x8c 20081 #define BFLL 0x8c 20082 #define BFLH 0x8d 20083 #define BCR 0x8e 20084 #define BCRL 0x8e 20085 #define BCRH 0x8f 20086 #define DSR 0x90 20087 #define DMR 0x91 20088 #define FCT 0x93 20089 #define DIR 0x94 20090 #define DCMD 0x95 20091 #define TIMER0 0x00 20092 #define TIMER1 0x08 20093 #define TIMER2 0x10 20094 #define TIMER3 0x18 20095 #define RXDMA 0x00 20096 #define TXDMA 0x20 20097 #define NOOP 0x00 20098 #define TXRESET 0x01 20099 #define TXENABLE 0x02 20100 #define TXDISABLE 0x03 20101 #define TXCRCINIT 0x04 20102 #define TXCRCEXCL 0x05 20103 #define TXEOM 0x06 20104 #define TXABORT 0x07 20105 #define MPON 0x08 20106 #define TXBUFCLR 0x09 20107 #define RXRESET 0x11 20108 #define RXENABLE 0x12 20109 #define RXDISABLE 0x13 20110 #define RXCRCINIT 0x14 20111 #define RXREJECT 0x15 20112 #define SEARCHMP 0x16 20113 #define RXCRCEXCL 0x17 20114 #define RXCRCCALC 0x18 20115 #define CHRESET 0x21 20116 #define HUNT 0x31 20117 #define SWABORT 0x01 20118 #define FEICLEAR 0x02 20119 #define TXINTE BIT7 20120 #define RXINTE BIT6 20121 #define TXRDYE BIT1 20122 #define RXRDYE BIT0 20123 #define UDRN BIT7 20124 #define IDLE BIT6 20125 #define SYNCD BIT4 20126 #define FLGD BIT4 20127 #define CCTS BIT3 20128 #define CDCD BIT2 20129 #define BRKD BIT1 20130 #define ABTD BIT1 20131 #define GAPD BIT1 20132 #define BRKE BIT0 20133 #define IDLD BIT0 20134 #define EOM BIT7 20135 #define PMP BIT6 20136 #define SHRT BIT6 20137 #define PE BIT5 20138 #define ABT BIT5 20139 #define FRME BIT4 20140 #define RBIT BIT4 20141 #define OVRN BIT3 20142 #define CRCE BIT2 20143 #define WAKEUP_CHARS 256 20144 #if SYNCLINK_GENERIC_HDLC 20145 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 20146 #endif 20147 #ifdef SANITY_CHECK 20148 #else 20149 #endif 20150 #if SYNCLINK_GENERIC_HDLC 20151 #endif 20152 #if SYNCLINK_GENERIC_HDLC 20153 #endif 20154 #if SYNCLINK_GENERIC_HDLC 20155 #endif 20156 #ifdef CMSPAR 20157 #endif 20158 #if SYNCLINK_GENERIC_HDLC 20159 #endif 20160 #if SYNCLINK_GENERIC_HDLC 20161 #endif 20162 /* LDV_COMMENT_END_PREP */ 20163 /* LDV_COMMENT_FUNCTION_CALL Kernel calls driver release function before driver will be uploaded from kernel. This function declared as "MODULE_EXIT(function name)". */ 20164 ldv_handler_precall(); 20165 synclinkmp_exit(); 20166 /* LDV_COMMENT_BEGIN_PREP */ 20167 #if 0 20168 #endif 20169 #if SYNCLINK_GENERIC_HDLC 20170 #endif 20171 #if SYNCLINK_GENERIC_HDLC 20172 #endif 20173 #define TESTFRAMESIZE 20 20174 #if SYNCLINK_GENERIC_HDLC 20175 #endif 20176 #define CALC_REGADDR() \ 20177 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 20178 if (info->port_num > 1) \ 20179 RegAddr += 256; \ 20180 if ( info->port_num & 1) { \ 20181 if (Addr > 0x7f) \ 20182 RegAddr += 0x40; \ 20183 else if (Addr > 0x1f && Addr < 0x60) \ 20184 RegAddr += 0x20; \ 20185 } 20186 /* LDV_COMMENT_END_PREP */ 20187 20188 /* LDV_COMMENT_FUNCTION_CALL Checks that all resources and locks are correctly released before the driver will be unloaded. */ 20189 ldv_final: ldv_check_final_state(); 20190 20191 /* LDV_COMMENT_END_FUNCTION_CALL_SECTION */ 20192 return; 20193 20194 } 20195 #endif 20196 20197 /* LDV_COMMENT_END_MAIN */
1 2 #include <linux/kernel.h> 3 bool ldv_is_err(const void *ptr); 4 bool ldv_is_err_or_null(const void *ptr); 5 void* ldv_err_ptr(long error); 6 long ldv_ptr_err(const void *ptr); 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 11 // Provide model function prototypes before their usage. 12 int ldv_usb_register(void); 13 int ldv_register_netdev(void); 14 #line 1 "/home/ldvuser/ref_launch/work/current--X--drivers--X--defaultlinux-4.5-rc1.tar.xz--X--134_1a--X--cpachecker/linux-4.5-rc1.tar.xz/csd_deg_dscv/8588/dscv_tempdir/dscv/ri/134_1a/drivers/tty/synclinkmp.c" 15 16 /* 17 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $ 18 * 19 * Device driver for Microgate SyncLink Multiport 20 * high speed multiprotocol serial adapter. 21 * 22 * written by Paul Fulghum for Microgate Corporation 23 * paulkf@microgate.com 24 * 25 * Microgate and SyncLink are trademarks of Microgate Corporation 26 * 27 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds 28 * This code is released under the GNU General Public License (GPL) 29 * 30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 32 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 33 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 34 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 40 * OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 43 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 44 #if defined(__i386__) 45 # define BREAKPOINT() asm(" int $3"); 46 #else 47 # define BREAKPOINT() { } 48 #endif 49 50 #define MAX_DEVICES 12 51 52 #include <linux/module.h> 53 #include <linux/errno.h> 54 #include <linux/signal.h> 55 #include <linux/sched.h> 56 #include <linux/timer.h> 57 #include <linux/interrupt.h> 58 #include <linux/pci.h> 59 #include <linux/tty.h> 60 #include <linux/tty_flip.h> 61 #include <linux/serial.h> 62 #include <linux/major.h> 63 #include <linux/string.h> 64 #include <linux/fcntl.h> 65 #include <linux/ptrace.h> 66 #include <linux/ioport.h> 67 #include <linux/mm.h> 68 #include <linux/seq_file.h> 69 #include <linux/slab.h> 70 #include <linux/netdevice.h> 71 #include <linux/vmalloc.h> 72 #include <linux/init.h> 73 #include <linux/delay.h> 74 #include <linux/ioctl.h> 75 76 #include <asm/io.h> 77 #include <asm/irq.h> 78 #include <asm/dma.h> 79 #include <linux/bitops.h> 80 #include <asm/types.h> 81 #include <linux/termios.h> 82 #include <linux/workqueue.h> 83 #include <linux/hdlc.h> 84 #include <linux/synclink.h> 85 86 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 87 #define SYNCLINK_GENERIC_HDLC 1 88 #else 89 #define SYNCLINK_GENERIC_HDLC 0 90 #endif 91 92 #define GET_USER(error,value,addr) error = get_user(value,addr) 93 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 94 #define PUT_USER(error,value,addr) error = put_user(value,addr) 95 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 96 97 #include <asm/uaccess.h> 98 99 static MGSL_PARAMS default_params = { 100 MGSL_MODE_HDLC, /* unsigned long mode */ 101 0, /* unsigned char loopback; */ 102 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ 103 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ 104 0, /* unsigned long clock_speed; */ 105 0xff, /* unsigned char addr_filter; */ 106 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ 107 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ 108 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ 109 9600, /* unsigned long data_rate; */ 110 8, /* unsigned char data_bits; */ 111 1, /* unsigned char stop_bits; */ 112 ASYNC_PARITY_NONE /* unsigned char parity; */ 113 }; 114 115 /* size in bytes of DMA data buffers */ 116 #define SCABUFSIZE 1024 117 #define SCA_MEM_SIZE 0x40000 118 #define SCA_BASE_SIZE 512 119 #define SCA_REG_SIZE 16 120 #define SCA_MAX_PORTS 4 121 #define SCAMAXDESC 128 122 123 #define BUFFERLISTSIZE 4096 124 125 /* SCA-I style DMA buffer descriptor */ 126 typedef struct _SCADESC 127 { 128 u16 next; /* lower l6 bits of next descriptor addr */ 129 u16 buf_ptr; /* lower 16 bits of buffer addr */ 130 u8 buf_base; /* upper 8 bits of buffer addr */ 131 u8 pad1; 132 u16 length; /* length of buffer */ 133 u8 status; /* status of buffer */ 134 u8 pad2; 135 } SCADESC, *PSCADESC; 136 137 typedef struct _SCADESC_EX 138 { 139 /* device driver bookkeeping section */ 140 char *virt_addr; /* virtual address of data buffer */ 141 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */ 142 } SCADESC_EX, *PSCADESC_EX; 143 144 /* The queue of BH actions to be performed */ 145 146 #define BH_RECEIVE 1 147 #define BH_TRANSMIT 2 148 #define BH_STATUS 4 149 150 #define IO_PIN_SHUTDOWN_LIMIT 100 151 152 struct _input_signal_events { 153 int ri_up; 154 int ri_down; 155 int dsr_up; 156 int dsr_down; 157 int dcd_up; 158 int dcd_down; 159 int cts_up; 160 int cts_down; 161 }; 162 163 /* 164 * Device instance data structure 165 */ 166 typedef struct _synclinkmp_info { 167 void *if_ptr; /* General purpose pointer (used by SPPP) */ 168 int magic; 169 struct tty_port port; 170 int line; 171 unsigned short close_delay; 172 unsigned short closing_wait; /* time to wait before closing */ 173 174 struct mgsl_icount icount; 175 176 int timeout; 177 int x_char; /* xon/xoff character */ 178 u16 read_status_mask1; /* break detection (SR1 indications) */ 179 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */ 180 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */ 181 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */ 182 unsigned char *tx_buf; 183 int tx_put; 184 int tx_get; 185 int tx_count; 186 187 wait_queue_head_t status_event_wait_q; 188 wait_queue_head_t event_wait_q; 189 struct timer_list tx_timer; /* HDLC transmit timeout timer */ 190 struct _synclinkmp_info *next_device; /* device list link */ 191 struct timer_list status_timer; /* input signal status check timer */ 192 193 spinlock_t lock; /* spinlock for synchronizing with ISR */ 194 struct work_struct task; /* task structure for scheduling bh */ 195 196 u32 max_frame_size; /* as set by device config */ 197 198 u32 pending_bh; 199 200 bool bh_running; /* Protection from multiple */ 201 int isr_overflow; 202 bool bh_requested; 203 204 int dcd_chkcount; /* check counts to prevent */ 205 int cts_chkcount; /* too many IRQs if a signal */ 206 int dsr_chkcount; /* is floating */ 207 int ri_chkcount; 208 209 char *buffer_list; /* virtual address of Rx & Tx buffer lists */ 210 unsigned long buffer_list_phys; 211 212 unsigned int rx_buf_count; /* count of total allocated Rx buffers */ 213 SCADESC *rx_buf_list; /* list of receive buffer entries */ 214 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */ 215 unsigned int current_rx_buf; 216 217 unsigned int tx_buf_count; /* count of total allocated Tx buffers */ 218 SCADESC *tx_buf_list; /* list of transmit buffer entries */ 219 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */ 220 unsigned int last_tx_buf; 221 222 unsigned char *tmp_rx_buf; 223 unsigned int tmp_rx_buf_count; 224 225 bool rx_enabled; 226 bool rx_overflow; 227 228 bool tx_enabled; 229 bool tx_active; 230 u32 idle_mode; 231 232 unsigned char ie0_value; 233 unsigned char ie1_value; 234 unsigned char ie2_value; 235 unsigned char ctrlreg_value; 236 unsigned char old_signals; 237 238 char device_name[25]; /* device instance name */ 239 240 int port_count; 241 int adapter_num; 242 int port_num; 243 244 struct _synclinkmp_info *port_array[SCA_MAX_PORTS]; 245 246 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */ 247 248 unsigned int irq_level; /* interrupt level */ 249 unsigned long irq_flags; 250 bool irq_requested; /* true if IRQ requested */ 251 252 MGSL_PARAMS params; /* communications parameters */ 253 254 unsigned char serial_signals; /* current serial signal states */ 255 256 bool irq_occurred; /* for diagnostics use */ 257 unsigned int init_error; /* Initialization startup error */ 258 259 u32 last_mem_alloc; 260 unsigned char* memory_base; /* shared memory address (PCI only) */ 261 u32 phys_memory_base; 262 int shared_mem_requested; 263 264 unsigned char* sca_base; /* HD64570 SCA Memory address */ 265 u32 phys_sca_base; 266 u32 sca_offset; 267 bool sca_base_requested; 268 269 unsigned char* lcr_base; /* local config registers (PCI only) */ 270 u32 phys_lcr_base; 271 u32 lcr_offset; 272 int lcr_mem_requested; 273 274 unsigned char* statctrl_base; /* status/control register memory */ 275 u32 phys_statctrl_base; 276 u32 statctrl_offset; 277 bool sca_statctrl_requested; 278 279 u32 misc_ctrl_value; 280 char *flag_buf; 281 bool drop_rts_on_tx_done; 282 283 struct _input_signal_events input_signal_events; 284 285 /* SPPP/Cisco HDLC device parts */ 286 int netcount; 287 spinlock_t netlock; 288 289 #if SYNCLINK_GENERIC_HDLC 290 struct net_device *netdev; 291 #endif 292 293 } SLMP_INFO; 294 295 #define MGSL_MAGIC 0x5401 296 297 /* 298 * define serial signal status change macros 299 */ 300 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */ 301 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */ 302 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */ 303 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */ 304 305 /* Common Register macros */ 306 #define LPR 0x00 307 #define PABR0 0x02 308 #define PABR1 0x03 309 #define WCRL 0x04 310 #define WCRM 0x05 311 #define WCRH 0x06 312 #define DPCR 0x08 313 #define DMER 0x09 314 #define ISR0 0x10 315 #define ISR1 0x11 316 #define ISR2 0x12 317 #define IER0 0x14 318 #define IER1 0x15 319 #define IER2 0x16 320 #define ITCR 0x18 321 #define INTVR 0x1a 322 #define IMVR 0x1c 323 324 /* MSCI Register macros */ 325 #define TRB 0x20 326 #define TRBL 0x20 327 #define TRBH 0x21 328 #define SR0 0x22 329 #define SR1 0x23 330 #define SR2 0x24 331 #define SR3 0x25 332 #define FST 0x26 333 #define IE0 0x28 334 #define IE1 0x29 335 #define IE2 0x2a 336 #define FIE 0x2b 337 #define CMD 0x2c 338 #define MD0 0x2e 339 #define MD1 0x2f 340 #define MD2 0x30 341 #define CTL 0x31 342 #define SA0 0x32 343 #define SA1 0x33 344 #define IDL 0x34 345 #define TMC 0x35 346 #define RXS 0x36 347 #define TXS 0x37 348 #define TRC0 0x38 349 #define TRC1 0x39 350 #define RRC 0x3a 351 #define CST0 0x3c 352 #define CST1 0x3d 353 354 /* Timer Register Macros */ 355 #define TCNT 0x60 356 #define TCNTL 0x60 357 #define TCNTH 0x61 358 #define TCONR 0x62 359 #define TCONRL 0x62 360 #define TCONRH 0x63 361 #define TMCS 0x64 362 #define TEPR 0x65 363 364 /* DMA Controller Register macros */ 365 #define DARL 0x80 366 #define DARH 0x81 367 #define DARB 0x82 368 #define BAR 0x80 369 #define BARL 0x80 370 #define BARH 0x81 371 #define BARB 0x82 372 #define SAR 0x84 373 #define SARL 0x84 374 #define SARH 0x85 375 #define SARB 0x86 376 #define CPB 0x86 377 #define CDA 0x88 378 #define CDAL 0x88 379 #define CDAH 0x89 380 #define EDA 0x8a 381 #define EDAL 0x8a 382 #define EDAH 0x8b 383 #define BFL 0x8c 384 #define BFLL 0x8c 385 #define BFLH 0x8d 386 #define BCR 0x8e 387 #define BCRL 0x8e 388 #define BCRH 0x8f 389 #define DSR 0x90 390 #define DMR 0x91 391 #define FCT 0x93 392 #define DIR 0x94 393 #define DCMD 0x95 394 395 /* combine with timer or DMA register address */ 396 #define TIMER0 0x00 397 #define TIMER1 0x08 398 #define TIMER2 0x10 399 #define TIMER3 0x18 400 #define RXDMA 0x00 401 #define TXDMA 0x20 402 403 /* SCA Command Codes */ 404 #define NOOP 0x00 405 #define TXRESET 0x01 406 #define TXENABLE 0x02 407 #define TXDISABLE 0x03 408 #define TXCRCINIT 0x04 409 #define TXCRCEXCL 0x05 410 #define TXEOM 0x06 411 #define TXABORT 0x07 412 #define MPON 0x08 413 #define TXBUFCLR 0x09 414 #define RXRESET 0x11 415 #define RXENABLE 0x12 416 #define RXDISABLE 0x13 417 #define RXCRCINIT 0x14 418 #define RXREJECT 0x15 419 #define SEARCHMP 0x16 420 #define RXCRCEXCL 0x17 421 #define RXCRCCALC 0x18 422 #define CHRESET 0x21 423 #define HUNT 0x31 424 425 /* DMA command codes */ 426 #define SWABORT 0x01 427 #define FEICLEAR 0x02 428 429 /* IE0 */ 430 #define TXINTE BIT7 431 #define RXINTE BIT6 432 #define TXRDYE BIT1 433 #define RXRDYE BIT0 434 435 /* IE1 & SR1 */ 436 #define UDRN BIT7 437 #define IDLE BIT6 438 #define SYNCD BIT4 439 #define FLGD BIT4 440 #define CCTS BIT3 441 #define CDCD BIT2 442 #define BRKD BIT1 443 #define ABTD BIT1 444 #define GAPD BIT1 445 #define BRKE BIT0 446 #define IDLD BIT0 447 448 /* IE2 & SR2 */ 449 #define EOM BIT7 450 #define PMP BIT6 451 #define SHRT BIT6 452 #define PE BIT5 453 #define ABT BIT5 454 #define FRME BIT4 455 #define RBIT BIT4 456 #define OVRN BIT3 457 #define CRCE BIT2 458 459 460 /* 461 * Global linked list of SyncLink devices 462 */ 463 static SLMP_INFO *synclinkmp_device_list = NULL; 464 static int synclinkmp_adapter_count = -1; 465 static int synclinkmp_device_count = 0; 466 467 /* 468 * Set this param to non-zero to load eax with the 469 * .text section address and breakpoint on module load. 470 * This is useful for use with gdb and add-symbol-file command. 471 */ 472 static bool break_on_load = 0; 473 474 /* 475 * Driver major number, defaults to zero to get auto 476 * assigned major number. May be forced as module parameter. 477 */ 478 static int ttymajor = 0; 479 480 /* 481 * Array of user specified options for ISA adapters. 482 */ 483 static int debug_level = 0; 484 static int maxframe[MAX_DEVICES] = {0,}; 485 486 module_param(break_on_load, bool, 0); 487 module_param(ttymajor, int, 0); 488 module_param(debug_level, int, 0); 489 module_param_array(maxframe, int, NULL, 0); 490 491 static char *driver_name = "SyncLink MultiPort driver"; 492 static char *driver_version = "$Revision: 4.38 $"; 493 494 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent); 495 static void synclinkmp_remove_one(struct pci_dev *dev); 496 497 static struct pci_device_id synclinkmp_pci_tbl[] = { 498 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, }, 499 { 0, }, /* terminate list */ 500 }; 501 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl); 502 503 MODULE_LICENSE("GPL"); 504 505 static struct pci_driver synclinkmp_pci_driver = { 506 .name = "synclinkmp", 507 .id_table = synclinkmp_pci_tbl, 508 .probe = synclinkmp_init_one, 509 .remove = synclinkmp_remove_one, 510 }; 511 512 513 static struct tty_driver *serial_driver; 514 515 /* number of characters left in xmit buffer before we ask for more */ 516 #define WAKEUP_CHARS 256 517 518 519 /* tty callbacks */ 520 521 static int open(struct tty_struct *tty, struct file * filp); 522 static void close(struct tty_struct *tty, struct file * filp); 523 static void hangup(struct tty_struct *tty); 524 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); 525 526 static int write(struct tty_struct *tty, const unsigned char *buf, int count); 527 static int put_char(struct tty_struct *tty, unsigned char ch); 528 static void send_xchar(struct tty_struct *tty, char ch); 529 static void wait_until_sent(struct tty_struct *tty, int timeout); 530 static int write_room(struct tty_struct *tty); 531 static void flush_chars(struct tty_struct *tty); 532 static void flush_buffer(struct tty_struct *tty); 533 static void tx_hold(struct tty_struct *tty); 534 static void tx_release(struct tty_struct *tty); 535 536 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg); 537 static int chars_in_buffer(struct tty_struct *tty); 538 static void throttle(struct tty_struct * tty); 539 static void unthrottle(struct tty_struct * tty); 540 static int set_break(struct tty_struct *tty, int break_state); 541 542 #if SYNCLINK_GENERIC_HDLC 543 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 544 static void hdlcdev_tx_done(SLMP_INFO *info); 545 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size); 546 static int hdlcdev_init(SLMP_INFO *info); 547 static void hdlcdev_exit(SLMP_INFO *info); 548 #endif 549 550 /* ioctl handlers */ 551 552 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount); 553 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params); 554 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params); 555 static int get_txidle(SLMP_INFO *info, int __user *idle_mode); 556 static int set_txidle(SLMP_INFO *info, int idle_mode); 557 static int tx_enable(SLMP_INFO *info, int enable); 558 static int tx_abort(SLMP_INFO *info); 559 static int rx_enable(SLMP_INFO *info, int enable); 560 static int modem_input_wait(SLMP_INFO *info,int arg); 561 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr); 562 static int tiocmget(struct tty_struct *tty); 563 static int tiocmset(struct tty_struct *tty, 564 unsigned int set, unsigned int clear); 565 static int set_break(struct tty_struct *tty, int break_state); 566 567 static void add_device(SLMP_INFO *info); 568 static void device_init(int adapter_num, struct pci_dev *pdev); 569 static int claim_resources(SLMP_INFO *info); 570 static void release_resources(SLMP_INFO *info); 571 572 static int startup(SLMP_INFO *info); 573 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info); 574 static int carrier_raised(struct tty_port *port); 575 static void shutdown(SLMP_INFO *info); 576 static void program_hw(SLMP_INFO *info); 577 static void change_params(SLMP_INFO *info); 578 579 static bool init_adapter(SLMP_INFO *info); 580 static bool register_test(SLMP_INFO *info); 581 static bool irq_test(SLMP_INFO *info); 582 static bool loopback_test(SLMP_INFO *info); 583 static int adapter_test(SLMP_INFO *info); 584 static bool memory_test(SLMP_INFO *info); 585 586 static void reset_adapter(SLMP_INFO *info); 587 static void reset_port(SLMP_INFO *info); 588 static void async_mode(SLMP_INFO *info); 589 static void hdlc_mode(SLMP_INFO *info); 590 591 static void rx_stop(SLMP_INFO *info); 592 static void rx_start(SLMP_INFO *info); 593 static void rx_reset_buffers(SLMP_INFO *info); 594 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last); 595 static bool rx_get_frame(SLMP_INFO *info); 596 597 static void tx_start(SLMP_INFO *info); 598 static void tx_stop(SLMP_INFO *info); 599 static void tx_load_fifo(SLMP_INFO *info); 600 static void tx_set_idle(SLMP_INFO *info); 601 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count); 602 603 static void get_signals(SLMP_INFO *info); 604 static void set_signals(SLMP_INFO *info); 605 static void enable_loopback(SLMP_INFO *info, int enable); 606 static void set_rate(SLMP_INFO *info, u32 data_rate); 607 608 static int bh_action(SLMP_INFO *info); 609 static void bh_handler(struct work_struct *work); 610 static void bh_receive(SLMP_INFO *info); 611 static void bh_transmit(SLMP_INFO *info); 612 static void bh_status(SLMP_INFO *info); 613 static void isr_timer(SLMP_INFO *info); 614 static void isr_rxint(SLMP_INFO *info); 615 static void isr_rxrdy(SLMP_INFO *info); 616 static void isr_txint(SLMP_INFO *info); 617 static void isr_txrdy(SLMP_INFO *info); 618 static void isr_rxdmaok(SLMP_INFO *info); 619 static void isr_rxdmaerror(SLMP_INFO *info); 620 static void isr_txdmaok(SLMP_INFO *info); 621 static void isr_txdmaerror(SLMP_INFO *info); 622 static void isr_io_pin(SLMP_INFO *info, u16 status); 623 624 static int alloc_dma_bufs(SLMP_INFO *info); 625 static void free_dma_bufs(SLMP_INFO *info); 626 static int alloc_buf_list(SLMP_INFO *info); 627 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count); 628 static int alloc_tmp_rx_buf(SLMP_INFO *info); 629 static void free_tmp_rx_buf(SLMP_INFO *info); 630 631 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count); 632 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit); 633 static void tx_timeout(unsigned long context); 634 static void status_timeout(unsigned long context); 635 636 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr); 637 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val); 638 static u16 read_reg16(SLMP_INFO *info, unsigned char addr); 639 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val); 640 static unsigned char read_status_reg(SLMP_INFO * info); 641 static void write_control_reg(SLMP_INFO * info); 642 643 644 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes 645 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes 646 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes 647 648 static u32 misc_ctrl_value = 0x007e4040; 649 static u32 lcr1_brdr_value = 0x00800028; 650 651 static u32 read_ahead_count = 8; 652 653 /* DPCR, DMA Priority Control 654 * 655 * 07..05 Not used, must be 0 656 * 04 BRC, bus release condition: 0=all transfers complete 657 * 1=release after 1 xfer on all channels 658 * 03 CCC, channel change condition: 0=every cycle 659 * 1=after each channel completes all xfers 660 * 02..00 PR<2..0>, priority 100=round robin 661 * 662 * 00000100 = 0x00 663 */ 664 static unsigned char dma_priority = 0x04; 665 666 // Number of bytes that can be written to shared RAM 667 // in a single write operation 668 static u32 sca_pci_load_interval = 64; 669 670 /* 671 * 1st function defined in .text section. Calling this function in 672 * init_module() followed by a breakpoint allows a remote debugger 673 * (gdb) to get the .text address for the add-symbol-file command. 674 * This allows remote debugging of dynamically loadable modules. 675 */ 676 static void* synclinkmp_get_text_ptr(void); 677 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;} 678 679 static inline int sanity_check(SLMP_INFO *info, 680 char *name, const char *routine) 681 { 682 #ifdef SANITY_CHECK 683 static const char *badmagic = 684 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n"; 685 static const char *badinfo = 686 "Warning: null synclinkmp_struct for (%s) in %s\n"; 687 688 if (!info) { 689 printk(badinfo, name, routine); 690 return 1; 691 } 692 if (info->magic != MGSL_MAGIC) { 693 printk(badmagic, name, routine); 694 return 1; 695 } 696 #else 697 if (!info) 698 return 1; 699 #endif 700 return 0; 701 } 702 703 /** 704 * line discipline callback wrappers 705 * 706 * The wrappers maintain line discipline references 707 * while calling into the line discipline. 708 * 709 * ldisc_receive_buf - pass receive data to line discipline 710 */ 711 712 static void ldisc_receive_buf(struct tty_struct *tty, 713 const __u8 *data, char *flags, int count) 714 { 715 struct tty_ldisc *ld; 716 if (!tty) 717 return; 718 ld = tty_ldisc_ref(tty); 719 if (ld) { 720 if (ld->ops->receive_buf) 721 ld->ops->receive_buf(tty, data, flags, count); 722 tty_ldisc_deref(ld); 723 } 724 } 725 726 /* tty callbacks */ 727 728 static int install(struct tty_driver *driver, struct tty_struct *tty) 729 { 730 SLMP_INFO *info; 731 int line = tty->index; 732 733 if (line >= synclinkmp_device_count) { 734 printk("%s(%d): open with invalid line #%d.\n", 735 __FILE__,__LINE__,line); 736 return -ENODEV; 737 } 738 739 info = synclinkmp_device_list; 740 while (info && info->line != line) 741 info = info->next_device; 742 if (sanity_check(info, tty->name, "open")) 743 return -ENODEV; 744 if (info->init_error) { 745 printk("%s(%d):%s device is not allocated, init error=%d\n", 746 __FILE__, __LINE__, info->device_name, 747 info->init_error); 748 return -ENODEV; 749 } 750 751 tty->driver_data = info; 752 753 return tty_port_install(&info->port, driver, tty); 754 } 755 756 /* Called when a port is opened. Init and enable port. 757 */ 758 static int open(struct tty_struct *tty, struct file *filp) 759 { 760 SLMP_INFO *info = tty->driver_data; 761 unsigned long flags; 762 int retval; 763 764 info->port.tty = tty; 765 766 if (debug_level >= DEBUG_LEVEL_INFO) 767 printk("%s(%d):%s open(), old ref count = %d\n", 768 __FILE__,__LINE__,tty->driver->name, info->port.count); 769 770 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; 771 772 spin_lock_irqsave(&info->netlock, flags); 773 if (info->netcount) { 774 retval = -EBUSY; 775 spin_unlock_irqrestore(&info->netlock, flags); 776 goto cleanup; 777 } 778 info->port.count++; 779 spin_unlock_irqrestore(&info->netlock, flags); 780 781 if (info->port.count == 1) { 782 /* 1st open on this device, init hardware */ 783 retval = startup(info); 784 if (retval < 0) 785 goto cleanup; 786 } 787 788 retval = block_til_ready(tty, filp, info); 789 if (retval) { 790 if (debug_level >= DEBUG_LEVEL_INFO) 791 printk("%s(%d):%s block_til_ready() returned %d\n", 792 __FILE__,__LINE__, info->device_name, retval); 793 goto cleanup; 794 } 795 796 if (debug_level >= DEBUG_LEVEL_INFO) 797 printk("%s(%d):%s open() success\n", 798 __FILE__,__LINE__, info->device_name); 799 retval = 0; 800 801 cleanup: 802 if (retval) { 803 if (tty->count == 1) 804 info->port.tty = NULL; /* tty layer will release tty struct */ 805 if(info->port.count) 806 info->port.count--; 807 } 808 809 return retval; 810 } 811 812 /* Called when port is closed. Wait for remaining data to be 813 * sent. Disable port and free resources. 814 */ 815 static void close(struct tty_struct *tty, struct file *filp) 816 { 817 SLMP_INFO * info = tty->driver_data; 818 819 if (sanity_check(info, tty->name, "close")) 820 return; 821 822 if (debug_level >= DEBUG_LEVEL_INFO) 823 printk("%s(%d):%s close() entry, count=%d\n", 824 __FILE__,__LINE__, info->device_name, info->port.count); 825 826 if (tty_port_close_start(&info->port, tty, filp) == 0) 827 goto cleanup; 828 829 mutex_lock(&info->port.mutex); 830 if (info->port.flags & ASYNC_INITIALIZED) 831 wait_until_sent(tty, info->timeout); 832 833 flush_buffer(tty); 834 tty_ldisc_flush(tty); 835 shutdown(info); 836 mutex_unlock(&info->port.mutex); 837 838 tty_port_close_end(&info->port, tty); 839 info->port.tty = NULL; 840 cleanup: 841 if (debug_level >= DEBUG_LEVEL_INFO) 842 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__, 843 tty->driver->name, info->port.count); 844 } 845 846 /* Called by tty_hangup() when a hangup is signaled. 847 * This is the same as closing all open descriptors for the port. 848 */ 849 static void hangup(struct tty_struct *tty) 850 { 851 SLMP_INFO *info = tty->driver_data; 852 unsigned long flags; 853 854 if (debug_level >= DEBUG_LEVEL_INFO) 855 printk("%s(%d):%s hangup()\n", 856 __FILE__,__LINE__, info->device_name ); 857 858 if (sanity_check(info, tty->name, "hangup")) 859 return; 860 861 mutex_lock(&info->port.mutex); 862 flush_buffer(tty); 863 shutdown(info); 864 865 spin_lock_irqsave(&info->port.lock, flags); 866 info->port.count = 0; 867 info->port.flags &= ~ASYNC_NORMAL_ACTIVE; 868 info->port.tty = NULL; 869 spin_unlock_irqrestore(&info->port.lock, flags); 870 mutex_unlock(&info->port.mutex); 871 872 wake_up_interruptible(&info->port.open_wait); 873 } 874 875 /* Set new termios settings 876 */ 877 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) 878 { 879 SLMP_INFO *info = tty->driver_data; 880 unsigned long flags; 881 882 if (debug_level >= DEBUG_LEVEL_INFO) 883 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__, 884 tty->driver->name ); 885 886 change_params(info); 887 888 /* Handle transition to B0 status */ 889 if (old_termios->c_cflag & CBAUD && 890 !(tty->termios.c_cflag & CBAUD)) { 891 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 892 spin_lock_irqsave(&info->lock,flags); 893 set_signals(info); 894 spin_unlock_irqrestore(&info->lock,flags); 895 } 896 897 /* Handle transition away from B0 status */ 898 if (!(old_termios->c_cflag & CBAUD) && 899 tty->termios.c_cflag & CBAUD) { 900 info->serial_signals |= SerialSignal_DTR; 901 if (!(tty->termios.c_cflag & CRTSCTS) || 902 !test_bit(TTY_THROTTLED, &tty->flags)) { 903 info->serial_signals |= SerialSignal_RTS; 904 } 905 spin_lock_irqsave(&info->lock,flags); 906 set_signals(info); 907 spin_unlock_irqrestore(&info->lock,flags); 908 } 909 910 /* Handle turning off CRTSCTS */ 911 if (old_termios->c_cflag & CRTSCTS && 912 !(tty->termios.c_cflag & CRTSCTS)) { 913 tty->hw_stopped = 0; 914 tx_release(tty); 915 } 916 } 917 918 /* Send a block of data 919 * 920 * Arguments: 921 * 922 * tty pointer to tty information structure 923 * buf pointer to buffer containing send data 924 * count size of send data in bytes 925 * 926 * Return Value: number of characters written 927 */ 928 static int write(struct tty_struct *tty, 929 const unsigned char *buf, int count) 930 { 931 int c, ret = 0; 932 SLMP_INFO *info = tty->driver_data; 933 unsigned long flags; 934 935 if (debug_level >= DEBUG_LEVEL_INFO) 936 printk("%s(%d):%s write() count=%d\n", 937 __FILE__,__LINE__,info->device_name,count); 938 939 if (sanity_check(info, tty->name, "write")) 940 goto cleanup; 941 942 if (!info->tx_buf) 943 goto cleanup; 944 945 if (info->params.mode == MGSL_MODE_HDLC) { 946 if (count > info->max_frame_size) { 947 ret = -EIO; 948 goto cleanup; 949 } 950 if (info->tx_active) 951 goto cleanup; 952 if (info->tx_count) { 953 /* send accumulated data from send_char() calls */ 954 /* as frame and wait before accepting more data. */ 955 tx_load_dma_buffer(info, info->tx_buf, info->tx_count); 956 goto start; 957 } 958 ret = info->tx_count = count; 959 tx_load_dma_buffer(info, buf, count); 960 goto start; 961 } 962 963 for (;;) { 964 c = min_t(int, count, 965 min(info->max_frame_size - info->tx_count - 1, 966 info->max_frame_size - info->tx_put)); 967 if (c <= 0) 968 break; 969 970 memcpy(info->tx_buf + info->tx_put, buf, c); 971 972 spin_lock_irqsave(&info->lock,flags); 973 info->tx_put += c; 974 if (info->tx_put >= info->max_frame_size) 975 info->tx_put -= info->max_frame_size; 976 info->tx_count += c; 977 spin_unlock_irqrestore(&info->lock,flags); 978 979 buf += c; 980 count -= c; 981 ret += c; 982 } 983 984 if (info->params.mode == MGSL_MODE_HDLC) { 985 if (count) { 986 ret = info->tx_count = 0; 987 goto cleanup; 988 } 989 tx_load_dma_buffer(info, info->tx_buf, info->tx_count); 990 } 991 start: 992 if (info->tx_count && !tty->stopped && !tty->hw_stopped) { 993 spin_lock_irqsave(&info->lock,flags); 994 if (!info->tx_active) 995 tx_start(info); 996 spin_unlock_irqrestore(&info->lock,flags); 997 } 998 999 cleanup: 1000 if (debug_level >= DEBUG_LEVEL_INFO) 1001 printk( "%s(%d):%s write() returning=%d\n", 1002 __FILE__,__LINE__,info->device_name,ret); 1003 return ret; 1004 } 1005 1006 /* Add a character to the transmit buffer. 1007 */ 1008 static int put_char(struct tty_struct *tty, unsigned char ch) 1009 { 1010 SLMP_INFO *info = tty->driver_data; 1011 unsigned long flags; 1012 int ret = 0; 1013 1014 if ( debug_level >= DEBUG_LEVEL_INFO ) { 1015 printk( "%s(%d):%s put_char(%d)\n", 1016 __FILE__,__LINE__,info->device_name,ch); 1017 } 1018 1019 if (sanity_check(info, tty->name, "put_char")) 1020 return 0; 1021 1022 if (!info->tx_buf) 1023 return 0; 1024 1025 spin_lock_irqsave(&info->lock,flags); 1026 1027 if ( (info->params.mode != MGSL_MODE_HDLC) || 1028 !info->tx_active ) { 1029 1030 if (info->tx_count < info->max_frame_size - 1) { 1031 info->tx_buf[info->tx_put++] = ch; 1032 if (info->tx_put >= info->max_frame_size) 1033 info->tx_put -= info->max_frame_size; 1034 info->tx_count++; 1035 ret = 1; 1036 } 1037 } 1038 1039 spin_unlock_irqrestore(&info->lock,flags); 1040 return ret; 1041 } 1042 1043 /* Send a high-priority XON/XOFF character 1044 */ 1045 static void send_xchar(struct tty_struct *tty, char ch) 1046 { 1047 SLMP_INFO *info = tty->driver_data; 1048 unsigned long flags; 1049 1050 if (debug_level >= DEBUG_LEVEL_INFO) 1051 printk("%s(%d):%s send_xchar(%d)\n", 1052 __FILE__,__LINE__, info->device_name, ch ); 1053 1054 if (sanity_check(info, tty->name, "send_xchar")) 1055 return; 1056 1057 info->x_char = ch; 1058 if (ch) { 1059 /* Make sure transmit interrupts are on */ 1060 spin_lock_irqsave(&info->lock,flags); 1061 if (!info->tx_enabled) 1062 tx_start(info); 1063 spin_unlock_irqrestore(&info->lock,flags); 1064 } 1065 } 1066 1067 /* Wait until the transmitter is empty. 1068 */ 1069 static void wait_until_sent(struct tty_struct *tty, int timeout) 1070 { 1071 SLMP_INFO * info = tty->driver_data; 1072 unsigned long orig_jiffies, char_time; 1073 1074 if (!info ) 1075 return; 1076 1077 if (debug_level >= DEBUG_LEVEL_INFO) 1078 printk("%s(%d):%s wait_until_sent() entry\n", 1079 __FILE__,__LINE__, info->device_name ); 1080 1081 if (sanity_check(info, tty->name, "wait_until_sent")) 1082 return; 1083 1084 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags)) 1085 goto exit; 1086 1087 orig_jiffies = jiffies; 1088 1089 /* Set check interval to 1/5 of estimated time to 1090 * send a character, and make it at least 1. The check 1091 * interval should also be less than the timeout. 1092 * Note: use tight timings here to satisfy the NIST-PCTS. 1093 */ 1094 1095 if ( info->params.data_rate ) { 1096 char_time = info->timeout/(32 * 5); 1097 if (!char_time) 1098 char_time++; 1099 } else 1100 char_time = 1; 1101 1102 if (timeout) 1103 char_time = min_t(unsigned long, char_time, timeout); 1104 1105 if ( info->params.mode == MGSL_MODE_HDLC ) { 1106 while (info->tx_active) { 1107 msleep_interruptible(jiffies_to_msecs(char_time)); 1108 if (signal_pending(current)) 1109 break; 1110 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 1111 break; 1112 } 1113 } else { 1114 /* 1115 * TODO: determine if there is something similar to USC16C32 1116 * TXSTATUS_ALL_SENT status 1117 */ 1118 while ( info->tx_active && info->tx_enabled) { 1119 msleep_interruptible(jiffies_to_msecs(char_time)); 1120 if (signal_pending(current)) 1121 break; 1122 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 1123 break; 1124 } 1125 } 1126 1127 exit: 1128 if (debug_level >= DEBUG_LEVEL_INFO) 1129 printk("%s(%d):%s wait_until_sent() exit\n", 1130 __FILE__,__LINE__, info->device_name ); 1131 } 1132 1133 /* Return the count of free bytes in transmit buffer 1134 */ 1135 static int write_room(struct tty_struct *tty) 1136 { 1137 SLMP_INFO *info = tty->driver_data; 1138 int ret; 1139 1140 if (sanity_check(info, tty->name, "write_room")) 1141 return 0; 1142 1143 if (info->params.mode == MGSL_MODE_HDLC) { 1144 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; 1145 } else { 1146 ret = info->max_frame_size - info->tx_count - 1; 1147 if (ret < 0) 1148 ret = 0; 1149 } 1150 1151 if (debug_level >= DEBUG_LEVEL_INFO) 1152 printk("%s(%d):%s write_room()=%d\n", 1153 __FILE__, __LINE__, info->device_name, ret); 1154 1155 return ret; 1156 } 1157 1158 /* enable transmitter and send remaining buffered characters 1159 */ 1160 static void flush_chars(struct tty_struct *tty) 1161 { 1162 SLMP_INFO *info = tty->driver_data; 1163 unsigned long flags; 1164 1165 if ( debug_level >= DEBUG_LEVEL_INFO ) 1166 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n", 1167 __FILE__,__LINE__,info->device_name,info->tx_count); 1168 1169 if (sanity_check(info, tty->name, "flush_chars")) 1170 return; 1171 1172 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped || 1173 !info->tx_buf) 1174 return; 1175 1176 if ( debug_level >= DEBUG_LEVEL_INFO ) 1177 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n", 1178 __FILE__,__LINE__,info->device_name ); 1179 1180 spin_lock_irqsave(&info->lock,flags); 1181 1182 if (!info->tx_active) { 1183 if ( (info->params.mode == MGSL_MODE_HDLC) && 1184 info->tx_count ) { 1185 /* operating in synchronous (frame oriented) mode */ 1186 /* copy data from circular tx_buf to */ 1187 /* transmit DMA buffer. */ 1188 tx_load_dma_buffer(info, 1189 info->tx_buf,info->tx_count); 1190 } 1191 tx_start(info); 1192 } 1193 1194 spin_unlock_irqrestore(&info->lock,flags); 1195 } 1196 1197 /* Discard all data in the send buffer 1198 */ 1199 static void flush_buffer(struct tty_struct *tty) 1200 { 1201 SLMP_INFO *info = tty->driver_data; 1202 unsigned long flags; 1203 1204 if (debug_level >= DEBUG_LEVEL_INFO) 1205 printk("%s(%d):%s flush_buffer() entry\n", 1206 __FILE__,__LINE__, info->device_name ); 1207 1208 if (sanity_check(info, tty->name, "flush_buffer")) 1209 return; 1210 1211 spin_lock_irqsave(&info->lock,flags); 1212 info->tx_count = info->tx_put = info->tx_get = 0; 1213 del_timer(&info->tx_timer); 1214 spin_unlock_irqrestore(&info->lock,flags); 1215 1216 tty_wakeup(tty); 1217 } 1218 1219 /* throttle (stop) transmitter 1220 */ 1221 static void tx_hold(struct tty_struct *tty) 1222 { 1223 SLMP_INFO *info = tty->driver_data; 1224 unsigned long flags; 1225 1226 if (sanity_check(info, tty->name, "tx_hold")) 1227 return; 1228 1229 if ( debug_level >= DEBUG_LEVEL_INFO ) 1230 printk("%s(%d):%s tx_hold()\n", 1231 __FILE__,__LINE__,info->device_name); 1232 1233 spin_lock_irqsave(&info->lock,flags); 1234 if (info->tx_enabled) 1235 tx_stop(info); 1236 spin_unlock_irqrestore(&info->lock,flags); 1237 } 1238 1239 /* release (start) transmitter 1240 */ 1241 static void tx_release(struct tty_struct *tty) 1242 { 1243 SLMP_INFO *info = tty->driver_data; 1244 unsigned long flags; 1245 1246 if (sanity_check(info, tty->name, "tx_release")) 1247 return; 1248 1249 if ( debug_level >= DEBUG_LEVEL_INFO ) 1250 printk("%s(%d):%s tx_release()\n", 1251 __FILE__,__LINE__,info->device_name); 1252 1253 spin_lock_irqsave(&info->lock,flags); 1254 if (!info->tx_enabled) 1255 tx_start(info); 1256 spin_unlock_irqrestore(&info->lock,flags); 1257 } 1258 1259 /* Service an IOCTL request 1260 * 1261 * Arguments: 1262 * 1263 * tty pointer to tty instance data 1264 * cmd IOCTL command code 1265 * arg command argument/context 1266 * 1267 * Return Value: 0 if success, otherwise error code 1268 */ 1269 static int ioctl(struct tty_struct *tty, 1270 unsigned int cmd, unsigned long arg) 1271 { 1272 SLMP_INFO *info = tty->driver_data; 1273 void __user *argp = (void __user *)arg; 1274 1275 if (debug_level >= DEBUG_LEVEL_INFO) 1276 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__, 1277 info->device_name, cmd ); 1278 1279 if (sanity_check(info, tty->name, "ioctl")) 1280 return -ENODEV; 1281 1282 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && 1283 (cmd != TIOCMIWAIT)) { 1284 if (tty->flags & (1 << TTY_IO_ERROR)) 1285 return -EIO; 1286 } 1287 1288 switch (cmd) { 1289 case MGSL_IOCGPARAMS: 1290 return get_params(info, argp); 1291 case MGSL_IOCSPARAMS: 1292 return set_params(info, argp); 1293 case MGSL_IOCGTXIDLE: 1294 return get_txidle(info, argp); 1295 case MGSL_IOCSTXIDLE: 1296 return set_txidle(info, (int)arg); 1297 case MGSL_IOCTXENABLE: 1298 return tx_enable(info, (int)arg); 1299 case MGSL_IOCRXENABLE: 1300 return rx_enable(info, (int)arg); 1301 case MGSL_IOCTXABORT: 1302 return tx_abort(info); 1303 case MGSL_IOCGSTATS: 1304 return get_stats(info, argp); 1305 case MGSL_IOCWAITEVENT: 1306 return wait_mgsl_event(info, argp); 1307 case MGSL_IOCLOOPTXDONE: 1308 return 0; // TODO: Not supported, need to document 1309 /* Wait for modem input (DCD,RI,DSR,CTS) change 1310 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS) 1311 */ 1312 case TIOCMIWAIT: 1313 return modem_input_wait(info,(int)arg); 1314 1315 /* 1316 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) 1317 * Return: write counters to the user passed counter struct 1318 * NB: both 1->0 and 0->1 transitions are counted except for 1319 * RI where only 0->1 is counted. 1320 */ 1321 default: 1322 return -ENOIOCTLCMD; 1323 } 1324 return 0; 1325 } 1326 1327 static int get_icount(struct tty_struct *tty, 1328 struct serial_icounter_struct *icount) 1329 { 1330 SLMP_INFO *info = tty->driver_data; 1331 struct mgsl_icount cnow; /* kernel counter temps */ 1332 unsigned long flags; 1333 1334 spin_lock_irqsave(&info->lock,flags); 1335 cnow = info->icount; 1336 spin_unlock_irqrestore(&info->lock,flags); 1337 1338 icount->cts = cnow.cts; 1339 icount->dsr = cnow.dsr; 1340 icount->rng = cnow.rng; 1341 icount->dcd = cnow.dcd; 1342 icount->rx = cnow.rx; 1343 icount->tx = cnow.tx; 1344 icount->frame = cnow.frame; 1345 icount->overrun = cnow.overrun; 1346 icount->parity = cnow.parity; 1347 icount->brk = cnow.brk; 1348 icount->buf_overrun = cnow.buf_overrun; 1349 1350 return 0; 1351 } 1352 1353 /* 1354 * /proc fs routines.... 1355 */ 1356 1357 static inline void line_info(struct seq_file *m, SLMP_INFO *info) 1358 { 1359 char stat_buf[30]; 1360 unsigned long flags; 1361 1362 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n" 1363 "\tIRQ=%d MaxFrameSize=%u\n", 1364 info->device_name, 1365 info->phys_sca_base, 1366 info->phys_memory_base, 1367 info->phys_statctrl_base, 1368 info->phys_lcr_base, 1369 info->irq_level, 1370 info->max_frame_size ); 1371 1372 /* output current serial signal states */ 1373 spin_lock_irqsave(&info->lock,flags); 1374 get_signals(info); 1375 spin_unlock_irqrestore(&info->lock,flags); 1376 1377 stat_buf[0] = 0; 1378 stat_buf[1] = 0; 1379 if (info->serial_signals & SerialSignal_RTS) 1380 strcat(stat_buf, "|RTS"); 1381 if (info->serial_signals & SerialSignal_CTS) 1382 strcat(stat_buf, "|CTS"); 1383 if (info->serial_signals & SerialSignal_DTR) 1384 strcat(stat_buf, "|DTR"); 1385 if (info->serial_signals & SerialSignal_DSR) 1386 strcat(stat_buf, "|DSR"); 1387 if (info->serial_signals & SerialSignal_DCD) 1388 strcat(stat_buf, "|CD"); 1389 if (info->serial_signals & SerialSignal_RI) 1390 strcat(stat_buf, "|RI"); 1391 1392 if (info->params.mode == MGSL_MODE_HDLC) { 1393 seq_printf(m, "\tHDLC txok:%d rxok:%d", 1394 info->icount.txok, info->icount.rxok); 1395 if (info->icount.txunder) 1396 seq_printf(m, " txunder:%d", info->icount.txunder); 1397 if (info->icount.txabort) 1398 seq_printf(m, " txabort:%d", info->icount.txabort); 1399 if (info->icount.rxshort) 1400 seq_printf(m, " rxshort:%d", info->icount.rxshort); 1401 if (info->icount.rxlong) 1402 seq_printf(m, " rxlong:%d", info->icount.rxlong); 1403 if (info->icount.rxover) 1404 seq_printf(m, " rxover:%d", info->icount.rxover); 1405 if (info->icount.rxcrc) 1406 seq_printf(m, " rxlong:%d", info->icount.rxcrc); 1407 } else { 1408 seq_printf(m, "\tASYNC tx:%d rx:%d", 1409 info->icount.tx, info->icount.rx); 1410 if (info->icount.frame) 1411 seq_printf(m, " fe:%d", info->icount.frame); 1412 if (info->icount.parity) 1413 seq_printf(m, " pe:%d", info->icount.parity); 1414 if (info->icount.brk) 1415 seq_printf(m, " brk:%d", info->icount.brk); 1416 if (info->icount.overrun) 1417 seq_printf(m, " oe:%d", info->icount.overrun); 1418 } 1419 1420 /* Append serial signal status to end */ 1421 seq_printf(m, " %s\n", stat_buf+1); 1422 1423 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 1424 info->tx_active,info->bh_requested,info->bh_running, 1425 info->pending_bh); 1426 } 1427 1428 /* Called to print information about devices 1429 */ 1430 static int synclinkmp_proc_show(struct seq_file *m, void *v) 1431 { 1432 SLMP_INFO *info; 1433 1434 seq_printf(m, "synclinkmp driver:%s\n", driver_version); 1435 1436 info = synclinkmp_device_list; 1437 while( info ) { 1438 line_info(m, info); 1439 info = info->next_device; 1440 } 1441 return 0; 1442 } 1443 1444 static int synclinkmp_proc_open(struct inode *inode, struct file *file) 1445 { 1446 return single_open(file, synclinkmp_proc_show, NULL); 1447 } 1448 1449 static const struct file_operations synclinkmp_proc_fops = { 1450 .owner = THIS_MODULE, 1451 .open = synclinkmp_proc_open, 1452 .read = seq_read, 1453 .llseek = seq_lseek, 1454 .release = single_release, 1455 }; 1456 1457 /* Return the count of bytes in transmit buffer 1458 */ 1459 static int chars_in_buffer(struct tty_struct *tty) 1460 { 1461 SLMP_INFO *info = tty->driver_data; 1462 1463 if (sanity_check(info, tty->name, "chars_in_buffer")) 1464 return 0; 1465 1466 if (debug_level >= DEBUG_LEVEL_INFO) 1467 printk("%s(%d):%s chars_in_buffer()=%d\n", 1468 __FILE__, __LINE__, info->device_name, info->tx_count); 1469 1470 return info->tx_count; 1471 } 1472 1473 /* Signal remote device to throttle send data (our receive data) 1474 */ 1475 static void throttle(struct tty_struct * tty) 1476 { 1477 SLMP_INFO *info = tty->driver_data; 1478 unsigned long flags; 1479 1480 if (debug_level >= DEBUG_LEVEL_INFO) 1481 printk("%s(%d):%s throttle() entry\n", 1482 __FILE__,__LINE__, info->device_name ); 1483 1484 if (sanity_check(info, tty->name, "throttle")) 1485 return; 1486 1487 if (I_IXOFF(tty)) 1488 send_xchar(tty, STOP_CHAR(tty)); 1489 1490 if (tty->termios.c_cflag & CRTSCTS) { 1491 spin_lock_irqsave(&info->lock,flags); 1492 info->serial_signals &= ~SerialSignal_RTS; 1493 set_signals(info); 1494 spin_unlock_irqrestore(&info->lock,flags); 1495 } 1496 } 1497 1498 /* Signal remote device to stop throttling send data (our receive data) 1499 */ 1500 static void unthrottle(struct tty_struct * tty) 1501 { 1502 SLMP_INFO *info = tty->driver_data; 1503 unsigned long flags; 1504 1505 if (debug_level >= DEBUG_LEVEL_INFO) 1506 printk("%s(%d):%s unthrottle() entry\n", 1507 __FILE__,__LINE__, info->device_name ); 1508 1509 if (sanity_check(info, tty->name, "unthrottle")) 1510 return; 1511 1512 if (I_IXOFF(tty)) { 1513 if (info->x_char) 1514 info->x_char = 0; 1515 else 1516 send_xchar(tty, START_CHAR(tty)); 1517 } 1518 1519 if (tty->termios.c_cflag & CRTSCTS) { 1520 spin_lock_irqsave(&info->lock,flags); 1521 info->serial_signals |= SerialSignal_RTS; 1522 set_signals(info); 1523 spin_unlock_irqrestore(&info->lock,flags); 1524 } 1525 } 1526 1527 /* set or clear transmit break condition 1528 * break_state -1=set break condition, 0=clear 1529 */ 1530 static int set_break(struct tty_struct *tty, int break_state) 1531 { 1532 unsigned char RegValue; 1533 SLMP_INFO * info = tty->driver_data; 1534 unsigned long flags; 1535 1536 if (debug_level >= DEBUG_LEVEL_INFO) 1537 printk("%s(%d):%s set_break(%d)\n", 1538 __FILE__,__LINE__, info->device_name, break_state); 1539 1540 if (sanity_check(info, tty->name, "set_break")) 1541 return -EINVAL; 1542 1543 spin_lock_irqsave(&info->lock,flags); 1544 RegValue = read_reg(info, CTL); 1545 if (break_state == -1) 1546 RegValue |= BIT3; 1547 else 1548 RegValue &= ~BIT3; 1549 write_reg(info, CTL, RegValue); 1550 spin_unlock_irqrestore(&info->lock,flags); 1551 return 0; 1552 } 1553 1554 #if SYNCLINK_GENERIC_HDLC 1555 1556 /** 1557 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 1558 * set encoding and frame check sequence (FCS) options 1559 * 1560 * dev pointer to network device structure 1561 * encoding serial encoding setting 1562 * parity FCS setting 1563 * 1564 * returns 0 if success, otherwise error code 1565 */ 1566 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 1567 unsigned short parity) 1568 { 1569 SLMP_INFO *info = dev_to_port(dev); 1570 unsigned char new_encoding; 1571 unsigned short new_crctype; 1572 1573 /* return error if TTY interface open */ 1574 if (info->port.count) 1575 return -EBUSY; 1576 1577 switch (encoding) 1578 { 1579 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 1580 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 1581 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 1582 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 1583 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 1584 default: return -EINVAL; 1585 } 1586 1587 switch (parity) 1588 { 1589 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 1590 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 1591 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 1592 default: return -EINVAL; 1593 } 1594 1595 info->params.encoding = new_encoding; 1596 info->params.crc_type = new_crctype; 1597 1598 /* if network interface up, reprogram hardware */ 1599 if (info->netcount) 1600 program_hw(info); 1601 1602 return 0; 1603 } 1604 1605 /** 1606 * called by generic HDLC layer to send frame 1607 * 1608 * skb socket buffer containing HDLC frame 1609 * dev pointer to network device structure 1610 */ 1611 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 1612 struct net_device *dev) 1613 { 1614 SLMP_INFO *info = dev_to_port(dev); 1615 unsigned long flags; 1616 1617 if (debug_level >= DEBUG_LEVEL_INFO) 1618 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); 1619 1620 /* stop sending until this frame completes */ 1621 netif_stop_queue(dev); 1622 1623 /* copy data to device buffers */ 1624 info->tx_count = skb->len; 1625 tx_load_dma_buffer(info, skb->data, skb->len); 1626 1627 /* update network statistics */ 1628 dev->stats.tx_packets++; 1629 dev->stats.tx_bytes += skb->len; 1630 1631 /* done with socket buffer, so free it */ 1632 dev_kfree_skb(skb); 1633 1634 /* save start time for transmit timeout detection */ 1635 dev->trans_start = jiffies; 1636 1637 /* start hardware transmitter if necessary */ 1638 spin_lock_irqsave(&info->lock,flags); 1639 if (!info->tx_active) 1640 tx_start(info); 1641 spin_unlock_irqrestore(&info->lock,flags); 1642 1643 return NETDEV_TX_OK; 1644 } 1645 1646 /** 1647 * called by network layer when interface enabled 1648 * claim resources and initialize hardware 1649 * 1650 * dev pointer to network device structure 1651 * 1652 * returns 0 if success, otherwise error code 1653 */ 1654 static int hdlcdev_open(struct net_device *dev) 1655 { 1656 SLMP_INFO *info = dev_to_port(dev); 1657 int rc; 1658 unsigned long flags; 1659 1660 if (debug_level >= DEBUG_LEVEL_INFO) 1661 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); 1662 1663 /* generic HDLC layer open processing */ 1664 rc = hdlc_open(dev); 1665 if (rc) 1666 return rc; 1667 1668 /* arbitrate between network and tty opens */ 1669 spin_lock_irqsave(&info->netlock, flags); 1670 if (info->port.count != 0 || info->netcount != 0) { 1671 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); 1672 spin_unlock_irqrestore(&info->netlock, flags); 1673 return -EBUSY; 1674 } 1675 info->netcount=1; 1676 spin_unlock_irqrestore(&info->netlock, flags); 1677 1678 /* claim resources and init adapter */ 1679 if ((rc = startup(info)) != 0) { 1680 spin_lock_irqsave(&info->netlock, flags); 1681 info->netcount=0; 1682 spin_unlock_irqrestore(&info->netlock, flags); 1683 return rc; 1684 } 1685 1686 /* assert RTS and DTR, apply hardware settings */ 1687 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; 1688 program_hw(info); 1689 1690 /* enable network layer transmit */ 1691 dev->trans_start = jiffies; 1692 netif_start_queue(dev); 1693 1694 /* inform generic HDLC layer of current DCD status */ 1695 spin_lock_irqsave(&info->lock, flags); 1696 get_signals(info); 1697 spin_unlock_irqrestore(&info->lock, flags); 1698 if (info->serial_signals & SerialSignal_DCD) 1699 netif_carrier_on(dev); 1700 else 1701 netif_carrier_off(dev); 1702 return 0; 1703 } 1704 1705 /** 1706 * called by network layer when interface is disabled 1707 * shutdown hardware and release resources 1708 * 1709 * dev pointer to network device structure 1710 * 1711 * returns 0 if success, otherwise error code 1712 */ 1713 static int hdlcdev_close(struct net_device *dev) 1714 { 1715 SLMP_INFO *info = dev_to_port(dev); 1716 unsigned long flags; 1717 1718 if (debug_level >= DEBUG_LEVEL_INFO) 1719 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); 1720 1721 netif_stop_queue(dev); 1722 1723 /* shutdown adapter and release resources */ 1724 shutdown(info); 1725 1726 hdlc_close(dev); 1727 1728 spin_lock_irqsave(&info->netlock, flags); 1729 info->netcount=0; 1730 spin_unlock_irqrestore(&info->netlock, flags); 1731 1732 return 0; 1733 } 1734 1735 /** 1736 * called by network layer to process IOCTL call to network device 1737 * 1738 * dev pointer to network device structure 1739 * ifr pointer to network interface request structure 1740 * cmd IOCTL command code 1741 * 1742 * returns 0 if success, otherwise error code 1743 */ 1744 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1745 { 1746 const size_t size = sizeof(sync_serial_settings); 1747 sync_serial_settings new_line; 1748 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1749 SLMP_INFO *info = dev_to_port(dev); 1750 unsigned int flags; 1751 1752 if (debug_level >= DEBUG_LEVEL_INFO) 1753 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); 1754 1755 /* return error if TTY interface open */ 1756 if (info->port.count) 1757 return -EBUSY; 1758 1759 if (cmd != SIOCWANDEV) 1760 return hdlc_ioctl(dev, ifr, cmd); 1761 1762 switch(ifr->ifr_settings.type) { 1763 case IF_GET_IFACE: /* return current sync_serial_settings */ 1764 1765 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 1766 if (ifr->ifr_settings.size < size) { 1767 ifr->ifr_settings.size = size; /* data size wanted */ 1768 return -ENOBUFS; 1769 } 1770 1771 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1772 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1773 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1774 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1775 1776 memset(&new_line, 0, sizeof(new_line)); 1777 switch (flags){ 1778 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1779 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1780 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1781 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1782 default: new_line.clock_type = CLOCK_DEFAULT; 1783 } 1784 1785 new_line.clock_rate = info->params.clock_speed; 1786 new_line.loopback = info->params.loopback ? 1:0; 1787 1788 if (copy_to_user(line, &new_line, size)) 1789 return -EFAULT; 1790 return 0; 1791 1792 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 1793 1794 if(!capable(CAP_NET_ADMIN)) 1795 return -EPERM; 1796 if (copy_from_user(&new_line, line, size)) 1797 return -EFAULT; 1798 1799 switch (new_line.clock_type) 1800 { 1801 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 1802 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 1803 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 1804 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 1805 case CLOCK_DEFAULT: flags = info->params.flags & 1806 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1807 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1808 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1809 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 1810 default: return -EINVAL; 1811 } 1812 1813 if (new_line.loopback != 0 && new_line.loopback != 1) 1814 return -EINVAL; 1815 1816 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1817 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1818 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1819 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1820 info->params.flags |= flags; 1821 1822 info->params.loopback = new_line.loopback; 1823 1824 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 1825 info->params.clock_speed = new_line.clock_rate; 1826 else 1827 info->params.clock_speed = 0; 1828 1829 /* if network interface up, reprogram hardware */ 1830 if (info->netcount) 1831 program_hw(info); 1832 return 0; 1833 1834 default: 1835 return hdlc_ioctl(dev, ifr, cmd); 1836 } 1837 } 1838 1839 /** 1840 * called by network layer when transmit timeout is detected 1841 * 1842 * dev pointer to network device structure 1843 */ 1844 static void hdlcdev_tx_timeout(struct net_device *dev) 1845 { 1846 SLMP_INFO *info = dev_to_port(dev); 1847 unsigned long flags; 1848 1849 if (debug_level >= DEBUG_LEVEL_INFO) 1850 printk("hdlcdev_tx_timeout(%s)\n",dev->name); 1851 1852 dev->stats.tx_errors++; 1853 dev->stats.tx_aborted_errors++; 1854 1855 spin_lock_irqsave(&info->lock,flags); 1856 tx_stop(info); 1857 spin_unlock_irqrestore(&info->lock,flags); 1858 1859 netif_wake_queue(dev); 1860 } 1861 1862 /** 1863 * called by device driver when transmit completes 1864 * reenable network layer transmit if stopped 1865 * 1866 * info pointer to device instance information 1867 */ 1868 static void hdlcdev_tx_done(SLMP_INFO *info) 1869 { 1870 if (netif_queue_stopped(info->netdev)) 1871 netif_wake_queue(info->netdev); 1872 } 1873 1874 /** 1875 * called by device driver when frame received 1876 * pass frame to network layer 1877 * 1878 * info pointer to device instance information 1879 * buf pointer to buffer contianing frame data 1880 * size count of data bytes in buf 1881 */ 1882 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size) 1883 { 1884 struct sk_buff *skb = dev_alloc_skb(size); 1885 struct net_device *dev = info->netdev; 1886 1887 if (debug_level >= DEBUG_LEVEL_INFO) 1888 printk("hdlcdev_rx(%s)\n",dev->name); 1889 1890 if (skb == NULL) { 1891 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", 1892 dev->name); 1893 dev->stats.rx_dropped++; 1894 return; 1895 } 1896 1897 memcpy(skb_put(skb, size), buf, size); 1898 1899 skb->protocol = hdlc_type_trans(skb, dev); 1900 1901 dev->stats.rx_packets++; 1902 dev->stats.rx_bytes += size; 1903 1904 netif_rx(skb); 1905 } 1906 1907 static const struct net_device_ops hdlcdev_ops = { 1908 .ndo_open = hdlcdev_open, 1909 .ndo_stop = hdlcdev_close, 1910 .ndo_change_mtu = hdlc_change_mtu, 1911 .ndo_start_xmit = hdlc_start_xmit, 1912 .ndo_do_ioctl = hdlcdev_ioctl, 1913 .ndo_tx_timeout = hdlcdev_tx_timeout, 1914 }; 1915 1916 /** 1917 * called by device driver when adding device instance 1918 * do generic HDLC initialization 1919 * 1920 * info pointer to device instance information 1921 * 1922 * returns 0 if success, otherwise error code 1923 */ 1924 static int hdlcdev_init(SLMP_INFO *info) 1925 { 1926 int rc; 1927 struct net_device *dev; 1928 hdlc_device *hdlc; 1929 1930 /* allocate and initialize network and HDLC layer objects */ 1931 1932 dev = alloc_hdlcdev(info); 1933 if (!dev) { 1934 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); 1935 return -ENOMEM; 1936 } 1937 1938 /* for network layer reporting purposes only */ 1939 dev->mem_start = info->phys_sca_base; 1940 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1; 1941 dev->irq = info->irq_level; 1942 1943 /* network layer callbacks and settings */ 1944 dev->netdev_ops = &hdlcdev_ops; 1945 dev->watchdog_timeo = 10 * HZ; 1946 dev->tx_queue_len = 50; 1947 1948 /* generic HDLC layer callbacks and settings */ 1949 hdlc = dev_to_hdlc(dev); 1950 hdlc->attach = hdlcdev_attach; 1951 hdlc->xmit = hdlcdev_xmit; 1952 1953 /* register objects with HDLC layer */ 1954 rc = register_hdlc_device(dev); 1955 if (rc) { 1956 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 1957 free_netdev(dev); 1958 return rc; 1959 } 1960 1961 info->netdev = dev; 1962 return 0; 1963 } 1964 1965 /** 1966 * called by device driver when removing device instance 1967 * do generic HDLC cleanup 1968 * 1969 * info pointer to device instance information 1970 */ 1971 static void hdlcdev_exit(SLMP_INFO *info) 1972 { 1973 unregister_hdlc_device(info->netdev); 1974 free_netdev(info->netdev); 1975 info->netdev = NULL; 1976 } 1977 1978 #endif /* CONFIG_HDLC */ 1979 1980 1981 /* Return next bottom half action to perform. 1982 * Return Value: BH action code or 0 if nothing to do. 1983 */ 1984 static int bh_action(SLMP_INFO *info) 1985 { 1986 unsigned long flags; 1987 int rc = 0; 1988 1989 spin_lock_irqsave(&info->lock,flags); 1990 1991 if (info->pending_bh & BH_RECEIVE) { 1992 info->pending_bh &= ~BH_RECEIVE; 1993 rc = BH_RECEIVE; 1994 } else if (info->pending_bh & BH_TRANSMIT) { 1995 info->pending_bh &= ~BH_TRANSMIT; 1996 rc = BH_TRANSMIT; 1997 } else if (info->pending_bh & BH_STATUS) { 1998 info->pending_bh &= ~BH_STATUS; 1999 rc = BH_STATUS; 2000 } 2001 2002 if (!rc) { 2003 /* Mark BH routine as complete */ 2004 info->bh_running = false; 2005 info->bh_requested = false; 2006 } 2007 2008 spin_unlock_irqrestore(&info->lock,flags); 2009 2010 return rc; 2011 } 2012 2013 /* Perform bottom half processing of work items queued by ISR. 2014 */ 2015 static void bh_handler(struct work_struct *work) 2016 { 2017 SLMP_INFO *info = container_of(work, SLMP_INFO, task); 2018 int action; 2019 2020 if ( debug_level >= DEBUG_LEVEL_BH ) 2021 printk( "%s(%d):%s bh_handler() entry\n", 2022 __FILE__,__LINE__,info->device_name); 2023 2024 info->bh_running = true; 2025 2026 while((action = bh_action(info)) != 0) { 2027 2028 /* Process work item */ 2029 if ( debug_level >= DEBUG_LEVEL_BH ) 2030 printk( "%s(%d):%s bh_handler() work item action=%d\n", 2031 __FILE__,__LINE__,info->device_name, action); 2032 2033 switch (action) { 2034 2035 case BH_RECEIVE: 2036 bh_receive(info); 2037 break; 2038 case BH_TRANSMIT: 2039 bh_transmit(info); 2040 break; 2041 case BH_STATUS: 2042 bh_status(info); 2043 break; 2044 default: 2045 /* unknown work item ID */ 2046 printk("%s(%d):%s Unknown work item ID=%08X!\n", 2047 __FILE__,__LINE__,info->device_name,action); 2048 break; 2049 } 2050 } 2051 2052 if ( debug_level >= DEBUG_LEVEL_BH ) 2053 printk( "%s(%d):%s bh_handler() exit\n", 2054 __FILE__,__LINE__,info->device_name); 2055 } 2056 2057 static void bh_receive(SLMP_INFO *info) 2058 { 2059 if ( debug_level >= DEBUG_LEVEL_BH ) 2060 printk( "%s(%d):%s bh_receive()\n", 2061 __FILE__,__LINE__,info->device_name); 2062 2063 while( rx_get_frame(info) ); 2064 } 2065 2066 static void bh_transmit(SLMP_INFO *info) 2067 { 2068 struct tty_struct *tty = info->port.tty; 2069 2070 if ( debug_level >= DEBUG_LEVEL_BH ) 2071 printk( "%s(%d):%s bh_transmit() entry\n", 2072 __FILE__,__LINE__,info->device_name); 2073 2074 if (tty) 2075 tty_wakeup(tty); 2076 } 2077 2078 static void bh_status(SLMP_INFO *info) 2079 { 2080 if ( debug_level >= DEBUG_LEVEL_BH ) 2081 printk( "%s(%d):%s bh_status() entry\n", 2082 __FILE__,__LINE__,info->device_name); 2083 2084 info->ri_chkcount = 0; 2085 info->dsr_chkcount = 0; 2086 info->dcd_chkcount = 0; 2087 info->cts_chkcount = 0; 2088 } 2089 2090 static void isr_timer(SLMP_INFO * info) 2091 { 2092 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; 2093 2094 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */ 2095 write_reg(info, IER2, 0); 2096 2097 /* TMCS, Timer Control/Status Register 2098 * 2099 * 07 CMF, Compare match flag (read only) 1=match 2100 * 06 ECMI, CMF Interrupt Enable: 0=disabled 2101 * 05 Reserved, must be 0 2102 * 04 TME, Timer Enable 2103 * 03..00 Reserved, must be 0 2104 * 2105 * 0000 0000 2106 */ 2107 write_reg(info, (unsigned char)(timer + TMCS), 0); 2108 2109 info->irq_occurred = true; 2110 2111 if ( debug_level >= DEBUG_LEVEL_ISR ) 2112 printk("%s(%d):%s isr_timer()\n", 2113 __FILE__,__LINE__,info->device_name); 2114 } 2115 2116 static void isr_rxint(SLMP_INFO * info) 2117 { 2118 struct tty_struct *tty = info->port.tty; 2119 struct mgsl_icount *icount = &info->icount; 2120 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD); 2121 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN; 2122 2123 /* clear status bits */ 2124 if (status) 2125 write_reg(info, SR1, status); 2126 2127 if (status2) 2128 write_reg(info, SR2, status2); 2129 2130 if ( debug_level >= DEBUG_LEVEL_ISR ) 2131 printk("%s(%d):%s isr_rxint status=%02X %02x\n", 2132 __FILE__,__LINE__,info->device_name,status,status2); 2133 2134 if (info->params.mode == MGSL_MODE_ASYNC) { 2135 if (status & BRKD) { 2136 icount->brk++; 2137 2138 /* process break detection if tty control 2139 * is not set to ignore it 2140 */ 2141 if (!(status & info->ignore_status_mask1)) { 2142 if (info->read_status_mask1 & BRKD) { 2143 tty_insert_flip_char(&info->port, 0, TTY_BREAK); 2144 if (tty && (info->port.flags & ASYNC_SAK)) 2145 do_SAK(tty); 2146 } 2147 } 2148 } 2149 } 2150 else { 2151 if (status & (FLGD|IDLD)) { 2152 if (status & FLGD) 2153 info->icount.exithunt++; 2154 else if (status & IDLD) 2155 info->icount.rxidle++; 2156 wake_up_interruptible(&info->event_wait_q); 2157 } 2158 } 2159 2160 if (status & CDCD) { 2161 /* simulate a common modem status change interrupt 2162 * for our handler 2163 */ 2164 get_signals( info ); 2165 isr_io_pin(info, 2166 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD)); 2167 } 2168 } 2169 2170 /* 2171 * handle async rx data interrupts 2172 */ 2173 static void isr_rxrdy(SLMP_INFO * info) 2174 { 2175 u16 status; 2176 unsigned char DataByte; 2177 struct mgsl_icount *icount = &info->icount; 2178 2179 if ( debug_level >= DEBUG_LEVEL_ISR ) 2180 printk("%s(%d):%s isr_rxrdy\n", 2181 __FILE__,__LINE__,info->device_name); 2182 2183 while((status = read_reg(info,CST0)) & BIT0) 2184 { 2185 int flag = 0; 2186 bool over = false; 2187 DataByte = read_reg(info,TRB); 2188 2189 icount->rx++; 2190 2191 if ( status & (PE + FRME + OVRN) ) { 2192 printk("%s(%d):%s rxerr=%04X\n", 2193 __FILE__,__LINE__,info->device_name,status); 2194 2195 /* update error statistics */ 2196 if (status & PE) 2197 icount->parity++; 2198 else if (status & FRME) 2199 icount->frame++; 2200 else if (status & OVRN) 2201 icount->overrun++; 2202 2203 /* discard char if tty control flags say so */ 2204 if (status & info->ignore_status_mask2) 2205 continue; 2206 2207 status &= info->read_status_mask2; 2208 2209 if (status & PE) 2210 flag = TTY_PARITY; 2211 else if (status & FRME) 2212 flag = TTY_FRAME; 2213 if (status & OVRN) { 2214 /* Overrun is special, since it's 2215 * reported immediately, and doesn't 2216 * affect the current character 2217 */ 2218 over = true; 2219 } 2220 } /* end of if (error) */ 2221 2222 tty_insert_flip_char(&info->port, DataByte, flag); 2223 if (over) 2224 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN); 2225 } 2226 2227 if ( debug_level >= DEBUG_LEVEL_ISR ) { 2228 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n", 2229 __FILE__,__LINE__,info->device_name, 2230 icount->rx,icount->brk,icount->parity, 2231 icount->frame,icount->overrun); 2232 } 2233 2234 tty_flip_buffer_push(&info->port); 2235 } 2236 2237 static void isr_txeom(SLMP_INFO * info, unsigned char status) 2238 { 2239 if ( debug_level >= DEBUG_LEVEL_ISR ) 2240 printk("%s(%d):%s isr_txeom status=%02x\n", 2241 __FILE__,__LINE__,info->device_name,status); 2242 2243 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ 2244 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ 2245 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 2246 2247 if (status & UDRN) { 2248 write_reg(info, CMD, TXRESET); 2249 write_reg(info, CMD, TXENABLE); 2250 } else 2251 write_reg(info, CMD, TXBUFCLR); 2252 2253 /* disable and clear tx interrupts */ 2254 info->ie0_value &= ~TXRDYE; 2255 info->ie1_value &= ~(IDLE + UDRN); 2256 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); 2257 write_reg(info, SR1, (unsigned char)(UDRN + IDLE)); 2258 2259 if ( info->tx_active ) { 2260 if (info->params.mode != MGSL_MODE_ASYNC) { 2261 if (status & UDRN) 2262 info->icount.txunder++; 2263 else if (status & IDLE) 2264 info->icount.txok++; 2265 } 2266 2267 info->tx_active = false; 2268 info->tx_count = info->tx_put = info->tx_get = 0; 2269 2270 del_timer(&info->tx_timer); 2271 2272 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) { 2273 info->serial_signals &= ~SerialSignal_RTS; 2274 info->drop_rts_on_tx_done = false; 2275 set_signals(info); 2276 } 2277 2278 #if SYNCLINK_GENERIC_HDLC 2279 if (info->netcount) 2280 hdlcdev_tx_done(info); 2281 else 2282 #endif 2283 { 2284 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2285 tx_stop(info); 2286 return; 2287 } 2288 info->pending_bh |= BH_TRANSMIT; 2289 } 2290 } 2291 } 2292 2293 2294 /* 2295 * handle tx status interrupts 2296 */ 2297 static void isr_txint(SLMP_INFO * info) 2298 { 2299 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS); 2300 2301 /* clear status bits */ 2302 write_reg(info, SR1, status); 2303 2304 if ( debug_level >= DEBUG_LEVEL_ISR ) 2305 printk("%s(%d):%s isr_txint status=%02x\n", 2306 __FILE__,__LINE__,info->device_name,status); 2307 2308 if (status & (UDRN + IDLE)) 2309 isr_txeom(info, status); 2310 2311 if (status & CCTS) { 2312 /* simulate a common modem status change interrupt 2313 * for our handler 2314 */ 2315 get_signals( info ); 2316 isr_io_pin(info, 2317 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS)); 2318 2319 } 2320 } 2321 2322 /* 2323 * handle async tx data interrupts 2324 */ 2325 static void isr_txrdy(SLMP_INFO * info) 2326 { 2327 if ( debug_level >= DEBUG_LEVEL_ISR ) 2328 printk("%s(%d):%s isr_txrdy() tx_count=%d\n", 2329 __FILE__,__LINE__,info->device_name,info->tx_count); 2330 2331 if (info->params.mode != MGSL_MODE_ASYNC) { 2332 /* disable TXRDY IRQ, enable IDLE IRQ */ 2333 info->ie0_value &= ~TXRDYE; 2334 info->ie1_value |= IDLE; 2335 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); 2336 return; 2337 } 2338 2339 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2340 tx_stop(info); 2341 return; 2342 } 2343 2344 if ( info->tx_count ) 2345 tx_load_fifo( info ); 2346 else { 2347 info->tx_active = false; 2348 info->ie0_value &= ~TXRDYE; 2349 write_reg(info, IE0, info->ie0_value); 2350 } 2351 2352 if (info->tx_count < WAKEUP_CHARS) 2353 info->pending_bh |= BH_TRANSMIT; 2354 } 2355 2356 static void isr_rxdmaok(SLMP_INFO * info) 2357 { 2358 /* BIT7 = EOT (end of transfer) 2359 * BIT6 = EOM (end of message/frame) 2360 */ 2361 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0; 2362 2363 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2364 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); 2365 2366 if ( debug_level >= DEBUG_LEVEL_ISR ) 2367 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n", 2368 __FILE__,__LINE__,info->device_name,status); 2369 2370 info->pending_bh |= BH_RECEIVE; 2371 } 2372 2373 static void isr_rxdmaerror(SLMP_INFO * info) 2374 { 2375 /* BIT5 = BOF (buffer overflow) 2376 * BIT4 = COF (counter overflow) 2377 */ 2378 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30; 2379 2380 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2381 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); 2382 2383 if ( debug_level >= DEBUG_LEVEL_ISR ) 2384 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n", 2385 __FILE__,__LINE__,info->device_name,status); 2386 2387 info->rx_overflow = true; 2388 info->pending_bh |= BH_RECEIVE; 2389 } 2390 2391 static void isr_txdmaok(SLMP_INFO * info) 2392 { 2393 unsigned char status_reg1 = read_reg(info, SR1); 2394 2395 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ 2396 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ 2397 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 2398 2399 if ( debug_level >= DEBUG_LEVEL_ISR ) 2400 printk("%s(%d):%s isr_txdmaok(), status=%02x\n", 2401 __FILE__,__LINE__,info->device_name,status_reg1); 2402 2403 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */ 2404 write_reg16(info, TRC0, 0); 2405 info->ie0_value |= TXRDYE; 2406 write_reg(info, IE0, info->ie0_value); 2407 } 2408 2409 static void isr_txdmaerror(SLMP_INFO * info) 2410 { 2411 /* BIT5 = BOF (buffer overflow) 2412 * BIT4 = COF (counter overflow) 2413 */ 2414 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30; 2415 2416 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2417 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); 2418 2419 if ( debug_level >= DEBUG_LEVEL_ISR ) 2420 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n", 2421 __FILE__,__LINE__,info->device_name,status); 2422 } 2423 2424 /* handle input serial signal changes 2425 */ 2426 static void isr_io_pin( SLMP_INFO *info, u16 status ) 2427 { 2428 struct mgsl_icount *icount; 2429 2430 if ( debug_level >= DEBUG_LEVEL_ISR ) 2431 printk("%s(%d):isr_io_pin status=%04X\n", 2432 __FILE__,__LINE__,status); 2433 2434 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED | 2435 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) { 2436 icount = &info->icount; 2437 /* update input line counters */ 2438 if (status & MISCSTATUS_RI_LATCHED) { 2439 icount->rng++; 2440 if ( status & SerialSignal_RI ) 2441 info->input_signal_events.ri_up++; 2442 else 2443 info->input_signal_events.ri_down++; 2444 } 2445 if (status & MISCSTATUS_DSR_LATCHED) { 2446 icount->dsr++; 2447 if ( status & SerialSignal_DSR ) 2448 info->input_signal_events.dsr_up++; 2449 else 2450 info->input_signal_events.dsr_down++; 2451 } 2452 if (status & MISCSTATUS_DCD_LATCHED) { 2453 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { 2454 info->ie1_value &= ~CDCD; 2455 write_reg(info, IE1, info->ie1_value); 2456 } 2457 icount->dcd++; 2458 if (status & SerialSignal_DCD) { 2459 info->input_signal_events.dcd_up++; 2460 } else 2461 info->input_signal_events.dcd_down++; 2462 #if SYNCLINK_GENERIC_HDLC 2463 if (info->netcount) { 2464 if (status & SerialSignal_DCD) 2465 netif_carrier_on(info->netdev); 2466 else 2467 netif_carrier_off(info->netdev); 2468 } 2469 #endif 2470 } 2471 if (status & MISCSTATUS_CTS_LATCHED) 2472 { 2473 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { 2474 info->ie1_value &= ~CCTS; 2475 write_reg(info, IE1, info->ie1_value); 2476 } 2477 icount->cts++; 2478 if ( status & SerialSignal_CTS ) 2479 info->input_signal_events.cts_up++; 2480 else 2481 info->input_signal_events.cts_down++; 2482 } 2483 wake_up_interruptible(&info->status_event_wait_q); 2484 wake_up_interruptible(&info->event_wait_q); 2485 2486 if ( (info->port.flags & ASYNC_CHECK_CD) && 2487 (status & MISCSTATUS_DCD_LATCHED) ) { 2488 if ( debug_level >= DEBUG_LEVEL_ISR ) 2489 printk("%s CD now %s...", info->device_name, 2490 (status & SerialSignal_DCD) ? "on" : "off"); 2491 if (status & SerialSignal_DCD) 2492 wake_up_interruptible(&info->port.open_wait); 2493 else { 2494 if ( debug_level >= DEBUG_LEVEL_ISR ) 2495 printk("doing serial hangup..."); 2496 if (info->port.tty) 2497 tty_hangup(info->port.tty); 2498 } 2499 } 2500 2501 if (tty_port_cts_enabled(&info->port) && 2502 (status & MISCSTATUS_CTS_LATCHED) ) { 2503 if ( info->port.tty ) { 2504 if (info->port.tty->hw_stopped) { 2505 if (status & SerialSignal_CTS) { 2506 if ( debug_level >= DEBUG_LEVEL_ISR ) 2507 printk("CTS tx start..."); 2508 info->port.tty->hw_stopped = 0; 2509 tx_start(info); 2510 info->pending_bh |= BH_TRANSMIT; 2511 return; 2512 } 2513 } else { 2514 if (!(status & SerialSignal_CTS)) { 2515 if ( debug_level >= DEBUG_LEVEL_ISR ) 2516 printk("CTS tx stop..."); 2517 info->port.tty->hw_stopped = 1; 2518 tx_stop(info); 2519 } 2520 } 2521 } 2522 } 2523 } 2524 2525 info->pending_bh |= BH_STATUS; 2526 } 2527 2528 /* Interrupt service routine entry point. 2529 * 2530 * Arguments: 2531 * irq interrupt number that caused interrupt 2532 * dev_id device ID supplied during interrupt registration 2533 * regs interrupted processor context 2534 */ 2535 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id) 2536 { 2537 SLMP_INFO *info = dev_id; 2538 unsigned char status, status0, status1=0; 2539 unsigned char dmastatus, dmastatus0, dmastatus1=0; 2540 unsigned char timerstatus0, timerstatus1=0; 2541 unsigned char shift; 2542 unsigned int i; 2543 unsigned short tmp; 2544 2545 if ( debug_level >= DEBUG_LEVEL_ISR ) 2546 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n", 2547 __FILE__, __LINE__, info->irq_level); 2548 2549 spin_lock(&info->lock); 2550 2551 for(;;) { 2552 2553 /* get status for SCA0 (ports 0-1) */ 2554 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */ 2555 status0 = (unsigned char)tmp; 2556 dmastatus0 = (unsigned char)(tmp>>8); 2557 timerstatus0 = read_reg(info, ISR2); 2558 2559 if ( debug_level >= DEBUG_LEVEL_ISR ) 2560 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n", 2561 __FILE__, __LINE__, info->device_name, 2562 status0, dmastatus0, timerstatus0); 2563 2564 if (info->port_count == 4) { 2565 /* get status for SCA1 (ports 2-3) */ 2566 tmp = read_reg16(info->port_array[2], ISR0); 2567 status1 = (unsigned char)tmp; 2568 dmastatus1 = (unsigned char)(tmp>>8); 2569 timerstatus1 = read_reg(info->port_array[2], ISR2); 2570 2571 if ( debug_level >= DEBUG_LEVEL_ISR ) 2572 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n", 2573 __FILE__,__LINE__,info->device_name, 2574 status1,dmastatus1,timerstatus1); 2575 } 2576 2577 if (!status0 && !dmastatus0 && !timerstatus0 && 2578 !status1 && !dmastatus1 && !timerstatus1) 2579 break; 2580 2581 for(i=0; i < info->port_count ; i++) { 2582 if (info->port_array[i] == NULL) 2583 continue; 2584 if (i < 2) { 2585 status = status0; 2586 dmastatus = dmastatus0; 2587 } else { 2588 status = status1; 2589 dmastatus = dmastatus1; 2590 } 2591 2592 shift = i & 1 ? 4 :0; 2593 2594 if (status & BIT0 << shift) 2595 isr_rxrdy(info->port_array[i]); 2596 if (status & BIT1 << shift) 2597 isr_txrdy(info->port_array[i]); 2598 if (status & BIT2 << shift) 2599 isr_rxint(info->port_array[i]); 2600 if (status & BIT3 << shift) 2601 isr_txint(info->port_array[i]); 2602 2603 if (dmastatus & BIT0 << shift) 2604 isr_rxdmaerror(info->port_array[i]); 2605 if (dmastatus & BIT1 << shift) 2606 isr_rxdmaok(info->port_array[i]); 2607 if (dmastatus & BIT2 << shift) 2608 isr_txdmaerror(info->port_array[i]); 2609 if (dmastatus & BIT3 << shift) 2610 isr_txdmaok(info->port_array[i]); 2611 } 2612 2613 if (timerstatus0 & (BIT5 | BIT4)) 2614 isr_timer(info->port_array[0]); 2615 if (timerstatus0 & (BIT7 | BIT6)) 2616 isr_timer(info->port_array[1]); 2617 if (timerstatus1 & (BIT5 | BIT4)) 2618 isr_timer(info->port_array[2]); 2619 if (timerstatus1 & (BIT7 | BIT6)) 2620 isr_timer(info->port_array[3]); 2621 } 2622 2623 for(i=0; i < info->port_count ; i++) { 2624 SLMP_INFO * port = info->port_array[i]; 2625 2626 /* Request bottom half processing if there's something 2627 * for it to do and the bh is not already running. 2628 * 2629 * Note: startup adapter diags require interrupts. 2630 * do not request bottom half processing if the 2631 * device is not open in a normal mode. 2632 */ 2633 if ( port && (port->port.count || port->netcount) && 2634 port->pending_bh && !port->bh_running && 2635 !port->bh_requested ) { 2636 if ( debug_level >= DEBUG_LEVEL_ISR ) 2637 printk("%s(%d):%s queueing bh task.\n", 2638 __FILE__,__LINE__,port->device_name); 2639 schedule_work(&port->task); 2640 port->bh_requested = true; 2641 } 2642 } 2643 2644 spin_unlock(&info->lock); 2645 2646 if ( debug_level >= DEBUG_LEVEL_ISR ) 2647 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n", 2648 __FILE__, __LINE__, info->irq_level); 2649 return IRQ_HANDLED; 2650 } 2651 2652 /* Initialize and start device. 2653 */ 2654 static int startup(SLMP_INFO * info) 2655 { 2656 if ( debug_level >= DEBUG_LEVEL_INFO ) 2657 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name); 2658 2659 if (info->port.flags & ASYNC_INITIALIZED) 2660 return 0; 2661 2662 if (!info->tx_buf) { 2663 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 2664 if (!info->tx_buf) { 2665 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", 2666 __FILE__,__LINE__,info->device_name); 2667 return -ENOMEM; 2668 } 2669 } 2670 2671 info->pending_bh = 0; 2672 2673 memset(&info->icount, 0, sizeof(info->icount)); 2674 2675 /* program hardware for current parameters */ 2676 reset_port(info); 2677 2678 change_params(info); 2679 2680 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); 2681 2682 if (info->port.tty) 2683 clear_bit(TTY_IO_ERROR, &info->port.tty->flags); 2684 2685 info->port.flags |= ASYNC_INITIALIZED; 2686 2687 return 0; 2688 } 2689 2690 /* Called by close() and hangup() to shutdown hardware 2691 */ 2692 static void shutdown(SLMP_INFO * info) 2693 { 2694 unsigned long flags; 2695 2696 if (!(info->port.flags & ASYNC_INITIALIZED)) 2697 return; 2698 2699 if (debug_level >= DEBUG_LEVEL_INFO) 2700 printk("%s(%d):%s synclinkmp_shutdown()\n", 2701 __FILE__,__LINE__, info->device_name ); 2702 2703 /* clear status wait queue because status changes */ 2704 /* can't happen after shutting down the hardware */ 2705 wake_up_interruptible(&info->status_event_wait_q); 2706 wake_up_interruptible(&info->event_wait_q); 2707 2708 del_timer(&info->tx_timer); 2709 del_timer(&info->status_timer); 2710 2711 kfree(info->tx_buf); 2712 info->tx_buf = NULL; 2713 2714 spin_lock_irqsave(&info->lock,flags); 2715 2716 reset_port(info); 2717 2718 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { 2719 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2720 set_signals(info); 2721 } 2722 2723 spin_unlock_irqrestore(&info->lock,flags); 2724 2725 if (info->port.tty) 2726 set_bit(TTY_IO_ERROR, &info->port.tty->flags); 2727 2728 info->port.flags &= ~ASYNC_INITIALIZED; 2729 } 2730 2731 static void program_hw(SLMP_INFO *info) 2732 { 2733 unsigned long flags; 2734 2735 spin_lock_irqsave(&info->lock,flags); 2736 2737 rx_stop(info); 2738 tx_stop(info); 2739 2740 info->tx_count = info->tx_put = info->tx_get = 0; 2741 2742 if (info->params.mode == MGSL_MODE_HDLC || info->netcount) 2743 hdlc_mode(info); 2744 else 2745 async_mode(info); 2746 2747 set_signals(info); 2748 2749 info->dcd_chkcount = 0; 2750 info->cts_chkcount = 0; 2751 info->ri_chkcount = 0; 2752 info->dsr_chkcount = 0; 2753 2754 info->ie1_value |= (CDCD|CCTS); 2755 write_reg(info, IE1, info->ie1_value); 2756 2757 get_signals(info); 2758 2759 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) ) 2760 rx_start(info); 2761 2762 spin_unlock_irqrestore(&info->lock,flags); 2763 } 2764 2765 /* Reconfigure adapter based on new parameters 2766 */ 2767 static void change_params(SLMP_INFO *info) 2768 { 2769 unsigned cflag; 2770 int bits_per_char; 2771 2772 if (!info->port.tty) 2773 return; 2774 2775 if (debug_level >= DEBUG_LEVEL_INFO) 2776 printk("%s(%d):%s change_params()\n", 2777 __FILE__,__LINE__, info->device_name ); 2778 2779 cflag = info->port.tty->termios.c_cflag; 2780 2781 /* if B0 rate (hangup) specified then negate RTS and DTR */ 2782 /* otherwise assert RTS and DTR */ 2783 if (cflag & CBAUD) 2784 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; 2785 else 2786 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2787 2788 /* byte size and parity */ 2789 2790 switch (cflag & CSIZE) { 2791 case CS5: info->params.data_bits = 5; break; 2792 case CS6: info->params.data_bits = 6; break; 2793 case CS7: info->params.data_bits = 7; break; 2794 case CS8: info->params.data_bits = 8; break; 2795 /* Never happens, but GCC is too dumb to figure it out */ 2796 default: info->params.data_bits = 7; break; 2797 } 2798 2799 if (cflag & CSTOPB) 2800 info->params.stop_bits = 2; 2801 else 2802 info->params.stop_bits = 1; 2803 2804 info->params.parity = ASYNC_PARITY_NONE; 2805 if (cflag & PARENB) { 2806 if (cflag & PARODD) 2807 info->params.parity = ASYNC_PARITY_ODD; 2808 else 2809 info->params.parity = ASYNC_PARITY_EVEN; 2810 #ifdef CMSPAR 2811 if (cflag & CMSPAR) 2812 info->params.parity = ASYNC_PARITY_SPACE; 2813 #endif 2814 } 2815 2816 /* calculate number of jiffies to transmit a full 2817 * FIFO (32 bytes) at specified data rate 2818 */ 2819 bits_per_char = info->params.data_bits + 2820 info->params.stop_bits + 1; 2821 2822 /* if port data rate is set to 460800 or less then 2823 * allow tty settings to override, otherwise keep the 2824 * current data rate. 2825 */ 2826 if (info->params.data_rate <= 460800) { 2827 info->params.data_rate = tty_get_baud_rate(info->port.tty); 2828 } 2829 2830 if ( info->params.data_rate ) { 2831 info->timeout = (32*HZ*bits_per_char) / 2832 info->params.data_rate; 2833 } 2834 info->timeout += HZ/50; /* Add .02 seconds of slop */ 2835 2836 if (cflag & CRTSCTS) 2837 info->port.flags |= ASYNC_CTS_FLOW; 2838 else 2839 info->port.flags &= ~ASYNC_CTS_FLOW; 2840 2841 if (cflag & CLOCAL) 2842 info->port.flags &= ~ASYNC_CHECK_CD; 2843 else 2844 info->port.flags |= ASYNC_CHECK_CD; 2845 2846 /* process tty input control flags */ 2847 2848 info->read_status_mask2 = OVRN; 2849 if (I_INPCK(info->port.tty)) 2850 info->read_status_mask2 |= PE | FRME; 2851 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) 2852 info->read_status_mask1 |= BRKD; 2853 if (I_IGNPAR(info->port.tty)) 2854 info->ignore_status_mask2 |= PE | FRME; 2855 if (I_IGNBRK(info->port.tty)) { 2856 info->ignore_status_mask1 |= BRKD; 2857 /* If ignoring parity and break indicators, ignore 2858 * overruns too. (For real raw support). 2859 */ 2860 if (I_IGNPAR(info->port.tty)) 2861 info->ignore_status_mask2 |= OVRN; 2862 } 2863 2864 program_hw(info); 2865 } 2866 2867 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount) 2868 { 2869 int err; 2870 2871 if (debug_level >= DEBUG_LEVEL_INFO) 2872 printk("%s(%d):%s get_params()\n", 2873 __FILE__,__LINE__, info->device_name); 2874 2875 if (!user_icount) { 2876 memset(&info->icount, 0, sizeof(info->icount)); 2877 } else { 2878 mutex_lock(&info->port.mutex); 2879 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); 2880 mutex_unlock(&info->port.mutex); 2881 if (err) 2882 return -EFAULT; 2883 } 2884 2885 return 0; 2886 } 2887 2888 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params) 2889 { 2890 int err; 2891 if (debug_level >= DEBUG_LEVEL_INFO) 2892 printk("%s(%d):%s get_params()\n", 2893 __FILE__,__LINE__, info->device_name); 2894 2895 mutex_lock(&info->port.mutex); 2896 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); 2897 mutex_unlock(&info->port.mutex); 2898 if (err) { 2899 if ( debug_level >= DEBUG_LEVEL_INFO ) 2900 printk( "%s(%d):%s get_params() user buffer copy failed\n", 2901 __FILE__,__LINE__,info->device_name); 2902 return -EFAULT; 2903 } 2904 2905 return 0; 2906 } 2907 2908 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params) 2909 { 2910 unsigned long flags; 2911 MGSL_PARAMS tmp_params; 2912 int err; 2913 2914 if (debug_level >= DEBUG_LEVEL_INFO) 2915 printk("%s(%d):%s set_params\n", 2916 __FILE__,__LINE__,info->device_name ); 2917 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); 2918 if (err) { 2919 if ( debug_level >= DEBUG_LEVEL_INFO ) 2920 printk( "%s(%d):%s set_params() user buffer copy failed\n", 2921 __FILE__,__LINE__,info->device_name); 2922 return -EFAULT; 2923 } 2924 2925 mutex_lock(&info->port.mutex); 2926 spin_lock_irqsave(&info->lock,flags); 2927 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); 2928 spin_unlock_irqrestore(&info->lock,flags); 2929 2930 change_params(info); 2931 mutex_unlock(&info->port.mutex); 2932 2933 return 0; 2934 } 2935 2936 static int get_txidle(SLMP_INFO * info, int __user *idle_mode) 2937 { 2938 int err; 2939 2940 if (debug_level >= DEBUG_LEVEL_INFO) 2941 printk("%s(%d):%s get_txidle()=%d\n", 2942 __FILE__,__LINE__, info->device_name, info->idle_mode); 2943 2944 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); 2945 if (err) { 2946 if ( debug_level >= DEBUG_LEVEL_INFO ) 2947 printk( "%s(%d):%s get_txidle() user buffer copy failed\n", 2948 __FILE__,__LINE__,info->device_name); 2949 return -EFAULT; 2950 } 2951 2952 return 0; 2953 } 2954 2955 static int set_txidle(SLMP_INFO * info, int idle_mode) 2956 { 2957 unsigned long flags; 2958 2959 if (debug_level >= DEBUG_LEVEL_INFO) 2960 printk("%s(%d):%s set_txidle(%d)\n", 2961 __FILE__,__LINE__,info->device_name, idle_mode ); 2962 2963 spin_lock_irqsave(&info->lock,flags); 2964 info->idle_mode = idle_mode; 2965 tx_set_idle( info ); 2966 spin_unlock_irqrestore(&info->lock,flags); 2967 return 0; 2968 } 2969 2970 static int tx_enable(SLMP_INFO * info, int enable) 2971 { 2972 unsigned long flags; 2973 2974 if (debug_level >= DEBUG_LEVEL_INFO) 2975 printk("%s(%d):%s tx_enable(%d)\n", 2976 __FILE__,__LINE__,info->device_name, enable); 2977 2978 spin_lock_irqsave(&info->lock,flags); 2979 if ( enable ) { 2980 if ( !info->tx_enabled ) { 2981 tx_start(info); 2982 } 2983 } else { 2984 if ( info->tx_enabled ) 2985 tx_stop(info); 2986 } 2987 spin_unlock_irqrestore(&info->lock,flags); 2988 return 0; 2989 } 2990 2991 /* abort send HDLC frame 2992 */ 2993 static int tx_abort(SLMP_INFO * info) 2994 { 2995 unsigned long flags; 2996 2997 if (debug_level >= DEBUG_LEVEL_INFO) 2998 printk("%s(%d):%s tx_abort()\n", 2999 __FILE__,__LINE__,info->device_name); 3000 3001 spin_lock_irqsave(&info->lock,flags); 3002 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) { 3003 info->ie1_value &= ~UDRN; 3004 info->ie1_value |= IDLE; 3005 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ 3006 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ 3007 3008 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 3009 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 3010 3011 write_reg(info, CMD, TXABORT); 3012 } 3013 spin_unlock_irqrestore(&info->lock,flags); 3014 return 0; 3015 } 3016 3017 static int rx_enable(SLMP_INFO * info, int enable) 3018 { 3019 unsigned long flags; 3020 3021 if (debug_level >= DEBUG_LEVEL_INFO) 3022 printk("%s(%d):%s rx_enable(%d)\n", 3023 __FILE__,__LINE__,info->device_name,enable); 3024 3025 spin_lock_irqsave(&info->lock,flags); 3026 if ( enable ) { 3027 if ( !info->rx_enabled ) 3028 rx_start(info); 3029 } else { 3030 if ( info->rx_enabled ) 3031 rx_stop(info); 3032 } 3033 spin_unlock_irqrestore(&info->lock,flags); 3034 return 0; 3035 } 3036 3037 /* wait for specified event to occur 3038 */ 3039 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr) 3040 { 3041 unsigned long flags; 3042 int s; 3043 int rc=0; 3044 struct mgsl_icount cprev, cnow; 3045 int events; 3046 int mask; 3047 struct _input_signal_events oldsigs, newsigs; 3048 DECLARE_WAITQUEUE(wait, current); 3049 3050 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); 3051 if (rc) { 3052 return -EFAULT; 3053 } 3054 3055 if (debug_level >= DEBUG_LEVEL_INFO) 3056 printk("%s(%d):%s wait_mgsl_event(%d)\n", 3057 __FILE__,__LINE__,info->device_name,mask); 3058 3059 spin_lock_irqsave(&info->lock,flags); 3060 3061 /* return immediately if state matches requested events */ 3062 get_signals(info); 3063 s = info->serial_signals; 3064 3065 events = mask & 3066 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 3067 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 3068 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 3069 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 3070 if (events) { 3071 spin_unlock_irqrestore(&info->lock,flags); 3072 goto exit; 3073 } 3074 3075 /* save current irq counts */ 3076 cprev = info->icount; 3077 oldsigs = info->input_signal_events; 3078 3079 /* enable hunt and idle irqs if needed */ 3080 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { 3081 unsigned char oldval = info->ie1_value; 3082 unsigned char newval = oldval + 3083 (mask & MgslEvent_ExitHuntMode ? FLGD:0) + 3084 (mask & MgslEvent_IdleReceived ? IDLD:0); 3085 if ( oldval != newval ) { 3086 info->ie1_value = newval; 3087 write_reg(info, IE1, info->ie1_value); 3088 } 3089 } 3090 3091 set_current_state(TASK_INTERRUPTIBLE); 3092 add_wait_queue(&info->event_wait_q, &wait); 3093 3094 spin_unlock_irqrestore(&info->lock,flags); 3095 3096 for(;;) { 3097 schedule(); 3098 if (signal_pending(current)) { 3099 rc = -ERESTARTSYS; 3100 break; 3101 } 3102 3103 /* get current irq counts */ 3104 spin_lock_irqsave(&info->lock,flags); 3105 cnow = info->icount; 3106 newsigs = info->input_signal_events; 3107 set_current_state(TASK_INTERRUPTIBLE); 3108 spin_unlock_irqrestore(&info->lock,flags); 3109 3110 /* if no change, wait aborted for some reason */ 3111 if (newsigs.dsr_up == oldsigs.dsr_up && 3112 newsigs.dsr_down == oldsigs.dsr_down && 3113 newsigs.dcd_up == oldsigs.dcd_up && 3114 newsigs.dcd_down == oldsigs.dcd_down && 3115 newsigs.cts_up == oldsigs.cts_up && 3116 newsigs.cts_down == oldsigs.cts_down && 3117 newsigs.ri_up == oldsigs.ri_up && 3118 newsigs.ri_down == oldsigs.ri_down && 3119 cnow.exithunt == cprev.exithunt && 3120 cnow.rxidle == cprev.rxidle) { 3121 rc = -EIO; 3122 break; 3123 } 3124 3125 events = mask & 3126 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 3127 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 3128 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 3129 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 3130 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 3131 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 3132 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 3133 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 3134 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 3135 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 3136 if (events) 3137 break; 3138 3139 cprev = cnow; 3140 oldsigs = newsigs; 3141 } 3142 3143 remove_wait_queue(&info->event_wait_q, &wait); 3144 set_current_state(TASK_RUNNING); 3145 3146 3147 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { 3148 spin_lock_irqsave(&info->lock,flags); 3149 if (!waitqueue_active(&info->event_wait_q)) { 3150 /* disable enable exit hunt mode/idle rcvd IRQs */ 3151 info->ie1_value &= ~(FLGD|IDLD); 3152 write_reg(info, IE1, info->ie1_value); 3153 } 3154 spin_unlock_irqrestore(&info->lock,flags); 3155 } 3156 exit: 3157 if ( rc == 0 ) 3158 PUT_USER(rc, events, mask_ptr); 3159 3160 return rc; 3161 } 3162 3163 static int modem_input_wait(SLMP_INFO *info,int arg) 3164 { 3165 unsigned long flags; 3166 int rc; 3167 struct mgsl_icount cprev, cnow; 3168 DECLARE_WAITQUEUE(wait, current); 3169 3170 /* save current irq counts */ 3171 spin_lock_irqsave(&info->lock,flags); 3172 cprev = info->icount; 3173 add_wait_queue(&info->status_event_wait_q, &wait); 3174 set_current_state(TASK_INTERRUPTIBLE); 3175 spin_unlock_irqrestore(&info->lock,flags); 3176 3177 for(;;) { 3178 schedule(); 3179 if (signal_pending(current)) { 3180 rc = -ERESTARTSYS; 3181 break; 3182 } 3183 3184 /* get new irq counts */ 3185 spin_lock_irqsave(&info->lock,flags); 3186 cnow = info->icount; 3187 set_current_state(TASK_INTERRUPTIBLE); 3188 spin_unlock_irqrestore(&info->lock,flags); 3189 3190 /* if no change, wait aborted for some reason */ 3191 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 3192 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 3193 rc = -EIO; 3194 break; 3195 } 3196 3197 /* check for change in caller specified modem input */ 3198 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 3199 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 3200 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 3201 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 3202 rc = 0; 3203 break; 3204 } 3205 3206 cprev = cnow; 3207 } 3208 remove_wait_queue(&info->status_event_wait_q, &wait); 3209 set_current_state(TASK_RUNNING); 3210 return rc; 3211 } 3212 3213 /* return the state of the serial control and status signals 3214 */ 3215 static int tiocmget(struct tty_struct *tty) 3216 { 3217 SLMP_INFO *info = tty->driver_data; 3218 unsigned int result; 3219 unsigned long flags; 3220 3221 spin_lock_irqsave(&info->lock,flags); 3222 get_signals(info); 3223 spin_unlock_irqrestore(&info->lock,flags); 3224 3225 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) | 3226 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) | 3227 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) | 3228 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) | 3229 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) | 3230 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0); 3231 3232 if (debug_level >= DEBUG_LEVEL_INFO) 3233 printk("%s(%d):%s tiocmget() value=%08X\n", 3234 __FILE__,__LINE__, info->device_name, result ); 3235 return result; 3236 } 3237 3238 /* set modem control signals (DTR/RTS) 3239 */ 3240 static int tiocmset(struct tty_struct *tty, 3241 unsigned int set, unsigned int clear) 3242 { 3243 SLMP_INFO *info = tty->driver_data; 3244 unsigned long flags; 3245 3246 if (debug_level >= DEBUG_LEVEL_INFO) 3247 printk("%s(%d):%s tiocmset(%x,%x)\n", 3248 __FILE__,__LINE__,info->device_name, set, clear); 3249 3250 if (set & TIOCM_RTS) 3251 info->serial_signals |= SerialSignal_RTS; 3252 if (set & TIOCM_DTR) 3253 info->serial_signals |= SerialSignal_DTR; 3254 if (clear & TIOCM_RTS) 3255 info->serial_signals &= ~SerialSignal_RTS; 3256 if (clear & TIOCM_DTR) 3257 info->serial_signals &= ~SerialSignal_DTR; 3258 3259 spin_lock_irqsave(&info->lock,flags); 3260 set_signals(info); 3261 spin_unlock_irqrestore(&info->lock,flags); 3262 3263 return 0; 3264 } 3265 3266 static int carrier_raised(struct tty_port *port) 3267 { 3268 SLMP_INFO *info = container_of(port, SLMP_INFO, port); 3269 unsigned long flags; 3270 3271 spin_lock_irqsave(&info->lock,flags); 3272 get_signals(info); 3273 spin_unlock_irqrestore(&info->lock,flags); 3274 3275 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0; 3276 } 3277 3278 static void dtr_rts(struct tty_port *port, int on) 3279 { 3280 SLMP_INFO *info = container_of(port, SLMP_INFO, port); 3281 unsigned long flags; 3282 3283 spin_lock_irqsave(&info->lock,flags); 3284 if (on) 3285 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; 3286 else 3287 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 3288 set_signals(info); 3289 spin_unlock_irqrestore(&info->lock,flags); 3290 } 3291 3292 /* Block the current process until the specified port is ready to open. 3293 */ 3294 static int block_til_ready(struct tty_struct *tty, struct file *filp, 3295 SLMP_INFO *info) 3296 { 3297 DECLARE_WAITQUEUE(wait, current); 3298 int retval; 3299 bool do_clocal = false; 3300 unsigned long flags; 3301 int cd; 3302 struct tty_port *port = &info->port; 3303 3304 if (debug_level >= DEBUG_LEVEL_INFO) 3305 printk("%s(%d):%s block_til_ready()\n", 3306 __FILE__,__LINE__, tty->driver->name ); 3307 3308 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ 3309 /* nonblock mode is set or port is not enabled */ 3310 /* just verify that callout device is not active */ 3311 port->flags |= ASYNC_NORMAL_ACTIVE; 3312 return 0; 3313 } 3314 3315 if (tty->termios.c_cflag & CLOCAL) 3316 do_clocal = true; 3317 3318 /* Wait for carrier detect and the line to become 3319 * free (i.e., not in use by the callout). While we are in 3320 * this loop, port->count is dropped by one, so that 3321 * close() knows when to free things. We restore it upon 3322 * exit, either normal or abnormal. 3323 */ 3324 3325 retval = 0; 3326 add_wait_queue(&port->open_wait, &wait); 3327 3328 if (debug_level >= DEBUG_LEVEL_INFO) 3329 printk("%s(%d):%s block_til_ready() before block, count=%d\n", 3330 __FILE__,__LINE__, tty->driver->name, port->count ); 3331 3332 spin_lock_irqsave(&info->lock, flags); 3333 port->count--; 3334 spin_unlock_irqrestore(&info->lock, flags); 3335 port->blocked_open++; 3336 3337 while (1) { 3338 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags)) 3339 tty_port_raise_dtr_rts(port); 3340 3341 set_current_state(TASK_INTERRUPTIBLE); 3342 3343 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ 3344 retval = (port->flags & ASYNC_HUP_NOTIFY) ? 3345 -EAGAIN : -ERESTARTSYS; 3346 break; 3347 } 3348 3349 cd = tty_port_carrier_raised(port); 3350 if (do_clocal || cd) 3351 break; 3352 3353 if (signal_pending(current)) { 3354 retval = -ERESTARTSYS; 3355 break; 3356 } 3357 3358 if (debug_level >= DEBUG_LEVEL_INFO) 3359 printk("%s(%d):%s block_til_ready() count=%d\n", 3360 __FILE__,__LINE__, tty->driver->name, port->count ); 3361 3362 tty_unlock(tty); 3363 schedule(); 3364 tty_lock(tty); 3365 } 3366 3367 set_current_state(TASK_RUNNING); 3368 remove_wait_queue(&port->open_wait, &wait); 3369 if (!tty_hung_up_p(filp)) 3370 port->count++; 3371 port->blocked_open--; 3372 3373 if (debug_level >= DEBUG_LEVEL_INFO) 3374 printk("%s(%d):%s block_til_ready() after, count=%d\n", 3375 __FILE__,__LINE__, tty->driver->name, port->count ); 3376 3377 if (!retval) 3378 port->flags |= ASYNC_NORMAL_ACTIVE; 3379 3380 return retval; 3381 } 3382 3383 static int alloc_dma_bufs(SLMP_INFO *info) 3384 { 3385 unsigned short BuffersPerFrame; 3386 unsigned short BufferCount; 3387 3388 // Force allocation to start at 64K boundary for each port. 3389 // This is necessary because *all* buffer descriptors for a port 3390 // *must* be in the same 64K block. All descriptors on a port 3391 // share a common 'base' address (upper 8 bits of 24 bits) programmed 3392 // into the CBP register. 3393 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num; 3394 3395 /* Calculate the number of DMA buffers necessary to hold the */ 3396 /* largest allowable frame size. Note: If the max frame size is */ 3397 /* not an even multiple of the DMA buffer size then we need to */ 3398 /* round the buffer count per frame up one. */ 3399 3400 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE); 3401 if ( info->max_frame_size % SCABUFSIZE ) 3402 BuffersPerFrame++; 3403 3404 /* calculate total number of data buffers (SCABUFSIZE) possible 3405 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory 3406 * for the descriptor list (BUFFERLISTSIZE). 3407 */ 3408 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE; 3409 3410 /* limit number of buffers to maximum amount of descriptors */ 3411 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC)) 3412 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC); 3413 3414 /* use enough buffers to transmit one max size frame */ 3415 info->tx_buf_count = BuffersPerFrame + 1; 3416 3417 /* never use more than half the available buffers for transmit */ 3418 if (info->tx_buf_count > (BufferCount/2)) 3419 info->tx_buf_count = BufferCount/2; 3420 3421 if (info->tx_buf_count > SCAMAXDESC) 3422 info->tx_buf_count = SCAMAXDESC; 3423 3424 /* use remaining buffers for receive */ 3425 info->rx_buf_count = BufferCount - info->tx_buf_count; 3426 3427 if (info->rx_buf_count > SCAMAXDESC) 3428 info->rx_buf_count = SCAMAXDESC; 3429 3430 if ( debug_level >= DEBUG_LEVEL_INFO ) 3431 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n", 3432 __FILE__,__LINE__, info->device_name, 3433 info->tx_buf_count,info->rx_buf_count); 3434 3435 if ( alloc_buf_list( info ) < 0 || 3436 alloc_frame_bufs(info, 3437 info->rx_buf_list, 3438 info->rx_buf_list_ex, 3439 info->rx_buf_count) < 0 || 3440 alloc_frame_bufs(info, 3441 info->tx_buf_list, 3442 info->tx_buf_list_ex, 3443 info->tx_buf_count) < 0 || 3444 alloc_tmp_rx_buf(info) < 0 ) { 3445 printk("%s(%d):%s Can't allocate DMA buffer memory\n", 3446 __FILE__,__LINE__, info->device_name); 3447 return -ENOMEM; 3448 } 3449 3450 rx_reset_buffers( info ); 3451 3452 return 0; 3453 } 3454 3455 /* Allocate DMA buffers for the transmit and receive descriptor lists. 3456 */ 3457 static int alloc_buf_list(SLMP_INFO *info) 3458 { 3459 unsigned int i; 3460 3461 /* build list in adapter shared memory */ 3462 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc; 3463 info->buffer_list_phys = info->port_array[0]->last_mem_alloc; 3464 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE; 3465 3466 memset(info->buffer_list, 0, BUFFERLISTSIZE); 3467 3468 /* Save virtual address pointers to the receive and */ 3469 /* transmit buffer lists. (Receive 1st). These pointers will */ 3470 /* be used by the processor to access the lists. */ 3471 info->rx_buf_list = (SCADESC *)info->buffer_list; 3472 3473 info->tx_buf_list = (SCADESC *)info->buffer_list; 3474 info->tx_buf_list += info->rx_buf_count; 3475 3476 /* Build links for circular buffer entry lists (tx and rx) 3477 * 3478 * Note: links are physical addresses read by the SCA device 3479 * to determine the next buffer entry to use. 3480 */ 3481 3482 for ( i = 0; i < info->rx_buf_count; i++ ) { 3483 /* calculate and store physical address of this buffer entry */ 3484 info->rx_buf_list_ex[i].phys_entry = 3485 info->buffer_list_phys + (i * SCABUFSIZE); 3486 3487 /* calculate and store physical address of */ 3488 /* next entry in cirular list of entries */ 3489 info->rx_buf_list[i].next = info->buffer_list_phys; 3490 if ( i < info->rx_buf_count - 1 ) 3491 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC); 3492 3493 info->rx_buf_list[i].length = SCABUFSIZE; 3494 } 3495 3496 for ( i = 0; i < info->tx_buf_count; i++ ) { 3497 /* calculate and store physical address of this buffer entry */ 3498 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys + 3499 ((info->rx_buf_count + i) * sizeof(SCADESC)); 3500 3501 /* calculate and store physical address of */ 3502 /* next entry in cirular list of entries */ 3503 3504 info->tx_buf_list[i].next = info->buffer_list_phys + 3505 info->rx_buf_count * sizeof(SCADESC); 3506 3507 if ( i < info->tx_buf_count - 1 ) 3508 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC); 3509 } 3510 3511 return 0; 3512 } 3513 3514 /* Allocate the frame DMA buffers used by the specified buffer list. 3515 */ 3516 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count) 3517 { 3518 int i; 3519 unsigned long phys_addr; 3520 3521 for ( i = 0; i < count; i++ ) { 3522 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc; 3523 phys_addr = info->port_array[0]->last_mem_alloc; 3524 info->port_array[0]->last_mem_alloc += SCABUFSIZE; 3525 3526 buf_list[i].buf_ptr = (unsigned short)phys_addr; 3527 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16); 3528 } 3529 3530 return 0; 3531 } 3532 3533 static void free_dma_bufs(SLMP_INFO *info) 3534 { 3535 info->buffer_list = NULL; 3536 info->rx_buf_list = NULL; 3537 info->tx_buf_list = NULL; 3538 } 3539 3540 /* allocate buffer large enough to hold max_frame_size. 3541 * This buffer is used to pass an assembled frame to the line discipline. 3542 */ 3543 static int alloc_tmp_rx_buf(SLMP_INFO *info) 3544 { 3545 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 3546 if (info->tmp_rx_buf == NULL) 3547 return -ENOMEM; 3548 /* unused flag buffer to satisfy receive_buf calling interface */ 3549 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL); 3550 if (!info->flag_buf) { 3551 kfree(info->tmp_rx_buf); 3552 info->tmp_rx_buf = NULL; 3553 return -ENOMEM; 3554 } 3555 return 0; 3556 } 3557 3558 static void free_tmp_rx_buf(SLMP_INFO *info) 3559 { 3560 kfree(info->tmp_rx_buf); 3561 info->tmp_rx_buf = NULL; 3562 kfree(info->flag_buf); 3563 info->flag_buf = NULL; 3564 } 3565 3566 static int claim_resources(SLMP_INFO *info) 3567 { 3568 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) { 3569 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n", 3570 __FILE__,__LINE__,info->device_name, info->phys_memory_base); 3571 info->init_error = DiagStatus_AddressConflict; 3572 goto errout; 3573 } 3574 else 3575 info->shared_mem_requested = true; 3576 3577 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) { 3578 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n", 3579 __FILE__,__LINE__,info->device_name, info->phys_lcr_base); 3580 info->init_error = DiagStatus_AddressConflict; 3581 goto errout; 3582 } 3583 else 3584 info->lcr_mem_requested = true; 3585 3586 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) { 3587 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n", 3588 __FILE__,__LINE__,info->device_name, info->phys_sca_base); 3589 info->init_error = DiagStatus_AddressConflict; 3590 goto errout; 3591 } 3592 else 3593 info->sca_base_requested = true; 3594 3595 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) { 3596 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n", 3597 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base); 3598 info->init_error = DiagStatus_AddressConflict; 3599 goto errout; 3600 } 3601 else 3602 info->sca_statctrl_requested = true; 3603 3604 info->memory_base = ioremap_nocache(info->phys_memory_base, 3605 SCA_MEM_SIZE); 3606 if (!info->memory_base) { 3607 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n", 3608 __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 3609 info->init_error = DiagStatus_CantAssignPciResources; 3610 goto errout; 3611 } 3612 3613 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE); 3614 if (!info->lcr_base) { 3615 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n", 3616 __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); 3617 info->init_error = DiagStatus_CantAssignPciResources; 3618 goto errout; 3619 } 3620 info->lcr_base += info->lcr_offset; 3621 3622 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE); 3623 if (!info->sca_base) { 3624 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n", 3625 __FILE__,__LINE__,info->device_name, info->phys_sca_base ); 3626 info->init_error = DiagStatus_CantAssignPciResources; 3627 goto errout; 3628 } 3629 info->sca_base += info->sca_offset; 3630 3631 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base, 3632 PAGE_SIZE); 3633 if (!info->statctrl_base) { 3634 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n", 3635 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base ); 3636 info->init_error = DiagStatus_CantAssignPciResources; 3637 goto errout; 3638 } 3639 info->statctrl_base += info->statctrl_offset; 3640 3641 if ( !memory_test(info) ) { 3642 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n", 3643 __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 3644 info->init_error = DiagStatus_MemoryError; 3645 goto errout; 3646 } 3647 3648 return 0; 3649 3650 errout: 3651 release_resources( info ); 3652 return -ENODEV; 3653 } 3654 3655 static void release_resources(SLMP_INFO *info) 3656 { 3657 if ( debug_level >= DEBUG_LEVEL_INFO ) 3658 printk( "%s(%d):%s release_resources() entry\n", 3659 __FILE__,__LINE__,info->device_name ); 3660 3661 if ( info->irq_requested ) { 3662 free_irq(info->irq_level, info); 3663 info->irq_requested = false; 3664 } 3665 3666 if ( info->shared_mem_requested ) { 3667 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE); 3668 info->shared_mem_requested = false; 3669 } 3670 if ( info->lcr_mem_requested ) { 3671 release_mem_region(info->phys_lcr_base + info->lcr_offset,128); 3672 info->lcr_mem_requested = false; 3673 } 3674 if ( info->sca_base_requested ) { 3675 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE); 3676 info->sca_base_requested = false; 3677 } 3678 if ( info->sca_statctrl_requested ) { 3679 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE); 3680 info->sca_statctrl_requested = false; 3681 } 3682 3683 if (info->memory_base){ 3684 iounmap(info->memory_base); 3685 info->memory_base = NULL; 3686 } 3687 3688 if (info->sca_base) { 3689 iounmap(info->sca_base - info->sca_offset); 3690 info->sca_base=NULL; 3691 } 3692 3693 if (info->statctrl_base) { 3694 iounmap(info->statctrl_base - info->statctrl_offset); 3695 info->statctrl_base=NULL; 3696 } 3697 3698 if (info->lcr_base){ 3699 iounmap(info->lcr_base - info->lcr_offset); 3700 info->lcr_base = NULL; 3701 } 3702 3703 if ( debug_level >= DEBUG_LEVEL_INFO ) 3704 printk( "%s(%d):%s release_resources() exit\n", 3705 __FILE__,__LINE__,info->device_name ); 3706 } 3707 3708 /* Add the specified device instance data structure to the 3709 * global linked list of devices and increment the device count. 3710 */ 3711 static void add_device(SLMP_INFO *info) 3712 { 3713 info->next_device = NULL; 3714 info->line = synclinkmp_device_count; 3715 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num); 3716 3717 if (info->line < MAX_DEVICES) { 3718 if (maxframe[info->line]) 3719 info->max_frame_size = maxframe[info->line]; 3720 } 3721 3722 synclinkmp_device_count++; 3723 3724 if ( !synclinkmp_device_list ) 3725 synclinkmp_device_list = info; 3726 else { 3727 SLMP_INFO *current_dev = synclinkmp_device_list; 3728 while( current_dev->next_device ) 3729 current_dev = current_dev->next_device; 3730 current_dev->next_device = info; 3731 } 3732 3733 if ( info->max_frame_size < 4096 ) 3734 info->max_frame_size = 4096; 3735 else if ( info->max_frame_size > 65535 ) 3736 info->max_frame_size = 65535; 3737 3738 printk( "SyncLink MultiPort %s: " 3739 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", 3740 info->device_name, 3741 info->phys_sca_base, 3742 info->phys_memory_base, 3743 info->phys_statctrl_base, 3744 info->phys_lcr_base, 3745 info->irq_level, 3746 info->max_frame_size ); 3747 3748 #if SYNCLINK_GENERIC_HDLC 3749 hdlcdev_init(info); 3750 #endif 3751 } 3752 3753 static const struct tty_port_operations port_ops = { 3754 .carrier_raised = carrier_raised, 3755 .dtr_rts = dtr_rts, 3756 }; 3757 3758 /* Allocate and initialize a device instance structure 3759 * 3760 * Return Value: pointer to SLMP_INFO if success, otherwise NULL 3761 */ 3762 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) 3763 { 3764 SLMP_INFO *info; 3765 3766 info = kzalloc(sizeof(SLMP_INFO), 3767 GFP_KERNEL); 3768 3769 if (!info) { 3770 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n", 3771 __FILE__,__LINE__, adapter_num, port_num); 3772 } else { 3773 tty_port_init(&info->port); 3774 info->port.ops = &port_ops; 3775 info->magic = MGSL_MAGIC; 3776 INIT_WORK(&info->task, bh_handler); 3777 info->max_frame_size = 4096; 3778 info->port.close_delay = 5*HZ/10; 3779 info->port.closing_wait = 30*HZ; 3780 init_waitqueue_head(&info->status_event_wait_q); 3781 init_waitqueue_head(&info->event_wait_q); 3782 spin_lock_init(&info->netlock); 3783 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 3784 info->idle_mode = HDLC_TXIDLE_FLAGS; 3785 info->adapter_num = adapter_num; 3786 info->port_num = port_num; 3787 3788 /* Copy configuration info to device instance data */ 3789 info->irq_level = pdev->irq; 3790 info->phys_lcr_base = pci_resource_start(pdev,0); 3791 info->phys_sca_base = pci_resource_start(pdev,2); 3792 info->phys_memory_base = pci_resource_start(pdev,3); 3793 info->phys_statctrl_base = pci_resource_start(pdev,4); 3794 3795 /* Because veremap only works on page boundaries we must map 3796 * a larger area than is actually implemented for the LCR 3797 * memory range. We map a full page starting at the page boundary. 3798 */ 3799 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1); 3800 info->phys_lcr_base &= ~(PAGE_SIZE-1); 3801 3802 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1); 3803 info->phys_sca_base &= ~(PAGE_SIZE-1); 3804 3805 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1); 3806 info->phys_statctrl_base &= ~(PAGE_SIZE-1); 3807 3808 info->bus_type = MGSL_BUS_TYPE_PCI; 3809 info->irq_flags = IRQF_SHARED; 3810 3811 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); 3812 setup_timer(&info->status_timer, status_timeout, 3813 (unsigned long)info); 3814 3815 /* Store the PCI9050 misc control register value because a flaw 3816 * in the PCI9050 prevents LCR registers from being read if 3817 * BIOS assigns an LCR base address with bit 7 set. 3818 * 3819 * Only the misc control register is accessed for which only 3820 * write access is needed, so set an initial value and change 3821 * bits to the device instance data as we write the value 3822 * to the actual misc control register. 3823 */ 3824 info->misc_ctrl_value = 0x087e4546; 3825 3826 /* initial port state is unknown - if startup errors 3827 * occur, init_error will be set to indicate the 3828 * problem. Once the port is fully initialized, 3829 * this value will be set to 0 to indicate the 3830 * port is available. 3831 */ 3832 info->init_error = -1; 3833 } 3834 3835 return info; 3836 } 3837 3838 static void device_init(int adapter_num, struct pci_dev *pdev) 3839 { 3840 SLMP_INFO *port_array[SCA_MAX_PORTS]; 3841 int port; 3842 3843 /* allocate device instances for up to SCA_MAX_PORTS devices */ 3844 for ( port = 0; port < SCA_MAX_PORTS; ++port ) { 3845 port_array[port] = alloc_dev(adapter_num,port,pdev); 3846 if( port_array[port] == NULL ) { 3847 for (--port; port >= 0; --port) { 3848 tty_port_destroy(&port_array[port]->port); 3849 kfree(port_array[port]); 3850 } 3851 return; 3852 } 3853 } 3854 3855 /* give copy of port_array to all ports and add to device list */ 3856 for ( port = 0; port < SCA_MAX_PORTS; ++port ) { 3857 memcpy(port_array[port]->port_array,port_array,sizeof(port_array)); 3858 add_device( port_array[port] ); 3859 spin_lock_init(&port_array[port]->lock); 3860 } 3861 3862 /* Allocate and claim adapter resources */ 3863 if ( !claim_resources(port_array[0]) ) { 3864 3865 alloc_dma_bufs(port_array[0]); 3866 3867 /* copy resource information from first port to others */ 3868 for ( port = 1; port < SCA_MAX_PORTS; ++port ) { 3869 port_array[port]->lock = port_array[0]->lock; 3870 port_array[port]->irq_level = port_array[0]->irq_level; 3871 port_array[port]->memory_base = port_array[0]->memory_base; 3872 port_array[port]->sca_base = port_array[0]->sca_base; 3873 port_array[port]->statctrl_base = port_array[0]->statctrl_base; 3874 port_array[port]->lcr_base = port_array[0]->lcr_base; 3875 alloc_dma_bufs(port_array[port]); 3876 } 3877 3878 if ( request_irq(port_array[0]->irq_level, 3879 synclinkmp_interrupt, 3880 port_array[0]->irq_flags, 3881 port_array[0]->device_name, 3882 port_array[0]) < 0 ) { 3883 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n", 3884 __FILE__,__LINE__, 3885 port_array[0]->device_name, 3886 port_array[0]->irq_level ); 3887 } 3888 else { 3889 port_array[0]->irq_requested = true; 3890 adapter_test(port_array[0]); 3891 } 3892 } 3893 } 3894 3895 static const struct tty_operations ops = { 3896 .install = install, 3897 .open = open, 3898 .close = close, 3899 .write = write, 3900 .put_char = put_char, 3901 .flush_chars = flush_chars, 3902 .write_room = write_room, 3903 .chars_in_buffer = chars_in_buffer, 3904 .flush_buffer = flush_buffer, 3905 .ioctl = ioctl, 3906 .throttle = throttle, 3907 .unthrottle = unthrottle, 3908 .send_xchar = send_xchar, 3909 .break_ctl = set_break, 3910 .wait_until_sent = wait_until_sent, 3911 .set_termios = set_termios, 3912 .stop = tx_hold, 3913 .start = tx_release, 3914 .hangup = hangup, 3915 .tiocmget = tiocmget, 3916 .tiocmset = tiocmset, 3917 .get_icount = get_icount, 3918 .proc_fops = &synclinkmp_proc_fops, 3919 }; 3920 3921 3922 static void synclinkmp_cleanup(void) 3923 { 3924 int rc; 3925 SLMP_INFO *info; 3926 SLMP_INFO *tmp; 3927 3928 printk("Unloading %s %s\n", driver_name, driver_version); 3929 3930 if (serial_driver) { 3931 rc = tty_unregister_driver(serial_driver); 3932 if (rc) 3933 printk("%s(%d) failed to unregister tty driver err=%d\n", 3934 __FILE__,__LINE__,rc); 3935 put_tty_driver(serial_driver); 3936 } 3937 3938 /* reset devices */ 3939 info = synclinkmp_device_list; 3940 while(info) { 3941 reset_port(info); 3942 info = info->next_device; 3943 } 3944 3945 /* release devices */ 3946 info = synclinkmp_device_list; 3947 while(info) { 3948 #if SYNCLINK_GENERIC_HDLC 3949 hdlcdev_exit(info); 3950 #endif 3951 free_dma_bufs(info); 3952 free_tmp_rx_buf(info); 3953 if ( info->port_num == 0 ) { 3954 if (info->sca_base) 3955 write_reg(info, LPR, 1); /* set low power mode */ 3956 release_resources(info); 3957 } 3958 tmp = info; 3959 info = info->next_device; 3960 tty_port_destroy(&tmp->port); 3961 kfree(tmp); 3962 } 3963 3964 pci_unregister_driver(&synclinkmp_pci_driver); 3965 } 3966 3967 /* Driver initialization entry point. 3968 */ 3969 3970 static int __init synclinkmp_init(void) 3971 { 3972 int rc; 3973 3974 if (break_on_load) { 3975 synclinkmp_get_text_ptr(); 3976 BREAKPOINT(); 3977 } 3978 3979 printk("%s %s\n", driver_name, driver_version); 3980 3981 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) { 3982 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); 3983 return rc; 3984 } 3985 3986 serial_driver = alloc_tty_driver(128); 3987 if (!serial_driver) { 3988 rc = -ENOMEM; 3989 goto error; 3990 } 3991 3992 /* Initialize the tty_driver structure */ 3993 3994 serial_driver->driver_name = "synclinkmp"; 3995 serial_driver->name = "ttySLM"; 3996 serial_driver->major = ttymajor; 3997 serial_driver->minor_start = 64; 3998 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 3999 serial_driver->subtype = SERIAL_TYPE_NORMAL; 4000 serial_driver->init_termios = tty_std_termios; 4001 serial_driver->init_termios.c_cflag = 4002 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 4003 serial_driver->init_termios.c_ispeed = 9600; 4004 serial_driver->init_termios.c_ospeed = 9600; 4005 serial_driver->flags = TTY_DRIVER_REAL_RAW; 4006 tty_set_operations(serial_driver, &ops); 4007 if ((rc = tty_register_driver(serial_driver)) < 0) { 4008 printk("%s(%d):Couldn't register serial driver\n", 4009 __FILE__,__LINE__); 4010 put_tty_driver(serial_driver); 4011 serial_driver = NULL; 4012 goto error; 4013 } 4014 4015 printk("%s %s, tty major#%d\n", 4016 driver_name, driver_version, 4017 serial_driver->major); 4018 4019 return 0; 4020 4021 error: 4022 synclinkmp_cleanup(); 4023 return rc; 4024 } 4025 4026 static void __exit synclinkmp_exit(void) 4027 { 4028 synclinkmp_cleanup(); 4029 } 4030 4031 module_init(synclinkmp_init); 4032 module_exit(synclinkmp_exit); 4033 4034 /* Set the port for internal loopback mode. 4035 * The TxCLK and RxCLK signals are generated from the BRG and 4036 * the TxD is looped back to the RxD internally. 4037 */ 4038 static void enable_loopback(SLMP_INFO *info, int enable) 4039 { 4040 if (enable) { 4041 /* MD2 (Mode Register 2) 4042 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback 4043 */ 4044 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); 4045 4046 /* degate external TxC clock source */ 4047 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4048 write_control_reg(info); 4049 4050 /* RXS/TXS (Rx/Tx clock source) 4051 * 07 Reserved, must be 0 4052 * 06..04 Clock Source, 100=BRG 4053 * 03..00 Clock Divisor, 0000=1 4054 */ 4055 write_reg(info, RXS, 0x40); 4056 write_reg(info, TXS, 0x40); 4057 4058 } else { 4059 /* MD2 (Mode Register 2) 4060 * 01..00 CNCT<1..0> Channel connection, 0=normal 4061 */ 4062 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); 4063 4064 /* RXS/TXS (Rx/Tx clock source) 4065 * 07 Reserved, must be 0 4066 * 06..04 Clock Source, 000=RxC/TxC Pin 4067 * 03..00 Clock Divisor, 0000=1 4068 */ 4069 write_reg(info, RXS, 0x00); 4070 write_reg(info, TXS, 0x00); 4071 } 4072 4073 /* set LinkSpeed if available, otherwise default to 2Mbps */ 4074 if (info->params.clock_speed) 4075 set_rate(info, info->params.clock_speed); 4076 else 4077 set_rate(info, 3686400); 4078 } 4079 4080 /* Set the baud rate register to the desired speed 4081 * 4082 * data_rate data rate of clock in bits per second 4083 * A data rate of 0 disables the AUX clock. 4084 */ 4085 static void set_rate( SLMP_INFO *info, u32 data_rate ) 4086 { 4087 u32 TMCValue; 4088 unsigned char BRValue; 4089 u32 Divisor=0; 4090 4091 /* fBRG = fCLK/(TMC * 2^BR) 4092 */ 4093 if (data_rate != 0) { 4094 Divisor = 14745600/data_rate; 4095 if (!Divisor) 4096 Divisor = 1; 4097 4098 TMCValue = Divisor; 4099 4100 BRValue = 0; 4101 if (TMCValue != 1 && TMCValue != 2) { 4102 /* BRValue of 0 provides 50/50 duty cycle *only* when 4103 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides 4104 * 50/50 duty cycle. 4105 */ 4106 BRValue = 1; 4107 TMCValue >>= 1; 4108 } 4109 4110 /* while TMCValue is too big for TMC register, divide 4111 * by 2 and increment BR exponent. 4112 */ 4113 for(; TMCValue > 256 && BRValue < 10; BRValue++) 4114 TMCValue >>= 1; 4115 4116 write_reg(info, TXS, 4117 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue)); 4118 write_reg(info, RXS, 4119 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue)); 4120 write_reg(info, TMC, (unsigned char)TMCValue); 4121 } 4122 else { 4123 write_reg(info, TXS,0); 4124 write_reg(info, RXS,0); 4125 write_reg(info, TMC, 0); 4126 } 4127 } 4128 4129 /* Disable receiver 4130 */ 4131 static void rx_stop(SLMP_INFO *info) 4132 { 4133 if (debug_level >= DEBUG_LEVEL_ISR) 4134 printk("%s(%d):%s rx_stop()\n", 4135 __FILE__,__LINE__, info->device_name ); 4136 4137 write_reg(info, CMD, RXRESET); 4138 4139 info->ie0_value &= ~RXRDYE; 4140 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */ 4141 4142 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ 4143 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ 4144 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */ 4145 4146 info->rx_enabled = false; 4147 info->rx_overflow = false; 4148 } 4149 4150 /* enable the receiver 4151 */ 4152 static void rx_start(SLMP_INFO *info) 4153 { 4154 int i; 4155 4156 if (debug_level >= DEBUG_LEVEL_ISR) 4157 printk("%s(%d):%s rx_start()\n", 4158 __FILE__,__LINE__, info->device_name ); 4159 4160 write_reg(info, CMD, RXRESET); 4161 4162 if ( info->params.mode == MGSL_MODE_HDLC ) { 4163 /* HDLC, disabe IRQ on rxdata */ 4164 info->ie0_value &= ~RXRDYE; 4165 write_reg(info, IE0, info->ie0_value); 4166 4167 /* Reset all Rx DMA buffers and program rx dma */ 4168 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ 4169 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ 4170 4171 for (i = 0; i < info->rx_buf_count; i++) { 4172 info->rx_buf_list[i].status = 0xff; 4173 4174 // throttle to 4 shared memory writes at a time to prevent 4175 // hogging local bus (keep latency time for DMA requests low). 4176 if (!(i % 4)) 4177 read_status_reg(info); 4178 } 4179 info->current_rx_buf = 0; 4180 4181 /* set current/1st descriptor address */ 4182 write_reg16(info, RXDMA + CDA, 4183 info->rx_buf_list_ex[0].phys_entry); 4184 4185 /* set new last rx descriptor address */ 4186 write_reg16(info, RXDMA + EDA, 4187 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry); 4188 4189 /* set buffer length (shared by all rx dma data buffers) */ 4190 write_reg16(info, RXDMA + BFL, SCABUFSIZE); 4191 4192 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */ 4193 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ 4194 } else { 4195 /* async, enable IRQ on rxdata */ 4196 info->ie0_value |= RXRDYE; 4197 write_reg(info, IE0, info->ie0_value); 4198 } 4199 4200 write_reg(info, CMD, RXENABLE); 4201 4202 info->rx_overflow = false; 4203 info->rx_enabled = true; 4204 } 4205 4206 /* Enable the transmitter and send a transmit frame if 4207 * one is loaded in the DMA buffers. 4208 */ 4209 static void tx_start(SLMP_INFO *info) 4210 { 4211 if (debug_level >= DEBUG_LEVEL_ISR) 4212 printk("%s(%d):%s tx_start() tx_count=%d\n", 4213 __FILE__,__LINE__, info->device_name,info->tx_count ); 4214 4215 if (!info->tx_enabled ) { 4216 write_reg(info, CMD, TXRESET); 4217 write_reg(info, CMD, TXENABLE); 4218 info->tx_enabled = true; 4219 } 4220 4221 if ( info->tx_count ) { 4222 4223 /* If auto RTS enabled and RTS is inactive, then assert */ 4224 /* RTS and set a flag indicating that the driver should */ 4225 /* negate RTS when the transmission completes. */ 4226 4227 info->drop_rts_on_tx_done = false; 4228 4229 if (info->params.mode != MGSL_MODE_ASYNC) { 4230 4231 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { 4232 get_signals( info ); 4233 if ( !(info->serial_signals & SerialSignal_RTS) ) { 4234 info->serial_signals |= SerialSignal_RTS; 4235 set_signals( info ); 4236 info->drop_rts_on_tx_done = true; 4237 } 4238 } 4239 4240 write_reg16(info, TRC0, 4241 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level)); 4242 4243 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 4244 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 4245 4246 /* set TX CDA (current descriptor address) */ 4247 write_reg16(info, TXDMA + CDA, 4248 info->tx_buf_list_ex[0].phys_entry); 4249 4250 /* set TX EDA (last descriptor address) */ 4251 write_reg16(info, TXDMA + EDA, 4252 info->tx_buf_list_ex[info->last_tx_buf].phys_entry); 4253 4254 /* enable underrun IRQ */ 4255 info->ie1_value &= ~IDLE; 4256 info->ie1_value |= UDRN; 4257 write_reg(info, IE1, info->ie1_value); 4258 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); 4259 4260 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */ 4261 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ 4262 4263 mod_timer(&info->tx_timer, jiffies + 4264 msecs_to_jiffies(5000)); 4265 } 4266 else { 4267 tx_load_fifo(info); 4268 /* async, enable IRQ on txdata */ 4269 info->ie0_value |= TXRDYE; 4270 write_reg(info, IE0, info->ie0_value); 4271 } 4272 4273 info->tx_active = true; 4274 } 4275 } 4276 4277 /* stop the transmitter and DMA 4278 */ 4279 static void tx_stop( SLMP_INFO *info ) 4280 { 4281 if (debug_level >= DEBUG_LEVEL_ISR) 4282 printk("%s(%d):%s tx_stop()\n", 4283 __FILE__,__LINE__, info->device_name ); 4284 4285 del_timer(&info->tx_timer); 4286 4287 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 4288 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 4289 4290 write_reg(info, CMD, TXRESET); 4291 4292 info->ie1_value &= ~(UDRN + IDLE); 4293 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ 4294 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ 4295 4296 info->ie0_value &= ~TXRDYE; 4297 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */ 4298 4299 info->tx_enabled = false; 4300 info->tx_active = false; 4301 } 4302 4303 /* Fill the transmit FIFO until the FIFO is full or 4304 * there is no more data to load. 4305 */ 4306 static void tx_load_fifo(SLMP_INFO *info) 4307 { 4308 u8 TwoBytes[2]; 4309 4310 /* do nothing is now tx data available and no XON/XOFF pending */ 4311 4312 if ( !info->tx_count && !info->x_char ) 4313 return; 4314 4315 /* load the Transmit FIFO until FIFOs full or all data sent */ 4316 4317 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { 4318 4319 /* there is more space in the transmit FIFO and */ 4320 /* there is more data in transmit buffer */ 4321 4322 if ( (info->tx_count > 1) && !info->x_char ) { 4323 /* write 16-bits */ 4324 TwoBytes[0] = info->tx_buf[info->tx_get++]; 4325 if (info->tx_get >= info->max_frame_size) 4326 info->tx_get -= info->max_frame_size; 4327 TwoBytes[1] = info->tx_buf[info->tx_get++]; 4328 if (info->tx_get >= info->max_frame_size) 4329 info->tx_get -= info->max_frame_size; 4330 4331 write_reg16(info, TRB, *((u16 *)TwoBytes)); 4332 4333 info->tx_count -= 2; 4334 info->icount.tx += 2; 4335 } else { 4336 /* only 1 byte left to transmit or 1 FIFO slot left */ 4337 4338 if (info->x_char) { 4339 /* transmit pending high priority char */ 4340 write_reg(info, TRB, info->x_char); 4341 info->x_char = 0; 4342 } else { 4343 write_reg(info, TRB, info->tx_buf[info->tx_get++]); 4344 if (info->tx_get >= info->max_frame_size) 4345 info->tx_get -= info->max_frame_size; 4346 info->tx_count--; 4347 } 4348 info->icount.tx++; 4349 } 4350 } 4351 } 4352 4353 /* Reset a port to a known state 4354 */ 4355 static void reset_port(SLMP_INFO *info) 4356 { 4357 if (info->sca_base) { 4358 4359 tx_stop(info); 4360 rx_stop(info); 4361 4362 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 4363 set_signals(info); 4364 4365 /* disable all port interrupts */ 4366 info->ie0_value = 0; 4367 info->ie1_value = 0; 4368 info->ie2_value = 0; 4369 write_reg(info, IE0, info->ie0_value); 4370 write_reg(info, IE1, info->ie1_value); 4371 write_reg(info, IE2, info->ie2_value); 4372 4373 write_reg(info, CMD, CHRESET); 4374 } 4375 } 4376 4377 /* Reset all the ports to a known state. 4378 */ 4379 static void reset_adapter(SLMP_INFO *info) 4380 { 4381 int i; 4382 4383 for ( i=0; i < SCA_MAX_PORTS; ++i) { 4384 if (info->port_array[i]) 4385 reset_port(info->port_array[i]); 4386 } 4387 } 4388 4389 /* Program port for asynchronous communications. 4390 */ 4391 static void async_mode(SLMP_INFO *info) 4392 { 4393 4394 unsigned char RegValue; 4395 4396 tx_stop(info); 4397 rx_stop(info); 4398 4399 /* MD0, Mode Register 0 4400 * 4401 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async 4402 * 04 AUTO, Auto-enable (RTS/CTS/DCD) 4403 * 03 Reserved, must be 0 4404 * 02 CRCCC, CRC Calculation, 0=disabled 4405 * 01..00 STOP<1..0> Stop bits (00=1,10=2) 4406 * 4407 * 0000 0000 4408 */ 4409 RegValue = 0x00; 4410 if (info->params.stop_bits != 1) 4411 RegValue |= BIT1; 4412 write_reg(info, MD0, RegValue); 4413 4414 /* MD1, Mode Register 1 4415 * 4416 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64 4417 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5 4418 * 03..02 RXCHR<1..0>, rx char size 4419 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd 4420 * 4421 * 0100 0000 4422 */ 4423 RegValue = 0x40; 4424 switch (info->params.data_bits) { 4425 case 7: RegValue |= BIT4 + BIT2; break; 4426 case 6: RegValue |= BIT5 + BIT3; break; 4427 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; 4428 } 4429 if (info->params.parity != ASYNC_PARITY_NONE) { 4430 RegValue |= BIT1; 4431 if (info->params.parity == ASYNC_PARITY_ODD) 4432 RegValue |= BIT0; 4433 } 4434 write_reg(info, MD1, RegValue); 4435 4436 /* MD2, Mode Register 2 4437 * 4438 * 07..02 Reserved, must be 0 4439 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback 4440 * 4441 * 0000 0000 4442 */ 4443 RegValue = 0x00; 4444 if (info->params.loopback) 4445 RegValue |= (BIT1 + BIT0); 4446 write_reg(info, MD2, RegValue); 4447 4448 /* RXS, Receive clock source 4449 * 4450 * 07 Reserved, must be 0 4451 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL 4452 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4453 */ 4454 RegValue=BIT6; 4455 write_reg(info, RXS, RegValue); 4456 4457 /* TXS, Transmit clock source 4458 * 4459 * 07 Reserved, must be 0 4460 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock 4461 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4462 */ 4463 RegValue=BIT6; 4464 write_reg(info, TXS, RegValue); 4465 4466 /* Control Register 4467 * 4468 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out 4469 */ 4470 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4471 write_control_reg(info); 4472 4473 tx_set_idle(info); 4474 4475 /* RRC Receive Ready Control 0 4476 * 4477 * 07..05 Reserved, must be 0 4478 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte 4479 */ 4480 write_reg(info, RRC, 0x00); 4481 4482 /* TRC0 Transmit Ready Control 0 4483 * 4484 * 07..05 Reserved, must be 0 4485 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes 4486 */ 4487 write_reg(info, TRC0, 0x10); 4488 4489 /* TRC1 Transmit Ready Control 1 4490 * 4491 * 07..05 Reserved, must be 0 4492 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1) 4493 */ 4494 write_reg(info, TRC1, 0x1e); 4495 4496 /* CTL, MSCI control register 4497 * 4498 * 07..06 Reserved, set to 0 4499 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) 4500 * 04 IDLC, idle control, 0=mark 1=idle register 4501 * 03 BRK, break, 0=off 1 =on (async) 4502 * 02 SYNCLD, sync char load enable (BSC) 1=enabled 4503 * 01 GOP, go active on poll (LOOP mode) 1=enabled 4504 * 00 RTS, RTS output control, 0=active 1=inactive 4505 * 4506 * 0001 0001 4507 */ 4508 RegValue = 0x10; 4509 if (!(info->serial_signals & SerialSignal_RTS)) 4510 RegValue |= 0x01; 4511 write_reg(info, CTL, RegValue); 4512 4513 /* enable status interrupts */ 4514 info->ie0_value |= TXINTE + RXINTE; 4515 write_reg(info, IE0, info->ie0_value); 4516 4517 /* enable break detect interrupt */ 4518 info->ie1_value = BRKD; 4519 write_reg(info, IE1, info->ie1_value); 4520 4521 /* enable rx overrun interrupt */ 4522 info->ie2_value = OVRN; 4523 write_reg(info, IE2, info->ie2_value); 4524 4525 set_rate( info, info->params.data_rate * 16 ); 4526 } 4527 4528 /* Program the SCA for HDLC communications. 4529 */ 4530 static void hdlc_mode(SLMP_INFO *info) 4531 { 4532 unsigned char RegValue; 4533 u32 DpllDivisor; 4534 4535 // Can't use DPLL because SCA outputs recovered clock on RxC when 4536 // DPLL mode selected. This causes output contention with RxC receiver. 4537 // Use of DPLL would require external hardware to disable RxC receiver 4538 // when DPLL mode selected. 4539 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL); 4540 4541 /* disable DMA interrupts */ 4542 write_reg(info, TXDMA + DIR, 0); 4543 write_reg(info, RXDMA + DIR, 0); 4544 4545 /* MD0, Mode Register 0 4546 * 4547 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC 4548 * 04 AUTO, Auto-enable (RTS/CTS/DCD) 4549 * 03 Reserved, must be 0 4550 * 02 CRCCC, CRC Calculation, 1=enabled 4551 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16 4552 * 00 CRC0, CRC initial value, 1 = all 1s 4553 * 4554 * 1000 0001 4555 */ 4556 RegValue = 0x81; 4557 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4558 RegValue |= BIT4; 4559 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4560 RegValue |= BIT4; 4561 if (info->params.crc_type == HDLC_CRC_16_CCITT) 4562 RegValue |= BIT2 + BIT1; 4563 write_reg(info, MD0, RegValue); 4564 4565 /* MD1, Mode Register 1 4566 * 4567 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check 4568 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits 4569 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits 4570 * 01..00 PMPM<1..0>, Parity mode, 00=no parity 4571 * 4572 * 0000 0000 4573 */ 4574 RegValue = 0x00; 4575 write_reg(info, MD1, RegValue); 4576 4577 /* MD2, Mode Register 2 4578 * 4579 * 07 NRZFM, 0=NRZ, 1=FM 4580 * 06..05 CODE<1..0> Encoding, 00=NRZ 4581 * 04..03 DRATE<1..0> DPLL Divisor, 00=8 4582 * 02 Reserved, must be 0 4583 * 01..00 CNCT<1..0> Channel connection, 0=normal 4584 * 4585 * 0000 0000 4586 */ 4587 RegValue = 0x00; 4588 switch(info->params.encoding) { 4589 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; 4590 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ 4591 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ 4592 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */ 4593 #if 0 4594 case HDLC_ENCODING_NRZB: /* not supported */ 4595 case HDLC_ENCODING_NRZI_MARK: /* not supported */ 4596 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */ 4597 #endif 4598 } 4599 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) { 4600 DpllDivisor = 16; 4601 RegValue |= BIT3; 4602 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) { 4603 DpllDivisor = 8; 4604 } else { 4605 DpllDivisor = 32; 4606 RegValue |= BIT4; 4607 } 4608 write_reg(info, MD2, RegValue); 4609 4610 4611 /* RXS, Receive clock source 4612 * 4613 * 07 Reserved, must be 0 4614 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL 4615 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4616 */ 4617 RegValue=0; 4618 if (info->params.flags & HDLC_FLAG_RXC_BRG) 4619 RegValue |= BIT6; 4620 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4621 RegValue |= BIT6 + BIT5; 4622 write_reg(info, RXS, RegValue); 4623 4624 /* TXS, Transmit clock source 4625 * 4626 * 07 Reserved, must be 0 4627 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock 4628 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4629 */ 4630 RegValue=0; 4631 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4632 RegValue |= BIT6; 4633 if (info->params.flags & HDLC_FLAG_TXC_DPLL) 4634 RegValue |= BIT6 + BIT5; 4635 write_reg(info, TXS, RegValue); 4636 4637 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4638 set_rate(info, info->params.clock_speed * DpllDivisor); 4639 else 4640 set_rate(info, info->params.clock_speed); 4641 4642 /* GPDATA (General Purpose I/O Data Register) 4643 * 4644 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out 4645 */ 4646 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4647 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4648 else 4649 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2)); 4650 write_control_reg(info); 4651 4652 /* RRC Receive Ready Control 0 4653 * 4654 * 07..05 Reserved, must be 0 4655 * 04..00 RRC<4..0> Rx FIFO trigger active 4656 */ 4657 write_reg(info, RRC, rx_active_fifo_level); 4658 4659 /* TRC0 Transmit Ready Control 0 4660 * 4661 * 07..05 Reserved, must be 0 4662 * 04..00 TRC<4..0> Tx FIFO trigger active 4663 */ 4664 write_reg(info, TRC0, tx_active_fifo_level); 4665 4666 /* TRC1 Transmit Ready Control 1 4667 * 4668 * 07..05 Reserved, must be 0 4669 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full) 4670 */ 4671 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1)); 4672 4673 /* DMR, DMA Mode Register 4674 * 4675 * 07..05 Reserved, must be 0 4676 * 04 TMOD, Transfer Mode: 1=chained-block 4677 * 03 Reserved, must be 0 4678 * 02 NF, Number of Frames: 1=multi-frame 4679 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled 4680 * 00 Reserved, must be 0 4681 * 4682 * 0001 0100 4683 */ 4684 write_reg(info, TXDMA + DMR, 0x14); 4685 write_reg(info, RXDMA + DMR, 0x14); 4686 4687 /* Set chain pointer base (upper 8 bits of 24 bit addr) */ 4688 write_reg(info, RXDMA + CPB, 4689 (unsigned char)(info->buffer_list_phys >> 16)); 4690 4691 /* Set chain pointer base (upper 8 bits of 24 bit addr) */ 4692 write_reg(info, TXDMA + CPB, 4693 (unsigned char)(info->buffer_list_phys >> 16)); 4694 4695 /* enable status interrupts. other code enables/disables 4696 * the individual sources for these two interrupt classes. 4697 */ 4698 info->ie0_value |= TXINTE + RXINTE; 4699 write_reg(info, IE0, info->ie0_value); 4700 4701 /* CTL, MSCI control register 4702 * 4703 * 07..06 Reserved, set to 0 4704 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) 4705 * 04 IDLC, idle control, 0=mark 1=idle register 4706 * 03 BRK, break, 0=off 1 =on (async) 4707 * 02 SYNCLD, sync char load enable (BSC) 1=enabled 4708 * 01 GOP, go active on poll (LOOP mode) 1=enabled 4709 * 00 RTS, RTS output control, 0=active 1=inactive 4710 * 4711 * 0001 0001 4712 */ 4713 RegValue = 0x10; 4714 if (!(info->serial_signals & SerialSignal_RTS)) 4715 RegValue |= 0x01; 4716 write_reg(info, CTL, RegValue); 4717 4718 /* preamble not supported ! */ 4719 4720 tx_set_idle(info); 4721 tx_stop(info); 4722 rx_stop(info); 4723 4724 set_rate(info, info->params.clock_speed); 4725 4726 if (info->params.loopback) 4727 enable_loopback(info,1); 4728 } 4729 4730 /* Set the transmit HDLC idle mode 4731 */ 4732 static void tx_set_idle(SLMP_INFO *info) 4733 { 4734 unsigned char RegValue = 0xff; 4735 4736 /* Map API idle mode to SCA register bits */ 4737 switch(info->idle_mode) { 4738 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break; 4739 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break; 4740 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break; 4741 case HDLC_TXIDLE_ONES: RegValue = 0xff; break; 4742 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break; 4743 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break; 4744 case HDLC_TXIDLE_MARK: RegValue = 0xff; break; 4745 } 4746 4747 write_reg(info, IDL, RegValue); 4748 } 4749 4750 /* Query the adapter for the state of the V24 status (input) signals. 4751 */ 4752 static void get_signals(SLMP_INFO *info) 4753 { 4754 u16 status = read_reg(info, SR3); 4755 u16 gpstatus = read_status_reg(info); 4756 u16 testbit; 4757 4758 /* clear all serial signals except RTS and DTR */ 4759 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR; 4760 4761 /* set serial signal bits to reflect MISR */ 4762 4763 if (!(status & BIT3)) 4764 info->serial_signals |= SerialSignal_CTS; 4765 4766 if ( !(status & BIT2)) 4767 info->serial_signals |= SerialSignal_DCD; 4768 4769 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7> 4770 if (!(gpstatus & testbit)) 4771 info->serial_signals |= SerialSignal_RI; 4772 4773 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6> 4774 if (!(gpstatus & testbit)) 4775 info->serial_signals |= SerialSignal_DSR; 4776 } 4777 4778 /* Set the state of RTS and DTR based on contents of 4779 * serial_signals member of device context. 4780 */ 4781 static void set_signals(SLMP_INFO *info) 4782 { 4783 unsigned char RegValue; 4784 u16 EnableBit; 4785 4786 RegValue = read_reg(info, CTL); 4787 if (info->serial_signals & SerialSignal_RTS) 4788 RegValue &= ~BIT0; 4789 else 4790 RegValue |= BIT0; 4791 write_reg(info, CTL, RegValue); 4792 4793 // Port 0..3 DTR is ctrl reg <1,3,5,7> 4794 EnableBit = BIT1 << (info->port_num*2); 4795 if (info->serial_signals & SerialSignal_DTR) 4796 info->port_array[0]->ctrlreg_value &= ~EnableBit; 4797 else 4798 info->port_array[0]->ctrlreg_value |= EnableBit; 4799 write_control_reg(info); 4800 } 4801 4802 /*******************/ 4803 /* DMA Buffer Code */ 4804 /*******************/ 4805 4806 /* Set the count for all receive buffers to SCABUFSIZE 4807 * and set the current buffer to the first buffer. This effectively 4808 * makes all buffers free and discards any data in buffers. 4809 */ 4810 static void rx_reset_buffers(SLMP_INFO *info) 4811 { 4812 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1); 4813 } 4814 4815 /* Free the buffers used by a received frame 4816 * 4817 * info pointer to device instance data 4818 * first index of 1st receive buffer of frame 4819 * last index of last receive buffer of frame 4820 */ 4821 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last) 4822 { 4823 bool done = false; 4824 4825 while(!done) { 4826 /* reset current buffer for reuse */ 4827 info->rx_buf_list[first].status = 0xff; 4828 4829 if (first == last) { 4830 done = true; 4831 /* set new last rx descriptor address */ 4832 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry); 4833 } 4834 4835 first++; 4836 if (first == info->rx_buf_count) 4837 first = 0; 4838 } 4839 4840 /* set current buffer to next buffer after last buffer of frame */ 4841 info->current_rx_buf = first; 4842 } 4843 4844 /* Return a received frame from the receive DMA buffers. 4845 * Only frames received without errors are returned. 4846 * 4847 * Return Value: true if frame returned, otherwise false 4848 */ 4849 static bool rx_get_frame(SLMP_INFO *info) 4850 { 4851 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ 4852 unsigned short status; 4853 unsigned int framesize = 0; 4854 bool ReturnCode = false; 4855 unsigned long flags; 4856 struct tty_struct *tty = info->port.tty; 4857 unsigned char addr_field = 0xff; 4858 SCADESC *desc; 4859 SCADESC_EX *desc_ex; 4860 4861 CheckAgain: 4862 /* assume no frame returned, set zero length */ 4863 framesize = 0; 4864 addr_field = 0xff; 4865 4866 /* 4867 * current_rx_buf points to the 1st buffer of the next available 4868 * receive frame. To find the last buffer of the frame look for 4869 * a non-zero status field in the buffer entries. (The status 4870 * field is set by the 16C32 after completing a receive frame. 4871 */ 4872 StartIndex = EndIndex = info->current_rx_buf; 4873 4874 for ( ;; ) { 4875 desc = &info->rx_buf_list[EndIndex]; 4876 desc_ex = &info->rx_buf_list_ex[EndIndex]; 4877 4878 if (desc->status == 0xff) 4879 goto Cleanup; /* current desc still in use, no frames available */ 4880 4881 if (framesize == 0 && info->params.addr_filter != 0xff) 4882 addr_field = desc_ex->virt_addr[0]; 4883 4884 framesize += desc->length; 4885 4886 /* Status != 0 means last buffer of frame */ 4887 if (desc->status) 4888 break; 4889 4890 EndIndex++; 4891 if (EndIndex == info->rx_buf_count) 4892 EndIndex = 0; 4893 4894 if (EndIndex == info->current_rx_buf) { 4895 /* all buffers have been 'used' but none mark */ 4896 /* the end of a frame. Reset buffers and receiver. */ 4897 if ( info->rx_enabled ){ 4898 spin_lock_irqsave(&info->lock,flags); 4899 rx_start(info); 4900 spin_unlock_irqrestore(&info->lock,flags); 4901 } 4902 goto Cleanup; 4903 } 4904 4905 } 4906 4907 /* check status of receive frame */ 4908 4909 /* frame status is byte stored after frame data 4910 * 4911 * 7 EOM (end of msg), 1 = last buffer of frame 4912 * 6 Short Frame, 1 = short frame 4913 * 5 Abort, 1 = frame aborted 4914 * 4 Residue, 1 = last byte is partial 4915 * 3 Overrun, 1 = overrun occurred during frame reception 4916 * 2 CRC, 1 = CRC error detected 4917 * 4918 */ 4919 status = desc->status; 4920 4921 /* ignore CRC bit if not using CRC (bit is undefined) */ 4922 /* Note:CRC is not save to data buffer */ 4923 if (info->params.crc_type == HDLC_CRC_NONE) 4924 status &= ~BIT2; 4925 4926 if (framesize == 0 || 4927 (addr_field != 0xff && addr_field != info->params.addr_filter)) { 4928 /* discard 0 byte frames, this seems to occur sometime 4929 * when remote is idling flags. 4930 */ 4931 rx_free_frame_buffers(info, StartIndex, EndIndex); 4932 goto CheckAgain; 4933 } 4934 4935 if (framesize < 2) 4936 status |= BIT6; 4937 4938 if (status & (BIT6+BIT5+BIT3+BIT2)) { 4939 /* received frame has errors, 4940 * update counts and mark frame size as 0 4941 */ 4942 if (status & BIT6) 4943 info->icount.rxshort++; 4944 else if (status & BIT5) 4945 info->icount.rxabort++; 4946 else if (status & BIT3) 4947 info->icount.rxover++; 4948 else 4949 info->icount.rxcrc++; 4950 4951 framesize = 0; 4952 #if SYNCLINK_GENERIC_HDLC 4953 { 4954 info->netdev->stats.rx_errors++; 4955 info->netdev->stats.rx_frame_errors++; 4956 } 4957 #endif 4958 } 4959 4960 if ( debug_level >= DEBUG_LEVEL_BH ) 4961 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n", 4962 __FILE__,__LINE__,info->device_name,status,framesize); 4963 4964 if ( debug_level >= DEBUG_LEVEL_DATA ) 4965 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr, 4966 min_t(unsigned int, framesize, SCABUFSIZE), 0); 4967 4968 if (framesize) { 4969 if (framesize > info->max_frame_size) 4970 info->icount.rxlong++; 4971 else { 4972 /* copy dma buffer(s) to contiguous intermediate buffer */ 4973 int copy_count = framesize; 4974 int index = StartIndex; 4975 unsigned char *ptmp = info->tmp_rx_buf; 4976 info->tmp_rx_buf_count = framesize; 4977 4978 info->icount.rxok++; 4979 4980 while(copy_count) { 4981 int partial_count = min(copy_count,SCABUFSIZE); 4982 memcpy( ptmp, 4983 info->rx_buf_list_ex[index].virt_addr, 4984 partial_count ); 4985 ptmp += partial_count; 4986 copy_count -= partial_count; 4987 4988 if ( ++index == info->rx_buf_count ) 4989 index = 0; 4990 } 4991 4992 #if SYNCLINK_GENERIC_HDLC 4993 if (info->netcount) 4994 hdlcdev_rx(info,info->tmp_rx_buf,framesize); 4995 else 4996 #endif 4997 ldisc_receive_buf(tty,info->tmp_rx_buf, 4998 info->flag_buf, framesize); 4999 } 5000 } 5001 /* Free the buffers used by this frame. */ 5002 rx_free_frame_buffers( info, StartIndex, EndIndex ); 5003 5004 ReturnCode = true; 5005 5006 Cleanup: 5007 if ( info->rx_enabled && info->rx_overflow ) { 5008 /* Receiver is enabled, but needs to restarted due to 5009 * rx buffer overflow. If buffers are empty, restart receiver. 5010 */ 5011 if (info->rx_buf_list[EndIndex].status == 0xff) { 5012 spin_lock_irqsave(&info->lock,flags); 5013 rx_start(info); 5014 spin_unlock_irqrestore(&info->lock,flags); 5015 } 5016 } 5017 5018 return ReturnCode; 5019 } 5020 5021 /* load the transmit DMA buffer with data 5022 */ 5023 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count) 5024 { 5025 unsigned short copy_count; 5026 unsigned int i = 0; 5027 SCADESC *desc; 5028 SCADESC_EX *desc_ex; 5029 5030 if ( debug_level >= DEBUG_LEVEL_DATA ) 5031 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1); 5032 5033 /* Copy source buffer to one or more DMA buffers, starting with 5034 * the first transmit dma buffer. 5035 */ 5036 for(i=0;;) 5037 { 5038 copy_count = min_t(unsigned int, count, SCABUFSIZE); 5039 5040 desc = &info->tx_buf_list[i]; 5041 desc_ex = &info->tx_buf_list_ex[i]; 5042 5043 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count); 5044 5045 desc->length = copy_count; 5046 desc->status = 0; 5047 5048 buf += copy_count; 5049 count -= copy_count; 5050 5051 if (!count) 5052 break; 5053 5054 i++; 5055 if (i >= info->tx_buf_count) 5056 i = 0; 5057 } 5058 5059 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */ 5060 info->last_tx_buf = ++i; 5061 } 5062 5063 static bool register_test(SLMP_INFO *info) 5064 { 5065 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96}; 5066 static unsigned int count = ARRAY_SIZE(testval); 5067 unsigned int i; 5068 bool rc = true; 5069 unsigned long flags; 5070 5071 spin_lock_irqsave(&info->lock,flags); 5072 reset_port(info); 5073 5074 /* assume failure */ 5075 info->init_error = DiagStatus_AddressFailure; 5076 5077 /* Write bit patterns to various registers but do it out of */ 5078 /* sync, then read back and verify values. */ 5079 5080 for (i = 0 ; i < count ; i++) { 5081 write_reg(info, TMC, testval[i]); 5082 write_reg(info, IDL, testval[(i+1)%count]); 5083 write_reg(info, SA0, testval[(i+2)%count]); 5084 write_reg(info, SA1, testval[(i+3)%count]); 5085 5086 if ( (read_reg(info, TMC) != testval[i]) || 5087 (read_reg(info, IDL) != testval[(i+1)%count]) || 5088 (read_reg(info, SA0) != testval[(i+2)%count]) || 5089 (read_reg(info, SA1) != testval[(i+3)%count]) ) 5090 { 5091 rc = false; 5092 break; 5093 } 5094 } 5095 5096 reset_port(info); 5097 spin_unlock_irqrestore(&info->lock,flags); 5098 5099 return rc; 5100 } 5101 5102 static bool irq_test(SLMP_INFO *info) 5103 { 5104 unsigned long timeout; 5105 unsigned long flags; 5106 5107 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; 5108 5109 spin_lock_irqsave(&info->lock,flags); 5110 reset_port(info); 5111 5112 /* assume failure */ 5113 info->init_error = DiagStatus_IrqFailure; 5114 info->irq_occurred = false; 5115 5116 /* setup timer0 on SCA0 to interrupt */ 5117 5118 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */ 5119 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); 5120 5121 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */ 5122 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */ 5123 5124 5125 /* TMCS, Timer Control/Status Register 5126 * 5127 * 07 CMF, Compare match flag (read only) 1=match 5128 * 06 ECMI, CMF Interrupt Enable: 1=enabled 5129 * 05 Reserved, must be 0 5130 * 04 TME, Timer Enable 5131 * 03..00 Reserved, must be 0 5132 * 5133 * 0101 0000 5134 */ 5135 write_reg(info, (unsigned char)(timer + TMCS), 0x50); 5136 5137 spin_unlock_irqrestore(&info->lock,flags); 5138 5139 timeout=100; 5140 while( timeout-- && !info->irq_occurred ) { 5141 msleep_interruptible(10); 5142 } 5143 5144 spin_lock_irqsave(&info->lock,flags); 5145 reset_port(info); 5146 spin_unlock_irqrestore(&info->lock,flags); 5147 5148 return info->irq_occurred; 5149 } 5150 5151 /* initialize individual SCA device (2 ports) 5152 */ 5153 static bool sca_init(SLMP_INFO *info) 5154 { 5155 /* set wait controller to single mem partition (low), no wait states */ 5156 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */ 5157 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */ 5158 write_reg(info, WCRL, 0); /* wait controller low range */ 5159 write_reg(info, WCRM, 0); /* wait controller mid range */ 5160 write_reg(info, WCRH, 0); /* wait controller high range */ 5161 5162 /* DPCR, DMA Priority Control 5163 * 5164 * 07..05 Not used, must be 0 5165 * 04 BRC, bus release condition: 0=all transfers complete 5166 * 03 CCC, channel change condition: 0=every cycle 5167 * 02..00 PR<2..0>, priority 100=round robin 5168 * 5169 * 00000100 = 0x04 5170 */ 5171 write_reg(info, DPCR, dma_priority); 5172 5173 /* DMA Master Enable, BIT7: 1=enable all channels */ 5174 write_reg(info, DMER, 0x80); 5175 5176 /* enable all interrupt classes */ 5177 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */ 5178 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */ 5179 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */ 5180 5181 /* ITCR, interrupt control register 5182 * 07 IPC, interrupt priority, 0=MSCI->DMA 5183 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle 5184 * 04 VOS, Vector Output, 0=unmodified vector 5185 * 03..00 Reserved, must be 0 5186 */ 5187 write_reg(info, ITCR, 0); 5188 5189 return true; 5190 } 5191 5192 /* initialize adapter hardware 5193 */ 5194 static bool init_adapter(SLMP_INFO *info) 5195 { 5196 int i; 5197 5198 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */ 5199 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); 5200 u32 readval; 5201 5202 info->misc_ctrl_value |= BIT30; 5203 *MiscCtrl = info->misc_ctrl_value; 5204 5205 /* 5206 * Force at least 170ns delay before clearing 5207 * reset bit. Each read from LCR takes at least 5208 * 30ns so 10 times for 300ns to be safe. 5209 */ 5210 for(i=0;i<10;i++) 5211 readval = *MiscCtrl; 5212 5213 info->misc_ctrl_value &= ~BIT30; 5214 *MiscCtrl = info->misc_ctrl_value; 5215 5216 /* init control reg (all DTRs off, all clksel=input) */ 5217 info->ctrlreg_value = 0xaa; 5218 write_control_reg(info); 5219 5220 { 5221 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c); 5222 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3); 5223 5224 switch(read_ahead_count) 5225 { 5226 case 16: 5227 lcr1_brdr_value |= BIT5 + BIT4 + BIT3; 5228 break; 5229 case 8: 5230 lcr1_brdr_value |= BIT5 + BIT4; 5231 break; 5232 case 4: 5233 lcr1_brdr_value |= BIT5 + BIT3; 5234 break; 5235 case 0: 5236 lcr1_brdr_value |= BIT5; 5237 break; 5238 } 5239 5240 *LCR1BRDR = lcr1_brdr_value; 5241 *MiscCtrl = misc_ctrl_value; 5242 } 5243 5244 sca_init(info->port_array[0]); 5245 sca_init(info->port_array[2]); 5246 5247 return true; 5248 } 5249 5250 /* Loopback an HDLC frame to test the hardware 5251 * interrupt and DMA functions. 5252 */ 5253 static bool loopback_test(SLMP_INFO *info) 5254 { 5255 #define TESTFRAMESIZE 20 5256 5257 unsigned long timeout; 5258 u16 count = TESTFRAMESIZE; 5259 unsigned char buf[TESTFRAMESIZE]; 5260 bool rc = false; 5261 unsigned long flags; 5262 5263 struct tty_struct *oldtty = info->port.tty; 5264 u32 speed = info->params.clock_speed; 5265 5266 info->params.clock_speed = 3686400; 5267 info->port.tty = NULL; 5268 5269 /* assume failure */ 5270 info->init_error = DiagStatus_DmaFailure; 5271 5272 /* build and send transmit frame */ 5273 for (count = 0; count < TESTFRAMESIZE;++count) 5274 buf[count] = (unsigned char)count; 5275 5276 memset(info->tmp_rx_buf,0,TESTFRAMESIZE); 5277 5278 /* program hardware for HDLC and enabled receiver */ 5279 spin_lock_irqsave(&info->lock,flags); 5280 hdlc_mode(info); 5281 enable_loopback(info,1); 5282 rx_start(info); 5283 info->tx_count = count; 5284 tx_load_dma_buffer(info,buf,count); 5285 tx_start(info); 5286 spin_unlock_irqrestore(&info->lock,flags); 5287 5288 /* wait for receive complete */ 5289 /* Set a timeout for waiting for interrupt. */ 5290 for ( timeout = 100; timeout; --timeout ) { 5291 msleep_interruptible(10); 5292 5293 if (rx_get_frame(info)) { 5294 rc = true; 5295 break; 5296 } 5297 } 5298 5299 /* verify received frame length and contents */ 5300 if (rc && 5301 ( info->tmp_rx_buf_count != count || 5302 memcmp(buf, info->tmp_rx_buf,count))) { 5303 rc = false; 5304 } 5305 5306 spin_lock_irqsave(&info->lock,flags); 5307 reset_adapter(info); 5308 spin_unlock_irqrestore(&info->lock,flags); 5309 5310 info->params.clock_speed = speed; 5311 info->port.tty = oldtty; 5312 5313 return rc; 5314 } 5315 5316 /* Perform diagnostics on hardware 5317 */ 5318 static int adapter_test( SLMP_INFO *info ) 5319 { 5320 unsigned long flags; 5321 if ( debug_level >= DEBUG_LEVEL_INFO ) 5322 printk( "%s(%d):Testing device %s\n", 5323 __FILE__,__LINE__,info->device_name ); 5324 5325 spin_lock_irqsave(&info->lock,flags); 5326 init_adapter(info); 5327 spin_unlock_irqrestore(&info->lock,flags); 5328 5329 info->port_array[0]->port_count = 0; 5330 5331 if ( register_test(info->port_array[0]) && 5332 register_test(info->port_array[1])) { 5333 5334 info->port_array[0]->port_count = 2; 5335 5336 if ( register_test(info->port_array[2]) && 5337 register_test(info->port_array[3]) ) 5338 info->port_array[0]->port_count += 2; 5339 } 5340 else { 5341 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n", 5342 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base)); 5343 return -ENODEV; 5344 } 5345 5346 if ( !irq_test(info->port_array[0]) || 5347 !irq_test(info->port_array[1]) || 5348 (info->port_count == 4 && !irq_test(info->port_array[2])) || 5349 (info->port_count == 4 && !irq_test(info->port_array[3]))) { 5350 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", 5351 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); 5352 return -ENODEV; 5353 } 5354 5355 if (!loopback_test(info->port_array[0]) || 5356 !loopback_test(info->port_array[1]) || 5357 (info->port_count == 4 && !loopback_test(info->port_array[2])) || 5358 (info->port_count == 4 && !loopback_test(info->port_array[3]))) { 5359 printk( "%s(%d):DMA test failure for device %s\n", 5360 __FILE__,__LINE__,info->device_name); 5361 return -ENODEV; 5362 } 5363 5364 if ( debug_level >= DEBUG_LEVEL_INFO ) 5365 printk( "%s(%d):device %s passed diagnostics\n", 5366 __FILE__,__LINE__,info->device_name ); 5367 5368 info->port_array[0]->init_error = 0; 5369 info->port_array[1]->init_error = 0; 5370 if ( info->port_count > 2 ) { 5371 info->port_array[2]->init_error = 0; 5372 info->port_array[3]->init_error = 0; 5373 } 5374 5375 return 0; 5376 } 5377 5378 /* Test the shared memory on a PCI adapter. 5379 */ 5380 static bool memory_test(SLMP_INFO *info) 5381 { 5382 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa, 5383 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; 5384 unsigned long count = ARRAY_SIZE(testval); 5385 unsigned long i; 5386 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long); 5387 unsigned long * addr = (unsigned long *)info->memory_base; 5388 5389 /* Test data lines with test pattern at one location. */ 5390 5391 for ( i = 0 ; i < count ; i++ ) { 5392 *addr = testval[i]; 5393 if ( *addr != testval[i] ) 5394 return false; 5395 } 5396 5397 /* Test address lines with incrementing pattern over */ 5398 /* entire address range. */ 5399 5400 for ( i = 0 ; i < limit ; i++ ) { 5401 *addr = i * 4; 5402 addr++; 5403 } 5404 5405 addr = (unsigned long *)info->memory_base; 5406 5407 for ( i = 0 ; i < limit ; i++ ) { 5408 if ( *addr != i * 4 ) 5409 return false; 5410 addr++; 5411 } 5412 5413 memset( info->memory_base, 0, SCA_MEM_SIZE ); 5414 return true; 5415 } 5416 5417 /* Load data into PCI adapter shared memory. 5418 * 5419 * The PCI9050 releases control of the local bus 5420 * after completing the current read or write operation. 5421 * 5422 * While the PCI9050 write FIFO not empty, the 5423 * PCI9050 treats all of the writes as a single transaction 5424 * and does not release the bus. This causes DMA latency problems 5425 * at high speeds when copying large data blocks to the shared memory. 5426 * 5427 * This function breaks a write into multiple transations by 5428 * interleaving a read which flushes the write FIFO and 'completes' 5429 * the write transation. This allows any pending DMA request to gain control 5430 * of the local bus in a timely fasion. 5431 */ 5432 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count) 5433 { 5434 /* A load interval of 16 allows for 4 32-bit writes at */ 5435 /* 136ns each for a maximum latency of 542ns on the local bus.*/ 5436 5437 unsigned short interval = count / sca_pci_load_interval; 5438 unsigned short i; 5439 5440 for ( i = 0 ; i < interval ; i++ ) 5441 { 5442 memcpy(dest, src, sca_pci_load_interval); 5443 read_status_reg(info); 5444 dest += sca_pci_load_interval; 5445 src += sca_pci_load_interval; 5446 } 5447 5448 memcpy(dest, src, count % sca_pci_load_interval); 5449 } 5450 5451 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit) 5452 { 5453 int i; 5454 int linecount; 5455 if (xmit) 5456 printk("%s tx data:\n",info->device_name); 5457 else 5458 printk("%s rx data:\n",info->device_name); 5459 5460 while(count) { 5461 if (count > 16) 5462 linecount = 16; 5463 else 5464 linecount = count; 5465 5466 for(i=0;i<linecount;i++) 5467 printk("%02X ",(unsigned char)data[i]); 5468 for(;i<17;i++) 5469 printk(" "); 5470 for(i=0;i<linecount;i++) { 5471 if (data[i]>=040 && data[i]<=0176) 5472 printk("%c",data[i]); 5473 else 5474 printk("."); 5475 } 5476 printk("\n"); 5477 5478 data += linecount; 5479 count -= linecount; 5480 } 5481 } /* end of trace_block() */ 5482 5483 /* called when HDLC frame times out 5484 * update stats and do tx completion processing 5485 */ 5486 static void tx_timeout(unsigned long context) 5487 { 5488 SLMP_INFO *info = (SLMP_INFO*)context; 5489 unsigned long flags; 5490 5491 if ( debug_level >= DEBUG_LEVEL_INFO ) 5492 printk( "%s(%d):%s tx_timeout()\n", 5493 __FILE__,__LINE__,info->device_name); 5494 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { 5495 info->icount.txtimeout++; 5496 } 5497 spin_lock_irqsave(&info->lock,flags); 5498 info->tx_active = false; 5499 info->tx_count = info->tx_put = info->tx_get = 0; 5500 5501 spin_unlock_irqrestore(&info->lock,flags); 5502 5503 #if SYNCLINK_GENERIC_HDLC 5504 if (info->netcount) 5505 hdlcdev_tx_done(info); 5506 else 5507 #endif 5508 bh_transmit(info); 5509 } 5510 5511 /* called to periodically check the DSR/RI modem signal input status 5512 */ 5513 static void status_timeout(unsigned long context) 5514 { 5515 u16 status = 0; 5516 SLMP_INFO *info = (SLMP_INFO*)context; 5517 unsigned long flags; 5518 unsigned char delta; 5519 5520 5521 spin_lock_irqsave(&info->lock,flags); 5522 get_signals(info); 5523 spin_unlock_irqrestore(&info->lock,flags); 5524 5525 /* check for DSR/RI state change */ 5526 5527 delta = info->old_signals ^ info->serial_signals; 5528 info->old_signals = info->serial_signals; 5529 5530 if (delta & SerialSignal_DSR) 5531 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR); 5532 5533 if (delta & SerialSignal_RI) 5534 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI); 5535 5536 if (delta & SerialSignal_DCD) 5537 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD); 5538 5539 if (delta & SerialSignal_CTS) 5540 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS); 5541 5542 if (status) 5543 isr_io_pin(info,status); 5544 5545 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); 5546 } 5547 5548 5549 /* Register Access Routines - 5550 * All registers are memory mapped 5551 */ 5552 #define CALC_REGADDR() \ 5553 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 5554 if (info->port_num > 1) \ 5555 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \ 5556 if ( info->port_num & 1) { \ 5557 if (Addr > 0x7f) \ 5558 RegAddr += 0x40; /* DMA access */ \ 5559 else if (Addr > 0x1f && Addr < 0x60) \ 5560 RegAddr += 0x20; /* MSCI access */ \ 5561 } 5562 5563 5564 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr) 5565 { 5566 CALC_REGADDR(); 5567 return *RegAddr; 5568 } 5569 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) 5570 { 5571 CALC_REGADDR(); 5572 *RegAddr = Value; 5573 } 5574 5575 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr) 5576 { 5577 CALC_REGADDR(); 5578 return *((u16 *)RegAddr); 5579 } 5580 5581 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value) 5582 { 5583 CALC_REGADDR(); 5584 *((u16 *)RegAddr) = Value; 5585 } 5586 5587 static unsigned char read_status_reg(SLMP_INFO * info) 5588 { 5589 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; 5590 return *RegAddr; 5591 } 5592 5593 static void write_control_reg(SLMP_INFO * info) 5594 { 5595 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; 5596 *RegAddr = info->port_array[0]->ctrlreg_value; 5597 } 5598 5599 5600 static int synclinkmp_init_one (struct pci_dev *dev, 5601 const struct pci_device_id *ent) 5602 { 5603 if (pci_enable_device(dev)) { 5604 printk("error enabling pci device %p\n", dev); 5605 return -EIO; 5606 } 5607 device_init( ++synclinkmp_adapter_count, dev ); 5608 return 0; 5609 } 5610 5611 static void synclinkmp_remove_one (struct pci_dev *dev) 5612 { 5613 } 5614 5615 5616 5617 5618 5619 /* LDV_COMMENT_BEGIN_MAIN */ 5620 #ifdef LDV_MAIN0_sequence_infinite_withcheck_stateful 5621 5622 /*###########################################################################*/ 5623 5624 /*############## Driver Environment Generator 0.2 output ####################*/ 5625 5626 /*###########################################################################*/ 5627 5628 5629 5630 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test if all kernel resources are correctly released by driver before driver will be unloaded. */ 5631 void ldv_check_final_state(void); 5632 5633 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result. */ 5634 void ldv_check_return_value(int res); 5635 5636 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result of probe() function. */ 5637 void ldv_check_return_value_probe(int res); 5638 5639 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Initializes the model. */ 5640 void ldv_initialize(void); 5641 5642 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Reinitializes the model between distinct model function calls. */ 5643 void ldv_handler_precall(void); 5644 5645 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Returns arbitrary interger value. */ 5646 int nondet_int(void); 5647 5648 /* LDV_COMMENT_VAR_DECLARE_LDV Special variable for LDV verifier. */ 5649 int LDV_IN_INTERRUPT; 5650 5651 /* LDV_COMMENT_FUNCTION_MAIN Main function for LDV verifier. */ 5652 void ldv_main0_sequence_infinite_withcheck_stateful(void) { 5653 5654 5655 5656 /* LDV_COMMENT_BEGIN_VARIABLE_DECLARATION_PART */ 5657 /*============================= VARIABLE DECLARATION PART =============================*/ 5658 /** STRUCT: struct type: pci_driver, struct name: synclinkmp_pci_driver **/ 5659 /* content: static int synclinkmp_init_one (struct pci_dev *dev, const struct pci_device_id *ent)*/ 5660 /* LDV_COMMENT_BEGIN_PREP */ 5661 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 5662 #if defined(__i386__) 5663 # define BREAKPOINT() asm(" int $3"); 5664 #else 5665 # define BREAKPOINT() { } 5666 #endif 5667 #define MAX_DEVICES 12 5668 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 5669 #define SYNCLINK_GENERIC_HDLC 1 5670 #else 5671 #define SYNCLINK_GENERIC_HDLC 0 5672 #endif 5673 #define GET_USER(error,value,addr) error = get_user(value,addr) 5674 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 5675 #define PUT_USER(error,value,addr) error = put_user(value,addr) 5676 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 5677 #define SCABUFSIZE 1024 5678 #define SCA_MEM_SIZE 0x40000 5679 #define SCA_BASE_SIZE 512 5680 #define SCA_REG_SIZE 16 5681 #define SCA_MAX_PORTS 4 5682 #define SCAMAXDESC 128 5683 #define BUFFERLISTSIZE 4096 5684 #define BH_RECEIVE 1 5685 #define BH_TRANSMIT 2 5686 #define BH_STATUS 4 5687 #define IO_PIN_SHUTDOWN_LIMIT 100 5688 #if SYNCLINK_GENERIC_HDLC 5689 #endif 5690 #define MGSL_MAGIC 0x5401 5691 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 5692 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 5693 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 5694 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 5695 #define LPR 0x00 5696 #define PABR0 0x02 5697 #define PABR1 0x03 5698 #define WCRL 0x04 5699 #define WCRM 0x05 5700 #define WCRH 0x06 5701 #define DPCR 0x08 5702 #define DMER 0x09 5703 #define ISR0 0x10 5704 #define ISR1 0x11 5705 #define ISR2 0x12 5706 #define IER0 0x14 5707 #define IER1 0x15 5708 #define IER2 0x16 5709 #define ITCR 0x18 5710 #define INTVR 0x1a 5711 #define IMVR 0x1c 5712 #define TRB 0x20 5713 #define TRBL 0x20 5714 #define TRBH 0x21 5715 #define SR0 0x22 5716 #define SR1 0x23 5717 #define SR2 0x24 5718 #define SR3 0x25 5719 #define FST 0x26 5720 #define IE0 0x28 5721 #define IE1 0x29 5722 #define IE2 0x2a 5723 #define FIE 0x2b 5724 #define CMD 0x2c 5725 #define MD0 0x2e 5726 #define MD1 0x2f 5727 #define MD2 0x30 5728 #define CTL 0x31 5729 #define SA0 0x32 5730 #define SA1 0x33 5731 #define IDL 0x34 5732 #define TMC 0x35 5733 #define RXS 0x36 5734 #define TXS 0x37 5735 #define TRC0 0x38 5736 #define TRC1 0x39 5737 #define RRC 0x3a 5738 #define CST0 0x3c 5739 #define CST1 0x3d 5740 #define TCNT 0x60 5741 #define TCNTL 0x60 5742 #define TCNTH 0x61 5743 #define TCONR 0x62 5744 #define TCONRL 0x62 5745 #define TCONRH 0x63 5746 #define TMCS 0x64 5747 #define TEPR 0x65 5748 #define DARL 0x80 5749 #define DARH 0x81 5750 #define DARB 0x82 5751 #define BAR 0x80 5752 #define BARL 0x80 5753 #define BARH 0x81 5754 #define BARB 0x82 5755 #define SAR 0x84 5756 #define SARL 0x84 5757 #define SARH 0x85 5758 #define SARB 0x86 5759 #define CPB 0x86 5760 #define CDA 0x88 5761 #define CDAL 0x88 5762 #define CDAH 0x89 5763 #define EDA 0x8a 5764 #define EDAL 0x8a 5765 #define EDAH 0x8b 5766 #define BFL 0x8c 5767 #define BFLL 0x8c 5768 #define BFLH 0x8d 5769 #define BCR 0x8e 5770 #define BCRL 0x8e 5771 #define BCRH 0x8f 5772 #define DSR 0x90 5773 #define DMR 0x91 5774 #define FCT 0x93 5775 #define DIR 0x94 5776 #define DCMD 0x95 5777 #define TIMER0 0x00 5778 #define TIMER1 0x08 5779 #define TIMER2 0x10 5780 #define TIMER3 0x18 5781 #define RXDMA 0x00 5782 #define TXDMA 0x20 5783 #define NOOP 0x00 5784 #define TXRESET 0x01 5785 #define TXENABLE 0x02 5786 #define TXDISABLE 0x03 5787 #define TXCRCINIT 0x04 5788 #define TXCRCEXCL 0x05 5789 #define TXEOM 0x06 5790 #define TXABORT 0x07 5791 #define MPON 0x08 5792 #define TXBUFCLR 0x09 5793 #define RXRESET 0x11 5794 #define RXENABLE 0x12 5795 #define RXDISABLE 0x13 5796 #define RXCRCINIT 0x14 5797 #define RXREJECT 0x15 5798 #define SEARCHMP 0x16 5799 #define RXCRCEXCL 0x17 5800 #define RXCRCCALC 0x18 5801 #define CHRESET 0x21 5802 #define HUNT 0x31 5803 #define SWABORT 0x01 5804 #define FEICLEAR 0x02 5805 #define TXINTE BIT7 5806 #define RXINTE BIT6 5807 #define TXRDYE BIT1 5808 #define RXRDYE BIT0 5809 #define UDRN BIT7 5810 #define IDLE BIT6 5811 #define SYNCD BIT4 5812 #define FLGD BIT4 5813 #define CCTS BIT3 5814 #define CDCD BIT2 5815 #define BRKD BIT1 5816 #define ABTD BIT1 5817 #define GAPD BIT1 5818 #define BRKE BIT0 5819 #define IDLD BIT0 5820 #define EOM BIT7 5821 #define PMP BIT6 5822 #define SHRT BIT6 5823 #define PE BIT5 5824 #define ABT BIT5 5825 #define FRME BIT4 5826 #define RBIT BIT4 5827 #define OVRN BIT3 5828 #define CRCE BIT2 5829 #define WAKEUP_CHARS 256 5830 #if SYNCLINK_GENERIC_HDLC 5831 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 5832 #endif 5833 #ifdef SANITY_CHECK 5834 #else 5835 #endif 5836 #if SYNCLINK_GENERIC_HDLC 5837 #endif 5838 #if SYNCLINK_GENERIC_HDLC 5839 #endif 5840 #if SYNCLINK_GENERIC_HDLC 5841 #endif 5842 #ifdef CMSPAR 5843 #endif 5844 #if SYNCLINK_GENERIC_HDLC 5845 #endif 5846 #if SYNCLINK_GENERIC_HDLC 5847 #endif 5848 #if 0 5849 #endif 5850 #if SYNCLINK_GENERIC_HDLC 5851 #endif 5852 #if SYNCLINK_GENERIC_HDLC 5853 #endif 5854 #define TESTFRAMESIZE 20 5855 #if SYNCLINK_GENERIC_HDLC 5856 #endif 5857 #define CALC_REGADDR() \ 5858 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 5859 if (info->port_num > 1) \ 5860 RegAddr += 256; \ 5861 if ( info->port_num & 1) { \ 5862 if (Addr > 0x7f) \ 5863 RegAddr += 0x40; \ 5864 else if (Addr > 0x1f && Addr < 0x60) \ 5865 RegAddr += 0x20; \ 5866 } 5867 /* LDV_COMMENT_END_PREP */ 5868 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_init_one" */ 5869 struct pci_dev * var_group1; 5870 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_init_one" */ 5871 const struct pci_device_id * var_synclinkmp_init_one_121_p1; 5872 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "synclinkmp_init_one" */ 5873 static int res_synclinkmp_init_one_121; 5874 /* content: static void synclinkmp_remove_one (struct pci_dev *dev)*/ 5875 /* LDV_COMMENT_BEGIN_PREP */ 5876 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 5877 #if defined(__i386__) 5878 # define BREAKPOINT() asm(" int $3"); 5879 #else 5880 # define BREAKPOINT() { } 5881 #endif 5882 #define MAX_DEVICES 12 5883 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 5884 #define SYNCLINK_GENERIC_HDLC 1 5885 #else 5886 #define SYNCLINK_GENERIC_HDLC 0 5887 #endif 5888 #define GET_USER(error,value,addr) error = get_user(value,addr) 5889 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 5890 #define PUT_USER(error,value,addr) error = put_user(value,addr) 5891 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 5892 #define SCABUFSIZE 1024 5893 #define SCA_MEM_SIZE 0x40000 5894 #define SCA_BASE_SIZE 512 5895 #define SCA_REG_SIZE 16 5896 #define SCA_MAX_PORTS 4 5897 #define SCAMAXDESC 128 5898 #define BUFFERLISTSIZE 4096 5899 #define BH_RECEIVE 1 5900 #define BH_TRANSMIT 2 5901 #define BH_STATUS 4 5902 #define IO_PIN_SHUTDOWN_LIMIT 100 5903 #if SYNCLINK_GENERIC_HDLC 5904 #endif 5905 #define MGSL_MAGIC 0x5401 5906 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 5907 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 5908 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 5909 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 5910 #define LPR 0x00 5911 #define PABR0 0x02 5912 #define PABR1 0x03 5913 #define WCRL 0x04 5914 #define WCRM 0x05 5915 #define WCRH 0x06 5916 #define DPCR 0x08 5917 #define DMER 0x09 5918 #define ISR0 0x10 5919 #define ISR1 0x11 5920 #define ISR2 0x12 5921 #define IER0 0x14 5922 #define IER1 0x15 5923 #define IER2 0x16 5924 #define ITCR 0x18 5925 #define INTVR 0x1a 5926 #define IMVR 0x1c 5927 #define TRB 0x20 5928 #define TRBL 0x20 5929 #define TRBH 0x21 5930 #define SR0 0x22 5931 #define SR1 0x23 5932 #define SR2 0x24 5933 #define SR3 0x25 5934 #define FST 0x26 5935 #define IE0 0x28 5936 #define IE1 0x29 5937 #define IE2 0x2a 5938 #define FIE 0x2b 5939 #define CMD 0x2c 5940 #define MD0 0x2e 5941 #define MD1 0x2f 5942 #define MD2 0x30 5943 #define CTL 0x31 5944 #define SA0 0x32 5945 #define SA1 0x33 5946 #define IDL 0x34 5947 #define TMC 0x35 5948 #define RXS 0x36 5949 #define TXS 0x37 5950 #define TRC0 0x38 5951 #define TRC1 0x39 5952 #define RRC 0x3a 5953 #define CST0 0x3c 5954 #define CST1 0x3d 5955 #define TCNT 0x60 5956 #define TCNTL 0x60 5957 #define TCNTH 0x61 5958 #define TCONR 0x62 5959 #define TCONRL 0x62 5960 #define TCONRH 0x63 5961 #define TMCS 0x64 5962 #define TEPR 0x65 5963 #define DARL 0x80 5964 #define DARH 0x81 5965 #define DARB 0x82 5966 #define BAR 0x80 5967 #define BARL 0x80 5968 #define BARH 0x81 5969 #define BARB 0x82 5970 #define SAR 0x84 5971 #define SARL 0x84 5972 #define SARH 0x85 5973 #define SARB 0x86 5974 #define CPB 0x86 5975 #define CDA 0x88 5976 #define CDAL 0x88 5977 #define CDAH 0x89 5978 #define EDA 0x8a 5979 #define EDAL 0x8a 5980 #define EDAH 0x8b 5981 #define BFL 0x8c 5982 #define BFLL 0x8c 5983 #define BFLH 0x8d 5984 #define BCR 0x8e 5985 #define BCRL 0x8e 5986 #define BCRH 0x8f 5987 #define DSR 0x90 5988 #define DMR 0x91 5989 #define FCT 0x93 5990 #define DIR 0x94 5991 #define DCMD 0x95 5992 #define TIMER0 0x00 5993 #define TIMER1 0x08 5994 #define TIMER2 0x10 5995 #define TIMER3 0x18 5996 #define RXDMA 0x00 5997 #define TXDMA 0x20 5998 #define NOOP 0x00 5999 #define TXRESET 0x01 6000 #define TXENABLE 0x02 6001 #define TXDISABLE 0x03 6002 #define TXCRCINIT 0x04 6003 #define TXCRCEXCL 0x05 6004 #define TXEOM 0x06 6005 #define TXABORT 0x07 6006 #define MPON 0x08 6007 #define TXBUFCLR 0x09 6008 #define RXRESET 0x11 6009 #define RXENABLE 0x12 6010 #define RXDISABLE 0x13 6011 #define RXCRCINIT 0x14 6012 #define RXREJECT 0x15 6013 #define SEARCHMP 0x16 6014 #define RXCRCEXCL 0x17 6015 #define RXCRCCALC 0x18 6016 #define CHRESET 0x21 6017 #define HUNT 0x31 6018 #define SWABORT 0x01 6019 #define FEICLEAR 0x02 6020 #define TXINTE BIT7 6021 #define RXINTE BIT6 6022 #define TXRDYE BIT1 6023 #define RXRDYE BIT0 6024 #define UDRN BIT7 6025 #define IDLE BIT6 6026 #define SYNCD BIT4 6027 #define FLGD BIT4 6028 #define CCTS BIT3 6029 #define CDCD BIT2 6030 #define BRKD BIT1 6031 #define ABTD BIT1 6032 #define GAPD BIT1 6033 #define BRKE BIT0 6034 #define IDLD BIT0 6035 #define EOM BIT7 6036 #define PMP BIT6 6037 #define SHRT BIT6 6038 #define PE BIT5 6039 #define ABT BIT5 6040 #define FRME BIT4 6041 #define RBIT BIT4 6042 #define OVRN BIT3 6043 #define CRCE BIT2 6044 #define WAKEUP_CHARS 256 6045 #if SYNCLINK_GENERIC_HDLC 6046 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6047 #endif 6048 #ifdef SANITY_CHECK 6049 #else 6050 #endif 6051 #if SYNCLINK_GENERIC_HDLC 6052 #endif 6053 #if SYNCLINK_GENERIC_HDLC 6054 #endif 6055 #if SYNCLINK_GENERIC_HDLC 6056 #endif 6057 #ifdef CMSPAR 6058 #endif 6059 #if SYNCLINK_GENERIC_HDLC 6060 #endif 6061 #if SYNCLINK_GENERIC_HDLC 6062 #endif 6063 #if 0 6064 #endif 6065 #if SYNCLINK_GENERIC_HDLC 6066 #endif 6067 #if SYNCLINK_GENERIC_HDLC 6068 #endif 6069 #define TESTFRAMESIZE 20 6070 #if SYNCLINK_GENERIC_HDLC 6071 #endif 6072 #define CALC_REGADDR() \ 6073 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6074 if (info->port_num > 1) \ 6075 RegAddr += 256; \ 6076 if ( info->port_num & 1) { \ 6077 if (Addr > 0x7f) \ 6078 RegAddr += 0x40; \ 6079 else if (Addr > 0x1f && Addr < 0x60) \ 6080 RegAddr += 0x20; \ 6081 } 6082 /* LDV_COMMENT_END_PREP */ 6083 6084 /** STRUCT: struct type: file_operations, struct name: synclinkmp_proc_fops **/ 6085 /* content: static int synclinkmp_proc_open(struct inode *inode, struct file *file)*/ 6086 /* LDV_COMMENT_BEGIN_PREP */ 6087 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6088 #if defined(__i386__) 6089 # define BREAKPOINT() asm(" int $3"); 6090 #else 6091 # define BREAKPOINT() { } 6092 #endif 6093 #define MAX_DEVICES 12 6094 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6095 #define SYNCLINK_GENERIC_HDLC 1 6096 #else 6097 #define SYNCLINK_GENERIC_HDLC 0 6098 #endif 6099 #define GET_USER(error,value,addr) error = get_user(value,addr) 6100 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6101 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6102 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6103 #define SCABUFSIZE 1024 6104 #define SCA_MEM_SIZE 0x40000 6105 #define SCA_BASE_SIZE 512 6106 #define SCA_REG_SIZE 16 6107 #define SCA_MAX_PORTS 4 6108 #define SCAMAXDESC 128 6109 #define BUFFERLISTSIZE 4096 6110 #define BH_RECEIVE 1 6111 #define BH_TRANSMIT 2 6112 #define BH_STATUS 4 6113 #define IO_PIN_SHUTDOWN_LIMIT 100 6114 #if SYNCLINK_GENERIC_HDLC 6115 #endif 6116 #define MGSL_MAGIC 0x5401 6117 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6118 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6119 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6120 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6121 #define LPR 0x00 6122 #define PABR0 0x02 6123 #define PABR1 0x03 6124 #define WCRL 0x04 6125 #define WCRM 0x05 6126 #define WCRH 0x06 6127 #define DPCR 0x08 6128 #define DMER 0x09 6129 #define ISR0 0x10 6130 #define ISR1 0x11 6131 #define ISR2 0x12 6132 #define IER0 0x14 6133 #define IER1 0x15 6134 #define IER2 0x16 6135 #define ITCR 0x18 6136 #define INTVR 0x1a 6137 #define IMVR 0x1c 6138 #define TRB 0x20 6139 #define TRBL 0x20 6140 #define TRBH 0x21 6141 #define SR0 0x22 6142 #define SR1 0x23 6143 #define SR2 0x24 6144 #define SR3 0x25 6145 #define FST 0x26 6146 #define IE0 0x28 6147 #define IE1 0x29 6148 #define IE2 0x2a 6149 #define FIE 0x2b 6150 #define CMD 0x2c 6151 #define MD0 0x2e 6152 #define MD1 0x2f 6153 #define MD2 0x30 6154 #define CTL 0x31 6155 #define SA0 0x32 6156 #define SA1 0x33 6157 #define IDL 0x34 6158 #define TMC 0x35 6159 #define RXS 0x36 6160 #define TXS 0x37 6161 #define TRC0 0x38 6162 #define TRC1 0x39 6163 #define RRC 0x3a 6164 #define CST0 0x3c 6165 #define CST1 0x3d 6166 #define TCNT 0x60 6167 #define TCNTL 0x60 6168 #define TCNTH 0x61 6169 #define TCONR 0x62 6170 #define TCONRL 0x62 6171 #define TCONRH 0x63 6172 #define TMCS 0x64 6173 #define TEPR 0x65 6174 #define DARL 0x80 6175 #define DARH 0x81 6176 #define DARB 0x82 6177 #define BAR 0x80 6178 #define BARL 0x80 6179 #define BARH 0x81 6180 #define BARB 0x82 6181 #define SAR 0x84 6182 #define SARL 0x84 6183 #define SARH 0x85 6184 #define SARB 0x86 6185 #define CPB 0x86 6186 #define CDA 0x88 6187 #define CDAL 0x88 6188 #define CDAH 0x89 6189 #define EDA 0x8a 6190 #define EDAL 0x8a 6191 #define EDAH 0x8b 6192 #define BFL 0x8c 6193 #define BFLL 0x8c 6194 #define BFLH 0x8d 6195 #define BCR 0x8e 6196 #define BCRL 0x8e 6197 #define BCRH 0x8f 6198 #define DSR 0x90 6199 #define DMR 0x91 6200 #define FCT 0x93 6201 #define DIR 0x94 6202 #define DCMD 0x95 6203 #define TIMER0 0x00 6204 #define TIMER1 0x08 6205 #define TIMER2 0x10 6206 #define TIMER3 0x18 6207 #define RXDMA 0x00 6208 #define TXDMA 0x20 6209 #define NOOP 0x00 6210 #define TXRESET 0x01 6211 #define TXENABLE 0x02 6212 #define TXDISABLE 0x03 6213 #define TXCRCINIT 0x04 6214 #define TXCRCEXCL 0x05 6215 #define TXEOM 0x06 6216 #define TXABORT 0x07 6217 #define MPON 0x08 6218 #define TXBUFCLR 0x09 6219 #define RXRESET 0x11 6220 #define RXENABLE 0x12 6221 #define RXDISABLE 0x13 6222 #define RXCRCINIT 0x14 6223 #define RXREJECT 0x15 6224 #define SEARCHMP 0x16 6225 #define RXCRCEXCL 0x17 6226 #define RXCRCCALC 0x18 6227 #define CHRESET 0x21 6228 #define HUNT 0x31 6229 #define SWABORT 0x01 6230 #define FEICLEAR 0x02 6231 #define TXINTE BIT7 6232 #define RXINTE BIT6 6233 #define TXRDYE BIT1 6234 #define RXRDYE BIT0 6235 #define UDRN BIT7 6236 #define IDLE BIT6 6237 #define SYNCD BIT4 6238 #define FLGD BIT4 6239 #define CCTS BIT3 6240 #define CDCD BIT2 6241 #define BRKD BIT1 6242 #define ABTD BIT1 6243 #define GAPD BIT1 6244 #define BRKE BIT0 6245 #define IDLD BIT0 6246 #define EOM BIT7 6247 #define PMP BIT6 6248 #define SHRT BIT6 6249 #define PE BIT5 6250 #define ABT BIT5 6251 #define FRME BIT4 6252 #define RBIT BIT4 6253 #define OVRN BIT3 6254 #define CRCE BIT2 6255 #define WAKEUP_CHARS 256 6256 #if SYNCLINK_GENERIC_HDLC 6257 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6258 #endif 6259 #ifdef SANITY_CHECK 6260 #else 6261 #endif 6262 /* LDV_COMMENT_END_PREP */ 6263 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_proc_open" */ 6264 struct inode * var_group2; 6265 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_proc_open" */ 6266 struct file * var_group3; 6267 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "synclinkmp_proc_open" */ 6268 static int res_synclinkmp_proc_open_21; 6269 /* LDV_COMMENT_BEGIN_PREP */ 6270 #if SYNCLINK_GENERIC_HDLC 6271 #endif 6272 #if SYNCLINK_GENERIC_HDLC 6273 #endif 6274 #if SYNCLINK_GENERIC_HDLC 6275 #endif 6276 #ifdef CMSPAR 6277 #endif 6278 #if SYNCLINK_GENERIC_HDLC 6279 #endif 6280 #if SYNCLINK_GENERIC_HDLC 6281 #endif 6282 #if 0 6283 #endif 6284 #if SYNCLINK_GENERIC_HDLC 6285 #endif 6286 #if SYNCLINK_GENERIC_HDLC 6287 #endif 6288 #define TESTFRAMESIZE 20 6289 #if SYNCLINK_GENERIC_HDLC 6290 #endif 6291 #define CALC_REGADDR() \ 6292 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6293 if (info->port_num > 1) \ 6294 RegAddr += 256; \ 6295 if ( info->port_num & 1) { \ 6296 if (Addr > 0x7f) \ 6297 RegAddr += 0x40; \ 6298 else if (Addr > 0x1f && Addr < 0x60) \ 6299 RegAddr += 0x20; \ 6300 } 6301 /* LDV_COMMENT_END_PREP */ 6302 6303 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 6304 /* content: static int hdlcdev_open(struct net_device *dev)*/ 6305 /* LDV_COMMENT_BEGIN_PREP */ 6306 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6307 #if defined(__i386__) 6308 # define BREAKPOINT() asm(" int $3"); 6309 #else 6310 # define BREAKPOINT() { } 6311 #endif 6312 #define MAX_DEVICES 12 6313 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6314 #define SYNCLINK_GENERIC_HDLC 1 6315 #else 6316 #define SYNCLINK_GENERIC_HDLC 0 6317 #endif 6318 #define GET_USER(error,value,addr) error = get_user(value,addr) 6319 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6320 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6321 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6322 #define SCABUFSIZE 1024 6323 #define SCA_MEM_SIZE 0x40000 6324 #define SCA_BASE_SIZE 512 6325 #define SCA_REG_SIZE 16 6326 #define SCA_MAX_PORTS 4 6327 #define SCAMAXDESC 128 6328 #define BUFFERLISTSIZE 4096 6329 #define BH_RECEIVE 1 6330 #define BH_TRANSMIT 2 6331 #define BH_STATUS 4 6332 #define IO_PIN_SHUTDOWN_LIMIT 100 6333 #if SYNCLINK_GENERIC_HDLC 6334 #endif 6335 #define MGSL_MAGIC 0x5401 6336 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6337 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6338 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6339 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6340 #define LPR 0x00 6341 #define PABR0 0x02 6342 #define PABR1 0x03 6343 #define WCRL 0x04 6344 #define WCRM 0x05 6345 #define WCRH 0x06 6346 #define DPCR 0x08 6347 #define DMER 0x09 6348 #define ISR0 0x10 6349 #define ISR1 0x11 6350 #define ISR2 0x12 6351 #define IER0 0x14 6352 #define IER1 0x15 6353 #define IER2 0x16 6354 #define ITCR 0x18 6355 #define INTVR 0x1a 6356 #define IMVR 0x1c 6357 #define TRB 0x20 6358 #define TRBL 0x20 6359 #define TRBH 0x21 6360 #define SR0 0x22 6361 #define SR1 0x23 6362 #define SR2 0x24 6363 #define SR3 0x25 6364 #define FST 0x26 6365 #define IE0 0x28 6366 #define IE1 0x29 6367 #define IE2 0x2a 6368 #define FIE 0x2b 6369 #define CMD 0x2c 6370 #define MD0 0x2e 6371 #define MD1 0x2f 6372 #define MD2 0x30 6373 #define CTL 0x31 6374 #define SA0 0x32 6375 #define SA1 0x33 6376 #define IDL 0x34 6377 #define TMC 0x35 6378 #define RXS 0x36 6379 #define TXS 0x37 6380 #define TRC0 0x38 6381 #define TRC1 0x39 6382 #define RRC 0x3a 6383 #define CST0 0x3c 6384 #define CST1 0x3d 6385 #define TCNT 0x60 6386 #define TCNTL 0x60 6387 #define TCNTH 0x61 6388 #define TCONR 0x62 6389 #define TCONRL 0x62 6390 #define TCONRH 0x63 6391 #define TMCS 0x64 6392 #define TEPR 0x65 6393 #define DARL 0x80 6394 #define DARH 0x81 6395 #define DARB 0x82 6396 #define BAR 0x80 6397 #define BARL 0x80 6398 #define BARH 0x81 6399 #define BARB 0x82 6400 #define SAR 0x84 6401 #define SARL 0x84 6402 #define SARH 0x85 6403 #define SARB 0x86 6404 #define CPB 0x86 6405 #define CDA 0x88 6406 #define CDAL 0x88 6407 #define CDAH 0x89 6408 #define EDA 0x8a 6409 #define EDAL 0x8a 6410 #define EDAH 0x8b 6411 #define BFL 0x8c 6412 #define BFLL 0x8c 6413 #define BFLH 0x8d 6414 #define BCR 0x8e 6415 #define BCRL 0x8e 6416 #define BCRH 0x8f 6417 #define DSR 0x90 6418 #define DMR 0x91 6419 #define FCT 0x93 6420 #define DIR 0x94 6421 #define DCMD 0x95 6422 #define TIMER0 0x00 6423 #define TIMER1 0x08 6424 #define TIMER2 0x10 6425 #define TIMER3 0x18 6426 #define RXDMA 0x00 6427 #define TXDMA 0x20 6428 #define NOOP 0x00 6429 #define TXRESET 0x01 6430 #define TXENABLE 0x02 6431 #define TXDISABLE 0x03 6432 #define TXCRCINIT 0x04 6433 #define TXCRCEXCL 0x05 6434 #define TXEOM 0x06 6435 #define TXABORT 0x07 6436 #define MPON 0x08 6437 #define TXBUFCLR 0x09 6438 #define RXRESET 0x11 6439 #define RXENABLE 0x12 6440 #define RXDISABLE 0x13 6441 #define RXCRCINIT 0x14 6442 #define RXREJECT 0x15 6443 #define SEARCHMP 0x16 6444 #define RXCRCEXCL 0x17 6445 #define RXCRCCALC 0x18 6446 #define CHRESET 0x21 6447 #define HUNT 0x31 6448 #define SWABORT 0x01 6449 #define FEICLEAR 0x02 6450 #define TXINTE BIT7 6451 #define RXINTE BIT6 6452 #define TXRDYE BIT1 6453 #define RXRDYE BIT0 6454 #define UDRN BIT7 6455 #define IDLE BIT6 6456 #define SYNCD BIT4 6457 #define FLGD BIT4 6458 #define CCTS BIT3 6459 #define CDCD BIT2 6460 #define BRKD BIT1 6461 #define ABTD BIT1 6462 #define GAPD BIT1 6463 #define BRKE BIT0 6464 #define IDLD BIT0 6465 #define EOM BIT7 6466 #define PMP BIT6 6467 #define SHRT BIT6 6468 #define PE BIT5 6469 #define ABT BIT5 6470 #define FRME BIT4 6471 #define RBIT BIT4 6472 #define OVRN BIT3 6473 #define CRCE BIT2 6474 #define WAKEUP_CHARS 256 6475 #if SYNCLINK_GENERIC_HDLC 6476 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6477 #endif 6478 #ifdef SANITY_CHECK 6479 #else 6480 #endif 6481 #if SYNCLINK_GENERIC_HDLC 6482 /* LDV_COMMENT_END_PREP */ 6483 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "hdlcdev_open" */ 6484 struct net_device * var_group4; 6485 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "hdlcdev_open" */ 6486 static int res_hdlcdev_open_28; 6487 /* LDV_COMMENT_BEGIN_PREP */ 6488 #endif 6489 #if SYNCLINK_GENERIC_HDLC 6490 #endif 6491 #if SYNCLINK_GENERIC_HDLC 6492 #endif 6493 #ifdef CMSPAR 6494 #endif 6495 #if SYNCLINK_GENERIC_HDLC 6496 #endif 6497 #if SYNCLINK_GENERIC_HDLC 6498 #endif 6499 #if 0 6500 #endif 6501 #if SYNCLINK_GENERIC_HDLC 6502 #endif 6503 #if SYNCLINK_GENERIC_HDLC 6504 #endif 6505 #define TESTFRAMESIZE 20 6506 #if SYNCLINK_GENERIC_HDLC 6507 #endif 6508 #define CALC_REGADDR() \ 6509 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6510 if (info->port_num > 1) \ 6511 RegAddr += 256; \ 6512 if ( info->port_num & 1) { \ 6513 if (Addr > 0x7f) \ 6514 RegAddr += 0x40; \ 6515 else if (Addr > 0x1f && Addr < 0x60) \ 6516 RegAddr += 0x20; \ 6517 } 6518 /* LDV_COMMENT_END_PREP */ 6519 /* content: static int hdlcdev_close(struct net_device *dev)*/ 6520 /* LDV_COMMENT_BEGIN_PREP */ 6521 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6522 #if defined(__i386__) 6523 # define BREAKPOINT() asm(" int $3"); 6524 #else 6525 # define BREAKPOINT() { } 6526 #endif 6527 #define MAX_DEVICES 12 6528 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6529 #define SYNCLINK_GENERIC_HDLC 1 6530 #else 6531 #define SYNCLINK_GENERIC_HDLC 0 6532 #endif 6533 #define GET_USER(error,value,addr) error = get_user(value,addr) 6534 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6535 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6536 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6537 #define SCABUFSIZE 1024 6538 #define SCA_MEM_SIZE 0x40000 6539 #define SCA_BASE_SIZE 512 6540 #define SCA_REG_SIZE 16 6541 #define SCA_MAX_PORTS 4 6542 #define SCAMAXDESC 128 6543 #define BUFFERLISTSIZE 4096 6544 #define BH_RECEIVE 1 6545 #define BH_TRANSMIT 2 6546 #define BH_STATUS 4 6547 #define IO_PIN_SHUTDOWN_LIMIT 100 6548 #if SYNCLINK_GENERIC_HDLC 6549 #endif 6550 #define MGSL_MAGIC 0x5401 6551 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6552 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6553 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6554 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6555 #define LPR 0x00 6556 #define PABR0 0x02 6557 #define PABR1 0x03 6558 #define WCRL 0x04 6559 #define WCRM 0x05 6560 #define WCRH 0x06 6561 #define DPCR 0x08 6562 #define DMER 0x09 6563 #define ISR0 0x10 6564 #define ISR1 0x11 6565 #define ISR2 0x12 6566 #define IER0 0x14 6567 #define IER1 0x15 6568 #define IER2 0x16 6569 #define ITCR 0x18 6570 #define INTVR 0x1a 6571 #define IMVR 0x1c 6572 #define TRB 0x20 6573 #define TRBL 0x20 6574 #define TRBH 0x21 6575 #define SR0 0x22 6576 #define SR1 0x23 6577 #define SR2 0x24 6578 #define SR3 0x25 6579 #define FST 0x26 6580 #define IE0 0x28 6581 #define IE1 0x29 6582 #define IE2 0x2a 6583 #define FIE 0x2b 6584 #define CMD 0x2c 6585 #define MD0 0x2e 6586 #define MD1 0x2f 6587 #define MD2 0x30 6588 #define CTL 0x31 6589 #define SA0 0x32 6590 #define SA1 0x33 6591 #define IDL 0x34 6592 #define TMC 0x35 6593 #define RXS 0x36 6594 #define TXS 0x37 6595 #define TRC0 0x38 6596 #define TRC1 0x39 6597 #define RRC 0x3a 6598 #define CST0 0x3c 6599 #define CST1 0x3d 6600 #define TCNT 0x60 6601 #define TCNTL 0x60 6602 #define TCNTH 0x61 6603 #define TCONR 0x62 6604 #define TCONRL 0x62 6605 #define TCONRH 0x63 6606 #define TMCS 0x64 6607 #define TEPR 0x65 6608 #define DARL 0x80 6609 #define DARH 0x81 6610 #define DARB 0x82 6611 #define BAR 0x80 6612 #define BARL 0x80 6613 #define BARH 0x81 6614 #define BARB 0x82 6615 #define SAR 0x84 6616 #define SARL 0x84 6617 #define SARH 0x85 6618 #define SARB 0x86 6619 #define CPB 0x86 6620 #define CDA 0x88 6621 #define CDAL 0x88 6622 #define CDAH 0x89 6623 #define EDA 0x8a 6624 #define EDAL 0x8a 6625 #define EDAH 0x8b 6626 #define BFL 0x8c 6627 #define BFLL 0x8c 6628 #define BFLH 0x8d 6629 #define BCR 0x8e 6630 #define BCRL 0x8e 6631 #define BCRH 0x8f 6632 #define DSR 0x90 6633 #define DMR 0x91 6634 #define FCT 0x93 6635 #define DIR 0x94 6636 #define DCMD 0x95 6637 #define TIMER0 0x00 6638 #define TIMER1 0x08 6639 #define TIMER2 0x10 6640 #define TIMER3 0x18 6641 #define RXDMA 0x00 6642 #define TXDMA 0x20 6643 #define NOOP 0x00 6644 #define TXRESET 0x01 6645 #define TXENABLE 0x02 6646 #define TXDISABLE 0x03 6647 #define TXCRCINIT 0x04 6648 #define TXCRCEXCL 0x05 6649 #define TXEOM 0x06 6650 #define TXABORT 0x07 6651 #define MPON 0x08 6652 #define TXBUFCLR 0x09 6653 #define RXRESET 0x11 6654 #define RXENABLE 0x12 6655 #define RXDISABLE 0x13 6656 #define RXCRCINIT 0x14 6657 #define RXREJECT 0x15 6658 #define SEARCHMP 0x16 6659 #define RXCRCEXCL 0x17 6660 #define RXCRCCALC 0x18 6661 #define CHRESET 0x21 6662 #define HUNT 0x31 6663 #define SWABORT 0x01 6664 #define FEICLEAR 0x02 6665 #define TXINTE BIT7 6666 #define RXINTE BIT6 6667 #define TXRDYE BIT1 6668 #define RXRDYE BIT0 6669 #define UDRN BIT7 6670 #define IDLE BIT6 6671 #define SYNCD BIT4 6672 #define FLGD BIT4 6673 #define CCTS BIT3 6674 #define CDCD BIT2 6675 #define BRKD BIT1 6676 #define ABTD BIT1 6677 #define GAPD BIT1 6678 #define BRKE BIT0 6679 #define IDLD BIT0 6680 #define EOM BIT7 6681 #define PMP BIT6 6682 #define SHRT BIT6 6683 #define PE BIT5 6684 #define ABT BIT5 6685 #define FRME BIT4 6686 #define RBIT BIT4 6687 #define OVRN BIT3 6688 #define CRCE BIT2 6689 #define WAKEUP_CHARS 256 6690 #if SYNCLINK_GENERIC_HDLC 6691 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6692 #endif 6693 #ifdef SANITY_CHECK 6694 #else 6695 #endif 6696 #if SYNCLINK_GENERIC_HDLC 6697 /* LDV_COMMENT_END_PREP */ 6698 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "hdlcdev_close" */ 6699 static int res_hdlcdev_close_29; 6700 /* LDV_COMMENT_BEGIN_PREP */ 6701 #endif 6702 #if SYNCLINK_GENERIC_HDLC 6703 #endif 6704 #if SYNCLINK_GENERIC_HDLC 6705 #endif 6706 #ifdef CMSPAR 6707 #endif 6708 #if SYNCLINK_GENERIC_HDLC 6709 #endif 6710 #if SYNCLINK_GENERIC_HDLC 6711 #endif 6712 #if 0 6713 #endif 6714 #if SYNCLINK_GENERIC_HDLC 6715 #endif 6716 #if SYNCLINK_GENERIC_HDLC 6717 #endif 6718 #define TESTFRAMESIZE 20 6719 #if SYNCLINK_GENERIC_HDLC 6720 #endif 6721 #define CALC_REGADDR() \ 6722 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6723 if (info->port_num > 1) \ 6724 RegAddr += 256; \ 6725 if ( info->port_num & 1) { \ 6726 if (Addr > 0x7f) \ 6727 RegAddr += 0x40; \ 6728 else if (Addr > 0x1f && Addr < 0x60) \ 6729 RegAddr += 0x20; \ 6730 } 6731 /* LDV_COMMENT_END_PREP */ 6732 /* content: static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)*/ 6733 /* LDV_COMMENT_BEGIN_PREP */ 6734 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6735 #if defined(__i386__) 6736 # define BREAKPOINT() asm(" int $3"); 6737 #else 6738 # define BREAKPOINT() { } 6739 #endif 6740 #define MAX_DEVICES 12 6741 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6742 #define SYNCLINK_GENERIC_HDLC 1 6743 #else 6744 #define SYNCLINK_GENERIC_HDLC 0 6745 #endif 6746 #define GET_USER(error,value,addr) error = get_user(value,addr) 6747 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6748 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6749 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6750 #define SCABUFSIZE 1024 6751 #define SCA_MEM_SIZE 0x40000 6752 #define SCA_BASE_SIZE 512 6753 #define SCA_REG_SIZE 16 6754 #define SCA_MAX_PORTS 4 6755 #define SCAMAXDESC 128 6756 #define BUFFERLISTSIZE 4096 6757 #define BH_RECEIVE 1 6758 #define BH_TRANSMIT 2 6759 #define BH_STATUS 4 6760 #define IO_PIN_SHUTDOWN_LIMIT 100 6761 #if SYNCLINK_GENERIC_HDLC 6762 #endif 6763 #define MGSL_MAGIC 0x5401 6764 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6765 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6766 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6767 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6768 #define LPR 0x00 6769 #define PABR0 0x02 6770 #define PABR1 0x03 6771 #define WCRL 0x04 6772 #define WCRM 0x05 6773 #define WCRH 0x06 6774 #define DPCR 0x08 6775 #define DMER 0x09 6776 #define ISR0 0x10 6777 #define ISR1 0x11 6778 #define ISR2 0x12 6779 #define IER0 0x14 6780 #define IER1 0x15 6781 #define IER2 0x16 6782 #define ITCR 0x18 6783 #define INTVR 0x1a 6784 #define IMVR 0x1c 6785 #define TRB 0x20 6786 #define TRBL 0x20 6787 #define TRBH 0x21 6788 #define SR0 0x22 6789 #define SR1 0x23 6790 #define SR2 0x24 6791 #define SR3 0x25 6792 #define FST 0x26 6793 #define IE0 0x28 6794 #define IE1 0x29 6795 #define IE2 0x2a 6796 #define FIE 0x2b 6797 #define CMD 0x2c 6798 #define MD0 0x2e 6799 #define MD1 0x2f 6800 #define MD2 0x30 6801 #define CTL 0x31 6802 #define SA0 0x32 6803 #define SA1 0x33 6804 #define IDL 0x34 6805 #define TMC 0x35 6806 #define RXS 0x36 6807 #define TXS 0x37 6808 #define TRC0 0x38 6809 #define TRC1 0x39 6810 #define RRC 0x3a 6811 #define CST0 0x3c 6812 #define CST1 0x3d 6813 #define TCNT 0x60 6814 #define TCNTL 0x60 6815 #define TCNTH 0x61 6816 #define TCONR 0x62 6817 #define TCONRL 0x62 6818 #define TCONRH 0x63 6819 #define TMCS 0x64 6820 #define TEPR 0x65 6821 #define DARL 0x80 6822 #define DARH 0x81 6823 #define DARB 0x82 6824 #define BAR 0x80 6825 #define BARL 0x80 6826 #define BARH 0x81 6827 #define BARB 0x82 6828 #define SAR 0x84 6829 #define SARL 0x84 6830 #define SARH 0x85 6831 #define SARB 0x86 6832 #define CPB 0x86 6833 #define CDA 0x88 6834 #define CDAL 0x88 6835 #define CDAH 0x89 6836 #define EDA 0x8a 6837 #define EDAL 0x8a 6838 #define EDAH 0x8b 6839 #define BFL 0x8c 6840 #define BFLL 0x8c 6841 #define BFLH 0x8d 6842 #define BCR 0x8e 6843 #define BCRL 0x8e 6844 #define BCRH 0x8f 6845 #define DSR 0x90 6846 #define DMR 0x91 6847 #define FCT 0x93 6848 #define DIR 0x94 6849 #define DCMD 0x95 6850 #define TIMER0 0x00 6851 #define TIMER1 0x08 6852 #define TIMER2 0x10 6853 #define TIMER3 0x18 6854 #define RXDMA 0x00 6855 #define TXDMA 0x20 6856 #define NOOP 0x00 6857 #define TXRESET 0x01 6858 #define TXENABLE 0x02 6859 #define TXDISABLE 0x03 6860 #define TXCRCINIT 0x04 6861 #define TXCRCEXCL 0x05 6862 #define TXEOM 0x06 6863 #define TXABORT 0x07 6864 #define MPON 0x08 6865 #define TXBUFCLR 0x09 6866 #define RXRESET 0x11 6867 #define RXENABLE 0x12 6868 #define RXDISABLE 0x13 6869 #define RXCRCINIT 0x14 6870 #define RXREJECT 0x15 6871 #define SEARCHMP 0x16 6872 #define RXCRCEXCL 0x17 6873 #define RXCRCCALC 0x18 6874 #define CHRESET 0x21 6875 #define HUNT 0x31 6876 #define SWABORT 0x01 6877 #define FEICLEAR 0x02 6878 #define TXINTE BIT7 6879 #define RXINTE BIT6 6880 #define TXRDYE BIT1 6881 #define RXRDYE BIT0 6882 #define UDRN BIT7 6883 #define IDLE BIT6 6884 #define SYNCD BIT4 6885 #define FLGD BIT4 6886 #define CCTS BIT3 6887 #define CDCD BIT2 6888 #define BRKD BIT1 6889 #define ABTD BIT1 6890 #define GAPD BIT1 6891 #define BRKE BIT0 6892 #define IDLD BIT0 6893 #define EOM BIT7 6894 #define PMP BIT6 6895 #define SHRT BIT6 6896 #define PE BIT5 6897 #define ABT BIT5 6898 #define FRME BIT4 6899 #define RBIT BIT4 6900 #define OVRN BIT3 6901 #define CRCE BIT2 6902 #define WAKEUP_CHARS 256 6903 #if SYNCLINK_GENERIC_HDLC 6904 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 6905 #endif 6906 #ifdef SANITY_CHECK 6907 #else 6908 #endif 6909 #if SYNCLINK_GENERIC_HDLC 6910 /* LDV_COMMENT_END_PREP */ 6911 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "hdlcdev_ioctl" */ 6912 struct ifreq * var_group5; 6913 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "hdlcdev_ioctl" */ 6914 int var_hdlcdev_ioctl_30_p2; 6915 /* LDV_COMMENT_BEGIN_PREP */ 6916 #endif 6917 #if SYNCLINK_GENERIC_HDLC 6918 #endif 6919 #if SYNCLINK_GENERIC_HDLC 6920 #endif 6921 #ifdef CMSPAR 6922 #endif 6923 #if SYNCLINK_GENERIC_HDLC 6924 #endif 6925 #if SYNCLINK_GENERIC_HDLC 6926 #endif 6927 #if 0 6928 #endif 6929 #if SYNCLINK_GENERIC_HDLC 6930 #endif 6931 #if SYNCLINK_GENERIC_HDLC 6932 #endif 6933 #define TESTFRAMESIZE 20 6934 #if SYNCLINK_GENERIC_HDLC 6935 #endif 6936 #define CALC_REGADDR() \ 6937 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 6938 if (info->port_num > 1) \ 6939 RegAddr += 256; \ 6940 if ( info->port_num & 1) { \ 6941 if (Addr > 0x7f) \ 6942 RegAddr += 0x40; \ 6943 else if (Addr > 0x1f && Addr < 0x60) \ 6944 RegAddr += 0x20; \ 6945 } 6946 /* LDV_COMMENT_END_PREP */ 6947 /* content: static void hdlcdev_tx_timeout(struct net_device *dev)*/ 6948 /* LDV_COMMENT_BEGIN_PREP */ 6949 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 6950 #if defined(__i386__) 6951 # define BREAKPOINT() asm(" int $3"); 6952 #else 6953 # define BREAKPOINT() { } 6954 #endif 6955 #define MAX_DEVICES 12 6956 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 6957 #define SYNCLINK_GENERIC_HDLC 1 6958 #else 6959 #define SYNCLINK_GENERIC_HDLC 0 6960 #endif 6961 #define GET_USER(error,value,addr) error = get_user(value,addr) 6962 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 6963 #define PUT_USER(error,value,addr) error = put_user(value,addr) 6964 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 6965 #define SCABUFSIZE 1024 6966 #define SCA_MEM_SIZE 0x40000 6967 #define SCA_BASE_SIZE 512 6968 #define SCA_REG_SIZE 16 6969 #define SCA_MAX_PORTS 4 6970 #define SCAMAXDESC 128 6971 #define BUFFERLISTSIZE 4096 6972 #define BH_RECEIVE 1 6973 #define BH_TRANSMIT 2 6974 #define BH_STATUS 4 6975 #define IO_PIN_SHUTDOWN_LIMIT 100 6976 #if SYNCLINK_GENERIC_HDLC 6977 #endif 6978 #define MGSL_MAGIC 0x5401 6979 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 6980 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 6981 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 6982 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 6983 #define LPR 0x00 6984 #define PABR0 0x02 6985 #define PABR1 0x03 6986 #define WCRL 0x04 6987 #define WCRM 0x05 6988 #define WCRH 0x06 6989 #define DPCR 0x08 6990 #define DMER 0x09 6991 #define ISR0 0x10 6992 #define ISR1 0x11 6993 #define ISR2 0x12 6994 #define IER0 0x14 6995 #define IER1 0x15 6996 #define IER2 0x16 6997 #define ITCR 0x18 6998 #define INTVR 0x1a 6999 #define IMVR 0x1c 7000 #define TRB 0x20 7001 #define TRBL 0x20 7002 #define TRBH 0x21 7003 #define SR0 0x22 7004 #define SR1 0x23 7005 #define SR2 0x24 7006 #define SR3 0x25 7007 #define FST 0x26 7008 #define IE0 0x28 7009 #define IE1 0x29 7010 #define IE2 0x2a 7011 #define FIE 0x2b 7012 #define CMD 0x2c 7013 #define MD0 0x2e 7014 #define MD1 0x2f 7015 #define MD2 0x30 7016 #define CTL 0x31 7017 #define SA0 0x32 7018 #define SA1 0x33 7019 #define IDL 0x34 7020 #define TMC 0x35 7021 #define RXS 0x36 7022 #define TXS 0x37 7023 #define TRC0 0x38 7024 #define TRC1 0x39 7025 #define RRC 0x3a 7026 #define CST0 0x3c 7027 #define CST1 0x3d 7028 #define TCNT 0x60 7029 #define TCNTL 0x60 7030 #define TCNTH 0x61 7031 #define TCONR 0x62 7032 #define TCONRL 0x62 7033 #define TCONRH 0x63 7034 #define TMCS 0x64 7035 #define TEPR 0x65 7036 #define DARL 0x80 7037 #define DARH 0x81 7038 #define DARB 0x82 7039 #define BAR 0x80 7040 #define BARL 0x80 7041 #define BARH 0x81 7042 #define BARB 0x82 7043 #define SAR 0x84 7044 #define SARL 0x84 7045 #define SARH 0x85 7046 #define SARB 0x86 7047 #define CPB 0x86 7048 #define CDA 0x88 7049 #define CDAL 0x88 7050 #define CDAH 0x89 7051 #define EDA 0x8a 7052 #define EDAL 0x8a 7053 #define EDAH 0x8b 7054 #define BFL 0x8c 7055 #define BFLL 0x8c 7056 #define BFLH 0x8d 7057 #define BCR 0x8e 7058 #define BCRL 0x8e 7059 #define BCRH 0x8f 7060 #define DSR 0x90 7061 #define DMR 0x91 7062 #define FCT 0x93 7063 #define DIR 0x94 7064 #define DCMD 0x95 7065 #define TIMER0 0x00 7066 #define TIMER1 0x08 7067 #define TIMER2 0x10 7068 #define TIMER3 0x18 7069 #define RXDMA 0x00 7070 #define TXDMA 0x20 7071 #define NOOP 0x00 7072 #define TXRESET 0x01 7073 #define TXENABLE 0x02 7074 #define TXDISABLE 0x03 7075 #define TXCRCINIT 0x04 7076 #define TXCRCEXCL 0x05 7077 #define TXEOM 0x06 7078 #define TXABORT 0x07 7079 #define MPON 0x08 7080 #define TXBUFCLR 0x09 7081 #define RXRESET 0x11 7082 #define RXENABLE 0x12 7083 #define RXDISABLE 0x13 7084 #define RXCRCINIT 0x14 7085 #define RXREJECT 0x15 7086 #define SEARCHMP 0x16 7087 #define RXCRCEXCL 0x17 7088 #define RXCRCCALC 0x18 7089 #define CHRESET 0x21 7090 #define HUNT 0x31 7091 #define SWABORT 0x01 7092 #define FEICLEAR 0x02 7093 #define TXINTE BIT7 7094 #define RXINTE BIT6 7095 #define TXRDYE BIT1 7096 #define RXRDYE BIT0 7097 #define UDRN BIT7 7098 #define IDLE BIT6 7099 #define SYNCD BIT4 7100 #define FLGD BIT4 7101 #define CCTS BIT3 7102 #define CDCD BIT2 7103 #define BRKD BIT1 7104 #define ABTD BIT1 7105 #define GAPD BIT1 7106 #define BRKE BIT0 7107 #define IDLD BIT0 7108 #define EOM BIT7 7109 #define PMP BIT6 7110 #define SHRT BIT6 7111 #define PE BIT5 7112 #define ABT BIT5 7113 #define FRME BIT4 7114 #define RBIT BIT4 7115 #define OVRN BIT3 7116 #define CRCE BIT2 7117 #define WAKEUP_CHARS 256 7118 #if SYNCLINK_GENERIC_HDLC 7119 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7120 #endif 7121 #ifdef SANITY_CHECK 7122 #else 7123 #endif 7124 #if SYNCLINK_GENERIC_HDLC 7125 /* LDV_COMMENT_END_PREP */ 7126 /* LDV_COMMENT_BEGIN_PREP */ 7127 #endif 7128 #if SYNCLINK_GENERIC_HDLC 7129 #endif 7130 #if SYNCLINK_GENERIC_HDLC 7131 #endif 7132 #ifdef CMSPAR 7133 #endif 7134 #if SYNCLINK_GENERIC_HDLC 7135 #endif 7136 #if SYNCLINK_GENERIC_HDLC 7137 #endif 7138 #if 0 7139 #endif 7140 #if SYNCLINK_GENERIC_HDLC 7141 #endif 7142 #if SYNCLINK_GENERIC_HDLC 7143 #endif 7144 #define TESTFRAMESIZE 20 7145 #if SYNCLINK_GENERIC_HDLC 7146 #endif 7147 #define CALC_REGADDR() \ 7148 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7149 if (info->port_num > 1) \ 7150 RegAddr += 256; \ 7151 if ( info->port_num & 1) { \ 7152 if (Addr > 0x7f) \ 7153 RegAddr += 0x40; \ 7154 else if (Addr > 0x1f && Addr < 0x60) \ 7155 RegAddr += 0x20; \ 7156 } 7157 /* LDV_COMMENT_END_PREP */ 7158 7159 /** STRUCT: struct type: tty_port_operations, struct name: port_ops **/ 7160 /* content: static int carrier_raised(struct tty_port *port)*/ 7161 /* LDV_COMMENT_BEGIN_PREP */ 7162 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 7163 #if defined(__i386__) 7164 # define BREAKPOINT() asm(" int $3"); 7165 #else 7166 # define BREAKPOINT() { } 7167 #endif 7168 #define MAX_DEVICES 12 7169 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 7170 #define SYNCLINK_GENERIC_HDLC 1 7171 #else 7172 #define SYNCLINK_GENERIC_HDLC 0 7173 #endif 7174 #define GET_USER(error,value,addr) error = get_user(value,addr) 7175 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 7176 #define PUT_USER(error,value,addr) error = put_user(value,addr) 7177 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 7178 #define SCABUFSIZE 1024 7179 #define SCA_MEM_SIZE 0x40000 7180 #define SCA_BASE_SIZE 512 7181 #define SCA_REG_SIZE 16 7182 #define SCA_MAX_PORTS 4 7183 #define SCAMAXDESC 128 7184 #define BUFFERLISTSIZE 4096 7185 #define BH_RECEIVE 1 7186 #define BH_TRANSMIT 2 7187 #define BH_STATUS 4 7188 #define IO_PIN_SHUTDOWN_LIMIT 100 7189 #if SYNCLINK_GENERIC_HDLC 7190 #endif 7191 #define MGSL_MAGIC 0x5401 7192 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 7193 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 7194 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 7195 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 7196 #define LPR 0x00 7197 #define PABR0 0x02 7198 #define PABR1 0x03 7199 #define WCRL 0x04 7200 #define WCRM 0x05 7201 #define WCRH 0x06 7202 #define DPCR 0x08 7203 #define DMER 0x09 7204 #define ISR0 0x10 7205 #define ISR1 0x11 7206 #define ISR2 0x12 7207 #define IER0 0x14 7208 #define IER1 0x15 7209 #define IER2 0x16 7210 #define ITCR 0x18 7211 #define INTVR 0x1a 7212 #define IMVR 0x1c 7213 #define TRB 0x20 7214 #define TRBL 0x20 7215 #define TRBH 0x21 7216 #define SR0 0x22 7217 #define SR1 0x23 7218 #define SR2 0x24 7219 #define SR3 0x25 7220 #define FST 0x26 7221 #define IE0 0x28 7222 #define IE1 0x29 7223 #define IE2 0x2a 7224 #define FIE 0x2b 7225 #define CMD 0x2c 7226 #define MD0 0x2e 7227 #define MD1 0x2f 7228 #define MD2 0x30 7229 #define CTL 0x31 7230 #define SA0 0x32 7231 #define SA1 0x33 7232 #define IDL 0x34 7233 #define TMC 0x35 7234 #define RXS 0x36 7235 #define TXS 0x37 7236 #define TRC0 0x38 7237 #define TRC1 0x39 7238 #define RRC 0x3a 7239 #define CST0 0x3c 7240 #define CST1 0x3d 7241 #define TCNT 0x60 7242 #define TCNTL 0x60 7243 #define TCNTH 0x61 7244 #define TCONR 0x62 7245 #define TCONRL 0x62 7246 #define TCONRH 0x63 7247 #define TMCS 0x64 7248 #define TEPR 0x65 7249 #define DARL 0x80 7250 #define DARH 0x81 7251 #define DARB 0x82 7252 #define BAR 0x80 7253 #define BARL 0x80 7254 #define BARH 0x81 7255 #define BARB 0x82 7256 #define SAR 0x84 7257 #define SARL 0x84 7258 #define SARH 0x85 7259 #define SARB 0x86 7260 #define CPB 0x86 7261 #define CDA 0x88 7262 #define CDAL 0x88 7263 #define CDAH 0x89 7264 #define EDA 0x8a 7265 #define EDAL 0x8a 7266 #define EDAH 0x8b 7267 #define BFL 0x8c 7268 #define BFLL 0x8c 7269 #define BFLH 0x8d 7270 #define BCR 0x8e 7271 #define BCRL 0x8e 7272 #define BCRH 0x8f 7273 #define DSR 0x90 7274 #define DMR 0x91 7275 #define FCT 0x93 7276 #define DIR 0x94 7277 #define DCMD 0x95 7278 #define TIMER0 0x00 7279 #define TIMER1 0x08 7280 #define TIMER2 0x10 7281 #define TIMER3 0x18 7282 #define RXDMA 0x00 7283 #define TXDMA 0x20 7284 #define NOOP 0x00 7285 #define TXRESET 0x01 7286 #define TXENABLE 0x02 7287 #define TXDISABLE 0x03 7288 #define TXCRCINIT 0x04 7289 #define TXCRCEXCL 0x05 7290 #define TXEOM 0x06 7291 #define TXABORT 0x07 7292 #define MPON 0x08 7293 #define TXBUFCLR 0x09 7294 #define RXRESET 0x11 7295 #define RXENABLE 0x12 7296 #define RXDISABLE 0x13 7297 #define RXCRCINIT 0x14 7298 #define RXREJECT 0x15 7299 #define SEARCHMP 0x16 7300 #define RXCRCEXCL 0x17 7301 #define RXCRCCALC 0x18 7302 #define CHRESET 0x21 7303 #define HUNT 0x31 7304 #define SWABORT 0x01 7305 #define FEICLEAR 0x02 7306 #define TXINTE BIT7 7307 #define RXINTE BIT6 7308 #define TXRDYE BIT1 7309 #define RXRDYE BIT0 7310 #define UDRN BIT7 7311 #define IDLE BIT6 7312 #define SYNCD BIT4 7313 #define FLGD BIT4 7314 #define CCTS BIT3 7315 #define CDCD BIT2 7316 #define BRKD BIT1 7317 #define ABTD BIT1 7318 #define GAPD BIT1 7319 #define BRKE BIT0 7320 #define IDLD BIT0 7321 #define EOM BIT7 7322 #define PMP BIT6 7323 #define SHRT BIT6 7324 #define PE BIT5 7325 #define ABT BIT5 7326 #define FRME BIT4 7327 #define RBIT BIT4 7328 #define OVRN BIT3 7329 #define CRCE BIT2 7330 #define WAKEUP_CHARS 256 7331 #if SYNCLINK_GENERIC_HDLC 7332 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7333 #endif 7334 #ifdef SANITY_CHECK 7335 #else 7336 #endif 7337 #if SYNCLINK_GENERIC_HDLC 7338 #endif 7339 #if SYNCLINK_GENERIC_HDLC 7340 #endif 7341 #if SYNCLINK_GENERIC_HDLC 7342 #endif 7343 #ifdef CMSPAR 7344 #endif 7345 /* LDV_COMMENT_END_PREP */ 7346 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "carrier_raised" */ 7347 struct tty_port * var_group6; 7348 /* LDV_COMMENT_BEGIN_PREP */ 7349 #if SYNCLINK_GENERIC_HDLC 7350 #endif 7351 #if SYNCLINK_GENERIC_HDLC 7352 #endif 7353 #if 0 7354 #endif 7355 #if SYNCLINK_GENERIC_HDLC 7356 #endif 7357 #if SYNCLINK_GENERIC_HDLC 7358 #endif 7359 #define TESTFRAMESIZE 20 7360 #if SYNCLINK_GENERIC_HDLC 7361 #endif 7362 #define CALC_REGADDR() \ 7363 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7364 if (info->port_num > 1) \ 7365 RegAddr += 256; \ 7366 if ( info->port_num & 1) { \ 7367 if (Addr > 0x7f) \ 7368 RegAddr += 0x40; \ 7369 else if (Addr > 0x1f && Addr < 0x60) \ 7370 RegAddr += 0x20; \ 7371 } 7372 /* LDV_COMMENT_END_PREP */ 7373 /* content: static void dtr_rts(struct tty_port *port, int on)*/ 7374 /* LDV_COMMENT_BEGIN_PREP */ 7375 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 7376 #if defined(__i386__) 7377 # define BREAKPOINT() asm(" int $3"); 7378 #else 7379 # define BREAKPOINT() { } 7380 #endif 7381 #define MAX_DEVICES 12 7382 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 7383 #define SYNCLINK_GENERIC_HDLC 1 7384 #else 7385 #define SYNCLINK_GENERIC_HDLC 0 7386 #endif 7387 #define GET_USER(error,value,addr) error = get_user(value,addr) 7388 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 7389 #define PUT_USER(error,value,addr) error = put_user(value,addr) 7390 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 7391 #define SCABUFSIZE 1024 7392 #define SCA_MEM_SIZE 0x40000 7393 #define SCA_BASE_SIZE 512 7394 #define SCA_REG_SIZE 16 7395 #define SCA_MAX_PORTS 4 7396 #define SCAMAXDESC 128 7397 #define BUFFERLISTSIZE 4096 7398 #define BH_RECEIVE 1 7399 #define BH_TRANSMIT 2 7400 #define BH_STATUS 4 7401 #define IO_PIN_SHUTDOWN_LIMIT 100 7402 #if SYNCLINK_GENERIC_HDLC 7403 #endif 7404 #define MGSL_MAGIC 0x5401 7405 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 7406 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 7407 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 7408 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 7409 #define LPR 0x00 7410 #define PABR0 0x02 7411 #define PABR1 0x03 7412 #define WCRL 0x04 7413 #define WCRM 0x05 7414 #define WCRH 0x06 7415 #define DPCR 0x08 7416 #define DMER 0x09 7417 #define ISR0 0x10 7418 #define ISR1 0x11 7419 #define ISR2 0x12 7420 #define IER0 0x14 7421 #define IER1 0x15 7422 #define IER2 0x16 7423 #define ITCR 0x18 7424 #define INTVR 0x1a 7425 #define IMVR 0x1c 7426 #define TRB 0x20 7427 #define TRBL 0x20 7428 #define TRBH 0x21 7429 #define SR0 0x22 7430 #define SR1 0x23 7431 #define SR2 0x24 7432 #define SR3 0x25 7433 #define FST 0x26 7434 #define IE0 0x28 7435 #define IE1 0x29 7436 #define IE2 0x2a 7437 #define FIE 0x2b 7438 #define CMD 0x2c 7439 #define MD0 0x2e 7440 #define MD1 0x2f 7441 #define MD2 0x30 7442 #define CTL 0x31 7443 #define SA0 0x32 7444 #define SA1 0x33 7445 #define IDL 0x34 7446 #define TMC 0x35 7447 #define RXS 0x36 7448 #define TXS 0x37 7449 #define TRC0 0x38 7450 #define TRC1 0x39 7451 #define RRC 0x3a 7452 #define CST0 0x3c 7453 #define CST1 0x3d 7454 #define TCNT 0x60 7455 #define TCNTL 0x60 7456 #define TCNTH 0x61 7457 #define TCONR 0x62 7458 #define TCONRL 0x62 7459 #define TCONRH 0x63 7460 #define TMCS 0x64 7461 #define TEPR 0x65 7462 #define DARL 0x80 7463 #define DARH 0x81 7464 #define DARB 0x82 7465 #define BAR 0x80 7466 #define BARL 0x80 7467 #define BARH 0x81 7468 #define BARB 0x82 7469 #define SAR 0x84 7470 #define SARL 0x84 7471 #define SARH 0x85 7472 #define SARB 0x86 7473 #define CPB 0x86 7474 #define CDA 0x88 7475 #define CDAL 0x88 7476 #define CDAH 0x89 7477 #define EDA 0x8a 7478 #define EDAL 0x8a 7479 #define EDAH 0x8b 7480 #define BFL 0x8c 7481 #define BFLL 0x8c 7482 #define BFLH 0x8d 7483 #define BCR 0x8e 7484 #define BCRL 0x8e 7485 #define BCRH 0x8f 7486 #define DSR 0x90 7487 #define DMR 0x91 7488 #define FCT 0x93 7489 #define DIR 0x94 7490 #define DCMD 0x95 7491 #define TIMER0 0x00 7492 #define TIMER1 0x08 7493 #define TIMER2 0x10 7494 #define TIMER3 0x18 7495 #define RXDMA 0x00 7496 #define TXDMA 0x20 7497 #define NOOP 0x00 7498 #define TXRESET 0x01 7499 #define TXENABLE 0x02 7500 #define TXDISABLE 0x03 7501 #define TXCRCINIT 0x04 7502 #define TXCRCEXCL 0x05 7503 #define TXEOM 0x06 7504 #define TXABORT 0x07 7505 #define MPON 0x08 7506 #define TXBUFCLR 0x09 7507 #define RXRESET 0x11 7508 #define RXENABLE 0x12 7509 #define RXDISABLE 0x13 7510 #define RXCRCINIT 0x14 7511 #define RXREJECT 0x15 7512 #define SEARCHMP 0x16 7513 #define RXCRCEXCL 0x17 7514 #define RXCRCCALC 0x18 7515 #define CHRESET 0x21 7516 #define HUNT 0x31 7517 #define SWABORT 0x01 7518 #define FEICLEAR 0x02 7519 #define TXINTE BIT7 7520 #define RXINTE BIT6 7521 #define TXRDYE BIT1 7522 #define RXRDYE BIT0 7523 #define UDRN BIT7 7524 #define IDLE BIT6 7525 #define SYNCD BIT4 7526 #define FLGD BIT4 7527 #define CCTS BIT3 7528 #define CDCD BIT2 7529 #define BRKD BIT1 7530 #define ABTD BIT1 7531 #define GAPD BIT1 7532 #define BRKE BIT0 7533 #define IDLD BIT0 7534 #define EOM BIT7 7535 #define PMP BIT6 7536 #define SHRT BIT6 7537 #define PE BIT5 7538 #define ABT BIT5 7539 #define FRME BIT4 7540 #define RBIT BIT4 7541 #define OVRN BIT3 7542 #define CRCE BIT2 7543 #define WAKEUP_CHARS 256 7544 #if SYNCLINK_GENERIC_HDLC 7545 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7546 #endif 7547 #ifdef SANITY_CHECK 7548 #else 7549 #endif 7550 #if SYNCLINK_GENERIC_HDLC 7551 #endif 7552 #if SYNCLINK_GENERIC_HDLC 7553 #endif 7554 #if SYNCLINK_GENERIC_HDLC 7555 #endif 7556 #ifdef CMSPAR 7557 #endif 7558 /* LDV_COMMENT_END_PREP */ 7559 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "dtr_rts" */ 7560 int var_dtr_rts_70_p1; 7561 /* LDV_COMMENT_BEGIN_PREP */ 7562 #if SYNCLINK_GENERIC_HDLC 7563 #endif 7564 #if SYNCLINK_GENERIC_HDLC 7565 #endif 7566 #if 0 7567 #endif 7568 #if SYNCLINK_GENERIC_HDLC 7569 #endif 7570 #if SYNCLINK_GENERIC_HDLC 7571 #endif 7572 #define TESTFRAMESIZE 20 7573 #if SYNCLINK_GENERIC_HDLC 7574 #endif 7575 #define CALC_REGADDR() \ 7576 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7577 if (info->port_num > 1) \ 7578 RegAddr += 256; \ 7579 if ( info->port_num & 1) { \ 7580 if (Addr > 0x7f) \ 7581 RegAddr += 0x40; \ 7582 else if (Addr > 0x1f && Addr < 0x60) \ 7583 RegAddr += 0x20; \ 7584 } 7585 /* LDV_COMMENT_END_PREP */ 7586 7587 /** STRUCT: struct type: tty_operations, struct name: ops **/ 7588 /* content: static int install(struct tty_driver *driver, struct tty_struct *tty)*/ 7589 /* LDV_COMMENT_BEGIN_PREP */ 7590 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 7591 #if defined(__i386__) 7592 # define BREAKPOINT() asm(" int $3"); 7593 #else 7594 # define BREAKPOINT() { } 7595 #endif 7596 #define MAX_DEVICES 12 7597 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 7598 #define SYNCLINK_GENERIC_HDLC 1 7599 #else 7600 #define SYNCLINK_GENERIC_HDLC 0 7601 #endif 7602 #define GET_USER(error,value,addr) error = get_user(value,addr) 7603 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 7604 #define PUT_USER(error,value,addr) error = put_user(value,addr) 7605 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 7606 #define SCABUFSIZE 1024 7607 #define SCA_MEM_SIZE 0x40000 7608 #define SCA_BASE_SIZE 512 7609 #define SCA_REG_SIZE 16 7610 #define SCA_MAX_PORTS 4 7611 #define SCAMAXDESC 128 7612 #define BUFFERLISTSIZE 4096 7613 #define BH_RECEIVE 1 7614 #define BH_TRANSMIT 2 7615 #define BH_STATUS 4 7616 #define IO_PIN_SHUTDOWN_LIMIT 100 7617 #if SYNCLINK_GENERIC_HDLC 7618 #endif 7619 #define MGSL_MAGIC 0x5401 7620 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 7621 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 7622 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 7623 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 7624 #define LPR 0x00 7625 #define PABR0 0x02 7626 #define PABR1 0x03 7627 #define WCRL 0x04 7628 #define WCRM 0x05 7629 #define WCRH 0x06 7630 #define DPCR 0x08 7631 #define DMER 0x09 7632 #define ISR0 0x10 7633 #define ISR1 0x11 7634 #define ISR2 0x12 7635 #define IER0 0x14 7636 #define IER1 0x15 7637 #define IER2 0x16 7638 #define ITCR 0x18 7639 #define INTVR 0x1a 7640 #define IMVR 0x1c 7641 #define TRB 0x20 7642 #define TRBL 0x20 7643 #define TRBH 0x21 7644 #define SR0 0x22 7645 #define SR1 0x23 7646 #define SR2 0x24 7647 #define SR3 0x25 7648 #define FST 0x26 7649 #define IE0 0x28 7650 #define IE1 0x29 7651 #define IE2 0x2a 7652 #define FIE 0x2b 7653 #define CMD 0x2c 7654 #define MD0 0x2e 7655 #define MD1 0x2f 7656 #define MD2 0x30 7657 #define CTL 0x31 7658 #define SA0 0x32 7659 #define SA1 0x33 7660 #define IDL 0x34 7661 #define TMC 0x35 7662 #define RXS 0x36 7663 #define TXS 0x37 7664 #define TRC0 0x38 7665 #define TRC1 0x39 7666 #define RRC 0x3a 7667 #define CST0 0x3c 7668 #define CST1 0x3d 7669 #define TCNT 0x60 7670 #define TCNTL 0x60 7671 #define TCNTH 0x61 7672 #define TCONR 0x62 7673 #define TCONRL 0x62 7674 #define TCONRH 0x63 7675 #define TMCS 0x64 7676 #define TEPR 0x65 7677 #define DARL 0x80 7678 #define DARH 0x81 7679 #define DARB 0x82 7680 #define BAR 0x80 7681 #define BARL 0x80 7682 #define BARH 0x81 7683 #define BARB 0x82 7684 #define SAR 0x84 7685 #define SARL 0x84 7686 #define SARH 0x85 7687 #define SARB 0x86 7688 #define CPB 0x86 7689 #define CDA 0x88 7690 #define CDAL 0x88 7691 #define CDAH 0x89 7692 #define EDA 0x8a 7693 #define EDAL 0x8a 7694 #define EDAH 0x8b 7695 #define BFL 0x8c 7696 #define BFLL 0x8c 7697 #define BFLH 0x8d 7698 #define BCR 0x8e 7699 #define BCRL 0x8e 7700 #define BCRH 0x8f 7701 #define DSR 0x90 7702 #define DMR 0x91 7703 #define FCT 0x93 7704 #define DIR 0x94 7705 #define DCMD 0x95 7706 #define TIMER0 0x00 7707 #define TIMER1 0x08 7708 #define TIMER2 0x10 7709 #define TIMER3 0x18 7710 #define RXDMA 0x00 7711 #define TXDMA 0x20 7712 #define NOOP 0x00 7713 #define TXRESET 0x01 7714 #define TXENABLE 0x02 7715 #define TXDISABLE 0x03 7716 #define TXCRCINIT 0x04 7717 #define TXCRCEXCL 0x05 7718 #define TXEOM 0x06 7719 #define TXABORT 0x07 7720 #define MPON 0x08 7721 #define TXBUFCLR 0x09 7722 #define RXRESET 0x11 7723 #define RXENABLE 0x12 7724 #define RXDISABLE 0x13 7725 #define RXCRCINIT 0x14 7726 #define RXREJECT 0x15 7727 #define SEARCHMP 0x16 7728 #define RXCRCEXCL 0x17 7729 #define RXCRCCALC 0x18 7730 #define CHRESET 0x21 7731 #define HUNT 0x31 7732 #define SWABORT 0x01 7733 #define FEICLEAR 0x02 7734 #define TXINTE BIT7 7735 #define RXINTE BIT6 7736 #define TXRDYE BIT1 7737 #define RXRDYE BIT0 7738 #define UDRN BIT7 7739 #define IDLE BIT6 7740 #define SYNCD BIT4 7741 #define FLGD BIT4 7742 #define CCTS BIT3 7743 #define CDCD BIT2 7744 #define BRKD BIT1 7745 #define ABTD BIT1 7746 #define GAPD BIT1 7747 #define BRKE BIT0 7748 #define IDLD BIT0 7749 #define EOM BIT7 7750 #define PMP BIT6 7751 #define SHRT BIT6 7752 #define PE BIT5 7753 #define ABT BIT5 7754 #define FRME BIT4 7755 #define RBIT BIT4 7756 #define OVRN BIT3 7757 #define CRCE BIT2 7758 #define WAKEUP_CHARS 256 7759 #if SYNCLINK_GENERIC_HDLC 7760 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7761 #endif 7762 #ifdef SANITY_CHECK 7763 #else 7764 #endif 7765 /* LDV_COMMENT_END_PREP */ 7766 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "install" */ 7767 struct tty_driver * var_group7; 7768 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "install" */ 7769 struct tty_struct * var_group8; 7770 /* LDV_COMMENT_BEGIN_PREP */ 7771 #if SYNCLINK_GENERIC_HDLC 7772 #endif 7773 #if SYNCLINK_GENERIC_HDLC 7774 #endif 7775 #if SYNCLINK_GENERIC_HDLC 7776 #endif 7777 #ifdef CMSPAR 7778 #endif 7779 #if SYNCLINK_GENERIC_HDLC 7780 #endif 7781 #if SYNCLINK_GENERIC_HDLC 7782 #endif 7783 #if 0 7784 #endif 7785 #if SYNCLINK_GENERIC_HDLC 7786 #endif 7787 #if SYNCLINK_GENERIC_HDLC 7788 #endif 7789 #define TESTFRAMESIZE 20 7790 #if SYNCLINK_GENERIC_HDLC 7791 #endif 7792 #define CALC_REGADDR() \ 7793 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 7794 if (info->port_num > 1) \ 7795 RegAddr += 256; \ 7796 if ( info->port_num & 1) { \ 7797 if (Addr > 0x7f) \ 7798 RegAddr += 0x40; \ 7799 else if (Addr > 0x1f && Addr < 0x60) \ 7800 RegAddr += 0x20; \ 7801 } 7802 /* LDV_COMMENT_END_PREP */ 7803 /* content: static int open(struct tty_struct *tty, struct file *filp)*/ 7804 /* LDV_COMMENT_BEGIN_PREP */ 7805 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 7806 #if defined(__i386__) 7807 # define BREAKPOINT() asm(" int $3"); 7808 #else 7809 # define BREAKPOINT() { } 7810 #endif 7811 #define MAX_DEVICES 12 7812 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 7813 #define SYNCLINK_GENERIC_HDLC 1 7814 #else 7815 #define SYNCLINK_GENERIC_HDLC 0 7816 #endif 7817 #define GET_USER(error,value,addr) error = get_user(value,addr) 7818 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 7819 #define PUT_USER(error,value,addr) error = put_user(value,addr) 7820 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 7821 #define SCABUFSIZE 1024 7822 #define SCA_MEM_SIZE 0x40000 7823 #define SCA_BASE_SIZE 512 7824 #define SCA_REG_SIZE 16 7825 #define SCA_MAX_PORTS 4 7826 #define SCAMAXDESC 128 7827 #define BUFFERLISTSIZE 4096 7828 #define BH_RECEIVE 1 7829 #define BH_TRANSMIT 2 7830 #define BH_STATUS 4 7831 #define IO_PIN_SHUTDOWN_LIMIT 100 7832 #if SYNCLINK_GENERIC_HDLC 7833 #endif 7834 #define MGSL_MAGIC 0x5401 7835 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 7836 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 7837 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 7838 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 7839 #define LPR 0x00 7840 #define PABR0 0x02 7841 #define PABR1 0x03 7842 #define WCRL 0x04 7843 #define WCRM 0x05 7844 #define WCRH 0x06 7845 #define DPCR 0x08 7846 #define DMER 0x09 7847 #define ISR0 0x10 7848 #define ISR1 0x11 7849 #define ISR2 0x12 7850 #define IER0 0x14 7851 #define IER1 0x15 7852 #define IER2 0x16 7853 #define ITCR 0x18 7854 #define INTVR 0x1a 7855 #define IMVR 0x1c 7856 #define TRB 0x20 7857 #define TRBL 0x20 7858 #define TRBH 0x21 7859 #define SR0 0x22 7860 #define SR1 0x23 7861 #define SR2 0x24 7862 #define SR3 0x25 7863 #define FST 0x26 7864 #define IE0 0x28 7865 #define IE1 0x29 7866 #define IE2 0x2a 7867 #define FIE 0x2b 7868 #define CMD 0x2c 7869 #define MD0 0x2e 7870 #define MD1 0x2f 7871 #define MD2 0x30 7872 #define CTL 0x31 7873 #define SA0 0x32 7874 #define SA1 0x33 7875 #define IDL 0x34 7876 #define TMC 0x35 7877 #define RXS 0x36 7878 #define TXS 0x37 7879 #define TRC0 0x38 7880 #define TRC1 0x39 7881 #define RRC 0x3a 7882 #define CST0 0x3c 7883 #define CST1 0x3d 7884 #define TCNT 0x60 7885 #define TCNTL 0x60 7886 #define TCNTH 0x61 7887 #define TCONR 0x62 7888 #define TCONRL 0x62 7889 #define TCONRH 0x63 7890 #define TMCS 0x64 7891 #define TEPR 0x65 7892 #define DARL 0x80 7893 #define DARH 0x81 7894 #define DARB 0x82 7895 #define BAR 0x80 7896 #define BARL 0x80 7897 #define BARH 0x81 7898 #define BARB 0x82 7899 #define SAR 0x84 7900 #define SARL 0x84 7901 #define SARH 0x85 7902 #define SARB 0x86 7903 #define CPB 0x86 7904 #define CDA 0x88 7905 #define CDAL 0x88 7906 #define CDAH 0x89 7907 #define EDA 0x8a 7908 #define EDAL 0x8a 7909 #define EDAH 0x8b 7910 #define BFL 0x8c 7911 #define BFLL 0x8c 7912 #define BFLH 0x8d 7913 #define BCR 0x8e 7914 #define BCRL 0x8e 7915 #define BCRH 0x8f 7916 #define DSR 0x90 7917 #define DMR 0x91 7918 #define FCT 0x93 7919 #define DIR 0x94 7920 #define DCMD 0x95 7921 #define TIMER0 0x00 7922 #define TIMER1 0x08 7923 #define TIMER2 0x10 7924 #define TIMER3 0x18 7925 #define RXDMA 0x00 7926 #define TXDMA 0x20 7927 #define NOOP 0x00 7928 #define TXRESET 0x01 7929 #define TXENABLE 0x02 7930 #define TXDISABLE 0x03 7931 #define TXCRCINIT 0x04 7932 #define TXCRCEXCL 0x05 7933 #define TXEOM 0x06 7934 #define TXABORT 0x07 7935 #define MPON 0x08 7936 #define TXBUFCLR 0x09 7937 #define RXRESET 0x11 7938 #define RXENABLE 0x12 7939 #define RXDISABLE 0x13 7940 #define RXCRCINIT 0x14 7941 #define RXREJECT 0x15 7942 #define SEARCHMP 0x16 7943 #define RXCRCEXCL 0x17 7944 #define RXCRCCALC 0x18 7945 #define CHRESET 0x21 7946 #define HUNT 0x31 7947 #define SWABORT 0x01 7948 #define FEICLEAR 0x02 7949 #define TXINTE BIT7 7950 #define RXINTE BIT6 7951 #define TXRDYE BIT1 7952 #define RXRDYE BIT0 7953 #define UDRN BIT7 7954 #define IDLE BIT6 7955 #define SYNCD BIT4 7956 #define FLGD BIT4 7957 #define CCTS BIT3 7958 #define CDCD BIT2 7959 #define BRKD BIT1 7960 #define ABTD BIT1 7961 #define GAPD BIT1 7962 #define BRKE BIT0 7963 #define IDLD BIT0 7964 #define EOM BIT7 7965 #define PMP BIT6 7966 #define SHRT BIT6 7967 #define PE BIT5 7968 #define ABT BIT5 7969 #define FRME BIT4 7970 #define RBIT BIT4 7971 #define OVRN BIT3 7972 #define CRCE BIT2 7973 #define WAKEUP_CHARS 256 7974 #if SYNCLINK_GENERIC_HDLC 7975 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 7976 #endif 7977 #ifdef SANITY_CHECK 7978 #else 7979 #endif 7980 /* LDV_COMMENT_END_PREP */ 7981 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "open" */ 7982 static int res_open_4; 7983 /* LDV_COMMENT_BEGIN_PREP */ 7984 #if SYNCLINK_GENERIC_HDLC 7985 #endif 7986 #if SYNCLINK_GENERIC_HDLC 7987 #endif 7988 #if SYNCLINK_GENERIC_HDLC 7989 #endif 7990 #ifdef CMSPAR 7991 #endif 7992 #if SYNCLINK_GENERIC_HDLC 7993 #endif 7994 #if SYNCLINK_GENERIC_HDLC 7995 #endif 7996 #if 0 7997 #endif 7998 #if SYNCLINK_GENERIC_HDLC 7999 #endif 8000 #if SYNCLINK_GENERIC_HDLC 8001 #endif 8002 #define TESTFRAMESIZE 20 8003 #if SYNCLINK_GENERIC_HDLC 8004 #endif 8005 #define CALC_REGADDR() \ 8006 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8007 if (info->port_num > 1) \ 8008 RegAddr += 256; \ 8009 if ( info->port_num & 1) { \ 8010 if (Addr > 0x7f) \ 8011 RegAddr += 0x40; \ 8012 else if (Addr > 0x1f && Addr < 0x60) \ 8013 RegAddr += 0x20; \ 8014 } 8015 /* LDV_COMMENT_END_PREP */ 8016 /* content: static void close(struct tty_struct *tty, struct file *filp)*/ 8017 /* LDV_COMMENT_BEGIN_PREP */ 8018 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8019 #if defined(__i386__) 8020 # define BREAKPOINT() asm(" int $3"); 8021 #else 8022 # define BREAKPOINT() { } 8023 #endif 8024 #define MAX_DEVICES 12 8025 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8026 #define SYNCLINK_GENERIC_HDLC 1 8027 #else 8028 #define SYNCLINK_GENERIC_HDLC 0 8029 #endif 8030 #define GET_USER(error,value,addr) error = get_user(value,addr) 8031 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8032 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8033 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8034 #define SCABUFSIZE 1024 8035 #define SCA_MEM_SIZE 0x40000 8036 #define SCA_BASE_SIZE 512 8037 #define SCA_REG_SIZE 16 8038 #define SCA_MAX_PORTS 4 8039 #define SCAMAXDESC 128 8040 #define BUFFERLISTSIZE 4096 8041 #define BH_RECEIVE 1 8042 #define BH_TRANSMIT 2 8043 #define BH_STATUS 4 8044 #define IO_PIN_SHUTDOWN_LIMIT 100 8045 #if SYNCLINK_GENERIC_HDLC 8046 #endif 8047 #define MGSL_MAGIC 0x5401 8048 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8049 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8050 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8051 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8052 #define LPR 0x00 8053 #define PABR0 0x02 8054 #define PABR1 0x03 8055 #define WCRL 0x04 8056 #define WCRM 0x05 8057 #define WCRH 0x06 8058 #define DPCR 0x08 8059 #define DMER 0x09 8060 #define ISR0 0x10 8061 #define ISR1 0x11 8062 #define ISR2 0x12 8063 #define IER0 0x14 8064 #define IER1 0x15 8065 #define IER2 0x16 8066 #define ITCR 0x18 8067 #define INTVR 0x1a 8068 #define IMVR 0x1c 8069 #define TRB 0x20 8070 #define TRBL 0x20 8071 #define TRBH 0x21 8072 #define SR0 0x22 8073 #define SR1 0x23 8074 #define SR2 0x24 8075 #define SR3 0x25 8076 #define FST 0x26 8077 #define IE0 0x28 8078 #define IE1 0x29 8079 #define IE2 0x2a 8080 #define FIE 0x2b 8081 #define CMD 0x2c 8082 #define MD0 0x2e 8083 #define MD1 0x2f 8084 #define MD2 0x30 8085 #define CTL 0x31 8086 #define SA0 0x32 8087 #define SA1 0x33 8088 #define IDL 0x34 8089 #define TMC 0x35 8090 #define RXS 0x36 8091 #define TXS 0x37 8092 #define TRC0 0x38 8093 #define TRC1 0x39 8094 #define RRC 0x3a 8095 #define CST0 0x3c 8096 #define CST1 0x3d 8097 #define TCNT 0x60 8098 #define TCNTL 0x60 8099 #define TCNTH 0x61 8100 #define TCONR 0x62 8101 #define TCONRL 0x62 8102 #define TCONRH 0x63 8103 #define TMCS 0x64 8104 #define TEPR 0x65 8105 #define DARL 0x80 8106 #define DARH 0x81 8107 #define DARB 0x82 8108 #define BAR 0x80 8109 #define BARL 0x80 8110 #define BARH 0x81 8111 #define BARB 0x82 8112 #define SAR 0x84 8113 #define SARL 0x84 8114 #define SARH 0x85 8115 #define SARB 0x86 8116 #define CPB 0x86 8117 #define CDA 0x88 8118 #define CDAL 0x88 8119 #define CDAH 0x89 8120 #define EDA 0x8a 8121 #define EDAL 0x8a 8122 #define EDAH 0x8b 8123 #define BFL 0x8c 8124 #define BFLL 0x8c 8125 #define BFLH 0x8d 8126 #define BCR 0x8e 8127 #define BCRL 0x8e 8128 #define BCRH 0x8f 8129 #define DSR 0x90 8130 #define DMR 0x91 8131 #define FCT 0x93 8132 #define DIR 0x94 8133 #define DCMD 0x95 8134 #define TIMER0 0x00 8135 #define TIMER1 0x08 8136 #define TIMER2 0x10 8137 #define TIMER3 0x18 8138 #define RXDMA 0x00 8139 #define TXDMA 0x20 8140 #define NOOP 0x00 8141 #define TXRESET 0x01 8142 #define TXENABLE 0x02 8143 #define TXDISABLE 0x03 8144 #define TXCRCINIT 0x04 8145 #define TXCRCEXCL 0x05 8146 #define TXEOM 0x06 8147 #define TXABORT 0x07 8148 #define MPON 0x08 8149 #define TXBUFCLR 0x09 8150 #define RXRESET 0x11 8151 #define RXENABLE 0x12 8152 #define RXDISABLE 0x13 8153 #define RXCRCINIT 0x14 8154 #define RXREJECT 0x15 8155 #define SEARCHMP 0x16 8156 #define RXCRCEXCL 0x17 8157 #define RXCRCCALC 0x18 8158 #define CHRESET 0x21 8159 #define HUNT 0x31 8160 #define SWABORT 0x01 8161 #define FEICLEAR 0x02 8162 #define TXINTE BIT7 8163 #define RXINTE BIT6 8164 #define TXRDYE BIT1 8165 #define RXRDYE BIT0 8166 #define UDRN BIT7 8167 #define IDLE BIT6 8168 #define SYNCD BIT4 8169 #define FLGD BIT4 8170 #define CCTS BIT3 8171 #define CDCD BIT2 8172 #define BRKD BIT1 8173 #define ABTD BIT1 8174 #define GAPD BIT1 8175 #define BRKE BIT0 8176 #define IDLD BIT0 8177 #define EOM BIT7 8178 #define PMP BIT6 8179 #define SHRT BIT6 8180 #define PE BIT5 8181 #define ABT BIT5 8182 #define FRME BIT4 8183 #define RBIT BIT4 8184 #define OVRN BIT3 8185 #define CRCE BIT2 8186 #define WAKEUP_CHARS 256 8187 #if SYNCLINK_GENERIC_HDLC 8188 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 8189 #endif 8190 #ifdef SANITY_CHECK 8191 #else 8192 #endif 8193 /* LDV_COMMENT_END_PREP */ 8194 /* LDV_COMMENT_BEGIN_PREP */ 8195 #if SYNCLINK_GENERIC_HDLC 8196 #endif 8197 #if SYNCLINK_GENERIC_HDLC 8198 #endif 8199 #if SYNCLINK_GENERIC_HDLC 8200 #endif 8201 #ifdef CMSPAR 8202 #endif 8203 #if SYNCLINK_GENERIC_HDLC 8204 #endif 8205 #if SYNCLINK_GENERIC_HDLC 8206 #endif 8207 #if 0 8208 #endif 8209 #if SYNCLINK_GENERIC_HDLC 8210 #endif 8211 #if SYNCLINK_GENERIC_HDLC 8212 #endif 8213 #define TESTFRAMESIZE 20 8214 #if SYNCLINK_GENERIC_HDLC 8215 #endif 8216 #define CALC_REGADDR() \ 8217 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8218 if (info->port_num > 1) \ 8219 RegAddr += 256; \ 8220 if ( info->port_num & 1) { \ 8221 if (Addr > 0x7f) \ 8222 RegAddr += 0x40; \ 8223 else if (Addr > 0x1f && Addr < 0x60) \ 8224 RegAddr += 0x20; \ 8225 } 8226 /* LDV_COMMENT_END_PREP */ 8227 /* content: static int write(struct tty_struct *tty, const unsigned char *buf, int count)*/ 8228 /* LDV_COMMENT_BEGIN_PREP */ 8229 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8230 #if defined(__i386__) 8231 # define BREAKPOINT() asm(" int $3"); 8232 #else 8233 # define BREAKPOINT() { } 8234 #endif 8235 #define MAX_DEVICES 12 8236 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8237 #define SYNCLINK_GENERIC_HDLC 1 8238 #else 8239 #define SYNCLINK_GENERIC_HDLC 0 8240 #endif 8241 #define GET_USER(error,value,addr) error = get_user(value,addr) 8242 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8243 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8244 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8245 #define SCABUFSIZE 1024 8246 #define SCA_MEM_SIZE 0x40000 8247 #define SCA_BASE_SIZE 512 8248 #define SCA_REG_SIZE 16 8249 #define SCA_MAX_PORTS 4 8250 #define SCAMAXDESC 128 8251 #define BUFFERLISTSIZE 4096 8252 #define BH_RECEIVE 1 8253 #define BH_TRANSMIT 2 8254 #define BH_STATUS 4 8255 #define IO_PIN_SHUTDOWN_LIMIT 100 8256 #if SYNCLINK_GENERIC_HDLC 8257 #endif 8258 #define MGSL_MAGIC 0x5401 8259 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8260 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8261 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8262 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8263 #define LPR 0x00 8264 #define PABR0 0x02 8265 #define PABR1 0x03 8266 #define WCRL 0x04 8267 #define WCRM 0x05 8268 #define WCRH 0x06 8269 #define DPCR 0x08 8270 #define DMER 0x09 8271 #define ISR0 0x10 8272 #define ISR1 0x11 8273 #define ISR2 0x12 8274 #define IER0 0x14 8275 #define IER1 0x15 8276 #define IER2 0x16 8277 #define ITCR 0x18 8278 #define INTVR 0x1a 8279 #define IMVR 0x1c 8280 #define TRB 0x20 8281 #define TRBL 0x20 8282 #define TRBH 0x21 8283 #define SR0 0x22 8284 #define SR1 0x23 8285 #define SR2 0x24 8286 #define SR3 0x25 8287 #define FST 0x26 8288 #define IE0 0x28 8289 #define IE1 0x29 8290 #define IE2 0x2a 8291 #define FIE 0x2b 8292 #define CMD 0x2c 8293 #define MD0 0x2e 8294 #define MD1 0x2f 8295 #define MD2 0x30 8296 #define CTL 0x31 8297 #define SA0 0x32 8298 #define SA1 0x33 8299 #define IDL 0x34 8300 #define TMC 0x35 8301 #define RXS 0x36 8302 #define TXS 0x37 8303 #define TRC0 0x38 8304 #define TRC1 0x39 8305 #define RRC 0x3a 8306 #define CST0 0x3c 8307 #define CST1 0x3d 8308 #define TCNT 0x60 8309 #define TCNTL 0x60 8310 #define TCNTH 0x61 8311 #define TCONR 0x62 8312 #define TCONRL 0x62 8313 #define TCONRH 0x63 8314 #define TMCS 0x64 8315 #define TEPR 0x65 8316 #define DARL 0x80 8317 #define DARH 0x81 8318 #define DARB 0x82 8319 #define BAR 0x80 8320 #define BARL 0x80 8321 #define BARH 0x81 8322 #define BARB 0x82 8323 #define SAR 0x84 8324 #define SARL 0x84 8325 #define SARH 0x85 8326 #define SARB 0x86 8327 #define CPB 0x86 8328 #define CDA 0x88 8329 #define CDAL 0x88 8330 #define CDAH 0x89 8331 #define EDA 0x8a 8332 #define EDAL 0x8a 8333 #define EDAH 0x8b 8334 #define BFL 0x8c 8335 #define BFLL 0x8c 8336 #define BFLH 0x8d 8337 #define BCR 0x8e 8338 #define BCRL 0x8e 8339 #define BCRH 0x8f 8340 #define DSR 0x90 8341 #define DMR 0x91 8342 #define FCT 0x93 8343 #define DIR 0x94 8344 #define DCMD 0x95 8345 #define TIMER0 0x00 8346 #define TIMER1 0x08 8347 #define TIMER2 0x10 8348 #define TIMER3 0x18 8349 #define RXDMA 0x00 8350 #define TXDMA 0x20 8351 #define NOOP 0x00 8352 #define TXRESET 0x01 8353 #define TXENABLE 0x02 8354 #define TXDISABLE 0x03 8355 #define TXCRCINIT 0x04 8356 #define TXCRCEXCL 0x05 8357 #define TXEOM 0x06 8358 #define TXABORT 0x07 8359 #define MPON 0x08 8360 #define TXBUFCLR 0x09 8361 #define RXRESET 0x11 8362 #define RXENABLE 0x12 8363 #define RXDISABLE 0x13 8364 #define RXCRCINIT 0x14 8365 #define RXREJECT 0x15 8366 #define SEARCHMP 0x16 8367 #define RXCRCEXCL 0x17 8368 #define RXCRCCALC 0x18 8369 #define CHRESET 0x21 8370 #define HUNT 0x31 8371 #define SWABORT 0x01 8372 #define FEICLEAR 0x02 8373 #define TXINTE BIT7 8374 #define RXINTE BIT6 8375 #define TXRDYE BIT1 8376 #define RXRDYE BIT0 8377 #define UDRN BIT7 8378 #define IDLE BIT6 8379 #define SYNCD BIT4 8380 #define FLGD BIT4 8381 #define CCTS BIT3 8382 #define CDCD BIT2 8383 #define BRKD BIT1 8384 #define ABTD BIT1 8385 #define GAPD BIT1 8386 #define BRKE BIT0 8387 #define IDLD BIT0 8388 #define EOM BIT7 8389 #define PMP BIT6 8390 #define SHRT BIT6 8391 #define PE BIT5 8392 #define ABT BIT5 8393 #define FRME BIT4 8394 #define RBIT BIT4 8395 #define OVRN BIT3 8396 #define CRCE BIT2 8397 #define WAKEUP_CHARS 256 8398 #if SYNCLINK_GENERIC_HDLC 8399 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 8400 #endif 8401 #ifdef SANITY_CHECK 8402 #else 8403 #endif 8404 /* LDV_COMMENT_END_PREP */ 8405 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "write" */ 8406 const unsigned char * var_write_8_p1; 8407 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "write" */ 8408 int var_write_8_p2; 8409 /* LDV_COMMENT_BEGIN_PREP */ 8410 #if SYNCLINK_GENERIC_HDLC 8411 #endif 8412 #if SYNCLINK_GENERIC_HDLC 8413 #endif 8414 #if SYNCLINK_GENERIC_HDLC 8415 #endif 8416 #ifdef CMSPAR 8417 #endif 8418 #if SYNCLINK_GENERIC_HDLC 8419 #endif 8420 #if SYNCLINK_GENERIC_HDLC 8421 #endif 8422 #if 0 8423 #endif 8424 #if SYNCLINK_GENERIC_HDLC 8425 #endif 8426 #if SYNCLINK_GENERIC_HDLC 8427 #endif 8428 #define TESTFRAMESIZE 20 8429 #if SYNCLINK_GENERIC_HDLC 8430 #endif 8431 #define CALC_REGADDR() \ 8432 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8433 if (info->port_num > 1) \ 8434 RegAddr += 256; \ 8435 if ( info->port_num & 1) { \ 8436 if (Addr > 0x7f) \ 8437 RegAddr += 0x40; \ 8438 else if (Addr > 0x1f && Addr < 0x60) \ 8439 RegAddr += 0x20; \ 8440 } 8441 /* LDV_COMMENT_END_PREP */ 8442 /* content: static int put_char(struct tty_struct *tty, unsigned char ch)*/ 8443 /* LDV_COMMENT_BEGIN_PREP */ 8444 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8445 #if defined(__i386__) 8446 # define BREAKPOINT() asm(" int $3"); 8447 #else 8448 # define BREAKPOINT() { } 8449 #endif 8450 #define MAX_DEVICES 12 8451 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8452 #define SYNCLINK_GENERIC_HDLC 1 8453 #else 8454 #define SYNCLINK_GENERIC_HDLC 0 8455 #endif 8456 #define GET_USER(error,value,addr) error = get_user(value,addr) 8457 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8458 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8459 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8460 #define SCABUFSIZE 1024 8461 #define SCA_MEM_SIZE 0x40000 8462 #define SCA_BASE_SIZE 512 8463 #define SCA_REG_SIZE 16 8464 #define SCA_MAX_PORTS 4 8465 #define SCAMAXDESC 128 8466 #define BUFFERLISTSIZE 4096 8467 #define BH_RECEIVE 1 8468 #define BH_TRANSMIT 2 8469 #define BH_STATUS 4 8470 #define IO_PIN_SHUTDOWN_LIMIT 100 8471 #if SYNCLINK_GENERIC_HDLC 8472 #endif 8473 #define MGSL_MAGIC 0x5401 8474 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8475 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8476 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8477 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8478 #define LPR 0x00 8479 #define PABR0 0x02 8480 #define PABR1 0x03 8481 #define WCRL 0x04 8482 #define WCRM 0x05 8483 #define WCRH 0x06 8484 #define DPCR 0x08 8485 #define DMER 0x09 8486 #define ISR0 0x10 8487 #define ISR1 0x11 8488 #define ISR2 0x12 8489 #define IER0 0x14 8490 #define IER1 0x15 8491 #define IER2 0x16 8492 #define ITCR 0x18 8493 #define INTVR 0x1a 8494 #define IMVR 0x1c 8495 #define TRB 0x20 8496 #define TRBL 0x20 8497 #define TRBH 0x21 8498 #define SR0 0x22 8499 #define SR1 0x23 8500 #define SR2 0x24 8501 #define SR3 0x25 8502 #define FST 0x26 8503 #define IE0 0x28 8504 #define IE1 0x29 8505 #define IE2 0x2a 8506 #define FIE 0x2b 8507 #define CMD 0x2c 8508 #define MD0 0x2e 8509 #define MD1 0x2f 8510 #define MD2 0x30 8511 #define CTL 0x31 8512 #define SA0 0x32 8513 #define SA1 0x33 8514 #define IDL 0x34 8515 #define TMC 0x35 8516 #define RXS 0x36 8517 #define TXS 0x37 8518 #define TRC0 0x38 8519 #define TRC1 0x39 8520 #define RRC 0x3a 8521 #define CST0 0x3c 8522 #define CST1 0x3d 8523 #define TCNT 0x60 8524 #define TCNTL 0x60 8525 #define TCNTH 0x61 8526 #define TCONR 0x62 8527 #define TCONRL 0x62 8528 #define TCONRH 0x63 8529 #define TMCS 0x64 8530 #define TEPR 0x65 8531 #define DARL 0x80 8532 #define DARH 0x81 8533 #define DARB 0x82 8534 #define BAR 0x80 8535 #define BARL 0x80 8536 #define BARH 0x81 8537 #define BARB 0x82 8538 #define SAR 0x84 8539 #define SARL 0x84 8540 #define SARH 0x85 8541 #define SARB 0x86 8542 #define CPB 0x86 8543 #define CDA 0x88 8544 #define CDAL 0x88 8545 #define CDAH 0x89 8546 #define EDA 0x8a 8547 #define EDAL 0x8a 8548 #define EDAH 0x8b 8549 #define BFL 0x8c 8550 #define BFLL 0x8c 8551 #define BFLH 0x8d 8552 #define BCR 0x8e 8553 #define BCRL 0x8e 8554 #define BCRH 0x8f 8555 #define DSR 0x90 8556 #define DMR 0x91 8557 #define FCT 0x93 8558 #define DIR 0x94 8559 #define DCMD 0x95 8560 #define TIMER0 0x00 8561 #define TIMER1 0x08 8562 #define TIMER2 0x10 8563 #define TIMER3 0x18 8564 #define RXDMA 0x00 8565 #define TXDMA 0x20 8566 #define NOOP 0x00 8567 #define TXRESET 0x01 8568 #define TXENABLE 0x02 8569 #define TXDISABLE 0x03 8570 #define TXCRCINIT 0x04 8571 #define TXCRCEXCL 0x05 8572 #define TXEOM 0x06 8573 #define TXABORT 0x07 8574 #define MPON 0x08 8575 #define TXBUFCLR 0x09 8576 #define RXRESET 0x11 8577 #define RXENABLE 0x12 8578 #define RXDISABLE 0x13 8579 #define RXCRCINIT 0x14 8580 #define RXREJECT 0x15 8581 #define SEARCHMP 0x16 8582 #define RXCRCEXCL 0x17 8583 #define RXCRCCALC 0x18 8584 #define CHRESET 0x21 8585 #define HUNT 0x31 8586 #define SWABORT 0x01 8587 #define FEICLEAR 0x02 8588 #define TXINTE BIT7 8589 #define RXINTE BIT6 8590 #define TXRDYE BIT1 8591 #define RXRDYE BIT0 8592 #define UDRN BIT7 8593 #define IDLE BIT6 8594 #define SYNCD BIT4 8595 #define FLGD BIT4 8596 #define CCTS BIT3 8597 #define CDCD BIT2 8598 #define BRKD BIT1 8599 #define ABTD BIT1 8600 #define GAPD BIT1 8601 #define BRKE BIT0 8602 #define IDLD BIT0 8603 #define EOM BIT7 8604 #define PMP BIT6 8605 #define SHRT BIT6 8606 #define PE BIT5 8607 #define ABT BIT5 8608 #define FRME BIT4 8609 #define RBIT BIT4 8610 #define OVRN BIT3 8611 #define CRCE BIT2 8612 #define WAKEUP_CHARS 256 8613 #if SYNCLINK_GENERIC_HDLC 8614 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 8615 #endif 8616 #ifdef SANITY_CHECK 8617 #else 8618 #endif 8619 /* LDV_COMMENT_END_PREP */ 8620 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "put_char" */ 8621 unsigned char var_put_char_9_p1; 8622 /* LDV_COMMENT_BEGIN_PREP */ 8623 #if SYNCLINK_GENERIC_HDLC 8624 #endif 8625 #if SYNCLINK_GENERIC_HDLC 8626 #endif 8627 #if SYNCLINK_GENERIC_HDLC 8628 #endif 8629 #ifdef CMSPAR 8630 #endif 8631 #if SYNCLINK_GENERIC_HDLC 8632 #endif 8633 #if SYNCLINK_GENERIC_HDLC 8634 #endif 8635 #if 0 8636 #endif 8637 #if SYNCLINK_GENERIC_HDLC 8638 #endif 8639 #if SYNCLINK_GENERIC_HDLC 8640 #endif 8641 #define TESTFRAMESIZE 20 8642 #if SYNCLINK_GENERIC_HDLC 8643 #endif 8644 #define CALC_REGADDR() \ 8645 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8646 if (info->port_num > 1) \ 8647 RegAddr += 256; \ 8648 if ( info->port_num & 1) { \ 8649 if (Addr > 0x7f) \ 8650 RegAddr += 0x40; \ 8651 else if (Addr > 0x1f && Addr < 0x60) \ 8652 RegAddr += 0x20; \ 8653 } 8654 /* LDV_COMMENT_END_PREP */ 8655 /* content: static void flush_chars(struct tty_struct *tty)*/ 8656 /* LDV_COMMENT_BEGIN_PREP */ 8657 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8658 #if defined(__i386__) 8659 # define BREAKPOINT() asm(" int $3"); 8660 #else 8661 # define BREAKPOINT() { } 8662 #endif 8663 #define MAX_DEVICES 12 8664 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8665 #define SYNCLINK_GENERIC_HDLC 1 8666 #else 8667 #define SYNCLINK_GENERIC_HDLC 0 8668 #endif 8669 #define GET_USER(error,value,addr) error = get_user(value,addr) 8670 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8671 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8672 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8673 #define SCABUFSIZE 1024 8674 #define SCA_MEM_SIZE 0x40000 8675 #define SCA_BASE_SIZE 512 8676 #define SCA_REG_SIZE 16 8677 #define SCA_MAX_PORTS 4 8678 #define SCAMAXDESC 128 8679 #define BUFFERLISTSIZE 4096 8680 #define BH_RECEIVE 1 8681 #define BH_TRANSMIT 2 8682 #define BH_STATUS 4 8683 #define IO_PIN_SHUTDOWN_LIMIT 100 8684 #if SYNCLINK_GENERIC_HDLC 8685 #endif 8686 #define MGSL_MAGIC 0x5401 8687 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8688 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8689 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8690 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8691 #define LPR 0x00 8692 #define PABR0 0x02 8693 #define PABR1 0x03 8694 #define WCRL 0x04 8695 #define WCRM 0x05 8696 #define WCRH 0x06 8697 #define DPCR 0x08 8698 #define DMER 0x09 8699 #define ISR0 0x10 8700 #define ISR1 0x11 8701 #define ISR2 0x12 8702 #define IER0 0x14 8703 #define IER1 0x15 8704 #define IER2 0x16 8705 #define ITCR 0x18 8706 #define INTVR 0x1a 8707 #define IMVR 0x1c 8708 #define TRB 0x20 8709 #define TRBL 0x20 8710 #define TRBH 0x21 8711 #define SR0 0x22 8712 #define SR1 0x23 8713 #define SR2 0x24 8714 #define SR3 0x25 8715 #define FST 0x26 8716 #define IE0 0x28 8717 #define IE1 0x29 8718 #define IE2 0x2a 8719 #define FIE 0x2b 8720 #define CMD 0x2c 8721 #define MD0 0x2e 8722 #define MD1 0x2f 8723 #define MD2 0x30 8724 #define CTL 0x31 8725 #define SA0 0x32 8726 #define SA1 0x33 8727 #define IDL 0x34 8728 #define TMC 0x35 8729 #define RXS 0x36 8730 #define TXS 0x37 8731 #define TRC0 0x38 8732 #define TRC1 0x39 8733 #define RRC 0x3a 8734 #define CST0 0x3c 8735 #define CST1 0x3d 8736 #define TCNT 0x60 8737 #define TCNTL 0x60 8738 #define TCNTH 0x61 8739 #define TCONR 0x62 8740 #define TCONRL 0x62 8741 #define TCONRH 0x63 8742 #define TMCS 0x64 8743 #define TEPR 0x65 8744 #define DARL 0x80 8745 #define DARH 0x81 8746 #define DARB 0x82 8747 #define BAR 0x80 8748 #define BARL 0x80 8749 #define BARH 0x81 8750 #define BARB 0x82 8751 #define SAR 0x84 8752 #define SARL 0x84 8753 #define SARH 0x85 8754 #define SARB 0x86 8755 #define CPB 0x86 8756 #define CDA 0x88 8757 #define CDAL 0x88 8758 #define CDAH 0x89 8759 #define EDA 0x8a 8760 #define EDAL 0x8a 8761 #define EDAH 0x8b 8762 #define BFL 0x8c 8763 #define BFLL 0x8c 8764 #define BFLH 0x8d 8765 #define BCR 0x8e 8766 #define BCRL 0x8e 8767 #define BCRH 0x8f 8768 #define DSR 0x90 8769 #define DMR 0x91 8770 #define FCT 0x93 8771 #define DIR 0x94 8772 #define DCMD 0x95 8773 #define TIMER0 0x00 8774 #define TIMER1 0x08 8775 #define TIMER2 0x10 8776 #define TIMER3 0x18 8777 #define RXDMA 0x00 8778 #define TXDMA 0x20 8779 #define NOOP 0x00 8780 #define TXRESET 0x01 8781 #define TXENABLE 0x02 8782 #define TXDISABLE 0x03 8783 #define TXCRCINIT 0x04 8784 #define TXCRCEXCL 0x05 8785 #define TXEOM 0x06 8786 #define TXABORT 0x07 8787 #define MPON 0x08 8788 #define TXBUFCLR 0x09 8789 #define RXRESET 0x11 8790 #define RXENABLE 0x12 8791 #define RXDISABLE 0x13 8792 #define RXCRCINIT 0x14 8793 #define RXREJECT 0x15 8794 #define SEARCHMP 0x16 8795 #define RXCRCEXCL 0x17 8796 #define RXCRCCALC 0x18 8797 #define CHRESET 0x21 8798 #define HUNT 0x31 8799 #define SWABORT 0x01 8800 #define FEICLEAR 0x02 8801 #define TXINTE BIT7 8802 #define RXINTE BIT6 8803 #define TXRDYE BIT1 8804 #define RXRDYE BIT0 8805 #define UDRN BIT7 8806 #define IDLE BIT6 8807 #define SYNCD BIT4 8808 #define FLGD BIT4 8809 #define CCTS BIT3 8810 #define CDCD BIT2 8811 #define BRKD BIT1 8812 #define ABTD BIT1 8813 #define GAPD BIT1 8814 #define BRKE BIT0 8815 #define IDLD BIT0 8816 #define EOM BIT7 8817 #define PMP BIT6 8818 #define SHRT BIT6 8819 #define PE BIT5 8820 #define ABT BIT5 8821 #define FRME BIT4 8822 #define RBIT BIT4 8823 #define OVRN BIT3 8824 #define CRCE BIT2 8825 #define WAKEUP_CHARS 256 8826 #if SYNCLINK_GENERIC_HDLC 8827 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 8828 #endif 8829 #ifdef SANITY_CHECK 8830 #else 8831 #endif 8832 /* LDV_COMMENT_END_PREP */ 8833 /* LDV_COMMENT_BEGIN_PREP */ 8834 #if SYNCLINK_GENERIC_HDLC 8835 #endif 8836 #if SYNCLINK_GENERIC_HDLC 8837 #endif 8838 #if SYNCLINK_GENERIC_HDLC 8839 #endif 8840 #ifdef CMSPAR 8841 #endif 8842 #if SYNCLINK_GENERIC_HDLC 8843 #endif 8844 #if SYNCLINK_GENERIC_HDLC 8845 #endif 8846 #if 0 8847 #endif 8848 #if SYNCLINK_GENERIC_HDLC 8849 #endif 8850 #if SYNCLINK_GENERIC_HDLC 8851 #endif 8852 #define TESTFRAMESIZE 20 8853 #if SYNCLINK_GENERIC_HDLC 8854 #endif 8855 #define CALC_REGADDR() \ 8856 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 8857 if (info->port_num > 1) \ 8858 RegAddr += 256; \ 8859 if ( info->port_num & 1) { \ 8860 if (Addr > 0x7f) \ 8861 RegAddr += 0x40; \ 8862 else if (Addr > 0x1f && Addr < 0x60) \ 8863 RegAddr += 0x20; \ 8864 } 8865 /* LDV_COMMENT_END_PREP */ 8866 /* content: static int write_room(struct tty_struct *tty)*/ 8867 /* LDV_COMMENT_BEGIN_PREP */ 8868 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 8869 #if defined(__i386__) 8870 # define BREAKPOINT() asm(" int $3"); 8871 #else 8872 # define BREAKPOINT() { } 8873 #endif 8874 #define MAX_DEVICES 12 8875 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 8876 #define SYNCLINK_GENERIC_HDLC 1 8877 #else 8878 #define SYNCLINK_GENERIC_HDLC 0 8879 #endif 8880 #define GET_USER(error,value,addr) error = get_user(value,addr) 8881 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 8882 #define PUT_USER(error,value,addr) error = put_user(value,addr) 8883 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 8884 #define SCABUFSIZE 1024 8885 #define SCA_MEM_SIZE 0x40000 8886 #define SCA_BASE_SIZE 512 8887 #define SCA_REG_SIZE 16 8888 #define SCA_MAX_PORTS 4 8889 #define SCAMAXDESC 128 8890 #define BUFFERLISTSIZE 4096 8891 #define BH_RECEIVE 1 8892 #define BH_TRANSMIT 2 8893 #define BH_STATUS 4 8894 #define IO_PIN_SHUTDOWN_LIMIT 100 8895 #if SYNCLINK_GENERIC_HDLC 8896 #endif 8897 #define MGSL_MAGIC 0x5401 8898 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 8899 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 8900 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 8901 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 8902 #define LPR 0x00 8903 #define PABR0 0x02 8904 #define PABR1 0x03 8905 #define WCRL 0x04 8906 #define WCRM 0x05 8907 #define WCRH 0x06 8908 #define DPCR 0x08 8909 #define DMER 0x09 8910 #define ISR0 0x10 8911 #define ISR1 0x11 8912 #define ISR2 0x12 8913 #define IER0 0x14 8914 #define IER1 0x15 8915 #define IER2 0x16 8916 #define ITCR 0x18 8917 #define INTVR 0x1a 8918 #define IMVR 0x1c 8919 #define TRB 0x20 8920 #define TRBL 0x20 8921 #define TRBH 0x21 8922 #define SR0 0x22 8923 #define SR1 0x23 8924 #define SR2 0x24 8925 #define SR3 0x25 8926 #define FST 0x26 8927 #define IE0 0x28 8928 #define IE1 0x29 8929 #define IE2 0x2a 8930 #define FIE 0x2b 8931 #define CMD 0x2c 8932 #define MD0 0x2e 8933 #define MD1 0x2f 8934 #define MD2 0x30 8935 #define CTL 0x31 8936 #define SA0 0x32 8937 #define SA1 0x33 8938 #define IDL 0x34 8939 #define TMC 0x35 8940 #define RXS 0x36 8941 #define TXS 0x37 8942 #define TRC0 0x38 8943 #define TRC1 0x39 8944 #define RRC 0x3a 8945 #define CST0 0x3c 8946 #define CST1 0x3d 8947 #define TCNT 0x60 8948 #define TCNTL 0x60 8949 #define TCNTH 0x61 8950 #define TCONR 0x62 8951 #define TCONRL 0x62 8952 #define TCONRH 0x63 8953 #define TMCS 0x64 8954 #define TEPR 0x65 8955 #define DARL 0x80 8956 #define DARH 0x81 8957 #define DARB 0x82 8958 #define BAR 0x80 8959 #define BARL 0x80 8960 #define BARH 0x81 8961 #define BARB 0x82 8962 #define SAR 0x84 8963 #define SARL 0x84 8964 #define SARH 0x85 8965 #define SARB 0x86 8966 #define CPB 0x86 8967 #define CDA 0x88 8968 #define CDAL 0x88 8969 #define CDAH 0x89 8970 #define EDA 0x8a 8971 #define EDAL 0x8a 8972 #define EDAH 0x8b 8973 #define BFL 0x8c 8974 #define BFLL 0x8c 8975 #define BFLH 0x8d 8976 #define BCR 0x8e 8977 #define BCRL 0x8e 8978 #define BCRH 0x8f 8979 #define DSR 0x90 8980 #define DMR 0x91 8981 #define FCT 0x93 8982 #define DIR 0x94 8983 #define DCMD 0x95 8984 #define TIMER0 0x00 8985 #define TIMER1 0x08 8986 #define TIMER2 0x10 8987 #define TIMER3 0x18 8988 #define RXDMA 0x00 8989 #define TXDMA 0x20 8990 #define NOOP 0x00 8991 #define TXRESET 0x01 8992 #define TXENABLE 0x02 8993 #define TXDISABLE 0x03 8994 #define TXCRCINIT 0x04 8995 #define TXCRCEXCL 0x05 8996 #define TXEOM 0x06 8997 #define TXABORT 0x07 8998 #define MPON 0x08 8999 #define TXBUFCLR 0x09 9000 #define RXRESET 0x11 9001 #define RXENABLE 0x12 9002 #define RXDISABLE 0x13 9003 #define RXCRCINIT 0x14 9004 #define RXREJECT 0x15 9005 #define SEARCHMP 0x16 9006 #define RXCRCEXCL 0x17 9007 #define RXCRCCALC 0x18 9008 #define CHRESET 0x21 9009 #define HUNT 0x31 9010 #define SWABORT 0x01 9011 #define FEICLEAR 0x02 9012 #define TXINTE BIT7 9013 #define RXINTE BIT6 9014 #define TXRDYE BIT1 9015 #define RXRDYE BIT0 9016 #define UDRN BIT7 9017 #define IDLE BIT6 9018 #define SYNCD BIT4 9019 #define FLGD BIT4 9020 #define CCTS BIT3 9021 #define CDCD BIT2 9022 #define BRKD BIT1 9023 #define ABTD BIT1 9024 #define GAPD BIT1 9025 #define BRKE BIT0 9026 #define IDLD BIT0 9027 #define EOM BIT7 9028 #define PMP BIT6 9029 #define SHRT BIT6 9030 #define PE BIT5 9031 #define ABT BIT5 9032 #define FRME BIT4 9033 #define RBIT BIT4 9034 #define OVRN BIT3 9035 #define CRCE BIT2 9036 #define WAKEUP_CHARS 256 9037 #if SYNCLINK_GENERIC_HDLC 9038 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9039 #endif 9040 #ifdef SANITY_CHECK 9041 #else 9042 #endif 9043 /* LDV_COMMENT_END_PREP */ 9044 /* LDV_COMMENT_BEGIN_PREP */ 9045 #if SYNCLINK_GENERIC_HDLC 9046 #endif 9047 #if SYNCLINK_GENERIC_HDLC 9048 #endif 9049 #if SYNCLINK_GENERIC_HDLC 9050 #endif 9051 #ifdef CMSPAR 9052 #endif 9053 #if SYNCLINK_GENERIC_HDLC 9054 #endif 9055 #if SYNCLINK_GENERIC_HDLC 9056 #endif 9057 #if 0 9058 #endif 9059 #if SYNCLINK_GENERIC_HDLC 9060 #endif 9061 #if SYNCLINK_GENERIC_HDLC 9062 #endif 9063 #define TESTFRAMESIZE 20 9064 #if SYNCLINK_GENERIC_HDLC 9065 #endif 9066 #define CALC_REGADDR() \ 9067 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9068 if (info->port_num > 1) \ 9069 RegAddr += 256; \ 9070 if ( info->port_num & 1) { \ 9071 if (Addr > 0x7f) \ 9072 RegAddr += 0x40; \ 9073 else if (Addr > 0x1f && Addr < 0x60) \ 9074 RegAddr += 0x20; \ 9075 } 9076 /* LDV_COMMENT_END_PREP */ 9077 /* content: static int chars_in_buffer(struct tty_struct *tty)*/ 9078 /* LDV_COMMENT_BEGIN_PREP */ 9079 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9080 #if defined(__i386__) 9081 # define BREAKPOINT() asm(" int $3"); 9082 #else 9083 # define BREAKPOINT() { } 9084 #endif 9085 #define MAX_DEVICES 12 9086 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9087 #define SYNCLINK_GENERIC_HDLC 1 9088 #else 9089 #define SYNCLINK_GENERIC_HDLC 0 9090 #endif 9091 #define GET_USER(error,value,addr) error = get_user(value,addr) 9092 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9093 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9094 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9095 #define SCABUFSIZE 1024 9096 #define SCA_MEM_SIZE 0x40000 9097 #define SCA_BASE_SIZE 512 9098 #define SCA_REG_SIZE 16 9099 #define SCA_MAX_PORTS 4 9100 #define SCAMAXDESC 128 9101 #define BUFFERLISTSIZE 4096 9102 #define BH_RECEIVE 1 9103 #define BH_TRANSMIT 2 9104 #define BH_STATUS 4 9105 #define IO_PIN_SHUTDOWN_LIMIT 100 9106 #if SYNCLINK_GENERIC_HDLC 9107 #endif 9108 #define MGSL_MAGIC 0x5401 9109 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9110 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9111 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9112 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9113 #define LPR 0x00 9114 #define PABR0 0x02 9115 #define PABR1 0x03 9116 #define WCRL 0x04 9117 #define WCRM 0x05 9118 #define WCRH 0x06 9119 #define DPCR 0x08 9120 #define DMER 0x09 9121 #define ISR0 0x10 9122 #define ISR1 0x11 9123 #define ISR2 0x12 9124 #define IER0 0x14 9125 #define IER1 0x15 9126 #define IER2 0x16 9127 #define ITCR 0x18 9128 #define INTVR 0x1a 9129 #define IMVR 0x1c 9130 #define TRB 0x20 9131 #define TRBL 0x20 9132 #define TRBH 0x21 9133 #define SR0 0x22 9134 #define SR1 0x23 9135 #define SR2 0x24 9136 #define SR3 0x25 9137 #define FST 0x26 9138 #define IE0 0x28 9139 #define IE1 0x29 9140 #define IE2 0x2a 9141 #define FIE 0x2b 9142 #define CMD 0x2c 9143 #define MD0 0x2e 9144 #define MD1 0x2f 9145 #define MD2 0x30 9146 #define CTL 0x31 9147 #define SA0 0x32 9148 #define SA1 0x33 9149 #define IDL 0x34 9150 #define TMC 0x35 9151 #define RXS 0x36 9152 #define TXS 0x37 9153 #define TRC0 0x38 9154 #define TRC1 0x39 9155 #define RRC 0x3a 9156 #define CST0 0x3c 9157 #define CST1 0x3d 9158 #define TCNT 0x60 9159 #define TCNTL 0x60 9160 #define TCNTH 0x61 9161 #define TCONR 0x62 9162 #define TCONRL 0x62 9163 #define TCONRH 0x63 9164 #define TMCS 0x64 9165 #define TEPR 0x65 9166 #define DARL 0x80 9167 #define DARH 0x81 9168 #define DARB 0x82 9169 #define BAR 0x80 9170 #define BARL 0x80 9171 #define BARH 0x81 9172 #define BARB 0x82 9173 #define SAR 0x84 9174 #define SARL 0x84 9175 #define SARH 0x85 9176 #define SARB 0x86 9177 #define CPB 0x86 9178 #define CDA 0x88 9179 #define CDAL 0x88 9180 #define CDAH 0x89 9181 #define EDA 0x8a 9182 #define EDAL 0x8a 9183 #define EDAH 0x8b 9184 #define BFL 0x8c 9185 #define BFLL 0x8c 9186 #define BFLH 0x8d 9187 #define BCR 0x8e 9188 #define BCRL 0x8e 9189 #define BCRH 0x8f 9190 #define DSR 0x90 9191 #define DMR 0x91 9192 #define FCT 0x93 9193 #define DIR 0x94 9194 #define DCMD 0x95 9195 #define TIMER0 0x00 9196 #define TIMER1 0x08 9197 #define TIMER2 0x10 9198 #define TIMER3 0x18 9199 #define RXDMA 0x00 9200 #define TXDMA 0x20 9201 #define NOOP 0x00 9202 #define TXRESET 0x01 9203 #define TXENABLE 0x02 9204 #define TXDISABLE 0x03 9205 #define TXCRCINIT 0x04 9206 #define TXCRCEXCL 0x05 9207 #define TXEOM 0x06 9208 #define TXABORT 0x07 9209 #define MPON 0x08 9210 #define TXBUFCLR 0x09 9211 #define RXRESET 0x11 9212 #define RXENABLE 0x12 9213 #define RXDISABLE 0x13 9214 #define RXCRCINIT 0x14 9215 #define RXREJECT 0x15 9216 #define SEARCHMP 0x16 9217 #define RXCRCEXCL 0x17 9218 #define RXCRCCALC 0x18 9219 #define CHRESET 0x21 9220 #define HUNT 0x31 9221 #define SWABORT 0x01 9222 #define FEICLEAR 0x02 9223 #define TXINTE BIT7 9224 #define RXINTE BIT6 9225 #define TXRDYE BIT1 9226 #define RXRDYE BIT0 9227 #define UDRN BIT7 9228 #define IDLE BIT6 9229 #define SYNCD BIT4 9230 #define FLGD BIT4 9231 #define CCTS BIT3 9232 #define CDCD BIT2 9233 #define BRKD BIT1 9234 #define ABTD BIT1 9235 #define GAPD BIT1 9236 #define BRKE BIT0 9237 #define IDLD BIT0 9238 #define EOM BIT7 9239 #define PMP BIT6 9240 #define SHRT BIT6 9241 #define PE BIT5 9242 #define ABT BIT5 9243 #define FRME BIT4 9244 #define RBIT BIT4 9245 #define OVRN BIT3 9246 #define CRCE BIT2 9247 #define WAKEUP_CHARS 256 9248 #if SYNCLINK_GENERIC_HDLC 9249 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9250 #endif 9251 #ifdef SANITY_CHECK 9252 #else 9253 #endif 9254 /* LDV_COMMENT_END_PREP */ 9255 /* LDV_COMMENT_BEGIN_PREP */ 9256 #if SYNCLINK_GENERIC_HDLC 9257 #endif 9258 #if SYNCLINK_GENERIC_HDLC 9259 #endif 9260 #if SYNCLINK_GENERIC_HDLC 9261 #endif 9262 #ifdef CMSPAR 9263 #endif 9264 #if SYNCLINK_GENERIC_HDLC 9265 #endif 9266 #if SYNCLINK_GENERIC_HDLC 9267 #endif 9268 #if 0 9269 #endif 9270 #if SYNCLINK_GENERIC_HDLC 9271 #endif 9272 #if SYNCLINK_GENERIC_HDLC 9273 #endif 9274 #define TESTFRAMESIZE 20 9275 #if SYNCLINK_GENERIC_HDLC 9276 #endif 9277 #define CALC_REGADDR() \ 9278 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9279 if (info->port_num > 1) \ 9280 RegAddr += 256; \ 9281 if ( info->port_num & 1) { \ 9282 if (Addr > 0x7f) \ 9283 RegAddr += 0x40; \ 9284 else if (Addr > 0x1f && Addr < 0x60) \ 9285 RegAddr += 0x20; \ 9286 } 9287 /* LDV_COMMENT_END_PREP */ 9288 /* content: static void flush_buffer(struct tty_struct *tty)*/ 9289 /* LDV_COMMENT_BEGIN_PREP */ 9290 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9291 #if defined(__i386__) 9292 # define BREAKPOINT() asm(" int $3"); 9293 #else 9294 # define BREAKPOINT() { } 9295 #endif 9296 #define MAX_DEVICES 12 9297 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9298 #define SYNCLINK_GENERIC_HDLC 1 9299 #else 9300 #define SYNCLINK_GENERIC_HDLC 0 9301 #endif 9302 #define GET_USER(error,value,addr) error = get_user(value,addr) 9303 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9304 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9305 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9306 #define SCABUFSIZE 1024 9307 #define SCA_MEM_SIZE 0x40000 9308 #define SCA_BASE_SIZE 512 9309 #define SCA_REG_SIZE 16 9310 #define SCA_MAX_PORTS 4 9311 #define SCAMAXDESC 128 9312 #define BUFFERLISTSIZE 4096 9313 #define BH_RECEIVE 1 9314 #define BH_TRANSMIT 2 9315 #define BH_STATUS 4 9316 #define IO_PIN_SHUTDOWN_LIMIT 100 9317 #if SYNCLINK_GENERIC_HDLC 9318 #endif 9319 #define MGSL_MAGIC 0x5401 9320 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9321 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9322 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9323 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9324 #define LPR 0x00 9325 #define PABR0 0x02 9326 #define PABR1 0x03 9327 #define WCRL 0x04 9328 #define WCRM 0x05 9329 #define WCRH 0x06 9330 #define DPCR 0x08 9331 #define DMER 0x09 9332 #define ISR0 0x10 9333 #define ISR1 0x11 9334 #define ISR2 0x12 9335 #define IER0 0x14 9336 #define IER1 0x15 9337 #define IER2 0x16 9338 #define ITCR 0x18 9339 #define INTVR 0x1a 9340 #define IMVR 0x1c 9341 #define TRB 0x20 9342 #define TRBL 0x20 9343 #define TRBH 0x21 9344 #define SR0 0x22 9345 #define SR1 0x23 9346 #define SR2 0x24 9347 #define SR3 0x25 9348 #define FST 0x26 9349 #define IE0 0x28 9350 #define IE1 0x29 9351 #define IE2 0x2a 9352 #define FIE 0x2b 9353 #define CMD 0x2c 9354 #define MD0 0x2e 9355 #define MD1 0x2f 9356 #define MD2 0x30 9357 #define CTL 0x31 9358 #define SA0 0x32 9359 #define SA1 0x33 9360 #define IDL 0x34 9361 #define TMC 0x35 9362 #define RXS 0x36 9363 #define TXS 0x37 9364 #define TRC0 0x38 9365 #define TRC1 0x39 9366 #define RRC 0x3a 9367 #define CST0 0x3c 9368 #define CST1 0x3d 9369 #define TCNT 0x60 9370 #define TCNTL 0x60 9371 #define TCNTH 0x61 9372 #define TCONR 0x62 9373 #define TCONRL 0x62 9374 #define TCONRH 0x63 9375 #define TMCS 0x64 9376 #define TEPR 0x65 9377 #define DARL 0x80 9378 #define DARH 0x81 9379 #define DARB 0x82 9380 #define BAR 0x80 9381 #define BARL 0x80 9382 #define BARH 0x81 9383 #define BARB 0x82 9384 #define SAR 0x84 9385 #define SARL 0x84 9386 #define SARH 0x85 9387 #define SARB 0x86 9388 #define CPB 0x86 9389 #define CDA 0x88 9390 #define CDAL 0x88 9391 #define CDAH 0x89 9392 #define EDA 0x8a 9393 #define EDAL 0x8a 9394 #define EDAH 0x8b 9395 #define BFL 0x8c 9396 #define BFLL 0x8c 9397 #define BFLH 0x8d 9398 #define BCR 0x8e 9399 #define BCRL 0x8e 9400 #define BCRH 0x8f 9401 #define DSR 0x90 9402 #define DMR 0x91 9403 #define FCT 0x93 9404 #define DIR 0x94 9405 #define DCMD 0x95 9406 #define TIMER0 0x00 9407 #define TIMER1 0x08 9408 #define TIMER2 0x10 9409 #define TIMER3 0x18 9410 #define RXDMA 0x00 9411 #define TXDMA 0x20 9412 #define NOOP 0x00 9413 #define TXRESET 0x01 9414 #define TXENABLE 0x02 9415 #define TXDISABLE 0x03 9416 #define TXCRCINIT 0x04 9417 #define TXCRCEXCL 0x05 9418 #define TXEOM 0x06 9419 #define TXABORT 0x07 9420 #define MPON 0x08 9421 #define TXBUFCLR 0x09 9422 #define RXRESET 0x11 9423 #define RXENABLE 0x12 9424 #define RXDISABLE 0x13 9425 #define RXCRCINIT 0x14 9426 #define RXREJECT 0x15 9427 #define SEARCHMP 0x16 9428 #define RXCRCEXCL 0x17 9429 #define RXCRCCALC 0x18 9430 #define CHRESET 0x21 9431 #define HUNT 0x31 9432 #define SWABORT 0x01 9433 #define FEICLEAR 0x02 9434 #define TXINTE BIT7 9435 #define RXINTE BIT6 9436 #define TXRDYE BIT1 9437 #define RXRDYE BIT0 9438 #define UDRN BIT7 9439 #define IDLE BIT6 9440 #define SYNCD BIT4 9441 #define FLGD BIT4 9442 #define CCTS BIT3 9443 #define CDCD BIT2 9444 #define BRKD BIT1 9445 #define ABTD BIT1 9446 #define GAPD BIT1 9447 #define BRKE BIT0 9448 #define IDLD BIT0 9449 #define EOM BIT7 9450 #define PMP BIT6 9451 #define SHRT BIT6 9452 #define PE BIT5 9453 #define ABT BIT5 9454 #define FRME BIT4 9455 #define RBIT BIT4 9456 #define OVRN BIT3 9457 #define CRCE BIT2 9458 #define WAKEUP_CHARS 256 9459 #if SYNCLINK_GENERIC_HDLC 9460 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9461 #endif 9462 #ifdef SANITY_CHECK 9463 #else 9464 #endif 9465 /* LDV_COMMENT_END_PREP */ 9466 /* LDV_COMMENT_BEGIN_PREP */ 9467 #if SYNCLINK_GENERIC_HDLC 9468 #endif 9469 #if SYNCLINK_GENERIC_HDLC 9470 #endif 9471 #if SYNCLINK_GENERIC_HDLC 9472 #endif 9473 #ifdef CMSPAR 9474 #endif 9475 #if SYNCLINK_GENERIC_HDLC 9476 #endif 9477 #if SYNCLINK_GENERIC_HDLC 9478 #endif 9479 #if 0 9480 #endif 9481 #if SYNCLINK_GENERIC_HDLC 9482 #endif 9483 #if SYNCLINK_GENERIC_HDLC 9484 #endif 9485 #define TESTFRAMESIZE 20 9486 #if SYNCLINK_GENERIC_HDLC 9487 #endif 9488 #define CALC_REGADDR() \ 9489 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9490 if (info->port_num > 1) \ 9491 RegAddr += 256; \ 9492 if ( info->port_num & 1) { \ 9493 if (Addr > 0x7f) \ 9494 RegAddr += 0x40; \ 9495 else if (Addr > 0x1f && Addr < 0x60) \ 9496 RegAddr += 0x20; \ 9497 } 9498 /* LDV_COMMENT_END_PREP */ 9499 /* content: static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg)*/ 9500 /* LDV_COMMENT_BEGIN_PREP */ 9501 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9502 #if defined(__i386__) 9503 # define BREAKPOINT() asm(" int $3"); 9504 #else 9505 # define BREAKPOINT() { } 9506 #endif 9507 #define MAX_DEVICES 12 9508 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9509 #define SYNCLINK_GENERIC_HDLC 1 9510 #else 9511 #define SYNCLINK_GENERIC_HDLC 0 9512 #endif 9513 #define GET_USER(error,value,addr) error = get_user(value,addr) 9514 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9515 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9516 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9517 #define SCABUFSIZE 1024 9518 #define SCA_MEM_SIZE 0x40000 9519 #define SCA_BASE_SIZE 512 9520 #define SCA_REG_SIZE 16 9521 #define SCA_MAX_PORTS 4 9522 #define SCAMAXDESC 128 9523 #define BUFFERLISTSIZE 4096 9524 #define BH_RECEIVE 1 9525 #define BH_TRANSMIT 2 9526 #define BH_STATUS 4 9527 #define IO_PIN_SHUTDOWN_LIMIT 100 9528 #if SYNCLINK_GENERIC_HDLC 9529 #endif 9530 #define MGSL_MAGIC 0x5401 9531 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9532 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9533 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9534 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9535 #define LPR 0x00 9536 #define PABR0 0x02 9537 #define PABR1 0x03 9538 #define WCRL 0x04 9539 #define WCRM 0x05 9540 #define WCRH 0x06 9541 #define DPCR 0x08 9542 #define DMER 0x09 9543 #define ISR0 0x10 9544 #define ISR1 0x11 9545 #define ISR2 0x12 9546 #define IER0 0x14 9547 #define IER1 0x15 9548 #define IER2 0x16 9549 #define ITCR 0x18 9550 #define INTVR 0x1a 9551 #define IMVR 0x1c 9552 #define TRB 0x20 9553 #define TRBL 0x20 9554 #define TRBH 0x21 9555 #define SR0 0x22 9556 #define SR1 0x23 9557 #define SR2 0x24 9558 #define SR3 0x25 9559 #define FST 0x26 9560 #define IE0 0x28 9561 #define IE1 0x29 9562 #define IE2 0x2a 9563 #define FIE 0x2b 9564 #define CMD 0x2c 9565 #define MD0 0x2e 9566 #define MD1 0x2f 9567 #define MD2 0x30 9568 #define CTL 0x31 9569 #define SA0 0x32 9570 #define SA1 0x33 9571 #define IDL 0x34 9572 #define TMC 0x35 9573 #define RXS 0x36 9574 #define TXS 0x37 9575 #define TRC0 0x38 9576 #define TRC1 0x39 9577 #define RRC 0x3a 9578 #define CST0 0x3c 9579 #define CST1 0x3d 9580 #define TCNT 0x60 9581 #define TCNTL 0x60 9582 #define TCNTH 0x61 9583 #define TCONR 0x62 9584 #define TCONRL 0x62 9585 #define TCONRH 0x63 9586 #define TMCS 0x64 9587 #define TEPR 0x65 9588 #define DARL 0x80 9589 #define DARH 0x81 9590 #define DARB 0x82 9591 #define BAR 0x80 9592 #define BARL 0x80 9593 #define BARH 0x81 9594 #define BARB 0x82 9595 #define SAR 0x84 9596 #define SARL 0x84 9597 #define SARH 0x85 9598 #define SARB 0x86 9599 #define CPB 0x86 9600 #define CDA 0x88 9601 #define CDAL 0x88 9602 #define CDAH 0x89 9603 #define EDA 0x8a 9604 #define EDAL 0x8a 9605 #define EDAH 0x8b 9606 #define BFL 0x8c 9607 #define BFLL 0x8c 9608 #define BFLH 0x8d 9609 #define BCR 0x8e 9610 #define BCRL 0x8e 9611 #define BCRH 0x8f 9612 #define DSR 0x90 9613 #define DMR 0x91 9614 #define FCT 0x93 9615 #define DIR 0x94 9616 #define DCMD 0x95 9617 #define TIMER0 0x00 9618 #define TIMER1 0x08 9619 #define TIMER2 0x10 9620 #define TIMER3 0x18 9621 #define RXDMA 0x00 9622 #define TXDMA 0x20 9623 #define NOOP 0x00 9624 #define TXRESET 0x01 9625 #define TXENABLE 0x02 9626 #define TXDISABLE 0x03 9627 #define TXCRCINIT 0x04 9628 #define TXCRCEXCL 0x05 9629 #define TXEOM 0x06 9630 #define TXABORT 0x07 9631 #define MPON 0x08 9632 #define TXBUFCLR 0x09 9633 #define RXRESET 0x11 9634 #define RXENABLE 0x12 9635 #define RXDISABLE 0x13 9636 #define RXCRCINIT 0x14 9637 #define RXREJECT 0x15 9638 #define SEARCHMP 0x16 9639 #define RXCRCEXCL 0x17 9640 #define RXCRCCALC 0x18 9641 #define CHRESET 0x21 9642 #define HUNT 0x31 9643 #define SWABORT 0x01 9644 #define FEICLEAR 0x02 9645 #define TXINTE BIT7 9646 #define RXINTE BIT6 9647 #define TXRDYE BIT1 9648 #define RXRDYE BIT0 9649 #define UDRN BIT7 9650 #define IDLE BIT6 9651 #define SYNCD BIT4 9652 #define FLGD BIT4 9653 #define CCTS BIT3 9654 #define CDCD BIT2 9655 #define BRKD BIT1 9656 #define ABTD BIT1 9657 #define GAPD BIT1 9658 #define BRKE BIT0 9659 #define IDLD BIT0 9660 #define EOM BIT7 9661 #define PMP BIT6 9662 #define SHRT BIT6 9663 #define PE BIT5 9664 #define ABT BIT5 9665 #define FRME BIT4 9666 #define RBIT BIT4 9667 #define OVRN BIT3 9668 #define CRCE BIT2 9669 #define WAKEUP_CHARS 256 9670 #if SYNCLINK_GENERIC_HDLC 9671 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9672 #endif 9673 #ifdef SANITY_CHECK 9674 #else 9675 #endif 9676 /* LDV_COMMENT_END_PREP */ 9677 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "ioctl" */ 9678 unsigned int var_ioctl_17_p1; 9679 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "ioctl" */ 9680 unsigned long var_ioctl_17_p2; 9681 /* LDV_COMMENT_BEGIN_PREP */ 9682 #if SYNCLINK_GENERIC_HDLC 9683 #endif 9684 #if SYNCLINK_GENERIC_HDLC 9685 #endif 9686 #if SYNCLINK_GENERIC_HDLC 9687 #endif 9688 #ifdef CMSPAR 9689 #endif 9690 #if SYNCLINK_GENERIC_HDLC 9691 #endif 9692 #if SYNCLINK_GENERIC_HDLC 9693 #endif 9694 #if 0 9695 #endif 9696 #if SYNCLINK_GENERIC_HDLC 9697 #endif 9698 #if SYNCLINK_GENERIC_HDLC 9699 #endif 9700 #define TESTFRAMESIZE 20 9701 #if SYNCLINK_GENERIC_HDLC 9702 #endif 9703 #define CALC_REGADDR() \ 9704 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9705 if (info->port_num > 1) \ 9706 RegAddr += 256; \ 9707 if ( info->port_num & 1) { \ 9708 if (Addr > 0x7f) \ 9709 RegAddr += 0x40; \ 9710 else if (Addr > 0x1f && Addr < 0x60) \ 9711 RegAddr += 0x20; \ 9712 } 9713 /* LDV_COMMENT_END_PREP */ 9714 /* content: static void throttle(struct tty_struct * tty)*/ 9715 /* LDV_COMMENT_BEGIN_PREP */ 9716 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9717 #if defined(__i386__) 9718 # define BREAKPOINT() asm(" int $3"); 9719 #else 9720 # define BREAKPOINT() { } 9721 #endif 9722 #define MAX_DEVICES 12 9723 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9724 #define SYNCLINK_GENERIC_HDLC 1 9725 #else 9726 #define SYNCLINK_GENERIC_HDLC 0 9727 #endif 9728 #define GET_USER(error,value,addr) error = get_user(value,addr) 9729 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9730 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9731 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9732 #define SCABUFSIZE 1024 9733 #define SCA_MEM_SIZE 0x40000 9734 #define SCA_BASE_SIZE 512 9735 #define SCA_REG_SIZE 16 9736 #define SCA_MAX_PORTS 4 9737 #define SCAMAXDESC 128 9738 #define BUFFERLISTSIZE 4096 9739 #define BH_RECEIVE 1 9740 #define BH_TRANSMIT 2 9741 #define BH_STATUS 4 9742 #define IO_PIN_SHUTDOWN_LIMIT 100 9743 #if SYNCLINK_GENERIC_HDLC 9744 #endif 9745 #define MGSL_MAGIC 0x5401 9746 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9747 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9748 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9749 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9750 #define LPR 0x00 9751 #define PABR0 0x02 9752 #define PABR1 0x03 9753 #define WCRL 0x04 9754 #define WCRM 0x05 9755 #define WCRH 0x06 9756 #define DPCR 0x08 9757 #define DMER 0x09 9758 #define ISR0 0x10 9759 #define ISR1 0x11 9760 #define ISR2 0x12 9761 #define IER0 0x14 9762 #define IER1 0x15 9763 #define IER2 0x16 9764 #define ITCR 0x18 9765 #define INTVR 0x1a 9766 #define IMVR 0x1c 9767 #define TRB 0x20 9768 #define TRBL 0x20 9769 #define TRBH 0x21 9770 #define SR0 0x22 9771 #define SR1 0x23 9772 #define SR2 0x24 9773 #define SR3 0x25 9774 #define FST 0x26 9775 #define IE0 0x28 9776 #define IE1 0x29 9777 #define IE2 0x2a 9778 #define FIE 0x2b 9779 #define CMD 0x2c 9780 #define MD0 0x2e 9781 #define MD1 0x2f 9782 #define MD2 0x30 9783 #define CTL 0x31 9784 #define SA0 0x32 9785 #define SA1 0x33 9786 #define IDL 0x34 9787 #define TMC 0x35 9788 #define RXS 0x36 9789 #define TXS 0x37 9790 #define TRC0 0x38 9791 #define TRC1 0x39 9792 #define RRC 0x3a 9793 #define CST0 0x3c 9794 #define CST1 0x3d 9795 #define TCNT 0x60 9796 #define TCNTL 0x60 9797 #define TCNTH 0x61 9798 #define TCONR 0x62 9799 #define TCONRL 0x62 9800 #define TCONRH 0x63 9801 #define TMCS 0x64 9802 #define TEPR 0x65 9803 #define DARL 0x80 9804 #define DARH 0x81 9805 #define DARB 0x82 9806 #define BAR 0x80 9807 #define BARL 0x80 9808 #define BARH 0x81 9809 #define BARB 0x82 9810 #define SAR 0x84 9811 #define SARL 0x84 9812 #define SARH 0x85 9813 #define SARB 0x86 9814 #define CPB 0x86 9815 #define CDA 0x88 9816 #define CDAL 0x88 9817 #define CDAH 0x89 9818 #define EDA 0x8a 9819 #define EDAL 0x8a 9820 #define EDAH 0x8b 9821 #define BFL 0x8c 9822 #define BFLL 0x8c 9823 #define BFLH 0x8d 9824 #define BCR 0x8e 9825 #define BCRL 0x8e 9826 #define BCRH 0x8f 9827 #define DSR 0x90 9828 #define DMR 0x91 9829 #define FCT 0x93 9830 #define DIR 0x94 9831 #define DCMD 0x95 9832 #define TIMER0 0x00 9833 #define TIMER1 0x08 9834 #define TIMER2 0x10 9835 #define TIMER3 0x18 9836 #define RXDMA 0x00 9837 #define TXDMA 0x20 9838 #define NOOP 0x00 9839 #define TXRESET 0x01 9840 #define TXENABLE 0x02 9841 #define TXDISABLE 0x03 9842 #define TXCRCINIT 0x04 9843 #define TXCRCEXCL 0x05 9844 #define TXEOM 0x06 9845 #define TXABORT 0x07 9846 #define MPON 0x08 9847 #define TXBUFCLR 0x09 9848 #define RXRESET 0x11 9849 #define RXENABLE 0x12 9850 #define RXDISABLE 0x13 9851 #define RXCRCINIT 0x14 9852 #define RXREJECT 0x15 9853 #define SEARCHMP 0x16 9854 #define RXCRCEXCL 0x17 9855 #define RXCRCCALC 0x18 9856 #define CHRESET 0x21 9857 #define HUNT 0x31 9858 #define SWABORT 0x01 9859 #define FEICLEAR 0x02 9860 #define TXINTE BIT7 9861 #define RXINTE BIT6 9862 #define TXRDYE BIT1 9863 #define RXRDYE BIT0 9864 #define UDRN BIT7 9865 #define IDLE BIT6 9866 #define SYNCD BIT4 9867 #define FLGD BIT4 9868 #define CCTS BIT3 9869 #define CDCD BIT2 9870 #define BRKD BIT1 9871 #define ABTD BIT1 9872 #define GAPD BIT1 9873 #define BRKE BIT0 9874 #define IDLD BIT0 9875 #define EOM BIT7 9876 #define PMP BIT6 9877 #define SHRT BIT6 9878 #define PE BIT5 9879 #define ABT BIT5 9880 #define FRME BIT4 9881 #define RBIT BIT4 9882 #define OVRN BIT3 9883 #define CRCE BIT2 9884 #define WAKEUP_CHARS 256 9885 #if SYNCLINK_GENERIC_HDLC 9886 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 9887 #endif 9888 #ifdef SANITY_CHECK 9889 #else 9890 #endif 9891 /* LDV_COMMENT_END_PREP */ 9892 /* LDV_COMMENT_BEGIN_PREP */ 9893 #if SYNCLINK_GENERIC_HDLC 9894 #endif 9895 #if SYNCLINK_GENERIC_HDLC 9896 #endif 9897 #if SYNCLINK_GENERIC_HDLC 9898 #endif 9899 #ifdef CMSPAR 9900 #endif 9901 #if SYNCLINK_GENERIC_HDLC 9902 #endif 9903 #if SYNCLINK_GENERIC_HDLC 9904 #endif 9905 #if 0 9906 #endif 9907 #if SYNCLINK_GENERIC_HDLC 9908 #endif 9909 #if SYNCLINK_GENERIC_HDLC 9910 #endif 9911 #define TESTFRAMESIZE 20 9912 #if SYNCLINK_GENERIC_HDLC 9913 #endif 9914 #define CALC_REGADDR() \ 9915 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 9916 if (info->port_num > 1) \ 9917 RegAddr += 256; \ 9918 if ( info->port_num & 1) { \ 9919 if (Addr > 0x7f) \ 9920 RegAddr += 0x40; \ 9921 else if (Addr > 0x1f && Addr < 0x60) \ 9922 RegAddr += 0x20; \ 9923 } 9924 /* LDV_COMMENT_END_PREP */ 9925 /* content: static void unthrottle(struct tty_struct * tty)*/ 9926 /* LDV_COMMENT_BEGIN_PREP */ 9927 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 9928 #if defined(__i386__) 9929 # define BREAKPOINT() asm(" int $3"); 9930 #else 9931 # define BREAKPOINT() { } 9932 #endif 9933 #define MAX_DEVICES 12 9934 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 9935 #define SYNCLINK_GENERIC_HDLC 1 9936 #else 9937 #define SYNCLINK_GENERIC_HDLC 0 9938 #endif 9939 #define GET_USER(error,value,addr) error = get_user(value,addr) 9940 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 9941 #define PUT_USER(error,value,addr) error = put_user(value,addr) 9942 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 9943 #define SCABUFSIZE 1024 9944 #define SCA_MEM_SIZE 0x40000 9945 #define SCA_BASE_SIZE 512 9946 #define SCA_REG_SIZE 16 9947 #define SCA_MAX_PORTS 4 9948 #define SCAMAXDESC 128 9949 #define BUFFERLISTSIZE 4096 9950 #define BH_RECEIVE 1 9951 #define BH_TRANSMIT 2 9952 #define BH_STATUS 4 9953 #define IO_PIN_SHUTDOWN_LIMIT 100 9954 #if SYNCLINK_GENERIC_HDLC 9955 #endif 9956 #define MGSL_MAGIC 0x5401 9957 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 9958 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 9959 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 9960 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 9961 #define LPR 0x00 9962 #define PABR0 0x02 9963 #define PABR1 0x03 9964 #define WCRL 0x04 9965 #define WCRM 0x05 9966 #define WCRH 0x06 9967 #define DPCR 0x08 9968 #define DMER 0x09 9969 #define ISR0 0x10 9970 #define ISR1 0x11 9971 #define ISR2 0x12 9972 #define IER0 0x14 9973 #define IER1 0x15 9974 #define IER2 0x16 9975 #define ITCR 0x18 9976 #define INTVR 0x1a 9977 #define IMVR 0x1c 9978 #define TRB 0x20 9979 #define TRBL 0x20 9980 #define TRBH 0x21 9981 #define SR0 0x22 9982 #define SR1 0x23 9983 #define SR2 0x24 9984 #define SR3 0x25 9985 #define FST 0x26 9986 #define IE0 0x28 9987 #define IE1 0x29 9988 #define IE2 0x2a 9989 #define FIE 0x2b 9990 #define CMD 0x2c 9991 #define MD0 0x2e 9992 #define MD1 0x2f 9993 #define MD2 0x30 9994 #define CTL 0x31 9995 #define SA0 0x32 9996 #define SA1 0x33 9997 #define IDL 0x34 9998 #define TMC 0x35 9999 #define RXS 0x36 10000 #define TXS 0x37 10001 #define TRC0 0x38 10002 #define TRC1 0x39 10003 #define RRC 0x3a 10004 #define CST0 0x3c 10005 #define CST1 0x3d 10006 #define TCNT 0x60 10007 #define TCNTL 0x60 10008 #define TCNTH 0x61 10009 #define TCONR 0x62 10010 #define TCONRL 0x62 10011 #define TCONRH 0x63 10012 #define TMCS 0x64 10013 #define TEPR 0x65 10014 #define DARL 0x80 10015 #define DARH 0x81 10016 #define DARB 0x82 10017 #define BAR 0x80 10018 #define BARL 0x80 10019 #define BARH 0x81 10020 #define BARB 0x82 10021 #define SAR 0x84 10022 #define SARL 0x84 10023 #define SARH 0x85 10024 #define SARB 0x86 10025 #define CPB 0x86 10026 #define CDA 0x88 10027 #define CDAL 0x88 10028 #define CDAH 0x89 10029 #define EDA 0x8a 10030 #define EDAL 0x8a 10031 #define EDAH 0x8b 10032 #define BFL 0x8c 10033 #define BFLL 0x8c 10034 #define BFLH 0x8d 10035 #define BCR 0x8e 10036 #define BCRL 0x8e 10037 #define BCRH 0x8f 10038 #define DSR 0x90 10039 #define DMR 0x91 10040 #define FCT 0x93 10041 #define DIR 0x94 10042 #define DCMD 0x95 10043 #define TIMER0 0x00 10044 #define TIMER1 0x08 10045 #define TIMER2 0x10 10046 #define TIMER3 0x18 10047 #define RXDMA 0x00 10048 #define TXDMA 0x20 10049 #define NOOP 0x00 10050 #define TXRESET 0x01 10051 #define TXENABLE 0x02 10052 #define TXDISABLE 0x03 10053 #define TXCRCINIT 0x04 10054 #define TXCRCEXCL 0x05 10055 #define TXEOM 0x06 10056 #define TXABORT 0x07 10057 #define MPON 0x08 10058 #define TXBUFCLR 0x09 10059 #define RXRESET 0x11 10060 #define RXENABLE 0x12 10061 #define RXDISABLE 0x13 10062 #define RXCRCINIT 0x14 10063 #define RXREJECT 0x15 10064 #define SEARCHMP 0x16 10065 #define RXCRCEXCL 0x17 10066 #define RXCRCCALC 0x18 10067 #define CHRESET 0x21 10068 #define HUNT 0x31 10069 #define SWABORT 0x01 10070 #define FEICLEAR 0x02 10071 #define TXINTE BIT7 10072 #define RXINTE BIT6 10073 #define TXRDYE BIT1 10074 #define RXRDYE BIT0 10075 #define UDRN BIT7 10076 #define IDLE BIT6 10077 #define SYNCD BIT4 10078 #define FLGD BIT4 10079 #define CCTS BIT3 10080 #define CDCD BIT2 10081 #define BRKD BIT1 10082 #define ABTD BIT1 10083 #define GAPD BIT1 10084 #define BRKE BIT0 10085 #define IDLD BIT0 10086 #define EOM BIT7 10087 #define PMP BIT6 10088 #define SHRT BIT6 10089 #define PE BIT5 10090 #define ABT BIT5 10091 #define FRME BIT4 10092 #define RBIT BIT4 10093 #define OVRN BIT3 10094 #define CRCE BIT2 10095 #define WAKEUP_CHARS 256 10096 #if SYNCLINK_GENERIC_HDLC 10097 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10098 #endif 10099 #ifdef SANITY_CHECK 10100 #else 10101 #endif 10102 /* LDV_COMMENT_END_PREP */ 10103 /* LDV_COMMENT_BEGIN_PREP */ 10104 #if SYNCLINK_GENERIC_HDLC 10105 #endif 10106 #if SYNCLINK_GENERIC_HDLC 10107 #endif 10108 #if SYNCLINK_GENERIC_HDLC 10109 #endif 10110 #ifdef CMSPAR 10111 #endif 10112 #if SYNCLINK_GENERIC_HDLC 10113 #endif 10114 #if SYNCLINK_GENERIC_HDLC 10115 #endif 10116 #if 0 10117 #endif 10118 #if SYNCLINK_GENERIC_HDLC 10119 #endif 10120 #if SYNCLINK_GENERIC_HDLC 10121 #endif 10122 #define TESTFRAMESIZE 20 10123 #if SYNCLINK_GENERIC_HDLC 10124 #endif 10125 #define CALC_REGADDR() \ 10126 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10127 if (info->port_num > 1) \ 10128 RegAddr += 256; \ 10129 if ( info->port_num & 1) { \ 10130 if (Addr > 0x7f) \ 10131 RegAddr += 0x40; \ 10132 else if (Addr > 0x1f && Addr < 0x60) \ 10133 RegAddr += 0x20; \ 10134 } 10135 /* LDV_COMMENT_END_PREP */ 10136 /* content: static void send_xchar(struct tty_struct *tty, char ch)*/ 10137 /* LDV_COMMENT_BEGIN_PREP */ 10138 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10139 #if defined(__i386__) 10140 # define BREAKPOINT() asm(" int $3"); 10141 #else 10142 # define BREAKPOINT() { } 10143 #endif 10144 #define MAX_DEVICES 12 10145 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10146 #define SYNCLINK_GENERIC_HDLC 1 10147 #else 10148 #define SYNCLINK_GENERIC_HDLC 0 10149 #endif 10150 #define GET_USER(error,value,addr) error = get_user(value,addr) 10151 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10152 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10153 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10154 #define SCABUFSIZE 1024 10155 #define SCA_MEM_SIZE 0x40000 10156 #define SCA_BASE_SIZE 512 10157 #define SCA_REG_SIZE 16 10158 #define SCA_MAX_PORTS 4 10159 #define SCAMAXDESC 128 10160 #define BUFFERLISTSIZE 4096 10161 #define BH_RECEIVE 1 10162 #define BH_TRANSMIT 2 10163 #define BH_STATUS 4 10164 #define IO_PIN_SHUTDOWN_LIMIT 100 10165 #if SYNCLINK_GENERIC_HDLC 10166 #endif 10167 #define MGSL_MAGIC 0x5401 10168 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 10169 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 10170 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 10171 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 10172 #define LPR 0x00 10173 #define PABR0 0x02 10174 #define PABR1 0x03 10175 #define WCRL 0x04 10176 #define WCRM 0x05 10177 #define WCRH 0x06 10178 #define DPCR 0x08 10179 #define DMER 0x09 10180 #define ISR0 0x10 10181 #define ISR1 0x11 10182 #define ISR2 0x12 10183 #define IER0 0x14 10184 #define IER1 0x15 10185 #define IER2 0x16 10186 #define ITCR 0x18 10187 #define INTVR 0x1a 10188 #define IMVR 0x1c 10189 #define TRB 0x20 10190 #define TRBL 0x20 10191 #define TRBH 0x21 10192 #define SR0 0x22 10193 #define SR1 0x23 10194 #define SR2 0x24 10195 #define SR3 0x25 10196 #define FST 0x26 10197 #define IE0 0x28 10198 #define IE1 0x29 10199 #define IE2 0x2a 10200 #define FIE 0x2b 10201 #define CMD 0x2c 10202 #define MD0 0x2e 10203 #define MD1 0x2f 10204 #define MD2 0x30 10205 #define CTL 0x31 10206 #define SA0 0x32 10207 #define SA1 0x33 10208 #define IDL 0x34 10209 #define TMC 0x35 10210 #define RXS 0x36 10211 #define TXS 0x37 10212 #define TRC0 0x38 10213 #define TRC1 0x39 10214 #define RRC 0x3a 10215 #define CST0 0x3c 10216 #define CST1 0x3d 10217 #define TCNT 0x60 10218 #define TCNTL 0x60 10219 #define TCNTH 0x61 10220 #define TCONR 0x62 10221 #define TCONRL 0x62 10222 #define TCONRH 0x63 10223 #define TMCS 0x64 10224 #define TEPR 0x65 10225 #define DARL 0x80 10226 #define DARH 0x81 10227 #define DARB 0x82 10228 #define BAR 0x80 10229 #define BARL 0x80 10230 #define BARH 0x81 10231 #define BARB 0x82 10232 #define SAR 0x84 10233 #define SARL 0x84 10234 #define SARH 0x85 10235 #define SARB 0x86 10236 #define CPB 0x86 10237 #define CDA 0x88 10238 #define CDAL 0x88 10239 #define CDAH 0x89 10240 #define EDA 0x8a 10241 #define EDAL 0x8a 10242 #define EDAH 0x8b 10243 #define BFL 0x8c 10244 #define BFLL 0x8c 10245 #define BFLH 0x8d 10246 #define BCR 0x8e 10247 #define BCRL 0x8e 10248 #define BCRH 0x8f 10249 #define DSR 0x90 10250 #define DMR 0x91 10251 #define FCT 0x93 10252 #define DIR 0x94 10253 #define DCMD 0x95 10254 #define TIMER0 0x00 10255 #define TIMER1 0x08 10256 #define TIMER2 0x10 10257 #define TIMER3 0x18 10258 #define RXDMA 0x00 10259 #define TXDMA 0x20 10260 #define NOOP 0x00 10261 #define TXRESET 0x01 10262 #define TXENABLE 0x02 10263 #define TXDISABLE 0x03 10264 #define TXCRCINIT 0x04 10265 #define TXCRCEXCL 0x05 10266 #define TXEOM 0x06 10267 #define TXABORT 0x07 10268 #define MPON 0x08 10269 #define TXBUFCLR 0x09 10270 #define RXRESET 0x11 10271 #define RXENABLE 0x12 10272 #define RXDISABLE 0x13 10273 #define RXCRCINIT 0x14 10274 #define RXREJECT 0x15 10275 #define SEARCHMP 0x16 10276 #define RXCRCEXCL 0x17 10277 #define RXCRCCALC 0x18 10278 #define CHRESET 0x21 10279 #define HUNT 0x31 10280 #define SWABORT 0x01 10281 #define FEICLEAR 0x02 10282 #define TXINTE BIT7 10283 #define RXINTE BIT6 10284 #define TXRDYE BIT1 10285 #define RXRDYE BIT0 10286 #define UDRN BIT7 10287 #define IDLE BIT6 10288 #define SYNCD BIT4 10289 #define FLGD BIT4 10290 #define CCTS BIT3 10291 #define CDCD BIT2 10292 #define BRKD BIT1 10293 #define ABTD BIT1 10294 #define GAPD BIT1 10295 #define BRKE BIT0 10296 #define IDLD BIT0 10297 #define EOM BIT7 10298 #define PMP BIT6 10299 #define SHRT BIT6 10300 #define PE BIT5 10301 #define ABT BIT5 10302 #define FRME BIT4 10303 #define RBIT BIT4 10304 #define OVRN BIT3 10305 #define CRCE BIT2 10306 #define WAKEUP_CHARS 256 10307 #if SYNCLINK_GENERIC_HDLC 10308 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10309 #endif 10310 #ifdef SANITY_CHECK 10311 #else 10312 #endif 10313 /* LDV_COMMENT_END_PREP */ 10314 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "send_xchar" */ 10315 char var_send_xchar_10_p1; 10316 /* LDV_COMMENT_BEGIN_PREP */ 10317 #if SYNCLINK_GENERIC_HDLC 10318 #endif 10319 #if SYNCLINK_GENERIC_HDLC 10320 #endif 10321 #if SYNCLINK_GENERIC_HDLC 10322 #endif 10323 #ifdef CMSPAR 10324 #endif 10325 #if SYNCLINK_GENERIC_HDLC 10326 #endif 10327 #if SYNCLINK_GENERIC_HDLC 10328 #endif 10329 #if 0 10330 #endif 10331 #if SYNCLINK_GENERIC_HDLC 10332 #endif 10333 #if SYNCLINK_GENERIC_HDLC 10334 #endif 10335 #define TESTFRAMESIZE 20 10336 #if SYNCLINK_GENERIC_HDLC 10337 #endif 10338 #define CALC_REGADDR() \ 10339 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10340 if (info->port_num > 1) \ 10341 RegAddr += 256; \ 10342 if ( info->port_num & 1) { \ 10343 if (Addr > 0x7f) \ 10344 RegAddr += 0x40; \ 10345 else if (Addr > 0x1f && Addr < 0x60) \ 10346 RegAddr += 0x20; \ 10347 } 10348 /* LDV_COMMENT_END_PREP */ 10349 /* content: static int set_break(struct tty_struct *tty, int break_state)*/ 10350 /* LDV_COMMENT_BEGIN_PREP */ 10351 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10352 #if defined(__i386__) 10353 # define BREAKPOINT() asm(" int $3"); 10354 #else 10355 # define BREAKPOINT() { } 10356 #endif 10357 #define MAX_DEVICES 12 10358 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10359 #define SYNCLINK_GENERIC_HDLC 1 10360 #else 10361 #define SYNCLINK_GENERIC_HDLC 0 10362 #endif 10363 #define GET_USER(error,value,addr) error = get_user(value,addr) 10364 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10365 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10366 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10367 #define SCABUFSIZE 1024 10368 #define SCA_MEM_SIZE 0x40000 10369 #define SCA_BASE_SIZE 512 10370 #define SCA_REG_SIZE 16 10371 #define SCA_MAX_PORTS 4 10372 #define SCAMAXDESC 128 10373 #define BUFFERLISTSIZE 4096 10374 #define BH_RECEIVE 1 10375 #define BH_TRANSMIT 2 10376 #define BH_STATUS 4 10377 #define IO_PIN_SHUTDOWN_LIMIT 100 10378 #if SYNCLINK_GENERIC_HDLC 10379 #endif 10380 #define MGSL_MAGIC 0x5401 10381 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 10382 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 10383 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 10384 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 10385 #define LPR 0x00 10386 #define PABR0 0x02 10387 #define PABR1 0x03 10388 #define WCRL 0x04 10389 #define WCRM 0x05 10390 #define WCRH 0x06 10391 #define DPCR 0x08 10392 #define DMER 0x09 10393 #define ISR0 0x10 10394 #define ISR1 0x11 10395 #define ISR2 0x12 10396 #define IER0 0x14 10397 #define IER1 0x15 10398 #define IER2 0x16 10399 #define ITCR 0x18 10400 #define INTVR 0x1a 10401 #define IMVR 0x1c 10402 #define TRB 0x20 10403 #define TRBL 0x20 10404 #define TRBH 0x21 10405 #define SR0 0x22 10406 #define SR1 0x23 10407 #define SR2 0x24 10408 #define SR3 0x25 10409 #define FST 0x26 10410 #define IE0 0x28 10411 #define IE1 0x29 10412 #define IE2 0x2a 10413 #define FIE 0x2b 10414 #define CMD 0x2c 10415 #define MD0 0x2e 10416 #define MD1 0x2f 10417 #define MD2 0x30 10418 #define CTL 0x31 10419 #define SA0 0x32 10420 #define SA1 0x33 10421 #define IDL 0x34 10422 #define TMC 0x35 10423 #define RXS 0x36 10424 #define TXS 0x37 10425 #define TRC0 0x38 10426 #define TRC1 0x39 10427 #define RRC 0x3a 10428 #define CST0 0x3c 10429 #define CST1 0x3d 10430 #define TCNT 0x60 10431 #define TCNTL 0x60 10432 #define TCNTH 0x61 10433 #define TCONR 0x62 10434 #define TCONRL 0x62 10435 #define TCONRH 0x63 10436 #define TMCS 0x64 10437 #define TEPR 0x65 10438 #define DARL 0x80 10439 #define DARH 0x81 10440 #define DARB 0x82 10441 #define BAR 0x80 10442 #define BARL 0x80 10443 #define BARH 0x81 10444 #define BARB 0x82 10445 #define SAR 0x84 10446 #define SARL 0x84 10447 #define SARH 0x85 10448 #define SARB 0x86 10449 #define CPB 0x86 10450 #define CDA 0x88 10451 #define CDAL 0x88 10452 #define CDAH 0x89 10453 #define EDA 0x8a 10454 #define EDAL 0x8a 10455 #define EDAH 0x8b 10456 #define BFL 0x8c 10457 #define BFLL 0x8c 10458 #define BFLH 0x8d 10459 #define BCR 0x8e 10460 #define BCRL 0x8e 10461 #define BCRH 0x8f 10462 #define DSR 0x90 10463 #define DMR 0x91 10464 #define FCT 0x93 10465 #define DIR 0x94 10466 #define DCMD 0x95 10467 #define TIMER0 0x00 10468 #define TIMER1 0x08 10469 #define TIMER2 0x10 10470 #define TIMER3 0x18 10471 #define RXDMA 0x00 10472 #define TXDMA 0x20 10473 #define NOOP 0x00 10474 #define TXRESET 0x01 10475 #define TXENABLE 0x02 10476 #define TXDISABLE 0x03 10477 #define TXCRCINIT 0x04 10478 #define TXCRCEXCL 0x05 10479 #define TXEOM 0x06 10480 #define TXABORT 0x07 10481 #define MPON 0x08 10482 #define TXBUFCLR 0x09 10483 #define RXRESET 0x11 10484 #define RXENABLE 0x12 10485 #define RXDISABLE 0x13 10486 #define RXCRCINIT 0x14 10487 #define RXREJECT 0x15 10488 #define SEARCHMP 0x16 10489 #define RXCRCEXCL 0x17 10490 #define RXCRCCALC 0x18 10491 #define CHRESET 0x21 10492 #define HUNT 0x31 10493 #define SWABORT 0x01 10494 #define FEICLEAR 0x02 10495 #define TXINTE BIT7 10496 #define RXINTE BIT6 10497 #define TXRDYE BIT1 10498 #define RXRDYE BIT0 10499 #define UDRN BIT7 10500 #define IDLE BIT6 10501 #define SYNCD BIT4 10502 #define FLGD BIT4 10503 #define CCTS BIT3 10504 #define CDCD BIT2 10505 #define BRKD BIT1 10506 #define ABTD BIT1 10507 #define GAPD BIT1 10508 #define BRKE BIT0 10509 #define IDLD BIT0 10510 #define EOM BIT7 10511 #define PMP BIT6 10512 #define SHRT BIT6 10513 #define PE BIT5 10514 #define ABT BIT5 10515 #define FRME BIT4 10516 #define RBIT BIT4 10517 #define OVRN BIT3 10518 #define CRCE BIT2 10519 #define WAKEUP_CHARS 256 10520 #if SYNCLINK_GENERIC_HDLC 10521 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10522 #endif 10523 #ifdef SANITY_CHECK 10524 #else 10525 #endif 10526 /* LDV_COMMENT_END_PREP */ 10527 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "set_break" */ 10528 int var_set_break_25_p1; 10529 /* LDV_COMMENT_BEGIN_PREP */ 10530 #if SYNCLINK_GENERIC_HDLC 10531 #endif 10532 #if SYNCLINK_GENERIC_HDLC 10533 #endif 10534 #if SYNCLINK_GENERIC_HDLC 10535 #endif 10536 #ifdef CMSPAR 10537 #endif 10538 #if SYNCLINK_GENERIC_HDLC 10539 #endif 10540 #if SYNCLINK_GENERIC_HDLC 10541 #endif 10542 #if 0 10543 #endif 10544 #if SYNCLINK_GENERIC_HDLC 10545 #endif 10546 #if SYNCLINK_GENERIC_HDLC 10547 #endif 10548 #define TESTFRAMESIZE 20 10549 #if SYNCLINK_GENERIC_HDLC 10550 #endif 10551 #define CALC_REGADDR() \ 10552 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10553 if (info->port_num > 1) \ 10554 RegAddr += 256; \ 10555 if ( info->port_num & 1) { \ 10556 if (Addr > 0x7f) \ 10557 RegAddr += 0x40; \ 10558 else if (Addr > 0x1f && Addr < 0x60) \ 10559 RegAddr += 0x20; \ 10560 } 10561 /* LDV_COMMENT_END_PREP */ 10562 /* content: static void wait_until_sent(struct tty_struct *tty, int timeout)*/ 10563 /* LDV_COMMENT_BEGIN_PREP */ 10564 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10565 #if defined(__i386__) 10566 # define BREAKPOINT() asm(" int $3"); 10567 #else 10568 # define BREAKPOINT() { } 10569 #endif 10570 #define MAX_DEVICES 12 10571 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10572 #define SYNCLINK_GENERIC_HDLC 1 10573 #else 10574 #define SYNCLINK_GENERIC_HDLC 0 10575 #endif 10576 #define GET_USER(error,value,addr) error = get_user(value,addr) 10577 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10578 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10579 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10580 #define SCABUFSIZE 1024 10581 #define SCA_MEM_SIZE 0x40000 10582 #define SCA_BASE_SIZE 512 10583 #define SCA_REG_SIZE 16 10584 #define SCA_MAX_PORTS 4 10585 #define SCAMAXDESC 128 10586 #define BUFFERLISTSIZE 4096 10587 #define BH_RECEIVE 1 10588 #define BH_TRANSMIT 2 10589 #define BH_STATUS 4 10590 #define IO_PIN_SHUTDOWN_LIMIT 100 10591 #if SYNCLINK_GENERIC_HDLC 10592 #endif 10593 #define MGSL_MAGIC 0x5401 10594 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 10595 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 10596 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 10597 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 10598 #define LPR 0x00 10599 #define PABR0 0x02 10600 #define PABR1 0x03 10601 #define WCRL 0x04 10602 #define WCRM 0x05 10603 #define WCRH 0x06 10604 #define DPCR 0x08 10605 #define DMER 0x09 10606 #define ISR0 0x10 10607 #define ISR1 0x11 10608 #define ISR2 0x12 10609 #define IER0 0x14 10610 #define IER1 0x15 10611 #define IER2 0x16 10612 #define ITCR 0x18 10613 #define INTVR 0x1a 10614 #define IMVR 0x1c 10615 #define TRB 0x20 10616 #define TRBL 0x20 10617 #define TRBH 0x21 10618 #define SR0 0x22 10619 #define SR1 0x23 10620 #define SR2 0x24 10621 #define SR3 0x25 10622 #define FST 0x26 10623 #define IE0 0x28 10624 #define IE1 0x29 10625 #define IE2 0x2a 10626 #define FIE 0x2b 10627 #define CMD 0x2c 10628 #define MD0 0x2e 10629 #define MD1 0x2f 10630 #define MD2 0x30 10631 #define CTL 0x31 10632 #define SA0 0x32 10633 #define SA1 0x33 10634 #define IDL 0x34 10635 #define TMC 0x35 10636 #define RXS 0x36 10637 #define TXS 0x37 10638 #define TRC0 0x38 10639 #define TRC1 0x39 10640 #define RRC 0x3a 10641 #define CST0 0x3c 10642 #define CST1 0x3d 10643 #define TCNT 0x60 10644 #define TCNTL 0x60 10645 #define TCNTH 0x61 10646 #define TCONR 0x62 10647 #define TCONRL 0x62 10648 #define TCONRH 0x63 10649 #define TMCS 0x64 10650 #define TEPR 0x65 10651 #define DARL 0x80 10652 #define DARH 0x81 10653 #define DARB 0x82 10654 #define BAR 0x80 10655 #define BARL 0x80 10656 #define BARH 0x81 10657 #define BARB 0x82 10658 #define SAR 0x84 10659 #define SARL 0x84 10660 #define SARH 0x85 10661 #define SARB 0x86 10662 #define CPB 0x86 10663 #define CDA 0x88 10664 #define CDAL 0x88 10665 #define CDAH 0x89 10666 #define EDA 0x8a 10667 #define EDAL 0x8a 10668 #define EDAH 0x8b 10669 #define BFL 0x8c 10670 #define BFLL 0x8c 10671 #define BFLH 0x8d 10672 #define BCR 0x8e 10673 #define BCRL 0x8e 10674 #define BCRH 0x8f 10675 #define DSR 0x90 10676 #define DMR 0x91 10677 #define FCT 0x93 10678 #define DIR 0x94 10679 #define DCMD 0x95 10680 #define TIMER0 0x00 10681 #define TIMER1 0x08 10682 #define TIMER2 0x10 10683 #define TIMER3 0x18 10684 #define RXDMA 0x00 10685 #define TXDMA 0x20 10686 #define NOOP 0x00 10687 #define TXRESET 0x01 10688 #define TXENABLE 0x02 10689 #define TXDISABLE 0x03 10690 #define TXCRCINIT 0x04 10691 #define TXCRCEXCL 0x05 10692 #define TXEOM 0x06 10693 #define TXABORT 0x07 10694 #define MPON 0x08 10695 #define TXBUFCLR 0x09 10696 #define RXRESET 0x11 10697 #define RXENABLE 0x12 10698 #define RXDISABLE 0x13 10699 #define RXCRCINIT 0x14 10700 #define RXREJECT 0x15 10701 #define SEARCHMP 0x16 10702 #define RXCRCEXCL 0x17 10703 #define RXCRCCALC 0x18 10704 #define CHRESET 0x21 10705 #define HUNT 0x31 10706 #define SWABORT 0x01 10707 #define FEICLEAR 0x02 10708 #define TXINTE BIT7 10709 #define RXINTE BIT6 10710 #define TXRDYE BIT1 10711 #define RXRDYE BIT0 10712 #define UDRN BIT7 10713 #define IDLE BIT6 10714 #define SYNCD BIT4 10715 #define FLGD BIT4 10716 #define CCTS BIT3 10717 #define CDCD BIT2 10718 #define BRKD BIT1 10719 #define ABTD BIT1 10720 #define GAPD BIT1 10721 #define BRKE BIT0 10722 #define IDLD BIT0 10723 #define EOM BIT7 10724 #define PMP BIT6 10725 #define SHRT BIT6 10726 #define PE BIT5 10727 #define ABT BIT5 10728 #define FRME BIT4 10729 #define RBIT BIT4 10730 #define OVRN BIT3 10731 #define CRCE BIT2 10732 #define WAKEUP_CHARS 256 10733 #if SYNCLINK_GENERIC_HDLC 10734 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10735 #endif 10736 #ifdef SANITY_CHECK 10737 #else 10738 #endif 10739 /* LDV_COMMENT_END_PREP */ 10740 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "wait_until_sent" */ 10741 int var_wait_until_sent_11_p1; 10742 /* LDV_COMMENT_BEGIN_PREP */ 10743 #if SYNCLINK_GENERIC_HDLC 10744 #endif 10745 #if SYNCLINK_GENERIC_HDLC 10746 #endif 10747 #if SYNCLINK_GENERIC_HDLC 10748 #endif 10749 #ifdef CMSPAR 10750 #endif 10751 #if SYNCLINK_GENERIC_HDLC 10752 #endif 10753 #if SYNCLINK_GENERIC_HDLC 10754 #endif 10755 #if 0 10756 #endif 10757 #if SYNCLINK_GENERIC_HDLC 10758 #endif 10759 #if SYNCLINK_GENERIC_HDLC 10760 #endif 10761 #define TESTFRAMESIZE 20 10762 #if SYNCLINK_GENERIC_HDLC 10763 #endif 10764 #define CALC_REGADDR() \ 10765 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10766 if (info->port_num > 1) \ 10767 RegAddr += 256; \ 10768 if ( info->port_num & 1) { \ 10769 if (Addr > 0x7f) \ 10770 RegAddr += 0x40; \ 10771 else if (Addr > 0x1f && Addr < 0x60) \ 10772 RegAddr += 0x20; \ 10773 } 10774 /* LDV_COMMENT_END_PREP */ 10775 /* content: static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)*/ 10776 /* LDV_COMMENT_BEGIN_PREP */ 10777 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10778 #if defined(__i386__) 10779 # define BREAKPOINT() asm(" int $3"); 10780 #else 10781 # define BREAKPOINT() { } 10782 #endif 10783 #define MAX_DEVICES 12 10784 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10785 #define SYNCLINK_GENERIC_HDLC 1 10786 #else 10787 #define SYNCLINK_GENERIC_HDLC 0 10788 #endif 10789 #define GET_USER(error,value,addr) error = get_user(value,addr) 10790 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 10791 #define PUT_USER(error,value,addr) error = put_user(value,addr) 10792 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 10793 #define SCABUFSIZE 1024 10794 #define SCA_MEM_SIZE 0x40000 10795 #define SCA_BASE_SIZE 512 10796 #define SCA_REG_SIZE 16 10797 #define SCA_MAX_PORTS 4 10798 #define SCAMAXDESC 128 10799 #define BUFFERLISTSIZE 4096 10800 #define BH_RECEIVE 1 10801 #define BH_TRANSMIT 2 10802 #define BH_STATUS 4 10803 #define IO_PIN_SHUTDOWN_LIMIT 100 10804 #if SYNCLINK_GENERIC_HDLC 10805 #endif 10806 #define MGSL_MAGIC 0x5401 10807 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 10808 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 10809 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 10810 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 10811 #define LPR 0x00 10812 #define PABR0 0x02 10813 #define PABR1 0x03 10814 #define WCRL 0x04 10815 #define WCRM 0x05 10816 #define WCRH 0x06 10817 #define DPCR 0x08 10818 #define DMER 0x09 10819 #define ISR0 0x10 10820 #define ISR1 0x11 10821 #define ISR2 0x12 10822 #define IER0 0x14 10823 #define IER1 0x15 10824 #define IER2 0x16 10825 #define ITCR 0x18 10826 #define INTVR 0x1a 10827 #define IMVR 0x1c 10828 #define TRB 0x20 10829 #define TRBL 0x20 10830 #define TRBH 0x21 10831 #define SR0 0x22 10832 #define SR1 0x23 10833 #define SR2 0x24 10834 #define SR3 0x25 10835 #define FST 0x26 10836 #define IE0 0x28 10837 #define IE1 0x29 10838 #define IE2 0x2a 10839 #define FIE 0x2b 10840 #define CMD 0x2c 10841 #define MD0 0x2e 10842 #define MD1 0x2f 10843 #define MD2 0x30 10844 #define CTL 0x31 10845 #define SA0 0x32 10846 #define SA1 0x33 10847 #define IDL 0x34 10848 #define TMC 0x35 10849 #define RXS 0x36 10850 #define TXS 0x37 10851 #define TRC0 0x38 10852 #define TRC1 0x39 10853 #define RRC 0x3a 10854 #define CST0 0x3c 10855 #define CST1 0x3d 10856 #define TCNT 0x60 10857 #define TCNTL 0x60 10858 #define TCNTH 0x61 10859 #define TCONR 0x62 10860 #define TCONRL 0x62 10861 #define TCONRH 0x63 10862 #define TMCS 0x64 10863 #define TEPR 0x65 10864 #define DARL 0x80 10865 #define DARH 0x81 10866 #define DARB 0x82 10867 #define BAR 0x80 10868 #define BARL 0x80 10869 #define BARH 0x81 10870 #define BARB 0x82 10871 #define SAR 0x84 10872 #define SARL 0x84 10873 #define SARH 0x85 10874 #define SARB 0x86 10875 #define CPB 0x86 10876 #define CDA 0x88 10877 #define CDAL 0x88 10878 #define CDAH 0x89 10879 #define EDA 0x8a 10880 #define EDAL 0x8a 10881 #define EDAH 0x8b 10882 #define BFL 0x8c 10883 #define BFLL 0x8c 10884 #define BFLH 0x8d 10885 #define BCR 0x8e 10886 #define BCRL 0x8e 10887 #define BCRH 0x8f 10888 #define DSR 0x90 10889 #define DMR 0x91 10890 #define FCT 0x93 10891 #define DIR 0x94 10892 #define DCMD 0x95 10893 #define TIMER0 0x00 10894 #define TIMER1 0x08 10895 #define TIMER2 0x10 10896 #define TIMER3 0x18 10897 #define RXDMA 0x00 10898 #define TXDMA 0x20 10899 #define NOOP 0x00 10900 #define TXRESET 0x01 10901 #define TXENABLE 0x02 10902 #define TXDISABLE 0x03 10903 #define TXCRCINIT 0x04 10904 #define TXCRCEXCL 0x05 10905 #define TXEOM 0x06 10906 #define TXABORT 0x07 10907 #define MPON 0x08 10908 #define TXBUFCLR 0x09 10909 #define RXRESET 0x11 10910 #define RXENABLE 0x12 10911 #define RXDISABLE 0x13 10912 #define RXCRCINIT 0x14 10913 #define RXREJECT 0x15 10914 #define SEARCHMP 0x16 10915 #define RXCRCEXCL 0x17 10916 #define RXCRCCALC 0x18 10917 #define CHRESET 0x21 10918 #define HUNT 0x31 10919 #define SWABORT 0x01 10920 #define FEICLEAR 0x02 10921 #define TXINTE BIT7 10922 #define RXINTE BIT6 10923 #define TXRDYE BIT1 10924 #define RXRDYE BIT0 10925 #define UDRN BIT7 10926 #define IDLE BIT6 10927 #define SYNCD BIT4 10928 #define FLGD BIT4 10929 #define CCTS BIT3 10930 #define CDCD BIT2 10931 #define BRKD BIT1 10932 #define ABTD BIT1 10933 #define GAPD BIT1 10934 #define BRKE BIT0 10935 #define IDLD BIT0 10936 #define EOM BIT7 10937 #define PMP BIT6 10938 #define SHRT BIT6 10939 #define PE BIT5 10940 #define ABT BIT5 10941 #define FRME BIT4 10942 #define RBIT BIT4 10943 #define OVRN BIT3 10944 #define CRCE BIT2 10945 #define WAKEUP_CHARS 256 10946 #if SYNCLINK_GENERIC_HDLC 10947 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 10948 #endif 10949 #ifdef SANITY_CHECK 10950 #else 10951 #endif 10952 /* LDV_COMMENT_END_PREP */ 10953 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "set_termios" */ 10954 struct ktermios * var_group9; 10955 /* LDV_COMMENT_BEGIN_PREP */ 10956 #if SYNCLINK_GENERIC_HDLC 10957 #endif 10958 #if SYNCLINK_GENERIC_HDLC 10959 #endif 10960 #if SYNCLINK_GENERIC_HDLC 10961 #endif 10962 #ifdef CMSPAR 10963 #endif 10964 #if SYNCLINK_GENERIC_HDLC 10965 #endif 10966 #if SYNCLINK_GENERIC_HDLC 10967 #endif 10968 #if 0 10969 #endif 10970 #if SYNCLINK_GENERIC_HDLC 10971 #endif 10972 #if SYNCLINK_GENERIC_HDLC 10973 #endif 10974 #define TESTFRAMESIZE 20 10975 #if SYNCLINK_GENERIC_HDLC 10976 #endif 10977 #define CALC_REGADDR() \ 10978 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 10979 if (info->port_num > 1) \ 10980 RegAddr += 256; \ 10981 if ( info->port_num & 1) { \ 10982 if (Addr > 0x7f) \ 10983 RegAddr += 0x40; \ 10984 else if (Addr > 0x1f && Addr < 0x60) \ 10985 RegAddr += 0x20; \ 10986 } 10987 /* LDV_COMMENT_END_PREP */ 10988 /* content: static void tx_hold(struct tty_struct *tty)*/ 10989 /* LDV_COMMENT_BEGIN_PREP */ 10990 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 10991 #if defined(__i386__) 10992 # define BREAKPOINT() asm(" int $3"); 10993 #else 10994 # define BREAKPOINT() { } 10995 #endif 10996 #define MAX_DEVICES 12 10997 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 10998 #define SYNCLINK_GENERIC_HDLC 1 10999 #else 11000 #define SYNCLINK_GENERIC_HDLC 0 11001 #endif 11002 #define GET_USER(error,value,addr) error = get_user(value,addr) 11003 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11004 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11005 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11006 #define SCABUFSIZE 1024 11007 #define SCA_MEM_SIZE 0x40000 11008 #define SCA_BASE_SIZE 512 11009 #define SCA_REG_SIZE 16 11010 #define SCA_MAX_PORTS 4 11011 #define SCAMAXDESC 128 11012 #define BUFFERLISTSIZE 4096 11013 #define BH_RECEIVE 1 11014 #define BH_TRANSMIT 2 11015 #define BH_STATUS 4 11016 #define IO_PIN_SHUTDOWN_LIMIT 100 11017 #if SYNCLINK_GENERIC_HDLC 11018 #endif 11019 #define MGSL_MAGIC 0x5401 11020 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11021 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11022 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11023 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11024 #define LPR 0x00 11025 #define PABR0 0x02 11026 #define PABR1 0x03 11027 #define WCRL 0x04 11028 #define WCRM 0x05 11029 #define WCRH 0x06 11030 #define DPCR 0x08 11031 #define DMER 0x09 11032 #define ISR0 0x10 11033 #define ISR1 0x11 11034 #define ISR2 0x12 11035 #define IER0 0x14 11036 #define IER1 0x15 11037 #define IER2 0x16 11038 #define ITCR 0x18 11039 #define INTVR 0x1a 11040 #define IMVR 0x1c 11041 #define TRB 0x20 11042 #define TRBL 0x20 11043 #define TRBH 0x21 11044 #define SR0 0x22 11045 #define SR1 0x23 11046 #define SR2 0x24 11047 #define SR3 0x25 11048 #define FST 0x26 11049 #define IE0 0x28 11050 #define IE1 0x29 11051 #define IE2 0x2a 11052 #define FIE 0x2b 11053 #define CMD 0x2c 11054 #define MD0 0x2e 11055 #define MD1 0x2f 11056 #define MD2 0x30 11057 #define CTL 0x31 11058 #define SA0 0x32 11059 #define SA1 0x33 11060 #define IDL 0x34 11061 #define TMC 0x35 11062 #define RXS 0x36 11063 #define TXS 0x37 11064 #define TRC0 0x38 11065 #define TRC1 0x39 11066 #define RRC 0x3a 11067 #define CST0 0x3c 11068 #define CST1 0x3d 11069 #define TCNT 0x60 11070 #define TCNTL 0x60 11071 #define TCNTH 0x61 11072 #define TCONR 0x62 11073 #define TCONRL 0x62 11074 #define TCONRH 0x63 11075 #define TMCS 0x64 11076 #define TEPR 0x65 11077 #define DARL 0x80 11078 #define DARH 0x81 11079 #define DARB 0x82 11080 #define BAR 0x80 11081 #define BARL 0x80 11082 #define BARH 0x81 11083 #define BARB 0x82 11084 #define SAR 0x84 11085 #define SARL 0x84 11086 #define SARH 0x85 11087 #define SARB 0x86 11088 #define CPB 0x86 11089 #define CDA 0x88 11090 #define CDAL 0x88 11091 #define CDAH 0x89 11092 #define EDA 0x8a 11093 #define EDAL 0x8a 11094 #define EDAH 0x8b 11095 #define BFL 0x8c 11096 #define BFLL 0x8c 11097 #define BFLH 0x8d 11098 #define BCR 0x8e 11099 #define BCRL 0x8e 11100 #define BCRH 0x8f 11101 #define DSR 0x90 11102 #define DMR 0x91 11103 #define FCT 0x93 11104 #define DIR 0x94 11105 #define DCMD 0x95 11106 #define TIMER0 0x00 11107 #define TIMER1 0x08 11108 #define TIMER2 0x10 11109 #define TIMER3 0x18 11110 #define RXDMA 0x00 11111 #define TXDMA 0x20 11112 #define NOOP 0x00 11113 #define TXRESET 0x01 11114 #define TXENABLE 0x02 11115 #define TXDISABLE 0x03 11116 #define TXCRCINIT 0x04 11117 #define TXCRCEXCL 0x05 11118 #define TXEOM 0x06 11119 #define TXABORT 0x07 11120 #define MPON 0x08 11121 #define TXBUFCLR 0x09 11122 #define RXRESET 0x11 11123 #define RXENABLE 0x12 11124 #define RXDISABLE 0x13 11125 #define RXCRCINIT 0x14 11126 #define RXREJECT 0x15 11127 #define SEARCHMP 0x16 11128 #define RXCRCEXCL 0x17 11129 #define RXCRCCALC 0x18 11130 #define CHRESET 0x21 11131 #define HUNT 0x31 11132 #define SWABORT 0x01 11133 #define FEICLEAR 0x02 11134 #define TXINTE BIT7 11135 #define RXINTE BIT6 11136 #define TXRDYE BIT1 11137 #define RXRDYE BIT0 11138 #define UDRN BIT7 11139 #define IDLE BIT6 11140 #define SYNCD BIT4 11141 #define FLGD BIT4 11142 #define CCTS BIT3 11143 #define CDCD BIT2 11144 #define BRKD BIT1 11145 #define ABTD BIT1 11146 #define GAPD BIT1 11147 #define BRKE BIT0 11148 #define IDLD BIT0 11149 #define EOM BIT7 11150 #define PMP BIT6 11151 #define SHRT BIT6 11152 #define PE BIT5 11153 #define ABT BIT5 11154 #define FRME BIT4 11155 #define RBIT BIT4 11156 #define OVRN BIT3 11157 #define CRCE BIT2 11158 #define WAKEUP_CHARS 256 11159 #if SYNCLINK_GENERIC_HDLC 11160 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11161 #endif 11162 #ifdef SANITY_CHECK 11163 #else 11164 #endif 11165 /* LDV_COMMENT_END_PREP */ 11166 /* LDV_COMMENT_BEGIN_PREP */ 11167 #if SYNCLINK_GENERIC_HDLC 11168 #endif 11169 #if SYNCLINK_GENERIC_HDLC 11170 #endif 11171 #if SYNCLINK_GENERIC_HDLC 11172 #endif 11173 #ifdef CMSPAR 11174 #endif 11175 #if SYNCLINK_GENERIC_HDLC 11176 #endif 11177 #if SYNCLINK_GENERIC_HDLC 11178 #endif 11179 #if 0 11180 #endif 11181 #if SYNCLINK_GENERIC_HDLC 11182 #endif 11183 #if SYNCLINK_GENERIC_HDLC 11184 #endif 11185 #define TESTFRAMESIZE 20 11186 #if SYNCLINK_GENERIC_HDLC 11187 #endif 11188 #define CALC_REGADDR() \ 11189 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 11190 if (info->port_num > 1) \ 11191 RegAddr += 256; \ 11192 if ( info->port_num & 1) { \ 11193 if (Addr > 0x7f) \ 11194 RegAddr += 0x40; \ 11195 else if (Addr > 0x1f && Addr < 0x60) \ 11196 RegAddr += 0x20; \ 11197 } 11198 /* LDV_COMMENT_END_PREP */ 11199 /* content: static void tx_release(struct tty_struct *tty)*/ 11200 /* LDV_COMMENT_BEGIN_PREP */ 11201 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 11202 #if defined(__i386__) 11203 # define BREAKPOINT() asm(" int $3"); 11204 #else 11205 # define BREAKPOINT() { } 11206 #endif 11207 #define MAX_DEVICES 12 11208 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 11209 #define SYNCLINK_GENERIC_HDLC 1 11210 #else 11211 #define SYNCLINK_GENERIC_HDLC 0 11212 #endif 11213 #define GET_USER(error,value,addr) error = get_user(value,addr) 11214 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11215 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11216 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11217 #define SCABUFSIZE 1024 11218 #define SCA_MEM_SIZE 0x40000 11219 #define SCA_BASE_SIZE 512 11220 #define SCA_REG_SIZE 16 11221 #define SCA_MAX_PORTS 4 11222 #define SCAMAXDESC 128 11223 #define BUFFERLISTSIZE 4096 11224 #define BH_RECEIVE 1 11225 #define BH_TRANSMIT 2 11226 #define BH_STATUS 4 11227 #define IO_PIN_SHUTDOWN_LIMIT 100 11228 #if SYNCLINK_GENERIC_HDLC 11229 #endif 11230 #define MGSL_MAGIC 0x5401 11231 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11232 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11233 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11234 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11235 #define LPR 0x00 11236 #define PABR0 0x02 11237 #define PABR1 0x03 11238 #define WCRL 0x04 11239 #define WCRM 0x05 11240 #define WCRH 0x06 11241 #define DPCR 0x08 11242 #define DMER 0x09 11243 #define ISR0 0x10 11244 #define ISR1 0x11 11245 #define ISR2 0x12 11246 #define IER0 0x14 11247 #define IER1 0x15 11248 #define IER2 0x16 11249 #define ITCR 0x18 11250 #define INTVR 0x1a 11251 #define IMVR 0x1c 11252 #define TRB 0x20 11253 #define TRBL 0x20 11254 #define TRBH 0x21 11255 #define SR0 0x22 11256 #define SR1 0x23 11257 #define SR2 0x24 11258 #define SR3 0x25 11259 #define FST 0x26 11260 #define IE0 0x28 11261 #define IE1 0x29 11262 #define IE2 0x2a 11263 #define FIE 0x2b 11264 #define CMD 0x2c 11265 #define MD0 0x2e 11266 #define MD1 0x2f 11267 #define MD2 0x30 11268 #define CTL 0x31 11269 #define SA0 0x32 11270 #define SA1 0x33 11271 #define IDL 0x34 11272 #define TMC 0x35 11273 #define RXS 0x36 11274 #define TXS 0x37 11275 #define TRC0 0x38 11276 #define TRC1 0x39 11277 #define RRC 0x3a 11278 #define CST0 0x3c 11279 #define CST1 0x3d 11280 #define TCNT 0x60 11281 #define TCNTL 0x60 11282 #define TCNTH 0x61 11283 #define TCONR 0x62 11284 #define TCONRL 0x62 11285 #define TCONRH 0x63 11286 #define TMCS 0x64 11287 #define TEPR 0x65 11288 #define DARL 0x80 11289 #define DARH 0x81 11290 #define DARB 0x82 11291 #define BAR 0x80 11292 #define BARL 0x80 11293 #define BARH 0x81 11294 #define BARB 0x82 11295 #define SAR 0x84 11296 #define SARL 0x84 11297 #define SARH 0x85 11298 #define SARB 0x86 11299 #define CPB 0x86 11300 #define CDA 0x88 11301 #define CDAL 0x88 11302 #define CDAH 0x89 11303 #define EDA 0x8a 11304 #define EDAL 0x8a 11305 #define EDAH 0x8b 11306 #define BFL 0x8c 11307 #define BFLL 0x8c 11308 #define BFLH 0x8d 11309 #define BCR 0x8e 11310 #define BCRL 0x8e 11311 #define BCRH 0x8f 11312 #define DSR 0x90 11313 #define DMR 0x91 11314 #define FCT 0x93 11315 #define DIR 0x94 11316 #define DCMD 0x95 11317 #define TIMER0 0x00 11318 #define TIMER1 0x08 11319 #define TIMER2 0x10 11320 #define TIMER3 0x18 11321 #define RXDMA 0x00 11322 #define TXDMA 0x20 11323 #define NOOP 0x00 11324 #define TXRESET 0x01 11325 #define TXENABLE 0x02 11326 #define TXDISABLE 0x03 11327 #define TXCRCINIT 0x04 11328 #define TXCRCEXCL 0x05 11329 #define TXEOM 0x06 11330 #define TXABORT 0x07 11331 #define MPON 0x08 11332 #define TXBUFCLR 0x09 11333 #define RXRESET 0x11 11334 #define RXENABLE 0x12 11335 #define RXDISABLE 0x13 11336 #define RXCRCINIT 0x14 11337 #define RXREJECT 0x15 11338 #define SEARCHMP 0x16 11339 #define RXCRCEXCL 0x17 11340 #define RXCRCCALC 0x18 11341 #define CHRESET 0x21 11342 #define HUNT 0x31 11343 #define SWABORT 0x01 11344 #define FEICLEAR 0x02 11345 #define TXINTE BIT7 11346 #define RXINTE BIT6 11347 #define TXRDYE BIT1 11348 #define RXRDYE BIT0 11349 #define UDRN BIT7 11350 #define IDLE BIT6 11351 #define SYNCD BIT4 11352 #define FLGD BIT4 11353 #define CCTS BIT3 11354 #define CDCD BIT2 11355 #define BRKD BIT1 11356 #define ABTD BIT1 11357 #define GAPD BIT1 11358 #define BRKE BIT0 11359 #define IDLD BIT0 11360 #define EOM BIT7 11361 #define PMP BIT6 11362 #define SHRT BIT6 11363 #define PE BIT5 11364 #define ABT BIT5 11365 #define FRME BIT4 11366 #define RBIT BIT4 11367 #define OVRN BIT3 11368 #define CRCE BIT2 11369 #define WAKEUP_CHARS 256 11370 #if SYNCLINK_GENERIC_HDLC 11371 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11372 #endif 11373 #ifdef SANITY_CHECK 11374 #else 11375 #endif 11376 /* LDV_COMMENT_END_PREP */ 11377 /* LDV_COMMENT_BEGIN_PREP */ 11378 #if SYNCLINK_GENERIC_HDLC 11379 #endif 11380 #if SYNCLINK_GENERIC_HDLC 11381 #endif 11382 #if SYNCLINK_GENERIC_HDLC 11383 #endif 11384 #ifdef CMSPAR 11385 #endif 11386 #if SYNCLINK_GENERIC_HDLC 11387 #endif 11388 #if SYNCLINK_GENERIC_HDLC 11389 #endif 11390 #if 0 11391 #endif 11392 #if SYNCLINK_GENERIC_HDLC 11393 #endif 11394 #if SYNCLINK_GENERIC_HDLC 11395 #endif 11396 #define TESTFRAMESIZE 20 11397 #if SYNCLINK_GENERIC_HDLC 11398 #endif 11399 #define CALC_REGADDR() \ 11400 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 11401 if (info->port_num > 1) \ 11402 RegAddr += 256; \ 11403 if ( info->port_num & 1) { \ 11404 if (Addr > 0x7f) \ 11405 RegAddr += 0x40; \ 11406 else if (Addr > 0x1f && Addr < 0x60) \ 11407 RegAddr += 0x20; \ 11408 } 11409 /* LDV_COMMENT_END_PREP */ 11410 /* content: static void hangup(struct tty_struct *tty)*/ 11411 /* LDV_COMMENT_BEGIN_PREP */ 11412 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 11413 #if defined(__i386__) 11414 # define BREAKPOINT() asm(" int $3"); 11415 #else 11416 # define BREAKPOINT() { } 11417 #endif 11418 #define MAX_DEVICES 12 11419 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 11420 #define SYNCLINK_GENERIC_HDLC 1 11421 #else 11422 #define SYNCLINK_GENERIC_HDLC 0 11423 #endif 11424 #define GET_USER(error,value,addr) error = get_user(value,addr) 11425 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11426 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11427 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11428 #define SCABUFSIZE 1024 11429 #define SCA_MEM_SIZE 0x40000 11430 #define SCA_BASE_SIZE 512 11431 #define SCA_REG_SIZE 16 11432 #define SCA_MAX_PORTS 4 11433 #define SCAMAXDESC 128 11434 #define BUFFERLISTSIZE 4096 11435 #define BH_RECEIVE 1 11436 #define BH_TRANSMIT 2 11437 #define BH_STATUS 4 11438 #define IO_PIN_SHUTDOWN_LIMIT 100 11439 #if SYNCLINK_GENERIC_HDLC 11440 #endif 11441 #define MGSL_MAGIC 0x5401 11442 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11443 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11444 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11445 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11446 #define LPR 0x00 11447 #define PABR0 0x02 11448 #define PABR1 0x03 11449 #define WCRL 0x04 11450 #define WCRM 0x05 11451 #define WCRH 0x06 11452 #define DPCR 0x08 11453 #define DMER 0x09 11454 #define ISR0 0x10 11455 #define ISR1 0x11 11456 #define ISR2 0x12 11457 #define IER0 0x14 11458 #define IER1 0x15 11459 #define IER2 0x16 11460 #define ITCR 0x18 11461 #define INTVR 0x1a 11462 #define IMVR 0x1c 11463 #define TRB 0x20 11464 #define TRBL 0x20 11465 #define TRBH 0x21 11466 #define SR0 0x22 11467 #define SR1 0x23 11468 #define SR2 0x24 11469 #define SR3 0x25 11470 #define FST 0x26 11471 #define IE0 0x28 11472 #define IE1 0x29 11473 #define IE2 0x2a 11474 #define FIE 0x2b 11475 #define CMD 0x2c 11476 #define MD0 0x2e 11477 #define MD1 0x2f 11478 #define MD2 0x30 11479 #define CTL 0x31 11480 #define SA0 0x32 11481 #define SA1 0x33 11482 #define IDL 0x34 11483 #define TMC 0x35 11484 #define RXS 0x36 11485 #define TXS 0x37 11486 #define TRC0 0x38 11487 #define TRC1 0x39 11488 #define RRC 0x3a 11489 #define CST0 0x3c 11490 #define CST1 0x3d 11491 #define TCNT 0x60 11492 #define TCNTL 0x60 11493 #define TCNTH 0x61 11494 #define TCONR 0x62 11495 #define TCONRL 0x62 11496 #define TCONRH 0x63 11497 #define TMCS 0x64 11498 #define TEPR 0x65 11499 #define DARL 0x80 11500 #define DARH 0x81 11501 #define DARB 0x82 11502 #define BAR 0x80 11503 #define BARL 0x80 11504 #define BARH 0x81 11505 #define BARB 0x82 11506 #define SAR 0x84 11507 #define SARL 0x84 11508 #define SARH 0x85 11509 #define SARB 0x86 11510 #define CPB 0x86 11511 #define CDA 0x88 11512 #define CDAL 0x88 11513 #define CDAH 0x89 11514 #define EDA 0x8a 11515 #define EDAL 0x8a 11516 #define EDAH 0x8b 11517 #define BFL 0x8c 11518 #define BFLL 0x8c 11519 #define BFLH 0x8d 11520 #define BCR 0x8e 11521 #define BCRL 0x8e 11522 #define BCRH 0x8f 11523 #define DSR 0x90 11524 #define DMR 0x91 11525 #define FCT 0x93 11526 #define DIR 0x94 11527 #define DCMD 0x95 11528 #define TIMER0 0x00 11529 #define TIMER1 0x08 11530 #define TIMER2 0x10 11531 #define TIMER3 0x18 11532 #define RXDMA 0x00 11533 #define TXDMA 0x20 11534 #define NOOP 0x00 11535 #define TXRESET 0x01 11536 #define TXENABLE 0x02 11537 #define TXDISABLE 0x03 11538 #define TXCRCINIT 0x04 11539 #define TXCRCEXCL 0x05 11540 #define TXEOM 0x06 11541 #define TXABORT 0x07 11542 #define MPON 0x08 11543 #define TXBUFCLR 0x09 11544 #define RXRESET 0x11 11545 #define RXENABLE 0x12 11546 #define RXDISABLE 0x13 11547 #define RXCRCINIT 0x14 11548 #define RXREJECT 0x15 11549 #define SEARCHMP 0x16 11550 #define RXCRCEXCL 0x17 11551 #define RXCRCCALC 0x18 11552 #define CHRESET 0x21 11553 #define HUNT 0x31 11554 #define SWABORT 0x01 11555 #define FEICLEAR 0x02 11556 #define TXINTE BIT7 11557 #define RXINTE BIT6 11558 #define TXRDYE BIT1 11559 #define RXRDYE BIT0 11560 #define UDRN BIT7 11561 #define IDLE BIT6 11562 #define SYNCD BIT4 11563 #define FLGD BIT4 11564 #define CCTS BIT3 11565 #define CDCD BIT2 11566 #define BRKD BIT1 11567 #define ABTD BIT1 11568 #define GAPD BIT1 11569 #define BRKE BIT0 11570 #define IDLD BIT0 11571 #define EOM BIT7 11572 #define PMP BIT6 11573 #define SHRT BIT6 11574 #define PE BIT5 11575 #define ABT BIT5 11576 #define FRME BIT4 11577 #define RBIT BIT4 11578 #define OVRN BIT3 11579 #define CRCE BIT2 11580 #define WAKEUP_CHARS 256 11581 #if SYNCLINK_GENERIC_HDLC 11582 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11583 #endif 11584 #ifdef SANITY_CHECK 11585 #else 11586 #endif 11587 /* LDV_COMMENT_END_PREP */ 11588 /* LDV_COMMENT_BEGIN_PREP */ 11589 #if SYNCLINK_GENERIC_HDLC 11590 #endif 11591 #if SYNCLINK_GENERIC_HDLC 11592 #endif 11593 #if SYNCLINK_GENERIC_HDLC 11594 #endif 11595 #ifdef CMSPAR 11596 #endif 11597 #if SYNCLINK_GENERIC_HDLC 11598 #endif 11599 #if SYNCLINK_GENERIC_HDLC 11600 #endif 11601 #if 0 11602 #endif 11603 #if SYNCLINK_GENERIC_HDLC 11604 #endif 11605 #if SYNCLINK_GENERIC_HDLC 11606 #endif 11607 #define TESTFRAMESIZE 20 11608 #if SYNCLINK_GENERIC_HDLC 11609 #endif 11610 #define CALC_REGADDR() \ 11611 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 11612 if (info->port_num > 1) \ 11613 RegAddr += 256; \ 11614 if ( info->port_num & 1) { \ 11615 if (Addr > 0x7f) \ 11616 RegAddr += 0x40; \ 11617 else if (Addr > 0x1f && Addr < 0x60) \ 11618 RegAddr += 0x20; \ 11619 } 11620 /* LDV_COMMENT_END_PREP */ 11621 /* content: static int tiocmget(struct tty_struct *tty)*/ 11622 /* LDV_COMMENT_BEGIN_PREP */ 11623 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 11624 #if defined(__i386__) 11625 # define BREAKPOINT() asm(" int $3"); 11626 #else 11627 # define BREAKPOINT() { } 11628 #endif 11629 #define MAX_DEVICES 12 11630 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 11631 #define SYNCLINK_GENERIC_HDLC 1 11632 #else 11633 #define SYNCLINK_GENERIC_HDLC 0 11634 #endif 11635 #define GET_USER(error,value,addr) error = get_user(value,addr) 11636 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11637 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11638 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11639 #define SCABUFSIZE 1024 11640 #define SCA_MEM_SIZE 0x40000 11641 #define SCA_BASE_SIZE 512 11642 #define SCA_REG_SIZE 16 11643 #define SCA_MAX_PORTS 4 11644 #define SCAMAXDESC 128 11645 #define BUFFERLISTSIZE 4096 11646 #define BH_RECEIVE 1 11647 #define BH_TRANSMIT 2 11648 #define BH_STATUS 4 11649 #define IO_PIN_SHUTDOWN_LIMIT 100 11650 #if SYNCLINK_GENERIC_HDLC 11651 #endif 11652 #define MGSL_MAGIC 0x5401 11653 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11654 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11655 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11656 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11657 #define LPR 0x00 11658 #define PABR0 0x02 11659 #define PABR1 0x03 11660 #define WCRL 0x04 11661 #define WCRM 0x05 11662 #define WCRH 0x06 11663 #define DPCR 0x08 11664 #define DMER 0x09 11665 #define ISR0 0x10 11666 #define ISR1 0x11 11667 #define ISR2 0x12 11668 #define IER0 0x14 11669 #define IER1 0x15 11670 #define IER2 0x16 11671 #define ITCR 0x18 11672 #define INTVR 0x1a 11673 #define IMVR 0x1c 11674 #define TRB 0x20 11675 #define TRBL 0x20 11676 #define TRBH 0x21 11677 #define SR0 0x22 11678 #define SR1 0x23 11679 #define SR2 0x24 11680 #define SR3 0x25 11681 #define FST 0x26 11682 #define IE0 0x28 11683 #define IE1 0x29 11684 #define IE2 0x2a 11685 #define FIE 0x2b 11686 #define CMD 0x2c 11687 #define MD0 0x2e 11688 #define MD1 0x2f 11689 #define MD2 0x30 11690 #define CTL 0x31 11691 #define SA0 0x32 11692 #define SA1 0x33 11693 #define IDL 0x34 11694 #define TMC 0x35 11695 #define RXS 0x36 11696 #define TXS 0x37 11697 #define TRC0 0x38 11698 #define TRC1 0x39 11699 #define RRC 0x3a 11700 #define CST0 0x3c 11701 #define CST1 0x3d 11702 #define TCNT 0x60 11703 #define TCNTL 0x60 11704 #define TCNTH 0x61 11705 #define TCONR 0x62 11706 #define TCONRL 0x62 11707 #define TCONRH 0x63 11708 #define TMCS 0x64 11709 #define TEPR 0x65 11710 #define DARL 0x80 11711 #define DARH 0x81 11712 #define DARB 0x82 11713 #define BAR 0x80 11714 #define BARL 0x80 11715 #define BARH 0x81 11716 #define BARB 0x82 11717 #define SAR 0x84 11718 #define SARL 0x84 11719 #define SARH 0x85 11720 #define SARB 0x86 11721 #define CPB 0x86 11722 #define CDA 0x88 11723 #define CDAL 0x88 11724 #define CDAH 0x89 11725 #define EDA 0x8a 11726 #define EDAL 0x8a 11727 #define EDAH 0x8b 11728 #define BFL 0x8c 11729 #define BFLL 0x8c 11730 #define BFLH 0x8d 11731 #define BCR 0x8e 11732 #define BCRL 0x8e 11733 #define BCRH 0x8f 11734 #define DSR 0x90 11735 #define DMR 0x91 11736 #define FCT 0x93 11737 #define DIR 0x94 11738 #define DCMD 0x95 11739 #define TIMER0 0x00 11740 #define TIMER1 0x08 11741 #define TIMER2 0x10 11742 #define TIMER3 0x18 11743 #define RXDMA 0x00 11744 #define TXDMA 0x20 11745 #define NOOP 0x00 11746 #define TXRESET 0x01 11747 #define TXENABLE 0x02 11748 #define TXDISABLE 0x03 11749 #define TXCRCINIT 0x04 11750 #define TXCRCEXCL 0x05 11751 #define TXEOM 0x06 11752 #define TXABORT 0x07 11753 #define MPON 0x08 11754 #define TXBUFCLR 0x09 11755 #define RXRESET 0x11 11756 #define RXENABLE 0x12 11757 #define RXDISABLE 0x13 11758 #define RXCRCINIT 0x14 11759 #define RXREJECT 0x15 11760 #define SEARCHMP 0x16 11761 #define RXCRCEXCL 0x17 11762 #define RXCRCCALC 0x18 11763 #define CHRESET 0x21 11764 #define HUNT 0x31 11765 #define SWABORT 0x01 11766 #define FEICLEAR 0x02 11767 #define TXINTE BIT7 11768 #define RXINTE BIT6 11769 #define TXRDYE BIT1 11770 #define RXRDYE BIT0 11771 #define UDRN BIT7 11772 #define IDLE BIT6 11773 #define SYNCD BIT4 11774 #define FLGD BIT4 11775 #define CCTS BIT3 11776 #define CDCD BIT2 11777 #define BRKD BIT1 11778 #define ABTD BIT1 11779 #define GAPD BIT1 11780 #define BRKE BIT0 11781 #define IDLD BIT0 11782 #define EOM BIT7 11783 #define PMP BIT6 11784 #define SHRT BIT6 11785 #define PE BIT5 11786 #define ABT BIT5 11787 #define FRME BIT4 11788 #define RBIT BIT4 11789 #define OVRN BIT3 11790 #define CRCE BIT2 11791 #define WAKEUP_CHARS 256 11792 #if SYNCLINK_GENERIC_HDLC 11793 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 11794 #endif 11795 #ifdef SANITY_CHECK 11796 #else 11797 #endif 11798 #if SYNCLINK_GENERIC_HDLC 11799 #endif 11800 #if SYNCLINK_GENERIC_HDLC 11801 #endif 11802 #if SYNCLINK_GENERIC_HDLC 11803 #endif 11804 #ifdef CMSPAR 11805 #endif 11806 /* LDV_COMMENT_END_PREP */ 11807 /* LDV_COMMENT_BEGIN_PREP */ 11808 #if SYNCLINK_GENERIC_HDLC 11809 #endif 11810 #if SYNCLINK_GENERIC_HDLC 11811 #endif 11812 #if 0 11813 #endif 11814 #if SYNCLINK_GENERIC_HDLC 11815 #endif 11816 #if SYNCLINK_GENERIC_HDLC 11817 #endif 11818 #define TESTFRAMESIZE 20 11819 #if SYNCLINK_GENERIC_HDLC 11820 #endif 11821 #define CALC_REGADDR() \ 11822 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 11823 if (info->port_num > 1) \ 11824 RegAddr += 256; \ 11825 if ( info->port_num & 1) { \ 11826 if (Addr > 0x7f) \ 11827 RegAddr += 0x40; \ 11828 else if (Addr > 0x1f && Addr < 0x60) \ 11829 RegAddr += 0x20; \ 11830 } 11831 /* LDV_COMMENT_END_PREP */ 11832 /* content: static int tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)*/ 11833 /* LDV_COMMENT_BEGIN_PREP */ 11834 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 11835 #if defined(__i386__) 11836 # define BREAKPOINT() asm(" int $3"); 11837 #else 11838 # define BREAKPOINT() { } 11839 #endif 11840 #define MAX_DEVICES 12 11841 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 11842 #define SYNCLINK_GENERIC_HDLC 1 11843 #else 11844 #define SYNCLINK_GENERIC_HDLC 0 11845 #endif 11846 #define GET_USER(error,value,addr) error = get_user(value,addr) 11847 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 11848 #define PUT_USER(error,value,addr) error = put_user(value,addr) 11849 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 11850 #define SCABUFSIZE 1024 11851 #define SCA_MEM_SIZE 0x40000 11852 #define SCA_BASE_SIZE 512 11853 #define SCA_REG_SIZE 16 11854 #define SCA_MAX_PORTS 4 11855 #define SCAMAXDESC 128 11856 #define BUFFERLISTSIZE 4096 11857 #define BH_RECEIVE 1 11858 #define BH_TRANSMIT 2 11859 #define BH_STATUS 4 11860 #define IO_PIN_SHUTDOWN_LIMIT 100 11861 #if SYNCLINK_GENERIC_HDLC 11862 #endif 11863 #define MGSL_MAGIC 0x5401 11864 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 11865 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 11866 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 11867 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 11868 #define LPR 0x00 11869 #define PABR0 0x02 11870 #define PABR1 0x03 11871 #define WCRL 0x04 11872 #define WCRM 0x05 11873 #define WCRH 0x06 11874 #define DPCR 0x08 11875 #define DMER 0x09 11876 #define ISR0 0x10 11877 #define ISR1 0x11 11878 #define ISR2 0x12 11879 #define IER0 0x14 11880 #define IER1 0x15 11881 #define IER2 0x16 11882 #define ITCR 0x18 11883 #define INTVR 0x1a 11884 #define IMVR 0x1c 11885 #define TRB 0x20 11886 #define TRBL 0x20 11887 #define TRBH 0x21 11888 #define SR0 0x22 11889 #define SR1 0x23 11890 #define SR2 0x24 11891 #define SR3 0x25 11892 #define FST 0x26 11893 #define IE0 0x28 11894 #define IE1 0x29 11895 #define IE2 0x2a 11896 #define FIE 0x2b 11897 #define CMD 0x2c 11898 #define MD0 0x2e 11899 #define MD1 0x2f 11900 #define MD2 0x30 11901 #define CTL 0x31 11902 #define SA0 0x32 11903 #define SA1 0x33 11904 #define IDL 0x34 11905 #define TMC 0x35 11906 #define RXS 0x36 11907 #define TXS 0x37 11908 #define TRC0 0x38 11909 #define TRC1 0x39 11910 #define RRC 0x3a 11911 #define CST0 0x3c 11912 #define CST1 0x3d 11913 #define TCNT 0x60 11914 #define TCNTL 0x60 11915 #define TCNTH 0x61 11916 #define TCONR 0x62 11917 #define TCONRL 0x62 11918 #define TCONRH 0x63 11919 #define TMCS 0x64 11920 #define TEPR 0x65 11921 #define DARL 0x80 11922 #define DARH 0x81 11923 #define DARB 0x82 11924 #define BAR 0x80 11925 #define BARL 0x80 11926 #define BARH 0x81 11927 #define BARB 0x82 11928 #define SAR 0x84 11929 #define SARL 0x84 11930 #define SARH 0x85 11931 #define SARB 0x86 11932 #define CPB 0x86 11933 #define CDA 0x88 11934 #define CDAL 0x88 11935 #define CDAH 0x89 11936 #define EDA 0x8a 11937 #define EDAL 0x8a 11938 #define EDAH 0x8b 11939 #define BFL 0x8c 11940 #define BFLL 0x8c 11941 #define BFLH 0x8d 11942 #define BCR 0x8e 11943 #define BCRL 0x8e 11944 #define BCRH 0x8f 11945 #define DSR 0x90 11946 #define DMR 0x91 11947 #define FCT 0x93 11948 #define DIR 0x94 11949 #define DCMD 0x95 11950 #define TIMER0 0x00 11951 #define TIMER1 0x08 11952 #define TIMER2 0x10 11953 #define TIMER3 0x18 11954 #define RXDMA 0x00 11955 #define TXDMA 0x20 11956 #define NOOP 0x00 11957 #define TXRESET 0x01 11958 #define TXENABLE 0x02 11959 #define TXDISABLE 0x03 11960 #define TXCRCINIT 0x04 11961 #define TXCRCEXCL 0x05 11962 #define TXEOM 0x06 11963 #define TXABORT 0x07 11964 #define MPON 0x08 11965 #define TXBUFCLR 0x09 11966 #define RXRESET 0x11 11967 #define RXENABLE 0x12 11968 #define RXDISABLE 0x13 11969 #define RXCRCINIT 0x14 11970 #define RXREJECT 0x15 11971 #define SEARCHMP 0x16 11972 #define RXCRCEXCL 0x17 11973 #define RXCRCCALC 0x18 11974 #define CHRESET 0x21 11975 #define HUNT 0x31 11976 #define SWABORT 0x01 11977 #define FEICLEAR 0x02 11978 #define TXINTE BIT7 11979 #define RXINTE BIT6 11980 #define TXRDYE BIT1 11981 #define RXRDYE BIT0 11982 #define UDRN BIT7 11983 #define IDLE BIT6 11984 #define SYNCD BIT4 11985 #define FLGD BIT4 11986 #define CCTS BIT3 11987 #define CDCD BIT2 11988 #define BRKD BIT1 11989 #define ABTD BIT1 11990 #define GAPD BIT1 11991 #define BRKE BIT0 11992 #define IDLD BIT0 11993 #define EOM BIT7 11994 #define PMP BIT6 11995 #define SHRT BIT6 11996 #define PE BIT5 11997 #define ABT BIT5 11998 #define FRME BIT4 11999 #define RBIT BIT4 12000 #define OVRN BIT3 12001 #define CRCE BIT2 12002 #define WAKEUP_CHARS 256 12003 #if SYNCLINK_GENERIC_HDLC 12004 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12005 #endif 12006 #ifdef SANITY_CHECK 12007 #else 12008 #endif 12009 #if SYNCLINK_GENERIC_HDLC 12010 #endif 12011 #if SYNCLINK_GENERIC_HDLC 12012 #endif 12013 #if SYNCLINK_GENERIC_HDLC 12014 #endif 12015 #ifdef CMSPAR 12016 #endif 12017 /* LDV_COMMENT_END_PREP */ 12018 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "tiocmset" */ 12019 unsigned int var_tiocmset_68_p1; 12020 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "tiocmset" */ 12021 unsigned int var_tiocmset_68_p2; 12022 /* LDV_COMMENT_BEGIN_PREP */ 12023 #if SYNCLINK_GENERIC_HDLC 12024 #endif 12025 #if SYNCLINK_GENERIC_HDLC 12026 #endif 12027 #if 0 12028 #endif 12029 #if SYNCLINK_GENERIC_HDLC 12030 #endif 12031 #if SYNCLINK_GENERIC_HDLC 12032 #endif 12033 #define TESTFRAMESIZE 20 12034 #if SYNCLINK_GENERIC_HDLC 12035 #endif 12036 #define CALC_REGADDR() \ 12037 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12038 if (info->port_num > 1) \ 12039 RegAddr += 256; \ 12040 if ( info->port_num & 1) { \ 12041 if (Addr > 0x7f) \ 12042 RegAddr += 0x40; \ 12043 else if (Addr > 0x1f && Addr < 0x60) \ 12044 RegAddr += 0x20; \ 12045 } 12046 /* LDV_COMMENT_END_PREP */ 12047 /* content: static int get_icount(struct tty_struct *tty, struct serial_icounter_struct *icount)*/ 12048 /* LDV_COMMENT_BEGIN_PREP */ 12049 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12050 #if defined(__i386__) 12051 # define BREAKPOINT() asm(" int $3"); 12052 #else 12053 # define BREAKPOINT() { } 12054 #endif 12055 #define MAX_DEVICES 12 12056 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12057 #define SYNCLINK_GENERIC_HDLC 1 12058 #else 12059 #define SYNCLINK_GENERIC_HDLC 0 12060 #endif 12061 #define GET_USER(error,value,addr) error = get_user(value,addr) 12062 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12063 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12064 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12065 #define SCABUFSIZE 1024 12066 #define SCA_MEM_SIZE 0x40000 12067 #define SCA_BASE_SIZE 512 12068 #define SCA_REG_SIZE 16 12069 #define SCA_MAX_PORTS 4 12070 #define SCAMAXDESC 128 12071 #define BUFFERLISTSIZE 4096 12072 #define BH_RECEIVE 1 12073 #define BH_TRANSMIT 2 12074 #define BH_STATUS 4 12075 #define IO_PIN_SHUTDOWN_LIMIT 100 12076 #if SYNCLINK_GENERIC_HDLC 12077 #endif 12078 #define MGSL_MAGIC 0x5401 12079 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12080 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12081 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12082 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12083 #define LPR 0x00 12084 #define PABR0 0x02 12085 #define PABR1 0x03 12086 #define WCRL 0x04 12087 #define WCRM 0x05 12088 #define WCRH 0x06 12089 #define DPCR 0x08 12090 #define DMER 0x09 12091 #define ISR0 0x10 12092 #define ISR1 0x11 12093 #define ISR2 0x12 12094 #define IER0 0x14 12095 #define IER1 0x15 12096 #define IER2 0x16 12097 #define ITCR 0x18 12098 #define INTVR 0x1a 12099 #define IMVR 0x1c 12100 #define TRB 0x20 12101 #define TRBL 0x20 12102 #define TRBH 0x21 12103 #define SR0 0x22 12104 #define SR1 0x23 12105 #define SR2 0x24 12106 #define SR3 0x25 12107 #define FST 0x26 12108 #define IE0 0x28 12109 #define IE1 0x29 12110 #define IE2 0x2a 12111 #define FIE 0x2b 12112 #define CMD 0x2c 12113 #define MD0 0x2e 12114 #define MD1 0x2f 12115 #define MD2 0x30 12116 #define CTL 0x31 12117 #define SA0 0x32 12118 #define SA1 0x33 12119 #define IDL 0x34 12120 #define TMC 0x35 12121 #define RXS 0x36 12122 #define TXS 0x37 12123 #define TRC0 0x38 12124 #define TRC1 0x39 12125 #define RRC 0x3a 12126 #define CST0 0x3c 12127 #define CST1 0x3d 12128 #define TCNT 0x60 12129 #define TCNTL 0x60 12130 #define TCNTH 0x61 12131 #define TCONR 0x62 12132 #define TCONRL 0x62 12133 #define TCONRH 0x63 12134 #define TMCS 0x64 12135 #define TEPR 0x65 12136 #define DARL 0x80 12137 #define DARH 0x81 12138 #define DARB 0x82 12139 #define BAR 0x80 12140 #define BARL 0x80 12141 #define BARH 0x81 12142 #define BARB 0x82 12143 #define SAR 0x84 12144 #define SARL 0x84 12145 #define SARH 0x85 12146 #define SARB 0x86 12147 #define CPB 0x86 12148 #define CDA 0x88 12149 #define CDAL 0x88 12150 #define CDAH 0x89 12151 #define EDA 0x8a 12152 #define EDAL 0x8a 12153 #define EDAH 0x8b 12154 #define BFL 0x8c 12155 #define BFLL 0x8c 12156 #define BFLH 0x8d 12157 #define BCR 0x8e 12158 #define BCRL 0x8e 12159 #define BCRH 0x8f 12160 #define DSR 0x90 12161 #define DMR 0x91 12162 #define FCT 0x93 12163 #define DIR 0x94 12164 #define DCMD 0x95 12165 #define TIMER0 0x00 12166 #define TIMER1 0x08 12167 #define TIMER2 0x10 12168 #define TIMER3 0x18 12169 #define RXDMA 0x00 12170 #define TXDMA 0x20 12171 #define NOOP 0x00 12172 #define TXRESET 0x01 12173 #define TXENABLE 0x02 12174 #define TXDISABLE 0x03 12175 #define TXCRCINIT 0x04 12176 #define TXCRCEXCL 0x05 12177 #define TXEOM 0x06 12178 #define TXABORT 0x07 12179 #define MPON 0x08 12180 #define TXBUFCLR 0x09 12181 #define RXRESET 0x11 12182 #define RXENABLE 0x12 12183 #define RXDISABLE 0x13 12184 #define RXCRCINIT 0x14 12185 #define RXREJECT 0x15 12186 #define SEARCHMP 0x16 12187 #define RXCRCEXCL 0x17 12188 #define RXCRCCALC 0x18 12189 #define CHRESET 0x21 12190 #define HUNT 0x31 12191 #define SWABORT 0x01 12192 #define FEICLEAR 0x02 12193 #define TXINTE BIT7 12194 #define RXINTE BIT6 12195 #define TXRDYE BIT1 12196 #define RXRDYE BIT0 12197 #define UDRN BIT7 12198 #define IDLE BIT6 12199 #define SYNCD BIT4 12200 #define FLGD BIT4 12201 #define CCTS BIT3 12202 #define CDCD BIT2 12203 #define BRKD BIT1 12204 #define ABTD BIT1 12205 #define GAPD BIT1 12206 #define BRKE BIT0 12207 #define IDLD BIT0 12208 #define EOM BIT7 12209 #define PMP BIT6 12210 #define SHRT BIT6 12211 #define PE BIT5 12212 #define ABT BIT5 12213 #define FRME BIT4 12214 #define RBIT BIT4 12215 #define OVRN BIT3 12216 #define CRCE BIT2 12217 #define WAKEUP_CHARS 256 12218 #if SYNCLINK_GENERIC_HDLC 12219 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12220 #endif 12221 #ifdef SANITY_CHECK 12222 #else 12223 #endif 12224 /* LDV_COMMENT_END_PREP */ 12225 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "get_icount" */ 12226 struct serial_icounter_struct * var_group10; 12227 /* LDV_COMMENT_BEGIN_PREP */ 12228 #if SYNCLINK_GENERIC_HDLC 12229 #endif 12230 #if SYNCLINK_GENERIC_HDLC 12231 #endif 12232 #if SYNCLINK_GENERIC_HDLC 12233 #endif 12234 #ifdef CMSPAR 12235 #endif 12236 #if SYNCLINK_GENERIC_HDLC 12237 #endif 12238 #if SYNCLINK_GENERIC_HDLC 12239 #endif 12240 #if 0 12241 #endif 12242 #if SYNCLINK_GENERIC_HDLC 12243 #endif 12244 #if SYNCLINK_GENERIC_HDLC 12245 #endif 12246 #define TESTFRAMESIZE 20 12247 #if SYNCLINK_GENERIC_HDLC 12248 #endif 12249 #define CALC_REGADDR() \ 12250 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12251 if (info->port_num > 1) \ 12252 RegAddr += 256; \ 12253 if ( info->port_num & 1) { \ 12254 if (Addr > 0x7f) \ 12255 RegAddr += 0x40; \ 12256 else if (Addr > 0x1f && Addr < 0x60) \ 12257 RegAddr += 0x20; \ 12258 } 12259 /* LDV_COMMENT_END_PREP */ 12260 12261 /** CALLBACK SECTION request_irq **/ 12262 /* content: static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)*/ 12263 /* LDV_COMMENT_BEGIN_PREP */ 12264 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12265 #if defined(__i386__) 12266 # define BREAKPOINT() asm(" int $3"); 12267 #else 12268 # define BREAKPOINT() { } 12269 #endif 12270 #define MAX_DEVICES 12 12271 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12272 #define SYNCLINK_GENERIC_HDLC 1 12273 #else 12274 #define SYNCLINK_GENERIC_HDLC 0 12275 #endif 12276 #define GET_USER(error,value,addr) error = get_user(value,addr) 12277 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12278 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12279 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12280 #define SCABUFSIZE 1024 12281 #define SCA_MEM_SIZE 0x40000 12282 #define SCA_BASE_SIZE 512 12283 #define SCA_REG_SIZE 16 12284 #define SCA_MAX_PORTS 4 12285 #define SCAMAXDESC 128 12286 #define BUFFERLISTSIZE 4096 12287 #define BH_RECEIVE 1 12288 #define BH_TRANSMIT 2 12289 #define BH_STATUS 4 12290 #define IO_PIN_SHUTDOWN_LIMIT 100 12291 #if SYNCLINK_GENERIC_HDLC 12292 #endif 12293 #define MGSL_MAGIC 0x5401 12294 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12295 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12296 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12297 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12298 #define LPR 0x00 12299 #define PABR0 0x02 12300 #define PABR1 0x03 12301 #define WCRL 0x04 12302 #define WCRM 0x05 12303 #define WCRH 0x06 12304 #define DPCR 0x08 12305 #define DMER 0x09 12306 #define ISR0 0x10 12307 #define ISR1 0x11 12308 #define ISR2 0x12 12309 #define IER0 0x14 12310 #define IER1 0x15 12311 #define IER2 0x16 12312 #define ITCR 0x18 12313 #define INTVR 0x1a 12314 #define IMVR 0x1c 12315 #define TRB 0x20 12316 #define TRBL 0x20 12317 #define TRBH 0x21 12318 #define SR0 0x22 12319 #define SR1 0x23 12320 #define SR2 0x24 12321 #define SR3 0x25 12322 #define FST 0x26 12323 #define IE0 0x28 12324 #define IE1 0x29 12325 #define IE2 0x2a 12326 #define FIE 0x2b 12327 #define CMD 0x2c 12328 #define MD0 0x2e 12329 #define MD1 0x2f 12330 #define MD2 0x30 12331 #define CTL 0x31 12332 #define SA0 0x32 12333 #define SA1 0x33 12334 #define IDL 0x34 12335 #define TMC 0x35 12336 #define RXS 0x36 12337 #define TXS 0x37 12338 #define TRC0 0x38 12339 #define TRC1 0x39 12340 #define RRC 0x3a 12341 #define CST0 0x3c 12342 #define CST1 0x3d 12343 #define TCNT 0x60 12344 #define TCNTL 0x60 12345 #define TCNTH 0x61 12346 #define TCONR 0x62 12347 #define TCONRL 0x62 12348 #define TCONRH 0x63 12349 #define TMCS 0x64 12350 #define TEPR 0x65 12351 #define DARL 0x80 12352 #define DARH 0x81 12353 #define DARB 0x82 12354 #define BAR 0x80 12355 #define BARL 0x80 12356 #define BARH 0x81 12357 #define BARB 0x82 12358 #define SAR 0x84 12359 #define SARL 0x84 12360 #define SARH 0x85 12361 #define SARB 0x86 12362 #define CPB 0x86 12363 #define CDA 0x88 12364 #define CDAL 0x88 12365 #define CDAH 0x89 12366 #define EDA 0x8a 12367 #define EDAL 0x8a 12368 #define EDAH 0x8b 12369 #define BFL 0x8c 12370 #define BFLL 0x8c 12371 #define BFLH 0x8d 12372 #define BCR 0x8e 12373 #define BCRL 0x8e 12374 #define BCRH 0x8f 12375 #define DSR 0x90 12376 #define DMR 0x91 12377 #define FCT 0x93 12378 #define DIR 0x94 12379 #define DCMD 0x95 12380 #define TIMER0 0x00 12381 #define TIMER1 0x08 12382 #define TIMER2 0x10 12383 #define TIMER3 0x18 12384 #define RXDMA 0x00 12385 #define TXDMA 0x20 12386 #define NOOP 0x00 12387 #define TXRESET 0x01 12388 #define TXENABLE 0x02 12389 #define TXDISABLE 0x03 12390 #define TXCRCINIT 0x04 12391 #define TXCRCEXCL 0x05 12392 #define TXEOM 0x06 12393 #define TXABORT 0x07 12394 #define MPON 0x08 12395 #define TXBUFCLR 0x09 12396 #define RXRESET 0x11 12397 #define RXENABLE 0x12 12398 #define RXDISABLE 0x13 12399 #define RXCRCINIT 0x14 12400 #define RXREJECT 0x15 12401 #define SEARCHMP 0x16 12402 #define RXCRCEXCL 0x17 12403 #define RXCRCCALC 0x18 12404 #define CHRESET 0x21 12405 #define HUNT 0x31 12406 #define SWABORT 0x01 12407 #define FEICLEAR 0x02 12408 #define TXINTE BIT7 12409 #define RXINTE BIT6 12410 #define TXRDYE BIT1 12411 #define RXRDYE BIT0 12412 #define UDRN BIT7 12413 #define IDLE BIT6 12414 #define SYNCD BIT4 12415 #define FLGD BIT4 12416 #define CCTS BIT3 12417 #define CDCD BIT2 12418 #define BRKD BIT1 12419 #define ABTD BIT1 12420 #define GAPD BIT1 12421 #define BRKE BIT0 12422 #define IDLD BIT0 12423 #define EOM BIT7 12424 #define PMP BIT6 12425 #define SHRT BIT6 12426 #define PE BIT5 12427 #define ABT BIT5 12428 #define FRME BIT4 12429 #define RBIT BIT4 12430 #define OVRN BIT3 12431 #define CRCE BIT2 12432 #define WAKEUP_CHARS 256 12433 #if SYNCLINK_GENERIC_HDLC 12434 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12435 #endif 12436 #ifdef SANITY_CHECK 12437 #else 12438 #endif 12439 #if SYNCLINK_GENERIC_HDLC 12440 #endif 12441 #if SYNCLINK_GENERIC_HDLC 12442 #endif 12443 #if SYNCLINK_GENERIC_HDLC 12444 #endif 12445 /* LDV_COMMENT_END_PREP */ 12446 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_interrupt" */ 12447 int var_synclinkmp_interrupt_52_p0; 12448 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "synclinkmp_interrupt" */ 12449 void * var_synclinkmp_interrupt_52_p1; 12450 /* LDV_COMMENT_BEGIN_PREP */ 12451 #ifdef CMSPAR 12452 #endif 12453 #if SYNCLINK_GENERIC_HDLC 12454 #endif 12455 #if SYNCLINK_GENERIC_HDLC 12456 #endif 12457 #if 0 12458 #endif 12459 #if SYNCLINK_GENERIC_HDLC 12460 #endif 12461 #if SYNCLINK_GENERIC_HDLC 12462 #endif 12463 #define TESTFRAMESIZE 20 12464 #if SYNCLINK_GENERIC_HDLC 12465 #endif 12466 #define CALC_REGADDR() \ 12467 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12468 if (info->port_num > 1) \ 12469 RegAddr += 256; \ 12470 if ( info->port_num & 1) { \ 12471 if (Addr > 0x7f) \ 12472 RegAddr += 0x40; \ 12473 else if (Addr > 0x1f && Addr < 0x60) \ 12474 RegAddr += 0x20; \ 12475 } 12476 /* LDV_COMMENT_END_PREP */ 12477 12478 12479 12480 12481 /* LDV_COMMENT_END_VARIABLE_DECLARATION_PART */ 12482 /* LDV_COMMENT_BEGIN_VARIABLE_INITIALIZING_PART */ 12483 /*============================= VARIABLE INITIALIZING PART =============================*/ 12484 LDV_IN_INTERRUPT=1; 12485 12486 12487 12488 12489 /* LDV_COMMENT_END_VARIABLE_INITIALIZING_PART */ 12490 /* LDV_COMMENT_BEGIN_FUNCTION_CALL_SECTION */ 12491 /*============================= FUNCTION CALL SECTION =============================*/ 12492 /* LDV_COMMENT_FUNCTION_CALL Initialize LDV model. */ 12493 ldv_initialize(); 12494 12495 /** INIT: init_type: ST_MODULE_INIT **/ 12496 /* content: static int __init synclinkmp_init(void)*/ 12497 /* LDV_COMMENT_BEGIN_PREP */ 12498 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12499 #if defined(__i386__) 12500 # define BREAKPOINT() asm(" int $3"); 12501 #else 12502 # define BREAKPOINT() { } 12503 #endif 12504 #define MAX_DEVICES 12 12505 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12506 #define SYNCLINK_GENERIC_HDLC 1 12507 #else 12508 #define SYNCLINK_GENERIC_HDLC 0 12509 #endif 12510 #define GET_USER(error,value,addr) error = get_user(value,addr) 12511 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12512 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12513 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12514 #define SCABUFSIZE 1024 12515 #define SCA_MEM_SIZE 0x40000 12516 #define SCA_BASE_SIZE 512 12517 #define SCA_REG_SIZE 16 12518 #define SCA_MAX_PORTS 4 12519 #define SCAMAXDESC 128 12520 #define BUFFERLISTSIZE 4096 12521 #define BH_RECEIVE 1 12522 #define BH_TRANSMIT 2 12523 #define BH_STATUS 4 12524 #define IO_PIN_SHUTDOWN_LIMIT 100 12525 #if SYNCLINK_GENERIC_HDLC 12526 #endif 12527 #define MGSL_MAGIC 0x5401 12528 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12529 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12530 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12531 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12532 #define LPR 0x00 12533 #define PABR0 0x02 12534 #define PABR1 0x03 12535 #define WCRL 0x04 12536 #define WCRM 0x05 12537 #define WCRH 0x06 12538 #define DPCR 0x08 12539 #define DMER 0x09 12540 #define ISR0 0x10 12541 #define ISR1 0x11 12542 #define ISR2 0x12 12543 #define IER0 0x14 12544 #define IER1 0x15 12545 #define IER2 0x16 12546 #define ITCR 0x18 12547 #define INTVR 0x1a 12548 #define IMVR 0x1c 12549 #define TRB 0x20 12550 #define TRBL 0x20 12551 #define TRBH 0x21 12552 #define SR0 0x22 12553 #define SR1 0x23 12554 #define SR2 0x24 12555 #define SR3 0x25 12556 #define FST 0x26 12557 #define IE0 0x28 12558 #define IE1 0x29 12559 #define IE2 0x2a 12560 #define FIE 0x2b 12561 #define CMD 0x2c 12562 #define MD0 0x2e 12563 #define MD1 0x2f 12564 #define MD2 0x30 12565 #define CTL 0x31 12566 #define SA0 0x32 12567 #define SA1 0x33 12568 #define IDL 0x34 12569 #define TMC 0x35 12570 #define RXS 0x36 12571 #define TXS 0x37 12572 #define TRC0 0x38 12573 #define TRC1 0x39 12574 #define RRC 0x3a 12575 #define CST0 0x3c 12576 #define CST1 0x3d 12577 #define TCNT 0x60 12578 #define TCNTL 0x60 12579 #define TCNTH 0x61 12580 #define TCONR 0x62 12581 #define TCONRL 0x62 12582 #define TCONRH 0x63 12583 #define TMCS 0x64 12584 #define TEPR 0x65 12585 #define DARL 0x80 12586 #define DARH 0x81 12587 #define DARB 0x82 12588 #define BAR 0x80 12589 #define BARL 0x80 12590 #define BARH 0x81 12591 #define BARB 0x82 12592 #define SAR 0x84 12593 #define SARL 0x84 12594 #define SARH 0x85 12595 #define SARB 0x86 12596 #define CPB 0x86 12597 #define CDA 0x88 12598 #define CDAL 0x88 12599 #define CDAH 0x89 12600 #define EDA 0x8a 12601 #define EDAL 0x8a 12602 #define EDAH 0x8b 12603 #define BFL 0x8c 12604 #define BFLL 0x8c 12605 #define BFLH 0x8d 12606 #define BCR 0x8e 12607 #define BCRL 0x8e 12608 #define BCRH 0x8f 12609 #define DSR 0x90 12610 #define DMR 0x91 12611 #define FCT 0x93 12612 #define DIR 0x94 12613 #define DCMD 0x95 12614 #define TIMER0 0x00 12615 #define TIMER1 0x08 12616 #define TIMER2 0x10 12617 #define TIMER3 0x18 12618 #define RXDMA 0x00 12619 #define TXDMA 0x20 12620 #define NOOP 0x00 12621 #define TXRESET 0x01 12622 #define TXENABLE 0x02 12623 #define TXDISABLE 0x03 12624 #define TXCRCINIT 0x04 12625 #define TXCRCEXCL 0x05 12626 #define TXEOM 0x06 12627 #define TXABORT 0x07 12628 #define MPON 0x08 12629 #define TXBUFCLR 0x09 12630 #define RXRESET 0x11 12631 #define RXENABLE 0x12 12632 #define RXDISABLE 0x13 12633 #define RXCRCINIT 0x14 12634 #define RXREJECT 0x15 12635 #define SEARCHMP 0x16 12636 #define RXCRCEXCL 0x17 12637 #define RXCRCCALC 0x18 12638 #define CHRESET 0x21 12639 #define HUNT 0x31 12640 #define SWABORT 0x01 12641 #define FEICLEAR 0x02 12642 #define TXINTE BIT7 12643 #define RXINTE BIT6 12644 #define TXRDYE BIT1 12645 #define RXRDYE BIT0 12646 #define UDRN BIT7 12647 #define IDLE BIT6 12648 #define SYNCD BIT4 12649 #define FLGD BIT4 12650 #define CCTS BIT3 12651 #define CDCD BIT2 12652 #define BRKD BIT1 12653 #define ABTD BIT1 12654 #define GAPD BIT1 12655 #define BRKE BIT0 12656 #define IDLD BIT0 12657 #define EOM BIT7 12658 #define PMP BIT6 12659 #define SHRT BIT6 12660 #define PE BIT5 12661 #define ABT BIT5 12662 #define FRME BIT4 12663 #define RBIT BIT4 12664 #define OVRN BIT3 12665 #define CRCE BIT2 12666 #define WAKEUP_CHARS 256 12667 #if SYNCLINK_GENERIC_HDLC 12668 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12669 #endif 12670 #ifdef SANITY_CHECK 12671 #else 12672 #endif 12673 #if SYNCLINK_GENERIC_HDLC 12674 #endif 12675 #if SYNCLINK_GENERIC_HDLC 12676 #endif 12677 #if SYNCLINK_GENERIC_HDLC 12678 #endif 12679 #ifdef CMSPAR 12680 #endif 12681 #if SYNCLINK_GENERIC_HDLC 12682 #endif 12683 #if SYNCLINK_GENERIC_HDLC 12684 #endif 12685 /* LDV_COMMENT_END_PREP */ 12686 /* LDV_COMMENT_FUNCTION_CALL Kernel calls driver init function after driver loading to kernel. This function declared as "MODULE_INIT(function name)". */ 12687 ldv_handler_precall(); 12688 if(synclinkmp_init()) 12689 goto ldv_final; 12690 /* LDV_COMMENT_BEGIN_PREP */ 12691 #if 0 12692 #endif 12693 #if SYNCLINK_GENERIC_HDLC 12694 #endif 12695 #if SYNCLINK_GENERIC_HDLC 12696 #endif 12697 #define TESTFRAMESIZE 20 12698 #if SYNCLINK_GENERIC_HDLC 12699 #endif 12700 #define CALC_REGADDR() \ 12701 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12702 if (info->port_num > 1) \ 12703 RegAddr += 256; \ 12704 if ( info->port_num & 1) { \ 12705 if (Addr > 0x7f) \ 12706 RegAddr += 0x40; \ 12707 else if (Addr > 0x1f && Addr < 0x60) \ 12708 RegAddr += 0x20; \ 12709 } 12710 /* LDV_COMMENT_END_PREP */ 12711 int ldv_s_synclinkmp_pci_driver_pci_driver = 0; 12712 12713 int ldv_s_synclinkmp_proc_fops_file_operations = 0; 12714 12715 int ldv_s_hdlcdev_ops_net_device_ops = 0; 12716 12717 12718 12719 12720 int ldv_s_ops_tty_operations = 0; 12721 12722 12723 12724 12725 12726 while( nondet_int() 12727 || !(ldv_s_synclinkmp_pci_driver_pci_driver == 0) 12728 || !(ldv_s_synclinkmp_proc_fops_file_operations == 0) 12729 || !(ldv_s_hdlcdev_ops_net_device_ops == 0) 12730 || !(ldv_s_ops_tty_operations == 0) 12731 ) { 12732 12733 switch(nondet_int()) { 12734 12735 case 0: { 12736 12737 /** STRUCT: struct type: pci_driver, struct name: synclinkmp_pci_driver **/ 12738 if(ldv_s_synclinkmp_pci_driver_pci_driver==0) { 12739 12740 /* content: static int synclinkmp_init_one (struct pci_dev *dev, const struct pci_device_id *ent)*/ 12741 /* LDV_COMMENT_BEGIN_PREP */ 12742 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12743 #if defined(__i386__) 12744 # define BREAKPOINT() asm(" int $3"); 12745 #else 12746 # define BREAKPOINT() { } 12747 #endif 12748 #define MAX_DEVICES 12 12749 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12750 #define SYNCLINK_GENERIC_HDLC 1 12751 #else 12752 #define SYNCLINK_GENERIC_HDLC 0 12753 #endif 12754 #define GET_USER(error,value,addr) error = get_user(value,addr) 12755 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12756 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12757 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12758 #define SCABUFSIZE 1024 12759 #define SCA_MEM_SIZE 0x40000 12760 #define SCA_BASE_SIZE 512 12761 #define SCA_REG_SIZE 16 12762 #define SCA_MAX_PORTS 4 12763 #define SCAMAXDESC 128 12764 #define BUFFERLISTSIZE 4096 12765 #define BH_RECEIVE 1 12766 #define BH_TRANSMIT 2 12767 #define BH_STATUS 4 12768 #define IO_PIN_SHUTDOWN_LIMIT 100 12769 #if SYNCLINK_GENERIC_HDLC 12770 #endif 12771 #define MGSL_MAGIC 0x5401 12772 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 12773 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 12774 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 12775 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 12776 #define LPR 0x00 12777 #define PABR0 0x02 12778 #define PABR1 0x03 12779 #define WCRL 0x04 12780 #define WCRM 0x05 12781 #define WCRH 0x06 12782 #define DPCR 0x08 12783 #define DMER 0x09 12784 #define ISR0 0x10 12785 #define ISR1 0x11 12786 #define ISR2 0x12 12787 #define IER0 0x14 12788 #define IER1 0x15 12789 #define IER2 0x16 12790 #define ITCR 0x18 12791 #define INTVR 0x1a 12792 #define IMVR 0x1c 12793 #define TRB 0x20 12794 #define TRBL 0x20 12795 #define TRBH 0x21 12796 #define SR0 0x22 12797 #define SR1 0x23 12798 #define SR2 0x24 12799 #define SR3 0x25 12800 #define FST 0x26 12801 #define IE0 0x28 12802 #define IE1 0x29 12803 #define IE2 0x2a 12804 #define FIE 0x2b 12805 #define CMD 0x2c 12806 #define MD0 0x2e 12807 #define MD1 0x2f 12808 #define MD2 0x30 12809 #define CTL 0x31 12810 #define SA0 0x32 12811 #define SA1 0x33 12812 #define IDL 0x34 12813 #define TMC 0x35 12814 #define RXS 0x36 12815 #define TXS 0x37 12816 #define TRC0 0x38 12817 #define TRC1 0x39 12818 #define RRC 0x3a 12819 #define CST0 0x3c 12820 #define CST1 0x3d 12821 #define TCNT 0x60 12822 #define TCNTL 0x60 12823 #define TCNTH 0x61 12824 #define TCONR 0x62 12825 #define TCONRL 0x62 12826 #define TCONRH 0x63 12827 #define TMCS 0x64 12828 #define TEPR 0x65 12829 #define DARL 0x80 12830 #define DARH 0x81 12831 #define DARB 0x82 12832 #define BAR 0x80 12833 #define BARL 0x80 12834 #define BARH 0x81 12835 #define BARB 0x82 12836 #define SAR 0x84 12837 #define SARL 0x84 12838 #define SARH 0x85 12839 #define SARB 0x86 12840 #define CPB 0x86 12841 #define CDA 0x88 12842 #define CDAL 0x88 12843 #define CDAH 0x89 12844 #define EDA 0x8a 12845 #define EDAL 0x8a 12846 #define EDAH 0x8b 12847 #define BFL 0x8c 12848 #define BFLL 0x8c 12849 #define BFLH 0x8d 12850 #define BCR 0x8e 12851 #define BCRL 0x8e 12852 #define BCRH 0x8f 12853 #define DSR 0x90 12854 #define DMR 0x91 12855 #define FCT 0x93 12856 #define DIR 0x94 12857 #define DCMD 0x95 12858 #define TIMER0 0x00 12859 #define TIMER1 0x08 12860 #define TIMER2 0x10 12861 #define TIMER3 0x18 12862 #define RXDMA 0x00 12863 #define TXDMA 0x20 12864 #define NOOP 0x00 12865 #define TXRESET 0x01 12866 #define TXENABLE 0x02 12867 #define TXDISABLE 0x03 12868 #define TXCRCINIT 0x04 12869 #define TXCRCEXCL 0x05 12870 #define TXEOM 0x06 12871 #define TXABORT 0x07 12872 #define MPON 0x08 12873 #define TXBUFCLR 0x09 12874 #define RXRESET 0x11 12875 #define RXENABLE 0x12 12876 #define RXDISABLE 0x13 12877 #define RXCRCINIT 0x14 12878 #define RXREJECT 0x15 12879 #define SEARCHMP 0x16 12880 #define RXCRCEXCL 0x17 12881 #define RXCRCCALC 0x18 12882 #define CHRESET 0x21 12883 #define HUNT 0x31 12884 #define SWABORT 0x01 12885 #define FEICLEAR 0x02 12886 #define TXINTE BIT7 12887 #define RXINTE BIT6 12888 #define TXRDYE BIT1 12889 #define RXRDYE BIT0 12890 #define UDRN BIT7 12891 #define IDLE BIT6 12892 #define SYNCD BIT4 12893 #define FLGD BIT4 12894 #define CCTS BIT3 12895 #define CDCD BIT2 12896 #define BRKD BIT1 12897 #define ABTD BIT1 12898 #define GAPD BIT1 12899 #define BRKE BIT0 12900 #define IDLD BIT0 12901 #define EOM BIT7 12902 #define PMP BIT6 12903 #define SHRT BIT6 12904 #define PE BIT5 12905 #define ABT BIT5 12906 #define FRME BIT4 12907 #define RBIT BIT4 12908 #define OVRN BIT3 12909 #define CRCE BIT2 12910 #define WAKEUP_CHARS 256 12911 #if SYNCLINK_GENERIC_HDLC 12912 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 12913 #endif 12914 #ifdef SANITY_CHECK 12915 #else 12916 #endif 12917 #if SYNCLINK_GENERIC_HDLC 12918 #endif 12919 #if SYNCLINK_GENERIC_HDLC 12920 #endif 12921 #if SYNCLINK_GENERIC_HDLC 12922 #endif 12923 #ifdef CMSPAR 12924 #endif 12925 #if SYNCLINK_GENERIC_HDLC 12926 #endif 12927 #if SYNCLINK_GENERIC_HDLC 12928 #endif 12929 #if 0 12930 #endif 12931 #if SYNCLINK_GENERIC_HDLC 12932 #endif 12933 #if SYNCLINK_GENERIC_HDLC 12934 #endif 12935 #define TESTFRAMESIZE 20 12936 #if SYNCLINK_GENERIC_HDLC 12937 #endif 12938 #define CALC_REGADDR() \ 12939 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 12940 if (info->port_num > 1) \ 12941 RegAddr += 256; \ 12942 if ( info->port_num & 1) { \ 12943 if (Addr > 0x7f) \ 12944 RegAddr += 0x40; \ 12945 else if (Addr > 0x1f && Addr < 0x60) \ 12946 RegAddr += 0x20; \ 12947 } 12948 /* LDV_COMMENT_END_PREP */ 12949 /* LDV_COMMENT_FUNCTION_CALL Function from field "probe" from driver structure with callbacks "synclinkmp_pci_driver". Standart function test for correct return result. */ 12950 res_synclinkmp_init_one_121 = synclinkmp_init_one( var_group1, var_synclinkmp_init_one_121_p1); 12951 ldv_check_return_value(res_synclinkmp_init_one_121); 12952 ldv_check_return_value_probe(res_synclinkmp_init_one_121); 12953 if(res_synclinkmp_init_one_121) 12954 goto ldv_module_exit; 12955 ldv_s_synclinkmp_pci_driver_pci_driver++; 12956 12957 } 12958 12959 } 12960 12961 break; 12962 case 1: { 12963 12964 /** STRUCT: struct type: pci_driver, struct name: synclinkmp_pci_driver **/ 12965 if(ldv_s_synclinkmp_pci_driver_pci_driver==1) { 12966 12967 /* content: static void synclinkmp_remove_one (struct pci_dev *dev)*/ 12968 /* LDV_COMMENT_BEGIN_PREP */ 12969 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 12970 #if defined(__i386__) 12971 # define BREAKPOINT() asm(" int $3"); 12972 #else 12973 # define BREAKPOINT() { } 12974 #endif 12975 #define MAX_DEVICES 12 12976 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 12977 #define SYNCLINK_GENERIC_HDLC 1 12978 #else 12979 #define SYNCLINK_GENERIC_HDLC 0 12980 #endif 12981 #define GET_USER(error,value,addr) error = get_user(value,addr) 12982 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 12983 #define PUT_USER(error,value,addr) error = put_user(value,addr) 12984 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 12985 #define SCABUFSIZE 1024 12986 #define SCA_MEM_SIZE 0x40000 12987 #define SCA_BASE_SIZE 512 12988 #define SCA_REG_SIZE 16 12989 #define SCA_MAX_PORTS 4 12990 #define SCAMAXDESC 128 12991 #define BUFFERLISTSIZE 4096 12992 #define BH_RECEIVE 1 12993 #define BH_TRANSMIT 2 12994 #define BH_STATUS 4 12995 #define IO_PIN_SHUTDOWN_LIMIT 100 12996 #if SYNCLINK_GENERIC_HDLC 12997 #endif 12998 #define MGSL_MAGIC 0x5401 12999 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13000 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13001 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13002 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13003 #define LPR 0x00 13004 #define PABR0 0x02 13005 #define PABR1 0x03 13006 #define WCRL 0x04 13007 #define WCRM 0x05 13008 #define WCRH 0x06 13009 #define DPCR 0x08 13010 #define DMER 0x09 13011 #define ISR0 0x10 13012 #define ISR1 0x11 13013 #define ISR2 0x12 13014 #define IER0 0x14 13015 #define IER1 0x15 13016 #define IER2 0x16 13017 #define ITCR 0x18 13018 #define INTVR 0x1a 13019 #define IMVR 0x1c 13020 #define TRB 0x20 13021 #define TRBL 0x20 13022 #define TRBH 0x21 13023 #define SR0 0x22 13024 #define SR1 0x23 13025 #define SR2 0x24 13026 #define SR3 0x25 13027 #define FST 0x26 13028 #define IE0 0x28 13029 #define IE1 0x29 13030 #define IE2 0x2a 13031 #define FIE 0x2b 13032 #define CMD 0x2c 13033 #define MD0 0x2e 13034 #define MD1 0x2f 13035 #define MD2 0x30 13036 #define CTL 0x31 13037 #define SA0 0x32 13038 #define SA1 0x33 13039 #define IDL 0x34 13040 #define TMC 0x35 13041 #define RXS 0x36 13042 #define TXS 0x37 13043 #define TRC0 0x38 13044 #define TRC1 0x39 13045 #define RRC 0x3a 13046 #define CST0 0x3c 13047 #define CST1 0x3d 13048 #define TCNT 0x60 13049 #define TCNTL 0x60 13050 #define TCNTH 0x61 13051 #define TCONR 0x62 13052 #define TCONRL 0x62 13053 #define TCONRH 0x63 13054 #define TMCS 0x64 13055 #define TEPR 0x65 13056 #define DARL 0x80 13057 #define DARH 0x81 13058 #define DARB 0x82 13059 #define BAR 0x80 13060 #define BARL 0x80 13061 #define BARH 0x81 13062 #define BARB 0x82 13063 #define SAR 0x84 13064 #define SARL 0x84 13065 #define SARH 0x85 13066 #define SARB 0x86 13067 #define CPB 0x86 13068 #define CDA 0x88 13069 #define CDAL 0x88 13070 #define CDAH 0x89 13071 #define EDA 0x8a 13072 #define EDAL 0x8a 13073 #define EDAH 0x8b 13074 #define BFL 0x8c 13075 #define BFLL 0x8c 13076 #define BFLH 0x8d 13077 #define BCR 0x8e 13078 #define BCRL 0x8e 13079 #define BCRH 0x8f 13080 #define DSR 0x90 13081 #define DMR 0x91 13082 #define FCT 0x93 13083 #define DIR 0x94 13084 #define DCMD 0x95 13085 #define TIMER0 0x00 13086 #define TIMER1 0x08 13087 #define TIMER2 0x10 13088 #define TIMER3 0x18 13089 #define RXDMA 0x00 13090 #define TXDMA 0x20 13091 #define NOOP 0x00 13092 #define TXRESET 0x01 13093 #define TXENABLE 0x02 13094 #define TXDISABLE 0x03 13095 #define TXCRCINIT 0x04 13096 #define TXCRCEXCL 0x05 13097 #define TXEOM 0x06 13098 #define TXABORT 0x07 13099 #define MPON 0x08 13100 #define TXBUFCLR 0x09 13101 #define RXRESET 0x11 13102 #define RXENABLE 0x12 13103 #define RXDISABLE 0x13 13104 #define RXCRCINIT 0x14 13105 #define RXREJECT 0x15 13106 #define SEARCHMP 0x16 13107 #define RXCRCEXCL 0x17 13108 #define RXCRCCALC 0x18 13109 #define CHRESET 0x21 13110 #define HUNT 0x31 13111 #define SWABORT 0x01 13112 #define FEICLEAR 0x02 13113 #define TXINTE BIT7 13114 #define RXINTE BIT6 13115 #define TXRDYE BIT1 13116 #define RXRDYE BIT0 13117 #define UDRN BIT7 13118 #define IDLE BIT6 13119 #define SYNCD BIT4 13120 #define FLGD BIT4 13121 #define CCTS BIT3 13122 #define CDCD BIT2 13123 #define BRKD BIT1 13124 #define ABTD BIT1 13125 #define GAPD BIT1 13126 #define BRKE BIT0 13127 #define IDLD BIT0 13128 #define EOM BIT7 13129 #define PMP BIT6 13130 #define SHRT BIT6 13131 #define PE BIT5 13132 #define ABT BIT5 13133 #define FRME BIT4 13134 #define RBIT BIT4 13135 #define OVRN BIT3 13136 #define CRCE BIT2 13137 #define WAKEUP_CHARS 256 13138 #if SYNCLINK_GENERIC_HDLC 13139 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 13140 #endif 13141 #ifdef SANITY_CHECK 13142 #else 13143 #endif 13144 #if SYNCLINK_GENERIC_HDLC 13145 #endif 13146 #if SYNCLINK_GENERIC_HDLC 13147 #endif 13148 #if SYNCLINK_GENERIC_HDLC 13149 #endif 13150 #ifdef CMSPAR 13151 #endif 13152 #if SYNCLINK_GENERIC_HDLC 13153 #endif 13154 #if SYNCLINK_GENERIC_HDLC 13155 #endif 13156 #if 0 13157 #endif 13158 #if SYNCLINK_GENERIC_HDLC 13159 #endif 13160 #if SYNCLINK_GENERIC_HDLC 13161 #endif 13162 #define TESTFRAMESIZE 20 13163 #if SYNCLINK_GENERIC_HDLC 13164 #endif 13165 #define CALC_REGADDR() \ 13166 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 13167 if (info->port_num > 1) \ 13168 RegAddr += 256; \ 13169 if ( info->port_num & 1) { \ 13170 if (Addr > 0x7f) \ 13171 RegAddr += 0x40; \ 13172 else if (Addr > 0x1f && Addr < 0x60) \ 13173 RegAddr += 0x20; \ 13174 } 13175 /* LDV_COMMENT_END_PREP */ 13176 /* LDV_COMMENT_FUNCTION_CALL Function from field "remove" from driver structure with callbacks "synclinkmp_pci_driver" */ 13177 ldv_handler_precall(); 13178 synclinkmp_remove_one( var_group1); 13179 ldv_s_synclinkmp_pci_driver_pci_driver=0; 13180 13181 } 13182 13183 } 13184 13185 break; 13186 case 2: { 13187 13188 /** STRUCT: struct type: file_operations, struct name: synclinkmp_proc_fops **/ 13189 if(ldv_s_synclinkmp_proc_fops_file_operations==0) { 13190 13191 /* content: static int synclinkmp_proc_open(struct inode *inode, struct file *file)*/ 13192 /* LDV_COMMENT_BEGIN_PREP */ 13193 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 13194 #if defined(__i386__) 13195 # define BREAKPOINT() asm(" int $3"); 13196 #else 13197 # define BREAKPOINT() { } 13198 #endif 13199 #define MAX_DEVICES 12 13200 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 13201 #define SYNCLINK_GENERIC_HDLC 1 13202 #else 13203 #define SYNCLINK_GENERIC_HDLC 0 13204 #endif 13205 #define GET_USER(error,value,addr) error = get_user(value,addr) 13206 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 13207 #define PUT_USER(error,value,addr) error = put_user(value,addr) 13208 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 13209 #define SCABUFSIZE 1024 13210 #define SCA_MEM_SIZE 0x40000 13211 #define SCA_BASE_SIZE 512 13212 #define SCA_REG_SIZE 16 13213 #define SCA_MAX_PORTS 4 13214 #define SCAMAXDESC 128 13215 #define BUFFERLISTSIZE 4096 13216 #define BH_RECEIVE 1 13217 #define BH_TRANSMIT 2 13218 #define BH_STATUS 4 13219 #define IO_PIN_SHUTDOWN_LIMIT 100 13220 #if SYNCLINK_GENERIC_HDLC 13221 #endif 13222 #define MGSL_MAGIC 0x5401 13223 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13224 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13225 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13226 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13227 #define LPR 0x00 13228 #define PABR0 0x02 13229 #define PABR1 0x03 13230 #define WCRL 0x04 13231 #define WCRM 0x05 13232 #define WCRH 0x06 13233 #define DPCR 0x08 13234 #define DMER 0x09 13235 #define ISR0 0x10 13236 #define ISR1 0x11 13237 #define ISR2 0x12 13238 #define IER0 0x14 13239 #define IER1 0x15 13240 #define IER2 0x16 13241 #define ITCR 0x18 13242 #define INTVR 0x1a 13243 #define IMVR 0x1c 13244 #define TRB 0x20 13245 #define TRBL 0x20 13246 #define TRBH 0x21 13247 #define SR0 0x22 13248 #define SR1 0x23 13249 #define SR2 0x24 13250 #define SR3 0x25 13251 #define FST 0x26 13252 #define IE0 0x28 13253 #define IE1 0x29 13254 #define IE2 0x2a 13255 #define FIE 0x2b 13256 #define CMD 0x2c 13257 #define MD0 0x2e 13258 #define MD1 0x2f 13259 #define MD2 0x30 13260 #define CTL 0x31 13261 #define SA0 0x32 13262 #define SA1 0x33 13263 #define IDL 0x34 13264 #define TMC 0x35 13265 #define RXS 0x36 13266 #define TXS 0x37 13267 #define TRC0 0x38 13268 #define TRC1 0x39 13269 #define RRC 0x3a 13270 #define CST0 0x3c 13271 #define CST1 0x3d 13272 #define TCNT 0x60 13273 #define TCNTL 0x60 13274 #define TCNTH 0x61 13275 #define TCONR 0x62 13276 #define TCONRL 0x62 13277 #define TCONRH 0x63 13278 #define TMCS 0x64 13279 #define TEPR 0x65 13280 #define DARL 0x80 13281 #define DARH 0x81 13282 #define DARB 0x82 13283 #define BAR 0x80 13284 #define BARL 0x80 13285 #define BARH 0x81 13286 #define BARB 0x82 13287 #define SAR 0x84 13288 #define SARL 0x84 13289 #define SARH 0x85 13290 #define SARB 0x86 13291 #define CPB 0x86 13292 #define CDA 0x88 13293 #define CDAL 0x88 13294 #define CDAH 0x89 13295 #define EDA 0x8a 13296 #define EDAL 0x8a 13297 #define EDAH 0x8b 13298 #define BFL 0x8c 13299 #define BFLL 0x8c 13300 #define BFLH 0x8d 13301 #define BCR 0x8e 13302 #define BCRL 0x8e 13303 #define BCRH 0x8f 13304 #define DSR 0x90 13305 #define DMR 0x91 13306 #define FCT 0x93 13307 #define DIR 0x94 13308 #define DCMD 0x95 13309 #define TIMER0 0x00 13310 #define TIMER1 0x08 13311 #define TIMER2 0x10 13312 #define TIMER3 0x18 13313 #define RXDMA 0x00 13314 #define TXDMA 0x20 13315 #define NOOP 0x00 13316 #define TXRESET 0x01 13317 #define TXENABLE 0x02 13318 #define TXDISABLE 0x03 13319 #define TXCRCINIT 0x04 13320 #define TXCRCEXCL 0x05 13321 #define TXEOM 0x06 13322 #define TXABORT 0x07 13323 #define MPON 0x08 13324 #define TXBUFCLR 0x09 13325 #define RXRESET 0x11 13326 #define RXENABLE 0x12 13327 #define RXDISABLE 0x13 13328 #define RXCRCINIT 0x14 13329 #define RXREJECT 0x15 13330 #define SEARCHMP 0x16 13331 #define RXCRCEXCL 0x17 13332 #define RXCRCCALC 0x18 13333 #define CHRESET 0x21 13334 #define HUNT 0x31 13335 #define SWABORT 0x01 13336 #define FEICLEAR 0x02 13337 #define TXINTE BIT7 13338 #define RXINTE BIT6 13339 #define TXRDYE BIT1 13340 #define RXRDYE BIT0 13341 #define UDRN BIT7 13342 #define IDLE BIT6 13343 #define SYNCD BIT4 13344 #define FLGD BIT4 13345 #define CCTS BIT3 13346 #define CDCD BIT2 13347 #define BRKD BIT1 13348 #define ABTD BIT1 13349 #define GAPD BIT1 13350 #define BRKE BIT0 13351 #define IDLD BIT0 13352 #define EOM BIT7 13353 #define PMP BIT6 13354 #define SHRT BIT6 13355 #define PE BIT5 13356 #define ABT BIT5 13357 #define FRME BIT4 13358 #define RBIT BIT4 13359 #define OVRN BIT3 13360 #define CRCE BIT2 13361 #define WAKEUP_CHARS 256 13362 #if SYNCLINK_GENERIC_HDLC 13363 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 13364 #endif 13365 #ifdef SANITY_CHECK 13366 #else 13367 #endif 13368 /* LDV_COMMENT_END_PREP */ 13369 /* LDV_COMMENT_FUNCTION_CALL Function from field "open" from driver structure with callbacks "synclinkmp_proc_fops". Standart function test for correct return result. */ 13370 ldv_handler_precall(); 13371 res_synclinkmp_proc_open_21 = synclinkmp_proc_open( var_group2, var_group3); 13372 ldv_check_return_value(res_synclinkmp_proc_open_21); 13373 if(res_synclinkmp_proc_open_21) 13374 goto ldv_module_exit; 13375 /* LDV_COMMENT_BEGIN_PREP */ 13376 #if SYNCLINK_GENERIC_HDLC 13377 #endif 13378 #if SYNCLINK_GENERIC_HDLC 13379 #endif 13380 #if SYNCLINK_GENERIC_HDLC 13381 #endif 13382 #ifdef CMSPAR 13383 #endif 13384 #if SYNCLINK_GENERIC_HDLC 13385 #endif 13386 #if SYNCLINK_GENERIC_HDLC 13387 #endif 13388 #if 0 13389 #endif 13390 #if SYNCLINK_GENERIC_HDLC 13391 #endif 13392 #if SYNCLINK_GENERIC_HDLC 13393 #endif 13394 #define TESTFRAMESIZE 20 13395 #if SYNCLINK_GENERIC_HDLC 13396 #endif 13397 #define CALC_REGADDR() \ 13398 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 13399 if (info->port_num > 1) \ 13400 RegAddr += 256; \ 13401 if ( info->port_num & 1) { \ 13402 if (Addr > 0x7f) \ 13403 RegAddr += 0x40; \ 13404 else if (Addr > 0x1f && Addr < 0x60) \ 13405 RegAddr += 0x20; \ 13406 } 13407 /* LDV_COMMENT_END_PREP */ 13408 ldv_s_synclinkmp_proc_fops_file_operations=0; 13409 13410 } 13411 13412 } 13413 13414 break; 13415 case 3: { 13416 13417 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 13418 if(ldv_s_hdlcdev_ops_net_device_ops==0) { 13419 13420 /* content: static int hdlcdev_open(struct net_device *dev)*/ 13421 /* LDV_COMMENT_BEGIN_PREP */ 13422 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 13423 #if defined(__i386__) 13424 # define BREAKPOINT() asm(" int $3"); 13425 #else 13426 # define BREAKPOINT() { } 13427 #endif 13428 #define MAX_DEVICES 12 13429 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 13430 #define SYNCLINK_GENERIC_HDLC 1 13431 #else 13432 #define SYNCLINK_GENERIC_HDLC 0 13433 #endif 13434 #define GET_USER(error,value,addr) error = get_user(value,addr) 13435 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 13436 #define PUT_USER(error,value,addr) error = put_user(value,addr) 13437 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 13438 #define SCABUFSIZE 1024 13439 #define SCA_MEM_SIZE 0x40000 13440 #define SCA_BASE_SIZE 512 13441 #define SCA_REG_SIZE 16 13442 #define SCA_MAX_PORTS 4 13443 #define SCAMAXDESC 128 13444 #define BUFFERLISTSIZE 4096 13445 #define BH_RECEIVE 1 13446 #define BH_TRANSMIT 2 13447 #define BH_STATUS 4 13448 #define IO_PIN_SHUTDOWN_LIMIT 100 13449 #if SYNCLINK_GENERIC_HDLC 13450 #endif 13451 #define MGSL_MAGIC 0x5401 13452 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13453 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13454 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13455 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13456 #define LPR 0x00 13457 #define PABR0 0x02 13458 #define PABR1 0x03 13459 #define WCRL 0x04 13460 #define WCRM 0x05 13461 #define WCRH 0x06 13462 #define DPCR 0x08 13463 #define DMER 0x09 13464 #define ISR0 0x10 13465 #define ISR1 0x11 13466 #define ISR2 0x12 13467 #define IER0 0x14 13468 #define IER1 0x15 13469 #define IER2 0x16 13470 #define ITCR 0x18 13471 #define INTVR 0x1a 13472 #define IMVR 0x1c 13473 #define TRB 0x20 13474 #define TRBL 0x20 13475 #define TRBH 0x21 13476 #define SR0 0x22 13477 #define SR1 0x23 13478 #define SR2 0x24 13479 #define SR3 0x25 13480 #define FST 0x26 13481 #define IE0 0x28 13482 #define IE1 0x29 13483 #define IE2 0x2a 13484 #define FIE 0x2b 13485 #define CMD 0x2c 13486 #define MD0 0x2e 13487 #define MD1 0x2f 13488 #define MD2 0x30 13489 #define CTL 0x31 13490 #define SA0 0x32 13491 #define SA1 0x33 13492 #define IDL 0x34 13493 #define TMC 0x35 13494 #define RXS 0x36 13495 #define TXS 0x37 13496 #define TRC0 0x38 13497 #define TRC1 0x39 13498 #define RRC 0x3a 13499 #define CST0 0x3c 13500 #define CST1 0x3d 13501 #define TCNT 0x60 13502 #define TCNTL 0x60 13503 #define TCNTH 0x61 13504 #define TCONR 0x62 13505 #define TCONRL 0x62 13506 #define TCONRH 0x63 13507 #define TMCS 0x64 13508 #define TEPR 0x65 13509 #define DARL 0x80 13510 #define DARH 0x81 13511 #define DARB 0x82 13512 #define BAR 0x80 13513 #define BARL 0x80 13514 #define BARH 0x81 13515 #define BARB 0x82 13516 #define SAR 0x84 13517 #define SARL 0x84 13518 #define SARH 0x85 13519 #define SARB 0x86 13520 #define CPB 0x86 13521 #define CDA 0x88 13522 #define CDAL 0x88 13523 #define CDAH 0x89 13524 #define EDA 0x8a 13525 #define EDAL 0x8a 13526 #define EDAH 0x8b 13527 #define BFL 0x8c 13528 #define BFLL 0x8c 13529 #define BFLH 0x8d 13530 #define BCR 0x8e 13531 #define BCRL 0x8e 13532 #define BCRH 0x8f 13533 #define DSR 0x90 13534 #define DMR 0x91 13535 #define FCT 0x93 13536 #define DIR 0x94 13537 #define DCMD 0x95 13538 #define TIMER0 0x00 13539 #define TIMER1 0x08 13540 #define TIMER2 0x10 13541 #define TIMER3 0x18 13542 #define RXDMA 0x00 13543 #define TXDMA 0x20 13544 #define NOOP 0x00 13545 #define TXRESET 0x01 13546 #define TXENABLE 0x02 13547 #define TXDISABLE 0x03 13548 #define TXCRCINIT 0x04 13549 #define TXCRCEXCL 0x05 13550 #define TXEOM 0x06 13551 #define TXABORT 0x07 13552 #define MPON 0x08 13553 #define TXBUFCLR 0x09 13554 #define RXRESET 0x11 13555 #define RXENABLE 0x12 13556 #define RXDISABLE 0x13 13557 #define RXCRCINIT 0x14 13558 #define RXREJECT 0x15 13559 #define SEARCHMP 0x16 13560 #define RXCRCEXCL 0x17 13561 #define RXCRCCALC 0x18 13562 #define CHRESET 0x21 13563 #define HUNT 0x31 13564 #define SWABORT 0x01 13565 #define FEICLEAR 0x02 13566 #define TXINTE BIT7 13567 #define RXINTE BIT6 13568 #define TXRDYE BIT1 13569 #define RXRDYE BIT0 13570 #define UDRN BIT7 13571 #define IDLE BIT6 13572 #define SYNCD BIT4 13573 #define FLGD BIT4 13574 #define CCTS BIT3 13575 #define CDCD BIT2 13576 #define BRKD BIT1 13577 #define ABTD BIT1 13578 #define GAPD BIT1 13579 #define BRKE BIT0 13580 #define IDLD BIT0 13581 #define EOM BIT7 13582 #define PMP BIT6 13583 #define SHRT BIT6 13584 #define PE BIT5 13585 #define ABT BIT5 13586 #define FRME BIT4 13587 #define RBIT BIT4 13588 #define OVRN BIT3 13589 #define CRCE BIT2 13590 #define WAKEUP_CHARS 256 13591 #if SYNCLINK_GENERIC_HDLC 13592 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 13593 #endif 13594 #ifdef SANITY_CHECK 13595 #else 13596 #endif 13597 #if SYNCLINK_GENERIC_HDLC 13598 /* LDV_COMMENT_END_PREP */ 13599 /* LDV_COMMENT_FUNCTION_CALL Function from field "ndo_open" from driver structure with callbacks "hdlcdev_ops". Standart function test for correct return result. */ 13600 ldv_handler_precall(); 13601 res_hdlcdev_open_28 = hdlcdev_open( var_group4); 13602 ldv_check_return_value(res_hdlcdev_open_28); 13603 if(res_hdlcdev_open_28 < 0) 13604 goto ldv_module_exit; 13605 /* LDV_COMMENT_BEGIN_PREP */ 13606 #endif 13607 #if SYNCLINK_GENERIC_HDLC 13608 #endif 13609 #if SYNCLINK_GENERIC_HDLC 13610 #endif 13611 #ifdef CMSPAR 13612 #endif 13613 #if SYNCLINK_GENERIC_HDLC 13614 #endif 13615 #if SYNCLINK_GENERIC_HDLC 13616 #endif 13617 #if 0 13618 #endif 13619 #if SYNCLINK_GENERIC_HDLC 13620 #endif 13621 #if SYNCLINK_GENERIC_HDLC 13622 #endif 13623 #define TESTFRAMESIZE 20 13624 #if SYNCLINK_GENERIC_HDLC 13625 #endif 13626 #define CALC_REGADDR() \ 13627 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 13628 if (info->port_num > 1) \ 13629 RegAddr += 256; \ 13630 if ( info->port_num & 1) { \ 13631 if (Addr > 0x7f) \ 13632 RegAddr += 0x40; \ 13633 else if (Addr > 0x1f && Addr < 0x60) \ 13634 RegAddr += 0x20; \ 13635 } 13636 /* LDV_COMMENT_END_PREP */ 13637 ldv_s_hdlcdev_ops_net_device_ops++; 13638 13639 } 13640 13641 } 13642 13643 break; 13644 case 4: { 13645 13646 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 13647 if(ldv_s_hdlcdev_ops_net_device_ops==1) { 13648 13649 /* content: static int hdlcdev_close(struct net_device *dev)*/ 13650 /* LDV_COMMENT_BEGIN_PREP */ 13651 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 13652 #if defined(__i386__) 13653 # define BREAKPOINT() asm(" int $3"); 13654 #else 13655 # define BREAKPOINT() { } 13656 #endif 13657 #define MAX_DEVICES 12 13658 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 13659 #define SYNCLINK_GENERIC_HDLC 1 13660 #else 13661 #define SYNCLINK_GENERIC_HDLC 0 13662 #endif 13663 #define GET_USER(error,value,addr) error = get_user(value,addr) 13664 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 13665 #define PUT_USER(error,value,addr) error = put_user(value,addr) 13666 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 13667 #define SCABUFSIZE 1024 13668 #define SCA_MEM_SIZE 0x40000 13669 #define SCA_BASE_SIZE 512 13670 #define SCA_REG_SIZE 16 13671 #define SCA_MAX_PORTS 4 13672 #define SCAMAXDESC 128 13673 #define BUFFERLISTSIZE 4096 13674 #define BH_RECEIVE 1 13675 #define BH_TRANSMIT 2 13676 #define BH_STATUS 4 13677 #define IO_PIN_SHUTDOWN_LIMIT 100 13678 #if SYNCLINK_GENERIC_HDLC 13679 #endif 13680 #define MGSL_MAGIC 0x5401 13681 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13682 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13683 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13684 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13685 #define LPR 0x00 13686 #define PABR0 0x02 13687 #define PABR1 0x03 13688 #define WCRL 0x04 13689 #define WCRM 0x05 13690 #define WCRH 0x06 13691 #define DPCR 0x08 13692 #define DMER 0x09 13693 #define ISR0 0x10 13694 #define ISR1 0x11 13695 #define ISR2 0x12 13696 #define IER0 0x14 13697 #define IER1 0x15 13698 #define IER2 0x16 13699 #define ITCR 0x18 13700 #define INTVR 0x1a 13701 #define IMVR 0x1c 13702 #define TRB 0x20 13703 #define TRBL 0x20 13704 #define TRBH 0x21 13705 #define SR0 0x22 13706 #define SR1 0x23 13707 #define SR2 0x24 13708 #define SR3 0x25 13709 #define FST 0x26 13710 #define IE0 0x28 13711 #define IE1 0x29 13712 #define IE2 0x2a 13713 #define FIE 0x2b 13714 #define CMD 0x2c 13715 #define MD0 0x2e 13716 #define MD1 0x2f 13717 #define MD2 0x30 13718 #define CTL 0x31 13719 #define SA0 0x32 13720 #define SA1 0x33 13721 #define IDL 0x34 13722 #define TMC 0x35 13723 #define RXS 0x36 13724 #define TXS 0x37 13725 #define TRC0 0x38 13726 #define TRC1 0x39 13727 #define RRC 0x3a 13728 #define CST0 0x3c 13729 #define CST1 0x3d 13730 #define TCNT 0x60 13731 #define TCNTL 0x60 13732 #define TCNTH 0x61 13733 #define TCONR 0x62 13734 #define TCONRL 0x62 13735 #define TCONRH 0x63 13736 #define TMCS 0x64 13737 #define TEPR 0x65 13738 #define DARL 0x80 13739 #define DARH 0x81 13740 #define DARB 0x82 13741 #define BAR 0x80 13742 #define BARL 0x80 13743 #define BARH 0x81 13744 #define BARB 0x82 13745 #define SAR 0x84 13746 #define SARL 0x84 13747 #define SARH 0x85 13748 #define SARB 0x86 13749 #define CPB 0x86 13750 #define CDA 0x88 13751 #define CDAL 0x88 13752 #define CDAH 0x89 13753 #define EDA 0x8a 13754 #define EDAL 0x8a 13755 #define EDAH 0x8b 13756 #define BFL 0x8c 13757 #define BFLL 0x8c 13758 #define BFLH 0x8d 13759 #define BCR 0x8e 13760 #define BCRL 0x8e 13761 #define BCRH 0x8f 13762 #define DSR 0x90 13763 #define DMR 0x91 13764 #define FCT 0x93 13765 #define DIR 0x94 13766 #define DCMD 0x95 13767 #define TIMER0 0x00 13768 #define TIMER1 0x08 13769 #define TIMER2 0x10 13770 #define TIMER3 0x18 13771 #define RXDMA 0x00 13772 #define TXDMA 0x20 13773 #define NOOP 0x00 13774 #define TXRESET 0x01 13775 #define TXENABLE 0x02 13776 #define TXDISABLE 0x03 13777 #define TXCRCINIT 0x04 13778 #define TXCRCEXCL 0x05 13779 #define TXEOM 0x06 13780 #define TXABORT 0x07 13781 #define MPON 0x08 13782 #define TXBUFCLR 0x09 13783 #define RXRESET 0x11 13784 #define RXENABLE 0x12 13785 #define RXDISABLE 0x13 13786 #define RXCRCINIT 0x14 13787 #define RXREJECT 0x15 13788 #define SEARCHMP 0x16 13789 #define RXCRCEXCL 0x17 13790 #define RXCRCCALC 0x18 13791 #define CHRESET 0x21 13792 #define HUNT 0x31 13793 #define SWABORT 0x01 13794 #define FEICLEAR 0x02 13795 #define TXINTE BIT7 13796 #define RXINTE BIT6 13797 #define TXRDYE BIT1 13798 #define RXRDYE BIT0 13799 #define UDRN BIT7 13800 #define IDLE BIT6 13801 #define SYNCD BIT4 13802 #define FLGD BIT4 13803 #define CCTS BIT3 13804 #define CDCD BIT2 13805 #define BRKD BIT1 13806 #define ABTD BIT1 13807 #define GAPD BIT1 13808 #define BRKE BIT0 13809 #define IDLD BIT0 13810 #define EOM BIT7 13811 #define PMP BIT6 13812 #define SHRT BIT6 13813 #define PE BIT5 13814 #define ABT BIT5 13815 #define FRME BIT4 13816 #define RBIT BIT4 13817 #define OVRN BIT3 13818 #define CRCE BIT2 13819 #define WAKEUP_CHARS 256 13820 #if SYNCLINK_GENERIC_HDLC 13821 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 13822 #endif 13823 #ifdef SANITY_CHECK 13824 #else 13825 #endif 13826 #if SYNCLINK_GENERIC_HDLC 13827 /* LDV_COMMENT_END_PREP */ 13828 /* LDV_COMMENT_FUNCTION_CALL Function from field "ndo_stop" from driver structure with callbacks "hdlcdev_ops". Standart function test for correct return result. */ 13829 ldv_handler_precall(); 13830 res_hdlcdev_close_29 = hdlcdev_close( var_group4); 13831 ldv_check_return_value(res_hdlcdev_close_29); 13832 if(res_hdlcdev_close_29) 13833 goto ldv_module_exit; 13834 /* LDV_COMMENT_BEGIN_PREP */ 13835 #endif 13836 #if SYNCLINK_GENERIC_HDLC 13837 #endif 13838 #if SYNCLINK_GENERIC_HDLC 13839 #endif 13840 #ifdef CMSPAR 13841 #endif 13842 #if SYNCLINK_GENERIC_HDLC 13843 #endif 13844 #if SYNCLINK_GENERIC_HDLC 13845 #endif 13846 #if 0 13847 #endif 13848 #if SYNCLINK_GENERIC_HDLC 13849 #endif 13850 #if SYNCLINK_GENERIC_HDLC 13851 #endif 13852 #define TESTFRAMESIZE 20 13853 #if SYNCLINK_GENERIC_HDLC 13854 #endif 13855 #define CALC_REGADDR() \ 13856 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 13857 if (info->port_num > 1) \ 13858 RegAddr += 256; \ 13859 if ( info->port_num & 1) { \ 13860 if (Addr > 0x7f) \ 13861 RegAddr += 0x40; \ 13862 else if (Addr > 0x1f && Addr < 0x60) \ 13863 RegAddr += 0x20; \ 13864 } 13865 /* LDV_COMMENT_END_PREP */ 13866 ldv_s_hdlcdev_ops_net_device_ops=0; 13867 13868 } 13869 13870 } 13871 13872 break; 13873 case 5: { 13874 13875 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 13876 13877 13878 /* content: static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)*/ 13879 /* LDV_COMMENT_BEGIN_PREP */ 13880 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 13881 #if defined(__i386__) 13882 # define BREAKPOINT() asm(" int $3"); 13883 #else 13884 # define BREAKPOINT() { } 13885 #endif 13886 #define MAX_DEVICES 12 13887 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 13888 #define SYNCLINK_GENERIC_HDLC 1 13889 #else 13890 #define SYNCLINK_GENERIC_HDLC 0 13891 #endif 13892 #define GET_USER(error,value,addr) error = get_user(value,addr) 13893 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 13894 #define PUT_USER(error,value,addr) error = put_user(value,addr) 13895 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 13896 #define SCABUFSIZE 1024 13897 #define SCA_MEM_SIZE 0x40000 13898 #define SCA_BASE_SIZE 512 13899 #define SCA_REG_SIZE 16 13900 #define SCA_MAX_PORTS 4 13901 #define SCAMAXDESC 128 13902 #define BUFFERLISTSIZE 4096 13903 #define BH_RECEIVE 1 13904 #define BH_TRANSMIT 2 13905 #define BH_STATUS 4 13906 #define IO_PIN_SHUTDOWN_LIMIT 100 13907 #if SYNCLINK_GENERIC_HDLC 13908 #endif 13909 #define MGSL_MAGIC 0x5401 13910 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 13911 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 13912 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 13913 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 13914 #define LPR 0x00 13915 #define PABR0 0x02 13916 #define PABR1 0x03 13917 #define WCRL 0x04 13918 #define WCRM 0x05 13919 #define WCRH 0x06 13920 #define DPCR 0x08 13921 #define DMER 0x09 13922 #define ISR0 0x10 13923 #define ISR1 0x11 13924 #define ISR2 0x12 13925 #define IER0 0x14 13926 #define IER1 0x15 13927 #define IER2 0x16 13928 #define ITCR 0x18 13929 #define INTVR 0x1a 13930 #define IMVR 0x1c 13931 #define TRB 0x20 13932 #define TRBL 0x20 13933 #define TRBH 0x21 13934 #define SR0 0x22 13935 #define SR1 0x23 13936 #define SR2 0x24 13937 #define SR3 0x25 13938 #define FST 0x26 13939 #define IE0 0x28 13940 #define IE1 0x29 13941 #define IE2 0x2a 13942 #define FIE 0x2b 13943 #define CMD 0x2c 13944 #define MD0 0x2e 13945 #define MD1 0x2f 13946 #define MD2 0x30 13947 #define CTL 0x31 13948 #define SA0 0x32 13949 #define SA1 0x33 13950 #define IDL 0x34 13951 #define TMC 0x35 13952 #define RXS 0x36 13953 #define TXS 0x37 13954 #define TRC0 0x38 13955 #define TRC1 0x39 13956 #define RRC 0x3a 13957 #define CST0 0x3c 13958 #define CST1 0x3d 13959 #define TCNT 0x60 13960 #define TCNTL 0x60 13961 #define TCNTH 0x61 13962 #define TCONR 0x62 13963 #define TCONRL 0x62 13964 #define TCONRH 0x63 13965 #define TMCS 0x64 13966 #define TEPR 0x65 13967 #define DARL 0x80 13968 #define DARH 0x81 13969 #define DARB 0x82 13970 #define BAR 0x80 13971 #define BARL 0x80 13972 #define BARH 0x81 13973 #define BARB 0x82 13974 #define SAR 0x84 13975 #define SARL 0x84 13976 #define SARH 0x85 13977 #define SARB 0x86 13978 #define CPB 0x86 13979 #define CDA 0x88 13980 #define CDAL 0x88 13981 #define CDAH 0x89 13982 #define EDA 0x8a 13983 #define EDAL 0x8a 13984 #define EDAH 0x8b 13985 #define BFL 0x8c 13986 #define BFLL 0x8c 13987 #define BFLH 0x8d 13988 #define BCR 0x8e 13989 #define BCRL 0x8e 13990 #define BCRH 0x8f 13991 #define DSR 0x90 13992 #define DMR 0x91 13993 #define FCT 0x93 13994 #define DIR 0x94 13995 #define DCMD 0x95 13996 #define TIMER0 0x00 13997 #define TIMER1 0x08 13998 #define TIMER2 0x10 13999 #define TIMER3 0x18 14000 #define RXDMA 0x00 14001 #define TXDMA 0x20 14002 #define NOOP 0x00 14003 #define TXRESET 0x01 14004 #define TXENABLE 0x02 14005 #define TXDISABLE 0x03 14006 #define TXCRCINIT 0x04 14007 #define TXCRCEXCL 0x05 14008 #define TXEOM 0x06 14009 #define TXABORT 0x07 14010 #define MPON 0x08 14011 #define TXBUFCLR 0x09 14012 #define RXRESET 0x11 14013 #define RXENABLE 0x12 14014 #define RXDISABLE 0x13 14015 #define RXCRCINIT 0x14 14016 #define RXREJECT 0x15 14017 #define SEARCHMP 0x16 14018 #define RXCRCEXCL 0x17 14019 #define RXCRCCALC 0x18 14020 #define CHRESET 0x21 14021 #define HUNT 0x31 14022 #define SWABORT 0x01 14023 #define FEICLEAR 0x02 14024 #define TXINTE BIT7 14025 #define RXINTE BIT6 14026 #define TXRDYE BIT1 14027 #define RXRDYE BIT0 14028 #define UDRN BIT7 14029 #define IDLE BIT6 14030 #define SYNCD BIT4 14031 #define FLGD BIT4 14032 #define CCTS BIT3 14033 #define CDCD BIT2 14034 #define BRKD BIT1 14035 #define ABTD BIT1 14036 #define GAPD BIT1 14037 #define BRKE BIT0 14038 #define IDLD BIT0 14039 #define EOM BIT7 14040 #define PMP BIT6 14041 #define SHRT BIT6 14042 #define PE BIT5 14043 #define ABT BIT5 14044 #define FRME BIT4 14045 #define RBIT BIT4 14046 #define OVRN BIT3 14047 #define CRCE BIT2 14048 #define WAKEUP_CHARS 256 14049 #if SYNCLINK_GENERIC_HDLC 14050 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14051 #endif 14052 #ifdef SANITY_CHECK 14053 #else 14054 #endif 14055 #if SYNCLINK_GENERIC_HDLC 14056 /* LDV_COMMENT_END_PREP */ 14057 /* LDV_COMMENT_FUNCTION_CALL Function from field "ndo_do_ioctl" from driver structure with callbacks "hdlcdev_ops" */ 14058 ldv_handler_precall(); 14059 hdlcdev_ioctl( var_group4, var_group5, var_hdlcdev_ioctl_30_p2); 14060 /* LDV_COMMENT_BEGIN_PREP */ 14061 #endif 14062 #if SYNCLINK_GENERIC_HDLC 14063 #endif 14064 #if SYNCLINK_GENERIC_HDLC 14065 #endif 14066 #ifdef CMSPAR 14067 #endif 14068 #if SYNCLINK_GENERIC_HDLC 14069 #endif 14070 #if SYNCLINK_GENERIC_HDLC 14071 #endif 14072 #if 0 14073 #endif 14074 #if SYNCLINK_GENERIC_HDLC 14075 #endif 14076 #if SYNCLINK_GENERIC_HDLC 14077 #endif 14078 #define TESTFRAMESIZE 20 14079 #if SYNCLINK_GENERIC_HDLC 14080 #endif 14081 #define CALC_REGADDR() \ 14082 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14083 if (info->port_num > 1) \ 14084 RegAddr += 256; \ 14085 if ( info->port_num & 1) { \ 14086 if (Addr > 0x7f) \ 14087 RegAddr += 0x40; \ 14088 else if (Addr > 0x1f && Addr < 0x60) \ 14089 RegAddr += 0x20; \ 14090 } 14091 /* LDV_COMMENT_END_PREP */ 14092 14093 14094 14095 14096 } 14097 14098 break; 14099 case 6: { 14100 14101 /** STRUCT: struct type: net_device_ops, struct name: hdlcdev_ops **/ 14102 14103 14104 /* content: static void hdlcdev_tx_timeout(struct net_device *dev)*/ 14105 /* LDV_COMMENT_BEGIN_PREP */ 14106 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 14107 #if defined(__i386__) 14108 # define BREAKPOINT() asm(" int $3"); 14109 #else 14110 # define BREAKPOINT() { } 14111 #endif 14112 #define MAX_DEVICES 12 14113 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 14114 #define SYNCLINK_GENERIC_HDLC 1 14115 #else 14116 #define SYNCLINK_GENERIC_HDLC 0 14117 #endif 14118 #define GET_USER(error,value,addr) error = get_user(value,addr) 14119 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 14120 #define PUT_USER(error,value,addr) error = put_user(value,addr) 14121 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 14122 #define SCABUFSIZE 1024 14123 #define SCA_MEM_SIZE 0x40000 14124 #define SCA_BASE_SIZE 512 14125 #define SCA_REG_SIZE 16 14126 #define SCA_MAX_PORTS 4 14127 #define SCAMAXDESC 128 14128 #define BUFFERLISTSIZE 4096 14129 #define BH_RECEIVE 1 14130 #define BH_TRANSMIT 2 14131 #define BH_STATUS 4 14132 #define IO_PIN_SHUTDOWN_LIMIT 100 14133 #if SYNCLINK_GENERIC_HDLC 14134 #endif 14135 #define MGSL_MAGIC 0x5401 14136 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 14137 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 14138 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 14139 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 14140 #define LPR 0x00 14141 #define PABR0 0x02 14142 #define PABR1 0x03 14143 #define WCRL 0x04 14144 #define WCRM 0x05 14145 #define WCRH 0x06 14146 #define DPCR 0x08 14147 #define DMER 0x09 14148 #define ISR0 0x10 14149 #define ISR1 0x11 14150 #define ISR2 0x12 14151 #define IER0 0x14 14152 #define IER1 0x15 14153 #define IER2 0x16 14154 #define ITCR 0x18 14155 #define INTVR 0x1a 14156 #define IMVR 0x1c 14157 #define TRB 0x20 14158 #define TRBL 0x20 14159 #define TRBH 0x21 14160 #define SR0 0x22 14161 #define SR1 0x23 14162 #define SR2 0x24 14163 #define SR3 0x25 14164 #define FST 0x26 14165 #define IE0 0x28 14166 #define IE1 0x29 14167 #define IE2 0x2a 14168 #define FIE 0x2b 14169 #define CMD 0x2c 14170 #define MD0 0x2e 14171 #define MD1 0x2f 14172 #define MD2 0x30 14173 #define CTL 0x31 14174 #define SA0 0x32 14175 #define SA1 0x33 14176 #define IDL 0x34 14177 #define TMC 0x35 14178 #define RXS 0x36 14179 #define TXS 0x37 14180 #define TRC0 0x38 14181 #define TRC1 0x39 14182 #define RRC 0x3a 14183 #define CST0 0x3c 14184 #define CST1 0x3d 14185 #define TCNT 0x60 14186 #define TCNTL 0x60 14187 #define TCNTH 0x61 14188 #define TCONR 0x62 14189 #define TCONRL 0x62 14190 #define TCONRH 0x63 14191 #define TMCS 0x64 14192 #define TEPR 0x65 14193 #define DARL 0x80 14194 #define DARH 0x81 14195 #define DARB 0x82 14196 #define BAR 0x80 14197 #define BARL 0x80 14198 #define BARH 0x81 14199 #define BARB 0x82 14200 #define SAR 0x84 14201 #define SARL 0x84 14202 #define SARH 0x85 14203 #define SARB 0x86 14204 #define CPB 0x86 14205 #define CDA 0x88 14206 #define CDAL 0x88 14207 #define CDAH 0x89 14208 #define EDA 0x8a 14209 #define EDAL 0x8a 14210 #define EDAH 0x8b 14211 #define BFL 0x8c 14212 #define BFLL 0x8c 14213 #define BFLH 0x8d 14214 #define BCR 0x8e 14215 #define BCRL 0x8e 14216 #define BCRH 0x8f 14217 #define DSR 0x90 14218 #define DMR 0x91 14219 #define FCT 0x93 14220 #define DIR 0x94 14221 #define DCMD 0x95 14222 #define TIMER0 0x00 14223 #define TIMER1 0x08 14224 #define TIMER2 0x10 14225 #define TIMER3 0x18 14226 #define RXDMA 0x00 14227 #define TXDMA 0x20 14228 #define NOOP 0x00 14229 #define TXRESET 0x01 14230 #define TXENABLE 0x02 14231 #define TXDISABLE 0x03 14232 #define TXCRCINIT 0x04 14233 #define TXCRCEXCL 0x05 14234 #define TXEOM 0x06 14235 #define TXABORT 0x07 14236 #define MPON 0x08 14237 #define TXBUFCLR 0x09 14238 #define RXRESET 0x11 14239 #define RXENABLE 0x12 14240 #define RXDISABLE 0x13 14241 #define RXCRCINIT 0x14 14242 #define RXREJECT 0x15 14243 #define SEARCHMP 0x16 14244 #define RXCRCEXCL 0x17 14245 #define RXCRCCALC 0x18 14246 #define CHRESET 0x21 14247 #define HUNT 0x31 14248 #define SWABORT 0x01 14249 #define FEICLEAR 0x02 14250 #define TXINTE BIT7 14251 #define RXINTE BIT6 14252 #define TXRDYE BIT1 14253 #define RXRDYE BIT0 14254 #define UDRN BIT7 14255 #define IDLE BIT6 14256 #define SYNCD BIT4 14257 #define FLGD BIT4 14258 #define CCTS BIT3 14259 #define CDCD BIT2 14260 #define BRKD BIT1 14261 #define ABTD BIT1 14262 #define GAPD BIT1 14263 #define BRKE BIT0 14264 #define IDLD BIT0 14265 #define EOM BIT7 14266 #define PMP BIT6 14267 #define SHRT BIT6 14268 #define PE BIT5 14269 #define ABT BIT5 14270 #define FRME BIT4 14271 #define RBIT BIT4 14272 #define OVRN BIT3 14273 #define CRCE BIT2 14274 #define WAKEUP_CHARS 256 14275 #if SYNCLINK_GENERIC_HDLC 14276 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14277 #endif 14278 #ifdef SANITY_CHECK 14279 #else 14280 #endif 14281 #if SYNCLINK_GENERIC_HDLC 14282 /* LDV_COMMENT_END_PREP */ 14283 /* LDV_COMMENT_FUNCTION_CALL Function from field "ndo_tx_timeout" from driver structure with callbacks "hdlcdev_ops" */ 14284 ldv_handler_precall(); 14285 hdlcdev_tx_timeout( var_group4); 14286 /* LDV_COMMENT_BEGIN_PREP */ 14287 #endif 14288 #if SYNCLINK_GENERIC_HDLC 14289 #endif 14290 #if SYNCLINK_GENERIC_HDLC 14291 #endif 14292 #ifdef CMSPAR 14293 #endif 14294 #if SYNCLINK_GENERIC_HDLC 14295 #endif 14296 #if SYNCLINK_GENERIC_HDLC 14297 #endif 14298 #if 0 14299 #endif 14300 #if SYNCLINK_GENERIC_HDLC 14301 #endif 14302 #if SYNCLINK_GENERIC_HDLC 14303 #endif 14304 #define TESTFRAMESIZE 20 14305 #if SYNCLINK_GENERIC_HDLC 14306 #endif 14307 #define CALC_REGADDR() \ 14308 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14309 if (info->port_num > 1) \ 14310 RegAddr += 256; \ 14311 if ( info->port_num & 1) { \ 14312 if (Addr > 0x7f) \ 14313 RegAddr += 0x40; \ 14314 else if (Addr > 0x1f && Addr < 0x60) \ 14315 RegAddr += 0x20; \ 14316 } 14317 /* LDV_COMMENT_END_PREP */ 14318 14319 14320 14321 14322 } 14323 14324 break; 14325 case 7: { 14326 14327 /** STRUCT: struct type: tty_port_operations, struct name: port_ops **/ 14328 14329 14330 /* content: static int carrier_raised(struct tty_port *port)*/ 14331 /* LDV_COMMENT_BEGIN_PREP */ 14332 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 14333 #if defined(__i386__) 14334 # define BREAKPOINT() asm(" int $3"); 14335 #else 14336 # define BREAKPOINT() { } 14337 #endif 14338 #define MAX_DEVICES 12 14339 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 14340 #define SYNCLINK_GENERIC_HDLC 1 14341 #else 14342 #define SYNCLINK_GENERIC_HDLC 0 14343 #endif 14344 #define GET_USER(error,value,addr) error = get_user(value,addr) 14345 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 14346 #define PUT_USER(error,value,addr) error = put_user(value,addr) 14347 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 14348 #define SCABUFSIZE 1024 14349 #define SCA_MEM_SIZE 0x40000 14350 #define SCA_BASE_SIZE 512 14351 #define SCA_REG_SIZE 16 14352 #define SCA_MAX_PORTS 4 14353 #define SCAMAXDESC 128 14354 #define BUFFERLISTSIZE 4096 14355 #define BH_RECEIVE 1 14356 #define BH_TRANSMIT 2 14357 #define BH_STATUS 4 14358 #define IO_PIN_SHUTDOWN_LIMIT 100 14359 #if SYNCLINK_GENERIC_HDLC 14360 #endif 14361 #define MGSL_MAGIC 0x5401 14362 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 14363 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 14364 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 14365 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 14366 #define LPR 0x00 14367 #define PABR0 0x02 14368 #define PABR1 0x03 14369 #define WCRL 0x04 14370 #define WCRM 0x05 14371 #define WCRH 0x06 14372 #define DPCR 0x08 14373 #define DMER 0x09 14374 #define ISR0 0x10 14375 #define ISR1 0x11 14376 #define ISR2 0x12 14377 #define IER0 0x14 14378 #define IER1 0x15 14379 #define IER2 0x16 14380 #define ITCR 0x18 14381 #define INTVR 0x1a 14382 #define IMVR 0x1c 14383 #define TRB 0x20 14384 #define TRBL 0x20 14385 #define TRBH 0x21 14386 #define SR0 0x22 14387 #define SR1 0x23 14388 #define SR2 0x24 14389 #define SR3 0x25 14390 #define FST 0x26 14391 #define IE0 0x28 14392 #define IE1 0x29 14393 #define IE2 0x2a 14394 #define FIE 0x2b 14395 #define CMD 0x2c 14396 #define MD0 0x2e 14397 #define MD1 0x2f 14398 #define MD2 0x30 14399 #define CTL 0x31 14400 #define SA0 0x32 14401 #define SA1 0x33 14402 #define IDL 0x34 14403 #define TMC 0x35 14404 #define RXS 0x36 14405 #define TXS 0x37 14406 #define TRC0 0x38 14407 #define TRC1 0x39 14408 #define RRC 0x3a 14409 #define CST0 0x3c 14410 #define CST1 0x3d 14411 #define TCNT 0x60 14412 #define TCNTL 0x60 14413 #define TCNTH 0x61 14414 #define TCONR 0x62 14415 #define TCONRL 0x62 14416 #define TCONRH 0x63 14417 #define TMCS 0x64 14418 #define TEPR 0x65 14419 #define DARL 0x80 14420 #define DARH 0x81 14421 #define DARB 0x82 14422 #define BAR 0x80 14423 #define BARL 0x80 14424 #define BARH 0x81 14425 #define BARB 0x82 14426 #define SAR 0x84 14427 #define SARL 0x84 14428 #define SARH 0x85 14429 #define SARB 0x86 14430 #define CPB 0x86 14431 #define CDA 0x88 14432 #define CDAL 0x88 14433 #define CDAH 0x89 14434 #define EDA 0x8a 14435 #define EDAL 0x8a 14436 #define EDAH 0x8b 14437 #define BFL 0x8c 14438 #define BFLL 0x8c 14439 #define BFLH 0x8d 14440 #define BCR 0x8e 14441 #define BCRL 0x8e 14442 #define BCRH 0x8f 14443 #define DSR 0x90 14444 #define DMR 0x91 14445 #define FCT 0x93 14446 #define DIR 0x94 14447 #define DCMD 0x95 14448 #define TIMER0 0x00 14449 #define TIMER1 0x08 14450 #define TIMER2 0x10 14451 #define TIMER3 0x18 14452 #define RXDMA 0x00 14453 #define TXDMA 0x20 14454 #define NOOP 0x00 14455 #define TXRESET 0x01 14456 #define TXENABLE 0x02 14457 #define TXDISABLE 0x03 14458 #define TXCRCINIT 0x04 14459 #define TXCRCEXCL 0x05 14460 #define TXEOM 0x06 14461 #define TXABORT 0x07 14462 #define MPON 0x08 14463 #define TXBUFCLR 0x09 14464 #define RXRESET 0x11 14465 #define RXENABLE 0x12 14466 #define RXDISABLE 0x13 14467 #define RXCRCINIT 0x14 14468 #define RXREJECT 0x15 14469 #define SEARCHMP 0x16 14470 #define RXCRCEXCL 0x17 14471 #define RXCRCCALC 0x18 14472 #define CHRESET 0x21 14473 #define HUNT 0x31 14474 #define SWABORT 0x01 14475 #define FEICLEAR 0x02 14476 #define TXINTE BIT7 14477 #define RXINTE BIT6 14478 #define TXRDYE BIT1 14479 #define RXRDYE BIT0 14480 #define UDRN BIT7 14481 #define IDLE BIT6 14482 #define SYNCD BIT4 14483 #define FLGD BIT4 14484 #define CCTS BIT3 14485 #define CDCD BIT2 14486 #define BRKD BIT1 14487 #define ABTD BIT1 14488 #define GAPD BIT1 14489 #define BRKE BIT0 14490 #define IDLD BIT0 14491 #define EOM BIT7 14492 #define PMP BIT6 14493 #define SHRT BIT6 14494 #define PE BIT5 14495 #define ABT BIT5 14496 #define FRME BIT4 14497 #define RBIT BIT4 14498 #define OVRN BIT3 14499 #define CRCE BIT2 14500 #define WAKEUP_CHARS 256 14501 #if SYNCLINK_GENERIC_HDLC 14502 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14503 #endif 14504 #ifdef SANITY_CHECK 14505 #else 14506 #endif 14507 #if SYNCLINK_GENERIC_HDLC 14508 #endif 14509 #if SYNCLINK_GENERIC_HDLC 14510 #endif 14511 #if SYNCLINK_GENERIC_HDLC 14512 #endif 14513 #ifdef CMSPAR 14514 #endif 14515 /* LDV_COMMENT_END_PREP */ 14516 /* LDV_COMMENT_FUNCTION_CALL Function from field "carrier_raised" from driver structure with callbacks "port_ops" */ 14517 ldv_handler_precall(); 14518 carrier_raised( var_group6); 14519 /* LDV_COMMENT_BEGIN_PREP */ 14520 #if SYNCLINK_GENERIC_HDLC 14521 #endif 14522 #if SYNCLINK_GENERIC_HDLC 14523 #endif 14524 #if 0 14525 #endif 14526 #if SYNCLINK_GENERIC_HDLC 14527 #endif 14528 #if SYNCLINK_GENERIC_HDLC 14529 #endif 14530 #define TESTFRAMESIZE 20 14531 #if SYNCLINK_GENERIC_HDLC 14532 #endif 14533 #define CALC_REGADDR() \ 14534 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14535 if (info->port_num > 1) \ 14536 RegAddr += 256; \ 14537 if ( info->port_num & 1) { \ 14538 if (Addr > 0x7f) \ 14539 RegAddr += 0x40; \ 14540 else if (Addr > 0x1f && Addr < 0x60) \ 14541 RegAddr += 0x20; \ 14542 } 14543 /* LDV_COMMENT_END_PREP */ 14544 14545 14546 14547 14548 } 14549 14550 break; 14551 case 8: { 14552 14553 /** STRUCT: struct type: tty_port_operations, struct name: port_ops **/ 14554 14555 14556 /* content: static void dtr_rts(struct tty_port *port, int on)*/ 14557 /* LDV_COMMENT_BEGIN_PREP */ 14558 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 14559 #if defined(__i386__) 14560 # define BREAKPOINT() asm(" int $3"); 14561 #else 14562 # define BREAKPOINT() { } 14563 #endif 14564 #define MAX_DEVICES 12 14565 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 14566 #define SYNCLINK_GENERIC_HDLC 1 14567 #else 14568 #define SYNCLINK_GENERIC_HDLC 0 14569 #endif 14570 #define GET_USER(error,value,addr) error = get_user(value,addr) 14571 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 14572 #define PUT_USER(error,value,addr) error = put_user(value,addr) 14573 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 14574 #define SCABUFSIZE 1024 14575 #define SCA_MEM_SIZE 0x40000 14576 #define SCA_BASE_SIZE 512 14577 #define SCA_REG_SIZE 16 14578 #define SCA_MAX_PORTS 4 14579 #define SCAMAXDESC 128 14580 #define BUFFERLISTSIZE 4096 14581 #define BH_RECEIVE 1 14582 #define BH_TRANSMIT 2 14583 #define BH_STATUS 4 14584 #define IO_PIN_SHUTDOWN_LIMIT 100 14585 #if SYNCLINK_GENERIC_HDLC 14586 #endif 14587 #define MGSL_MAGIC 0x5401 14588 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 14589 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 14590 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 14591 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 14592 #define LPR 0x00 14593 #define PABR0 0x02 14594 #define PABR1 0x03 14595 #define WCRL 0x04 14596 #define WCRM 0x05 14597 #define WCRH 0x06 14598 #define DPCR 0x08 14599 #define DMER 0x09 14600 #define ISR0 0x10 14601 #define ISR1 0x11 14602 #define ISR2 0x12 14603 #define IER0 0x14 14604 #define IER1 0x15 14605 #define IER2 0x16 14606 #define ITCR 0x18 14607 #define INTVR 0x1a 14608 #define IMVR 0x1c 14609 #define TRB 0x20 14610 #define TRBL 0x20 14611 #define TRBH 0x21 14612 #define SR0 0x22 14613 #define SR1 0x23 14614 #define SR2 0x24 14615 #define SR3 0x25 14616 #define FST 0x26 14617 #define IE0 0x28 14618 #define IE1 0x29 14619 #define IE2 0x2a 14620 #define FIE 0x2b 14621 #define CMD 0x2c 14622 #define MD0 0x2e 14623 #define MD1 0x2f 14624 #define MD2 0x30 14625 #define CTL 0x31 14626 #define SA0 0x32 14627 #define SA1 0x33 14628 #define IDL 0x34 14629 #define TMC 0x35 14630 #define RXS 0x36 14631 #define TXS 0x37 14632 #define TRC0 0x38 14633 #define TRC1 0x39 14634 #define RRC 0x3a 14635 #define CST0 0x3c 14636 #define CST1 0x3d 14637 #define TCNT 0x60 14638 #define TCNTL 0x60 14639 #define TCNTH 0x61 14640 #define TCONR 0x62 14641 #define TCONRL 0x62 14642 #define TCONRH 0x63 14643 #define TMCS 0x64 14644 #define TEPR 0x65 14645 #define DARL 0x80 14646 #define DARH 0x81 14647 #define DARB 0x82 14648 #define BAR 0x80 14649 #define BARL 0x80 14650 #define BARH 0x81 14651 #define BARB 0x82 14652 #define SAR 0x84 14653 #define SARL 0x84 14654 #define SARH 0x85 14655 #define SARB 0x86 14656 #define CPB 0x86 14657 #define CDA 0x88 14658 #define CDAL 0x88 14659 #define CDAH 0x89 14660 #define EDA 0x8a 14661 #define EDAL 0x8a 14662 #define EDAH 0x8b 14663 #define BFL 0x8c 14664 #define BFLL 0x8c 14665 #define BFLH 0x8d 14666 #define BCR 0x8e 14667 #define BCRL 0x8e 14668 #define BCRH 0x8f 14669 #define DSR 0x90 14670 #define DMR 0x91 14671 #define FCT 0x93 14672 #define DIR 0x94 14673 #define DCMD 0x95 14674 #define TIMER0 0x00 14675 #define TIMER1 0x08 14676 #define TIMER2 0x10 14677 #define TIMER3 0x18 14678 #define RXDMA 0x00 14679 #define TXDMA 0x20 14680 #define NOOP 0x00 14681 #define TXRESET 0x01 14682 #define TXENABLE 0x02 14683 #define TXDISABLE 0x03 14684 #define TXCRCINIT 0x04 14685 #define TXCRCEXCL 0x05 14686 #define TXEOM 0x06 14687 #define TXABORT 0x07 14688 #define MPON 0x08 14689 #define TXBUFCLR 0x09 14690 #define RXRESET 0x11 14691 #define RXENABLE 0x12 14692 #define RXDISABLE 0x13 14693 #define RXCRCINIT 0x14 14694 #define RXREJECT 0x15 14695 #define SEARCHMP 0x16 14696 #define RXCRCEXCL 0x17 14697 #define RXCRCCALC 0x18 14698 #define CHRESET 0x21 14699 #define HUNT 0x31 14700 #define SWABORT 0x01 14701 #define FEICLEAR 0x02 14702 #define TXINTE BIT7 14703 #define RXINTE BIT6 14704 #define TXRDYE BIT1 14705 #define RXRDYE BIT0 14706 #define UDRN BIT7 14707 #define IDLE BIT6 14708 #define SYNCD BIT4 14709 #define FLGD BIT4 14710 #define CCTS BIT3 14711 #define CDCD BIT2 14712 #define BRKD BIT1 14713 #define ABTD BIT1 14714 #define GAPD BIT1 14715 #define BRKE BIT0 14716 #define IDLD BIT0 14717 #define EOM BIT7 14718 #define PMP BIT6 14719 #define SHRT BIT6 14720 #define PE BIT5 14721 #define ABT BIT5 14722 #define FRME BIT4 14723 #define RBIT BIT4 14724 #define OVRN BIT3 14725 #define CRCE BIT2 14726 #define WAKEUP_CHARS 256 14727 #if SYNCLINK_GENERIC_HDLC 14728 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14729 #endif 14730 #ifdef SANITY_CHECK 14731 #else 14732 #endif 14733 #if SYNCLINK_GENERIC_HDLC 14734 #endif 14735 #if SYNCLINK_GENERIC_HDLC 14736 #endif 14737 #if SYNCLINK_GENERIC_HDLC 14738 #endif 14739 #ifdef CMSPAR 14740 #endif 14741 /* LDV_COMMENT_END_PREP */ 14742 /* LDV_COMMENT_FUNCTION_CALL Function from field "dtr_rts" from driver structure with callbacks "port_ops" */ 14743 ldv_handler_precall(); 14744 dtr_rts( var_group6, var_dtr_rts_70_p1); 14745 /* LDV_COMMENT_BEGIN_PREP */ 14746 #if SYNCLINK_GENERIC_HDLC 14747 #endif 14748 #if SYNCLINK_GENERIC_HDLC 14749 #endif 14750 #if 0 14751 #endif 14752 #if SYNCLINK_GENERIC_HDLC 14753 #endif 14754 #if SYNCLINK_GENERIC_HDLC 14755 #endif 14756 #define TESTFRAMESIZE 20 14757 #if SYNCLINK_GENERIC_HDLC 14758 #endif 14759 #define CALC_REGADDR() \ 14760 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14761 if (info->port_num > 1) \ 14762 RegAddr += 256; \ 14763 if ( info->port_num & 1) { \ 14764 if (Addr > 0x7f) \ 14765 RegAddr += 0x40; \ 14766 else if (Addr > 0x1f && Addr < 0x60) \ 14767 RegAddr += 0x20; \ 14768 } 14769 /* LDV_COMMENT_END_PREP */ 14770 14771 14772 14773 14774 } 14775 14776 break; 14777 case 9: { 14778 14779 /** STRUCT: struct type: tty_operations, struct name: ops **/ 14780 if(ldv_s_ops_tty_operations==0) { 14781 14782 /* content: static int open(struct tty_struct *tty, struct file *filp)*/ 14783 /* LDV_COMMENT_BEGIN_PREP */ 14784 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 14785 #if defined(__i386__) 14786 # define BREAKPOINT() asm(" int $3"); 14787 #else 14788 # define BREAKPOINT() { } 14789 #endif 14790 #define MAX_DEVICES 12 14791 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 14792 #define SYNCLINK_GENERIC_HDLC 1 14793 #else 14794 #define SYNCLINK_GENERIC_HDLC 0 14795 #endif 14796 #define GET_USER(error,value,addr) error = get_user(value,addr) 14797 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 14798 #define PUT_USER(error,value,addr) error = put_user(value,addr) 14799 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 14800 #define SCABUFSIZE 1024 14801 #define SCA_MEM_SIZE 0x40000 14802 #define SCA_BASE_SIZE 512 14803 #define SCA_REG_SIZE 16 14804 #define SCA_MAX_PORTS 4 14805 #define SCAMAXDESC 128 14806 #define BUFFERLISTSIZE 4096 14807 #define BH_RECEIVE 1 14808 #define BH_TRANSMIT 2 14809 #define BH_STATUS 4 14810 #define IO_PIN_SHUTDOWN_LIMIT 100 14811 #if SYNCLINK_GENERIC_HDLC 14812 #endif 14813 #define MGSL_MAGIC 0x5401 14814 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 14815 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 14816 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 14817 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 14818 #define LPR 0x00 14819 #define PABR0 0x02 14820 #define PABR1 0x03 14821 #define WCRL 0x04 14822 #define WCRM 0x05 14823 #define WCRH 0x06 14824 #define DPCR 0x08 14825 #define DMER 0x09 14826 #define ISR0 0x10 14827 #define ISR1 0x11 14828 #define ISR2 0x12 14829 #define IER0 0x14 14830 #define IER1 0x15 14831 #define IER2 0x16 14832 #define ITCR 0x18 14833 #define INTVR 0x1a 14834 #define IMVR 0x1c 14835 #define TRB 0x20 14836 #define TRBL 0x20 14837 #define TRBH 0x21 14838 #define SR0 0x22 14839 #define SR1 0x23 14840 #define SR2 0x24 14841 #define SR3 0x25 14842 #define FST 0x26 14843 #define IE0 0x28 14844 #define IE1 0x29 14845 #define IE2 0x2a 14846 #define FIE 0x2b 14847 #define CMD 0x2c 14848 #define MD0 0x2e 14849 #define MD1 0x2f 14850 #define MD2 0x30 14851 #define CTL 0x31 14852 #define SA0 0x32 14853 #define SA1 0x33 14854 #define IDL 0x34 14855 #define TMC 0x35 14856 #define RXS 0x36 14857 #define TXS 0x37 14858 #define TRC0 0x38 14859 #define TRC1 0x39 14860 #define RRC 0x3a 14861 #define CST0 0x3c 14862 #define CST1 0x3d 14863 #define TCNT 0x60 14864 #define TCNTL 0x60 14865 #define TCNTH 0x61 14866 #define TCONR 0x62 14867 #define TCONRL 0x62 14868 #define TCONRH 0x63 14869 #define TMCS 0x64 14870 #define TEPR 0x65 14871 #define DARL 0x80 14872 #define DARH 0x81 14873 #define DARB 0x82 14874 #define BAR 0x80 14875 #define BARL 0x80 14876 #define BARH 0x81 14877 #define BARB 0x82 14878 #define SAR 0x84 14879 #define SARL 0x84 14880 #define SARH 0x85 14881 #define SARB 0x86 14882 #define CPB 0x86 14883 #define CDA 0x88 14884 #define CDAL 0x88 14885 #define CDAH 0x89 14886 #define EDA 0x8a 14887 #define EDAL 0x8a 14888 #define EDAH 0x8b 14889 #define BFL 0x8c 14890 #define BFLL 0x8c 14891 #define BFLH 0x8d 14892 #define BCR 0x8e 14893 #define BCRL 0x8e 14894 #define BCRH 0x8f 14895 #define DSR 0x90 14896 #define DMR 0x91 14897 #define FCT 0x93 14898 #define DIR 0x94 14899 #define DCMD 0x95 14900 #define TIMER0 0x00 14901 #define TIMER1 0x08 14902 #define TIMER2 0x10 14903 #define TIMER3 0x18 14904 #define RXDMA 0x00 14905 #define TXDMA 0x20 14906 #define NOOP 0x00 14907 #define TXRESET 0x01 14908 #define TXENABLE 0x02 14909 #define TXDISABLE 0x03 14910 #define TXCRCINIT 0x04 14911 #define TXCRCEXCL 0x05 14912 #define TXEOM 0x06 14913 #define TXABORT 0x07 14914 #define MPON 0x08 14915 #define TXBUFCLR 0x09 14916 #define RXRESET 0x11 14917 #define RXENABLE 0x12 14918 #define RXDISABLE 0x13 14919 #define RXCRCINIT 0x14 14920 #define RXREJECT 0x15 14921 #define SEARCHMP 0x16 14922 #define RXCRCEXCL 0x17 14923 #define RXCRCCALC 0x18 14924 #define CHRESET 0x21 14925 #define HUNT 0x31 14926 #define SWABORT 0x01 14927 #define FEICLEAR 0x02 14928 #define TXINTE BIT7 14929 #define RXINTE BIT6 14930 #define TXRDYE BIT1 14931 #define RXRDYE BIT0 14932 #define UDRN BIT7 14933 #define IDLE BIT6 14934 #define SYNCD BIT4 14935 #define FLGD BIT4 14936 #define CCTS BIT3 14937 #define CDCD BIT2 14938 #define BRKD BIT1 14939 #define ABTD BIT1 14940 #define GAPD BIT1 14941 #define BRKE BIT0 14942 #define IDLD BIT0 14943 #define EOM BIT7 14944 #define PMP BIT6 14945 #define SHRT BIT6 14946 #define PE BIT5 14947 #define ABT BIT5 14948 #define FRME BIT4 14949 #define RBIT BIT4 14950 #define OVRN BIT3 14951 #define CRCE BIT2 14952 #define WAKEUP_CHARS 256 14953 #if SYNCLINK_GENERIC_HDLC 14954 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 14955 #endif 14956 #ifdef SANITY_CHECK 14957 #else 14958 #endif 14959 /* LDV_COMMENT_END_PREP */ 14960 /* LDV_COMMENT_FUNCTION_CALL Function from field "open" from driver structure with callbacks "ops". Standart function test for correct return result. */ 14961 ldv_handler_precall(); 14962 res_open_4 = open( var_group8, var_group3); 14963 ldv_check_return_value(res_open_4); 14964 if(res_open_4) 14965 goto ldv_module_exit; 14966 /* LDV_COMMENT_BEGIN_PREP */ 14967 #if SYNCLINK_GENERIC_HDLC 14968 #endif 14969 #if SYNCLINK_GENERIC_HDLC 14970 #endif 14971 #if SYNCLINK_GENERIC_HDLC 14972 #endif 14973 #ifdef CMSPAR 14974 #endif 14975 #if SYNCLINK_GENERIC_HDLC 14976 #endif 14977 #if SYNCLINK_GENERIC_HDLC 14978 #endif 14979 #if 0 14980 #endif 14981 #if SYNCLINK_GENERIC_HDLC 14982 #endif 14983 #if SYNCLINK_GENERIC_HDLC 14984 #endif 14985 #define TESTFRAMESIZE 20 14986 #if SYNCLINK_GENERIC_HDLC 14987 #endif 14988 #define CALC_REGADDR() \ 14989 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 14990 if (info->port_num > 1) \ 14991 RegAddr += 256; \ 14992 if ( info->port_num & 1) { \ 14993 if (Addr > 0x7f) \ 14994 RegAddr += 0x40; \ 14995 else if (Addr > 0x1f && Addr < 0x60) \ 14996 RegAddr += 0x20; \ 14997 } 14998 /* LDV_COMMENT_END_PREP */ 14999 ldv_s_ops_tty_operations++; 15000 15001 } 15002 15003 } 15004 15005 break; 15006 case 10: { 15007 15008 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15009 if(ldv_s_ops_tty_operations==1) { 15010 15011 /* content: static void close(struct tty_struct *tty, struct file *filp)*/ 15012 /* LDV_COMMENT_BEGIN_PREP */ 15013 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15014 #if defined(__i386__) 15015 # define BREAKPOINT() asm(" int $3"); 15016 #else 15017 # define BREAKPOINT() { } 15018 #endif 15019 #define MAX_DEVICES 12 15020 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15021 #define SYNCLINK_GENERIC_HDLC 1 15022 #else 15023 #define SYNCLINK_GENERIC_HDLC 0 15024 #endif 15025 #define GET_USER(error,value,addr) error = get_user(value,addr) 15026 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15027 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15028 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15029 #define SCABUFSIZE 1024 15030 #define SCA_MEM_SIZE 0x40000 15031 #define SCA_BASE_SIZE 512 15032 #define SCA_REG_SIZE 16 15033 #define SCA_MAX_PORTS 4 15034 #define SCAMAXDESC 128 15035 #define BUFFERLISTSIZE 4096 15036 #define BH_RECEIVE 1 15037 #define BH_TRANSMIT 2 15038 #define BH_STATUS 4 15039 #define IO_PIN_SHUTDOWN_LIMIT 100 15040 #if SYNCLINK_GENERIC_HDLC 15041 #endif 15042 #define MGSL_MAGIC 0x5401 15043 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15044 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15045 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15046 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15047 #define LPR 0x00 15048 #define PABR0 0x02 15049 #define PABR1 0x03 15050 #define WCRL 0x04 15051 #define WCRM 0x05 15052 #define WCRH 0x06 15053 #define DPCR 0x08 15054 #define DMER 0x09 15055 #define ISR0 0x10 15056 #define ISR1 0x11 15057 #define ISR2 0x12 15058 #define IER0 0x14 15059 #define IER1 0x15 15060 #define IER2 0x16 15061 #define ITCR 0x18 15062 #define INTVR 0x1a 15063 #define IMVR 0x1c 15064 #define TRB 0x20 15065 #define TRBL 0x20 15066 #define TRBH 0x21 15067 #define SR0 0x22 15068 #define SR1 0x23 15069 #define SR2 0x24 15070 #define SR3 0x25 15071 #define FST 0x26 15072 #define IE0 0x28 15073 #define IE1 0x29 15074 #define IE2 0x2a 15075 #define FIE 0x2b 15076 #define CMD 0x2c 15077 #define MD0 0x2e 15078 #define MD1 0x2f 15079 #define MD2 0x30 15080 #define CTL 0x31 15081 #define SA0 0x32 15082 #define SA1 0x33 15083 #define IDL 0x34 15084 #define TMC 0x35 15085 #define RXS 0x36 15086 #define TXS 0x37 15087 #define TRC0 0x38 15088 #define TRC1 0x39 15089 #define RRC 0x3a 15090 #define CST0 0x3c 15091 #define CST1 0x3d 15092 #define TCNT 0x60 15093 #define TCNTL 0x60 15094 #define TCNTH 0x61 15095 #define TCONR 0x62 15096 #define TCONRL 0x62 15097 #define TCONRH 0x63 15098 #define TMCS 0x64 15099 #define TEPR 0x65 15100 #define DARL 0x80 15101 #define DARH 0x81 15102 #define DARB 0x82 15103 #define BAR 0x80 15104 #define BARL 0x80 15105 #define BARH 0x81 15106 #define BARB 0x82 15107 #define SAR 0x84 15108 #define SARL 0x84 15109 #define SARH 0x85 15110 #define SARB 0x86 15111 #define CPB 0x86 15112 #define CDA 0x88 15113 #define CDAL 0x88 15114 #define CDAH 0x89 15115 #define EDA 0x8a 15116 #define EDAL 0x8a 15117 #define EDAH 0x8b 15118 #define BFL 0x8c 15119 #define BFLL 0x8c 15120 #define BFLH 0x8d 15121 #define BCR 0x8e 15122 #define BCRL 0x8e 15123 #define BCRH 0x8f 15124 #define DSR 0x90 15125 #define DMR 0x91 15126 #define FCT 0x93 15127 #define DIR 0x94 15128 #define DCMD 0x95 15129 #define TIMER0 0x00 15130 #define TIMER1 0x08 15131 #define TIMER2 0x10 15132 #define TIMER3 0x18 15133 #define RXDMA 0x00 15134 #define TXDMA 0x20 15135 #define NOOP 0x00 15136 #define TXRESET 0x01 15137 #define TXENABLE 0x02 15138 #define TXDISABLE 0x03 15139 #define TXCRCINIT 0x04 15140 #define TXCRCEXCL 0x05 15141 #define TXEOM 0x06 15142 #define TXABORT 0x07 15143 #define MPON 0x08 15144 #define TXBUFCLR 0x09 15145 #define RXRESET 0x11 15146 #define RXENABLE 0x12 15147 #define RXDISABLE 0x13 15148 #define RXCRCINIT 0x14 15149 #define RXREJECT 0x15 15150 #define SEARCHMP 0x16 15151 #define RXCRCEXCL 0x17 15152 #define RXCRCCALC 0x18 15153 #define CHRESET 0x21 15154 #define HUNT 0x31 15155 #define SWABORT 0x01 15156 #define FEICLEAR 0x02 15157 #define TXINTE BIT7 15158 #define RXINTE BIT6 15159 #define TXRDYE BIT1 15160 #define RXRDYE BIT0 15161 #define UDRN BIT7 15162 #define IDLE BIT6 15163 #define SYNCD BIT4 15164 #define FLGD BIT4 15165 #define CCTS BIT3 15166 #define CDCD BIT2 15167 #define BRKD BIT1 15168 #define ABTD BIT1 15169 #define GAPD BIT1 15170 #define BRKE BIT0 15171 #define IDLD BIT0 15172 #define EOM BIT7 15173 #define PMP BIT6 15174 #define SHRT BIT6 15175 #define PE BIT5 15176 #define ABT BIT5 15177 #define FRME BIT4 15178 #define RBIT BIT4 15179 #define OVRN BIT3 15180 #define CRCE BIT2 15181 #define WAKEUP_CHARS 256 15182 #if SYNCLINK_GENERIC_HDLC 15183 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 15184 #endif 15185 #ifdef SANITY_CHECK 15186 #else 15187 #endif 15188 /* LDV_COMMENT_END_PREP */ 15189 /* LDV_COMMENT_FUNCTION_CALL Function from field "close" from driver structure with callbacks "ops" */ 15190 ldv_handler_precall(); 15191 close( var_group8, var_group3); 15192 /* LDV_COMMENT_BEGIN_PREP */ 15193 #if SYNCLINK_GENERIC_HDLC 15194 #endif 15195 #if SYNCLINK_GENERIC_HDLC 15196 #endif 15197 #if SYNCLINK_GENERIC_HDLC 15198 #endif 15199 #ifdef CMSPAR 15200 #endif 15201 #if SYNCLINK_GENERIC_HDLC 15202 #endif 15203 #if SYNCLINK_GENERIC_HDLC 15204 #endif 15205 #if 0 15206 #endif 15207 #if SYNCLINK_GENERIC_HDLC 15208 #endif 15209 #if SYNCLINK_GENERIC_HDLC 15210 #endif 15211 #define TESTFRAMESIZE 20 15212 #if SYNCLINK_GENERIC_HDLC 15213 #endif 15214 #define CALC_REGADDR() \ 15215 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 15216 if (info->port_num > 1) \ 15217 RegAddr += 256; \ 15218 if ( info->port_num & 1) { \ 15219 if (Addr > 0x7f) \ 15220 RegAddr += 0x40; \ 15221 else if (Addr > 0x1f && Addr < 0x60) \ 15222 RegAddr += 0x20; \ 15223 } 15224 /* LDV_COMMENT_END_PREP */ 15225 ldv_s_ops_tty_operations=0; 15226 15227 } 15228 15229 } 15230 15231 break; 15232 case 11: { 15233 15234 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15235 15236 15237 /* content: static int install(struct tty_driver *driver, struct tty_struct *tty)*/ 15238 /* LDV_COMMENT_BEGIN_PREP */ 15239 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15240 #if defined(__i386__) 15241 # define BREAKPOINT() asm(" int $3"); 15242 #else 15243 # define BREAKPOINT() { } 15244 #endif 15245 #define MAX_DEVICES 12 15246 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15247 #define SYNCLINK_GENERIC_HDLC 1 15248 #else 15249 #define SYNCLINK_GENERIC_HDLC 0 15250 #endif 15251 #define GET_USER(error,value,addr) error = get_user(value,addr) 15252 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15253 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15254 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15255 #define SCABUFSIZE 1024 15256 #define SCA_MEM_SIZE 0x40000 15257 #define SCA_BASE_SIZE 512 15258 #define SCA_REG_SIZE 16 15259 #define SCA_MAX_PORTS 4 15260 #define SCAMAXDESC 128 15261 #define BUFFERLISTSIZE 4096 15262 #define BH_RECEIVE 1 15263 #define BH_TRANSMIT 2 15264 #define BH_STATUS 4 15265 #define IO_PIN_SHUTDOWN_LIMIT 100 15266 #if SYNCLINK_GENERIC_HDLC 15267 #endif 15268 #define MGSL_MAGIC 0x5401 15269 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15270 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15271 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15272 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15273 #define LPR 0x00 15274 #define PABR0 0x02 15275 #define PABR1 0x03 15276 #define WCRL 0x04 15277 #define WCRM 0x05 15278 #define WCRH 0x06 15279 #define DPCR 0x08 15280 #define DMER 0x09 15281 #define ISR0 0x10 15282 #define ISR1 0x11 15283 #define ISR2 0x12 15284 #define IER0 0x14 15285 #define IER1 0x15 15286 #define IER2 0x16 15287 #define ITCR 0x18 15288 #define INTVR 0x1a 15289 #define IMVR 0x1c 15290 #define TRB 0x20 15291 #define TRBL 0x20 15292 #define TRBH 0x21 15293 #define SR0 0x22 15294 #define SR1 0x23 15295 #define SR2 0x24 15296 #define SR3 0x25 15297 #define FST 0x26 15298 #define IE0 0x28 15299 #define IE1 0x29 15300 #define IE2 0x2a 15301 #define FIE 0x2b 15302 #define CMD 0x2c 15303 #define MD0 0x2e 15304 #define MD1 0x2f 15305 #define MD2 0x30 15306 #define CTL 0x31 15307 #define SA0 0x32 15308 #define SA1 0x33 15309 #define IDL 0x34 15310 #define TMC 0x35 15311 #define RXS 0x36 15312 #define TXS 0x37 15313 #define TRC0 0x38 15314 #define TRC1 0x39 15315 #define RRC 0x3a 15316 #define CST0 0x3c 15317 #define CST1 0x3d 15318 #define TCNT 0x60 15319 #define TCNTL 0x60 15320 #define TCNTH 0x61 15321 #define TCONR 0x62 15322 #define TCONRL 0x62 15323 #define TCONRH 0x63 15324 #define TMCS 0x64 15325 #define TEPR 0x65 15326 #define DARL 0x80 15327 #define DARH 0x81 15328 #define DARB 0x82 15329 #define BAR 0x80 15330 #define BARL 0x80 15331 #define BARH 0x81 15332 #define BARB 0x82 15333 #define SAR 0x84 15334 #define SARL 0x84 15335 #define SARH 0x85 15336 #define SARB 0x86 15337 #define CPB 0x86 15338 #define CDA 0x88 15339 #define CDAL 0x88 15340 #define CDAH 0x89 15341 #define EDA 0x8a 15342 #define EDAL 0x8a 15343 #define EDAH 0x8b 15344 #define BFL 0x8c 15345 #define BFLL 0x8c 15346 #define BFLH 0x8d 15347 #define BCR 0x8e 15348 #define BCRL 0x8e 15349 #define BCRH 0x8f 15350 #define DSR 0x90 15351 #define DMR 0x91 15352 #define FCT 0x93 15353 #define DIR 0x94 15354 #define DCMD 0x95 15355 #define TIMER0 0x00 15356 #define TIMER1 0x08 15357 #define TIMER2 0x10 15358 #define TIMER3 0x18 15359 #define RXDMA 0x00 15360 #define TXDMA 0x20 15361 #define NOOP 0x00 15362 #define TXRESET 0x01 15363 #define TXENABLE 0x02 15364 #define TXDISABLE 0x03 15365 #define TXCRCINIT 0x04 15366 #define TXCRCEXCL 0x05 15367 #define TXEOM 0x06 15368 #define TXABORT 0x07 15369 #define MPON 0x08 15370 #define TXBUFCLR 0x09 15371 #define RXRESET 0x11 15372 #define RXENABLE 0x12 15373 #define RXDISABLE 0x13 15374 #define RXCRCINIT 0x14 15375 #define RXREJECT 0x15 15376 #define SEARCHMP 0x16 15377 #define RXCRCEXCL 0x17 15378 #define RXCRCCALC 0x18 15379 #define CHRESET 0x21 15380 #define HUNT 0x31 15381 #define SWABORT 0x01 15382 #define FEICLEAR 0x02 15383 #define TXINTE BIT7 15384 #define RXINTE BIT6 15385 #define TXRDYE BIT1 15386 #define RXRDYE BIT0 15387 #define UDRN BIT7 15388 #define IDLE BIT6 15389 #define SYNCD BIT4 15390 #define FLGD BIT4 15391 #define CCTS BIT3 15392 #define CDCD BIT2 15393 #define BRKD BIT1 15394 #define ABTD BIT1 15395 #define GAPD BIT1 15396 #define BRKE BIT0 15397 #define IDLD BIT0 15398 #define EOM BIT7 15399 #define PMP BIT6 15400 #define SHRT BIT6 15401 #define PE BIT5 15402 #define ABT BIT5 15403 #define FRME BIT4 15404 #define RBIT BIT4 15405 #define OVRN BIT3 15406 #define CRCE BIT2 15407 #define WAKEUP_CHARS 256 15408 #if SYNCLINK_GENERIC_HDLC 15409 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 15410 #endif 15411 #ifdef SANITY_CHECK 15412 #else 15413 #endif 15414 /* LDV_COMMENT_END_PREP */ 15415 /* LDV_COMMENT_FUNCTION_CALL Function from field "install" from driver structure with callbacks "ops" */ 15416 ldv_handler_precall(); 15417 install( var_group7, var_group8); 15418 /* LDV_COMMENT_BEGIN_PREP */ 15419 #if SYNCLINK_GENERIC_HDLC 15420 #endif 15421 #if SYNCLINK_GENERIC_HDLC 15422 #endif 15423 #if SYNCLINK_GENERIC_HDLC 15424 #endif 15425 #ifdef CMSPAR 15426 #endif 15427 #if SYNCLINK_GENERIC_HDLC 15428 #endif 15429 #if SYNCLINK_GENERIC_HDLC 15430 #endif 15431 #if 0 15432 #endif 15433 #if SYNCLINK_GENERIC_HDLC 15434 #endif 15435 #if SYNCLINK_GENERIC_HDLC 15436 #endif 15437 #define TESTFRAMESIZE 20 15438 #if SYNCLINK_GENERIC_HDLC 15439 #endif 15440 #define CALC_REGADDR() \ 15441 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 15442 if (info->port_num > 1) \ 15443 RegAddr += 256; \ 15444 if ( info->port_num & 1) { \ 15445 if (Addr > 0x7f) \ 15446 RegAddr += 0x40; \ 15447 else if (Addr > 0x1f && Addr < 0x60) \ 15448 RegAddr += 0x20; \ 15449 } 15450 /* LDV_COMMENT_END_PREP */ 15451 15452 15453 15454 15455 } 15456 15457 break; 15458 case 12: { 15459 15460 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15461 15462 15463 /* content: static int write(struct tty_struct *tty, const unsigned char *buf, int count)*/ 15464 /* LDV_COMMENT_BEGIN_PREP */ 15465 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15466 #if defined(__i386__) 15467 # define BREAKPOINT() asm(" int $3"); 15468 #else 15469 # define BREAKPOINT() { } 15470 #endif 15471 #define MAX_DEVICES 12 15472 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15473 #define SYNCLINK_GENERIC_HDLC 1 15474 #else 15475 #define SYNCLINK_GENERIC_HDLC 0 15476 #endif 15477 #define GET_USER(error,value,addr) error = get_user(value,addr) 15478 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15479 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15480 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15481 #define SCABUFSIZE 1024 15482 #define SCA_MEM_SIZE 0x40000 15483 #define SCA_BASE_SIZE 512 15484 #define SCA_REG_SIZE 16 15485 #define SCA_MAX_PORTS 4 15486 #define SCAMAXDESC 128 15487 #define BUFFERLISTSIZE 4096 15488 #define BH_RECEIVE 1 15489 #define BH_TRANSMIT 2 15490 #define BH_STATUS 4 15491 #define IO_PIN_SHUTDOWN_LIMIT 100 15492 #if SYNCLINK_GENERIC_HDLC 15493 #endif 15494 #define MGSL_MAGIC 0x5401 15495 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15496 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15497 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15498 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15499 #define LPR 0x00 15500 #define PABR0 0x02 15501 #define PABR1 0x03 15502 #define WCRL 0x04 15503 #define WCRM 0x05 15504 #define WCRH 0x06 15505 #define DPCR 0x08 15506 #define DMER 0x09 15507 #define ISR0 0x10 15508 #define ISR1 0x11 15509 #define ISR2 0x12 15510 #define IER0 0x14 15511 #define IER1 0x15 15512 #define IER2 0x16 15513 #define ITCR 0x18 15514 #define INTVR 0x1a 15515 #define IMVR 0x1c 15516 #define TRB 0x20 15517 #define TRBL 0x20 15518 #define TRBH 0x21 15519 #define SR0 0x22 15520 #define SR1 0x23 15521 #define SR2 0x24 15522 #define SR3 0x25 15523 #define FST 0x26 15524 #define IE0 0x28 15525 #define IE1 0x29 15526 #define IE2 0x2a 15527 #define FIE 0x2b 15528 #define CMD 0x2c 15529 #define MD0 0x2e 15530 #define MD1 0x2f 15531 #define MD2 0x30 15532 #define CTL 0x31 15533 #define SA0 0x32 15534 #define SA1 0x33 15535 #define IDL 0x34 15536 #define TMC 0x35 15537 #define RXS 0x36 15538 #define TXS 0x37 15539 #define TRC0 0x38 15540 #define TRC1 0x39 15541 #define RRC 0x3a 15542 #define CST0 0x3c 15543 #define CST1 0x3d 15544 #define TCNT 0x60 15545 #define TCNTL 0x60 15546 #define TCNTH 0x61 15547 #define TCONR 0x62 15548 #define TCONRL 0x62 15549 #define TCONRH 0x63 15550 #define TMCS 0x64 15551 #define TEPR 0x65 15552 #define DARL 0x80 15553 #define DARH 0x81 15554 #define DARB 0x82 15555 #define BAR 0x80 15556 #define BARL 0x80 15557 #define BARH 0x81 15558 #define BARB 0x82 15559 #define SAR 0x84 15560 #define SARL 0x84 15561 #define SARH 0x85 15562 #define SARB 0x86 15563 #define CPB 0x86 15564 #define CDA 0x88 15565 #define CDAL 0x88 15566 #define CDAH 0x89 15567 #define EDA 0x8a 15568 #define EDAL 0x8a 15569 #define EDAH 0x8b 15570 #define BFL 0x8c 15571 #define BFLL 0x8c 15572 #define BFLH 0x8d 15573 #define BCR 0x8e 15574 #define BCRL 0x8e 15575 #define BCRH 0x8f 15576 #define DSR 0x90 15577 #define DMR 0x91 15578 #define FCT 0x93 15579 #define DIR 0x94 15580 #define DCMD 0x95 15581 #define TIMER0 0x00 15582 #define TIMER1 0x08 15583 #define TIMER2 0x10 15584 #define TIMER3 0x18 15585 #define RXDMA 0x00 15586 #define TXDMA 0x20 15587 #define NOOP 0x00 15588 #define TXRESET 0x01 15589 #define TXENABLE 0x02 15590 #define TXDISABLE 0x03 15591 #define TXCRCINIT 0x04 15592 #define TXCRCEXCL 0x05 15593 #define TXEOM 0x06 15594 #define TXABORT 0x07 15595 #define MPON 0x08 15596 #define TXBUFCLR 0x09 15597 #define RXRESET 0x11 15598 #define RXENABLE 0x12 15599 #define RXDISABLE 0x13 15600 #define RXCRCINIT 0x14 15601 #define RXREJECT 0x15 15602 #define SEARCHMP 0x16 15603 #define RXCRCEXCL 0x17 15604 #define RXCRCCALC 0x18 15605 #define CHRESET 0x21 15606 #define HUNT 0x31 15607 #define SWABORT 0x01 15608 #define FEICLEAR 0x02 15609 #define TXINTE BIT7 15610 #define RXINTE BIT6 15611 #define TXRDYE BIT1 15612 #define RXRDYE BIT0 15613 #define UDRN BIT7 15614 #define IDLE BIT6 15615 #define SYNCD BIT4 15616 #define FLGD BIT4 15617 #define CCTS BIT3 15618 #define CDCD BIT2 15619 #define BRKD BIT1 15620 #define ABTD BIT1 15621 #define GAPD BIT1 15622 #define BRKE BIT0 15623 #define IDLD BIT0 15624 #define EOM BIT7 15625 #define PMP BIT6 15626 #define SHRT BIT6 15627 #define PE BIT5 15628 #define ABT BIT5 15629 #define FRME BIT4 15630 #define RBIT BIT4 15631 #define OVRN BIT3 15632 #define CRCE BIT2 15633 #define WAKEUP_CHARS 256 15634 #if SYNCLINK_GENERIC_HDLC 15635 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 15636 #endif 15637 #ifdef SANITY_CHECK 15638 #else 15639 #endif 15640 /* LDV_COMMENT_END_PREP */ 15641 /* LDV_COMMENT_FUNCTION_CALL Function from field "write" from driver structure with callbacks "ops" */ 15642 ldv_handler_precall(); 15643 write( var_group8, var_write_8_p1, var_write_8_p2); 15644 /* LDV_COMMENT_BEGIN_PREP */ 15645 #if SYNCLINK_GENERIC_HDLC 15646 #endif 15647 #if SYNCLINK_GENERIC_HDLC 15648 #endif 15649 #if SYNCLINK_GENERIC_HDLC 15650 #endif 15651 #ifdef CMSPAR 15652 #endif 15653 #if SYNCLINK_GENERIC_HDLC 15654 #endif 15655 #if SYNCLINK_GENERIC_HDLC 15656 #endif 15657 #if 0 15658 #endif 15659 #if SYNCLINK_GENERIC_HDLC 15660 #endif 15661 #if SYNCLINK_GENERIC_HDLC 15662 #endif 15663 #define TESTFRAMESIZE 20 15664 #if SYNCLINK_GENERIC_HDLC 15665 #endif 15666 #define CALC_REGADDR() \ 15667 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 15668 if (info->port_num > 1) \ 15669 RegAddr += 256; \ 15670 if ( info->port_num & 1) { \ 15671 if (Addr > 0x7f) \ 15672 RegAddr += 0x40; \ 15673 else if (Addr > 0x1f && Addr < 0x60) \ 15674 RegAddr += 0x20; \ 15675 } 15676 /* LDV_COMMENT_END_PREP */ 15677 15678 15679 15680 15681 } 15682 15683 break; 15684 case 13: { 15685 15686 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15687 15688 15689 /* content: static int put_char(struct tty_struct *tty, unsigned char ch)*/ 15690 /* LDV_COMMENT_BEGIN_PREP */ 15691 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15692 #if defined(__i386__) 15693 # define BREAKPOINT() asm(" int $3"); 15694 #else 15695 # define BREAKPOINT() { } 15696 #endif 15697 #define MAX_DEVICES 12 15698 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15699 #define SYNCLINK_GENERIC_HDLC 1 15700 #else 15701 #define SYNCLINK_GENERIC_HDLC 0 15702 #endif 15703 #define GET_USER(error,value,addr) error = get_user(value,addr) 15704 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15705 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15706 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15707 #define SCABUFSIZE 1024 15708 #define SCA_MEM_SIZE 0x40000 15709 #define SCA_BASE_SIZE 512 15710 #define SCA_REG_SIZE 16 15711 #define SCA_MAX_PORTS 4 15712 #define SCAMAXDESC 128 15713 #define BUFFERLISTSIZE 4096 15714 #define BH_RECEIVE 1 15715 #define BH_TRANSMIT 2 15716 #define BH_STATUS 4 15717 #define IO_PIN_SHUTDOWN_LIMIT 100 15718 #if SYNCLINK_GENERIC_HDLC 15719 #endif 15720 #define MGSL_MAGIC 0x5401 15721 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15722 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15723 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15724 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15725 #define LPR 0x00 15726 #define PABR0 0x02 15727 #define PABR1 0x03 15728 #define WCRL 0x04 15729 #define WCRM 0x05 15730 #define WCRH 0x06 15731 #define DPCR 0x08 15732 #define DMER 0x09 15733 #define ISR0 0x10 15734 #define ISR1 0x11 15735 #define ISR2 0x12 15736 #define IER0 0x14 15737 #define IER1 0x15 15738 #define IER2 0x16 15739 #define ITCR 0x18 15740 #define INTVR 0x1a 15741 #define IMVR 0x1c 15742 #define TRB 0x20 15743 #define TRBL 0x20 15744 #define TRBH 0x21 15745 #define SR0 0x22 15746 #define SR1 0x23 15747 #define SR2 0x24 15748 #define SR3 0x25 15749 #define FST 0x26 15750 #define IE0 0x28 15751 #define IE1 0x29 15752 #define IE2 0x2a 15753 #define FIE 0x2b 15754 #define CMD 0x2c 15755 #define MD0 0x2e 15756 #define MD1 0x2f 15757 #define MD2 0x30 15758 #define CTL 0x31 15759 #define SA0 0x32 15760 #define SA1 0x33 15761 #define IDL 0x34 15762 #define TMC 0x35 15763 #define RXS 0x36 15764 #define TXS 0x37 15765 #define TRC0 0x38 15766 #define TRC1 0x39 15767 #define RRC 0x3a 15768 #define CST0 0x3c 15769 #define CST1 0x3d 15770 #define TCNT 0x60 15771 #define TCNTL 0x60 15772 #define TCNTH 0x61 15773 #define TCONR 0x62 15774 #define TCONRL 0x62 15775 #define TCONRH 0x63 15776 #define TMCS 0x64 15777 #define TEPR 0x65 15778 #define DARL 0x80 15779 #define DARH 0x81 15780 #define DARB 0x82 15781 #define BAR 0x80 15782 #define BARL 0x80 15783 #define BARH 0x81 15784 #define BARB 0x82 15785 #define SAR 0x84 15786 #define SARL 0x84 15787 #define SARH 0x85 15788 #define SARB 0x86 15789 #define CPB 0x86 15790 #define CDA 0x88 15791 #define CDAL 0x88 15792 #define CDAH 0x89 15793 #define EDA 0x8a 15794 #define EDAL 0x8a 15795 #define EDAH 0x8b 15796 #define BFL 0x8c 15797 #define BFLL 0x8c 15798 #define BFLH 0x8d 15799 #define BCR 0x8e 15800 #define BCRL 0x8e 15801 #define BCRH 0x8f 15802 #define DSR 0x90 15803 #define DMR 0x91 15804 #define FCT 0x93 15805 #define DIR 0x94 15806 #define DCMD 0x95 15807 #define TIMER0 0x00 15808 #define TIMER1 0x08 15809 #define TIMER2 0x10 15810 #define TIMER3 0x18 15811 #define RXDMA 0x00 15812 #define TXDMA 0x20 15813 #define NOOP 0x00 15814 #define TXRESET 0x01 15815 #define TXENABLE 0x02 15816 #define TXDISABLE 0x03 15817 #define TXCRCINIT 0x04 15818 #define TXCRCEXCL 0x05 15819 #define TXEOM 0x06 15820 #define TXABORT 0x07 15821 #define MPON 0x08 15822 #define TXBUFCLR 0x09 15823 #define RXRESET 0x11 15824 #define RXENABLE 0x12 15825 #define RXDISABLE 0x13 15826 #define RXCRCINIT 0x14 15827 #define RXREJECT 0x15 15828 #define SEARCHMP 0x16 15829 #define RXCRCEXCL 0x17 15830 #define RXCRCCALC 0x18 15831 #define CHRESET 0x21 15832 #define HUNT 0x31 15833 #define SWABORT 0x01 15834 #define FEICLEAR 0x02 15835 #define TXINTE BIT7 15836 #define RXINTE BIT6 15837 #define TXRDYE BIT1 15838 #define RXRDYE BIT0 15839 #define UDRN BIT7 15840 #define IDLE BIT6 15841 #define SYNCD BIT4 15842 #define FLGD BIT4 15843 #define CCTS BIT3 15844 #define CDCD BIT2 15845 #define BRKD BIT1 15846 #define ABTD BIT1 15847 #define GAPD BIT1 15848 #define BRKE BIT0 15849 #define IDLD BIT0 15850 #define EOM BIT7 15851 #define PMP BIT6 15852 #define SHRT BIT6 15853 #define PE BIT5 15854 #define ABT BIT5 15855 #define FRME BIT4 15856 #define RBIT BIT4 15857 #define OVRN BIT3 15858 #define CRCE BIT2 15859 #define WAKEUP_CHARS 256 15860 #if SYNCLINK_GENERIC_HDLC 15861 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 15862 #endif 15863 #ifdef SANITY_CHECK 15864 #else 15865 #endif 15866 /* LDV_COMMENT_END_PREP */ 15867 /* LDV_COMMENT_FUNCTION_CALL Function from field "put_char" from driver structure with callbacks "ops" */ 15868 ldv_handler_precall(); 15869 put_char( var_group8, var_put_char_9_p1); 15870 /* LDV_COMMENT_BEGIN_PREP */ 15871 #if SYNCLINK_GENERIC_HDLC 15872 #endif 15873 #if SYNCLINK_GENERIC_HDLC 15874 #endif 15875 #if SYNCLINK_GENERIC_HDLC 15876 #endif 15877 #ifdef CMSPAR 15878 #endif 15879 #if SYNCLINK_GENERIC_HDLC 15880 #endif 15881 #if SYNCLINK_GENERIC_HDLC 15882 #endif 15883 #if 0 15884 #endif 15885 #if SYNCLINK_GENERIC_HDLC 15886 #endif 15887 #if SYNCLINK_GENERIC_HDLC 15888 #endif 15889 #define TESTFRAMESIZE 20 15890 #if SYNCLINK_GENERIC_HDLC 15891 #endif 15892 #define CALC_REGADDR() \ 15893 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 15894 if (info->port_num > 1) \ 15895 RegAddr += 256; \ 15896 if ( info->port_num & 1) { \ 15897 if (Addr > 0x7f) \ 15898 RegAddr += 0x40; \ 15899 else if (Addr > 0x1f && Addr < 0x60) \ 15900 RegAddr += 0x20; \ 15901 } 15902 /* LDV_COMMENT_END_PREP */ 15903 15904 15905 15906 15907 } 15908 15909 break; 15910 case 14: { 15911 15912 /** STRUCT: struct type: tty_operations, struct name: ops **/ 15913 15914 15915 /* content: static void flush_chars(struct tty_struct *tty)*/ 15916 /* LDV_COMMENT_BEGIN_PREP */ 15917 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 15918 #if defined(__i386__) 15919 # define BREAKPOINT() asm(" int $3"); 15920 #else 15921 # define BREAKPOINT() { } 15922 #endif 15923 #define MAX_DEVICES 12 15924 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 15925 #define SYNCLINK_GENERIC_HDLC 1 15926 #else 15927 #define SYNCLINK_GENERIC_HDLC 0 15928 #endif 15929 #define GET_USER(error,value,addr) error = get_user(value,addr) 15930 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 15931 #define PUT_USER(error,value,addr) error = put_user(value,addr) 15932 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 15933 #define SCABUFSIZE 1024 15934 #define SCA_MEM_SIZE 0x40000 15935 #define SCA_BASE_SIZE 512 15936 #define SCA_REG_SIZE 16 15937 #define SCA_MAX_PORTS 4 15938 #define SCAMAXDESC 128 15939 #define BUFFERLISTSIZE 4096 15940 #define BH_RECEIVE 1 15941 #define BH_TRANSMIT 2 15942 #define BH_STATUS 4 15943 #define IO_PIN_SHUTDOWN_LIMIT 100 15944 #if SYNCLINK_GENERIC_HDLC 15945 #endif 15946 #define MGSL_MAGIC 0x5401 15947 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 15948 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 15949 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 15950 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 15951 #define LPR 0x00 15952 #define PABR0 0x02 15953 #define PABR1 0x03 15954 #define WCRL 0x04 15955 #define WCRM 0x05 15956 #define WCRH 0x06 15957 #define DPCR 0x08 15958 #define DMER 0x09 15959 #define ISR0 0x10 15960 #define ISR1 0x11 15961 #define ISR2 0x12 15962 #define IER0 0x14 15963 #define IER1 0x15 15964 #define IER2 0x16 15965 #define ITCR 0x18 15966 #define INTVR 0x1a 15967 #define IMVR 0x1c 15968 #define TRB 0x20 15969 #define TRBL 0x20 15970 #define TRBH 0x21 15971 #define SR0 0x22 15972 #define SR1 0x23 15973 #define SR2 0x24 15974 #define SR3 0x25 15975 #define FST 0x26 15976 #define IE0 0x28 15977 #define IE1 0x29 15978 #define IE2 0x2a 15979 #define FIE 0x2b 15980 #define CMD 0x2c 15981 #define MD0 0x2e 15982 #define MD1 0x2f 15983 #define MD2 0x30 15984 #define CTL 0x31 15985 #define SA0 0x32 15986 #define SA1 0x33 15987 #define IDL 0x34 15988 #define TMC 0x35 15989 #define RXS 0x36 15990 #define TXS 0x37 15991 #define TRC0 0x38 15992 #define TRC1 0x39 15993 #define RRC 0x3a 15994 #define CST0 0x3c 15995 #define CST1 0x3d 15996 #define TCNT 0x60 15997 #define TCNTL 0x60 15998 #define TCNTH 0x61 15999 #define TCONR 0x62 16000 #define TCONRL 0x62 16001 #define TCONRH 0x63 16002 #define TMCS 0x64 16003 #define TEPR 0x65 16004 #define DARL 0x80 16005 #define DARH 0x81 16006 #define DARB 0x82 16007 #define BAR 0x80 16008 #define BARL 0x80 16009 #define BARH 0x81 16010 #define BARB 0x82 16011 #define SAR 0x84 16012 #define SARL 0x84 16013 #define SARH 0x85 16014 #define SARB 0x86 16015 #define CPB 0x86 16016 #define CDA 0x88 16017 #define CDAL 0x88 16018 #define CDAH 0x89 16019 #define EDA 0x8a 16020 #define EDAL 0x8a 16021 #define EDAH 0x8b 16022 #define BFL 0x8c 16023 #define BFLL 0x8c 16024 #define BFLH 0x8d 16025 #define BCR 0x8e 16026 #define BCRL 0x8e 16027 #define BCRH 0x8f 16028 #define DSR 0x90 16029 #define DMR 0x91 16030 #define FCT 0x93 16031 #define DIR 0x94 16032 #define DCMD 0x95 16033 #define TIMER0 0x00 16034 #define TIMER1 0x08 16035 #define TIMER2 0x10 16036 #define TIMER3 0x18 16037 #define RXDMA 0x00 16038 #define TXDMA 0x20 16039 #define NOOP 0x00 16040 #define TXRESET 0x01 16041 #define TXENABLE 0x02 16042 #define TXDISABLE 0x03 16043 #define TXCRCINIT 0x04 16044 #define TXCRCEXCL 0x05 16045 #define TXEOM 0x06 16046 #define TXABORT 0x07 16047 #define MPON 0x08 16048 #define TXBUFCLR 0x09 16049 #define RXRESET 0x11 16050 #define RXENABLE 0x12 16051 #define RXDISABLE 0x13 16052 #define RXCRCINIT 0x14 16053 #define RXREJECT 0x15 16054 #define SEARCHMP 0x16 16055 #define RXCRCEXCL 0x17 16056 #define RXCRCCALC 0x18 16057 #define CHRESET 0x21 16058 #define HUNT 0x31 16059 #define SWABORT 0x01 16060 #define FEICLEAR 0x02 16061 #define TXINTE BIT7 16062 #define RXINTE BIT6 16063 #define TXRDYE BIT1 16064 #define RXRDYE BIT0 16065 #define UDRN BIT7 16066 #define IDLE BIT6 16067 #define SYNCD BIT4 16068 #define FLGD BIT4 16069 #define CCTS BIT3 16070 #define CDCD BIT2 16071 #define BRKD BIT1 16072 #define ABTD BIT1 16073 #define GAPD BIT1 16074 #define BRKE BIT0 16075 #define IDLD BIT0 16076 #define EOM BIT7 16077 #define PMP BIT6 16078 #define SHRT BIT6 16079 #define PE BIT5 16080 #define ABT BIT5 16081 #define FRME BIT4 16082 #define RBIT BIT4 16083 #define OVRN BIT3 16084 #define CRCE BIT2 16085 #define WAKEUP_CHARS 256 16086 #if SYNCLINK_GENERIC_HDLC 16087 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16088 #endif 16089 #ifdef SANITY_CHECK 16090 #else 16091 #endif 16092 /* LDV_COMMENT_END_PREP */ 16093 /* LDV_COMMENT_FUNCTION_CALL Function from field "flush_chars" from driver structure with callbacks "ops" */ 16094 ldv_handler_precall(); 16095 flush_chars( var_group8); 16096 /* LDV_COMMENT_BEGIN_PREP */ 16097 #if SYNCLINK_GENERIC_HDLC 16098 #endif 16099 #if SYNCLINK_GENERIC_HDLC 16100 #endif 16101 #if SYNCLINK_GENERIC_HDLC 16102 #endif 16103 #ifdef CMSPAR 16104 #endif 16105 #if SYNCLINK_GENERIC_HDLC 16106 #endif 16107 #if SYNCLINK_GENERIC_HDLC 16108 #endif 16109 #if 0 16110 #endif 16111 #if SYNCLINK_GENERIC_HDLC 16112 #endif 16113 #if SYNCLINK_GENERIC_HDLC 16114 #endif 16115 #define TESTFRAMESIZE 20 16116 #if SYNCLINK_GENERIC_HDLC 16117 #endif 16118 #define CALC_REGADDR() \ 16119 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 16120 if (info->port_num > 1) \ 16121 RegAddr += 256; \ 16122 if ( info->port_num & 1) { \ 16123 if (Addr > 0x7f) \ 16124 RegAddr += 0x40; \ 16125 else if (Addr > 0x1f && Addr < 0x60) \ 16126 RegAddr += 0x20; \ 16127 } 16128 /* LDV_COMMENT_END_PREP */ 16129 16130 16131 16132 16133 } 16134 16135 break; 16136 case 15: { 16137 16138 /** STRUCT: struct type: tty_operations, struct name: ops **/ 16139 16140 16141 /* content: static int write_room(struct tty_struct *tty)*/ 16142 /* LDV_COMMENT_BEGIN_PREP */ 16143 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 16144 #if defined(__i386__) 16145 # define BREAKPOINT() asm(" int $3"); 16146 #else 16147 # define BREAKPOINT() { } 16148 #endif 16149 #define MAX_DEVICES 12 16150 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 16151 #define SYNCLINK_GENERIC_HDLC 1 16152 #else 16153 #define SYNCLINK_GENERIC_HDLC 0 16154 #endif 16155 #define GET_USER(error,value,addr) error = get_user(value,addr) 16156 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 16157 #define PUT_USER(error,value,addr) error = put_user(value,addr) 16158 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 16159 #define SCABUFSIZE 1024 16160 #define SCA_MEM_SIZE 0x40000 16161 #define SCA_BASE_SIZE 512 16162 #define SCA_REG_SIZE 16 16163 #define SCA_MAX_PORTS 4 16164 #define SCAMAXDESC 128 16165 #define BUFFERLISTSIZE 4096 16166 #define BH_RECEIVE 1 16167 #define BH_TRANSMIT 2 16168 #define BH_STATUS 4 16169 #define IO_PIN_SHUTDOWN_LIMIT 100 16170 #if SYNCLINK_GENERIC_HDLC 16171 #endif 16172 #define MGSL_MAGIC 0x5401 16173 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 16174 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 16175 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 16176 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 16177 #define LPR 0x00 16178 #define PABR0 0x02 16179 #define PABR1 0x03 16180 #define WCRL 0x04 16181 #define WCRM 0x05 16182 #define WCRH 0x06 16183 #define DPCR 0x08 16184 #define DMER 0x09 16185 #define ISR0 0x10 16186 #define ISR1 0x11 16187 #define ISR2 0x12 16188 #define IER0 0x14 16189 #define IER1 0x15 16190 #define IER2 0x16 16191 #define ITCR 0x18 16192 #define INTVR 0x1a 16193 #define IMVR 0x1c 16194 #define TRB 0x20 16195 #define TRBL 0x20 16196 #define TRBH 0x21 16197 #define SR0 0x22 16198 #define SR1 0x23 16199 #define SR2 0x24 16200 #define SR3 0x25 16201 #define FST 0x26 16202 #define IE0 0x28 16203 #define IE1 0x29 16204 #define IE2 0x2a 16205 #define FIE 0x2b 16206 #define CMD 0x2c 16207 #define MD0 0x2e 16208 #define MD1 0x2f 16209 #define MD2 0x30 16210 #define CTL 0x31 16211 #define SA0 0x32 16212 #define SA1 0x33 16213 #define IDL 0x34 16214 #define TMC 0x35 16215 #define RXS 0x36 16216 #define TXS 0x37 16217 #define TRC0 0x38 16218 #define TRC1 0x39 16219 #define RRC 0x3a 16220 #define CST0 0x3c 16221 #define CST1 0x3d 16222 #define TCNT 0x60 16223 #define TCNTL 0x60 16224 #define TCNTH 0x61 16225 #define TCONR 0x62 16226 #define TCONRL 0x62 16227 #define TCONRH 0x63 16228 #define TMCS 0x64 16229 #define TEPR 0x65 16230 #define DARL 0x80 16231 #define DARH 0x81 16232 #define DARB 0x82 16233 #define BAR 0x80 16234 #define BARL 0x80 16235 #define BARH 0x81 16236 #define BARB 0x82 16237 #define SAR 0x84 16238 #define SARL 0x84 16239 #define SARH 0x85 16240 #define SARB 0x86 16241 #define CPB 0x86 16242 #define CDA 0x88 16243 #define CDAL 0x88 16244 #define CDAH 0x89 16245 #define EDA 0x8a 16246 #define EDAL 0x8a 16247 #define EDAH 0x8b 16248 #define BFL 0x8c 16249 #define BFLL 0x8c 16250 #define BFLH 0x8d 16251 #define BCR 0x8e 16252 #define BCRL 0x8e 16253 #define BCRH 0x8f 16254 #define DSR 0x90 16255 #define DMR 0x91 16256 #define FCT 0x93 16257 #define DIR 0x94 16258 #define DCMD 0x95 16259 #define TIMER0 0x00 16260 #define TIMER1 0x08 16261 #define TIMER2 0x10 16262 #define TIMER3 0x18 16263 #define RXDMA 0x00 16264 #define TXDMA 0x20 16265 #define NOOP 0x00 16266 #define TXRESET 0x01 16267 #define TXENABLE 0x02 16268 #define TXDISABLE 0x03 16269 #define TXCRCINIT 0x04 16270 #define TXCRCEXCL 0x05 16271 #define TXEOM 0x06 16272 #define TXABORT 0x07 16273 #define MPON 0x08 16274 #define TXBUFCLR 0x09 16275 #define RXRESET 0x11 16276 #define RXENABLE 0x12 16277 #define RXDISABLE 0x13 16278 #define RXCRCINIT 0x14 16279 #define RXREJECT 0x15 16280 #define SEARCHMP 0x16 16281 #define RXCRCEXCL 0x17 16282 #define RXCRCCALC 0x18 16283 #define CHRESET 0x21 16284 #define HUNT 0x31 16285 #define SWABORT 0x01 16286 #define FEICLEAR 0x02 16287 #define TXINTE BIT7 16288 #define RXINTE BIT6 16289 #define TXRDYE BIT1 16290 #define RXRDYE BIT0 16291 #define UDRN BIT7 16292 #define IDLE BIT6 16293 #define SYNCD BIT4 16294 #define FLGD BIT4 16295 #define CCTS BIT3 16296 #define CDCD BIT2 16297 #define BRKD BIT1 16298 #define ABTD BIT1 16299 #define GAPD BIT1 16300 #define BRKE BIT0 16301 #define IDLD BIT0 16302 #define EOM BIT7 16303 #define PMP BIT6 16304 #define SHRT BIT6 16305 #define PE BIT5 16306 #define ABT BIT5 16307 #define FRME BIT4 16308 #define RBIT BIT4 16309 #define OVRN BIT3 16310 #define CRCE BIT2 16311 #define WAKEUP_CHARS 256 16312 #if SYNCLINK_GENERIC_HDLC 16313 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16314 #endif 16315 #ifdef SANITY_CHECK 16316 #else 16317 #endif 16318 /* LDV_COMMENT_END_PREP */ 16319 /* LDV_COMMENT_FUNCTION_CALL Function from field "write_room" from driver structure with callbacks "ops" */ 16320 ldv_handler_precall(); 16321 write_room( var_group8); 16322 /* LDV_COMMENT_BEGIN_PREP */ 16323 #if SYNCLINK_GENERIC_HDLC 16324 #endif 16325 #if SYNCLINK_GENERIC_HDLC 16326 #endif 16327 #if SYNCLINK_GENERIC_HDLC 16328 #endif 16329 #ifdef CMSPAR 16330 #endif 16331 #if SYNCLINK_GENERIC_HDLC 16332 #endif 16333 #if SYNCLINK_GENERIC_HDLC 16334 #endif 16335 #if 0 16336 #endif 16337 #if SYNCLINK_GENERIC_HDLC 16338 #endif 16339 #if SYNCLINK_GENERIC_HDLC 16340 #endif 16341 #define TESTFRAMESIZE 20 16342 #if SYNCLINK_GENERIC_HDLC 16343 #endif 16344 #define CALC_REGADDR() \ 16345 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 16346 if (info->port_num > 1) \ 16347 RegAddr += 256; \ 16348 if ( info->port_num & 1) { \ 16349 if (Addr > 0x7f) \ 16350 RegAddr += 0x40; \ 16351 else if (Addr > 0x1f && Addr < 0x60) \ 16352 RegAddr += 0x20; \ 16353 } 16354 /* LDV_COMMENT_END_PREP */ 16355 16356 16357 16358 16359 } 16360 16361 break; 16362 case 16: { 16363 16364 /** STRUCT: struct type: tty_operations, struct name: ops **/ 16365 16366 16367 /* content: static int chars_in_buffer(struct tty_struct *tty)*/ 16368 /* LDV_COMMENT_BEGIN_PREP */ 16369 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 16370 #if defined(__i386__) 16371 # define BREAKPOINT() asm(" int $3"); 16372 #else 16373 # define BREAKPOINT() { } 16374 #endif 16375 #define MAX_DEVICES 12 16376 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 16377 #define SYNCLINK_GENERIC_HDLC 1 16378 #else 16379 #define SYNCLINK_GENERIC_HDLC 0 16380 #endif 16381 #define GET_USER(error,value,addr) error = get_user(value,addr) 16382 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 16383 #define PUT_USER(error,value,addr) error = put_user(value,addr) 16384 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 16385 #define SCABUFSIZE 1024 16386 #define SCA_MEM_SIZE 0x40000 16387 #define SCA_BASE_SIZE 512 16388 #define SCA_REG_SIZE 16 16389 #define SCA_MAX_PORTS 4 16390 #define SCAMAXDESC 128 16391 #define BUFFERLISTSIZE 4096 16392 #define BH_RECEIVE 1 16393 #define BH_TRANSMIT 2 16394 #define BH_STATUS 4 16395 #define IO_PIN_SHUTDOWN_LIMIT 100 16396 #if SYNCLINK_GENERIC_HDLC 16397 #endif 16398 #define MGSL_MAGIC 0x5401 16399 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 16400 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 16401 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 16402 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 16403 #define LPR 0x00 16404 #define PABR0 0x02 16405 #define PABR1 0x03 16406 #define WCRL 0x04 16407 #define WCRM 0x05 16408 #define WCRH 0x06 16409 #define DPCR 0x08 16410 #define DMER 0x09 16411 #define ISR0 0x10 16412 #define ISR1 0x11 16413 #define ISR2 0x12 16414 #define IER0 0x14 16415 #define IER1 0x15 16416 #define IER2 0x16 16417 #define ITCR 0x18 16418 #define INTVR 0x1a 16419 #define IMVR 0x1c 16420 #define TRB 0x20 16421 #define TRBL 0x20 16422 #define TRBH 0x21 16423 #define SR0 0x22 16424 #define SR1 0x23 16425 #define SR2 0x24 16426 #define SR3 0x25 16427 #define FST 0x26 16428 #define IE0 0x28 16429 #define IE1 0x29 16430 #define IE2 0x2a 16431 #define FIE 0x2b 16432 #define CMD 0x2c 16433 #define MD0 0x2e 16434 #define MD1 0x2f 16435 #define MD2 0x30 16436 #define CTL 0x31 16437 #define SA0 0x32 16438 #define SA1 0x33 16439 #define IDL 0x34 16440 #define TMC 0x35 16441 #define RXS 0x36 16442 #define TXS 0x37 16443 #define TRC0 0x38 16444 #define TRC1 0x39 16445 #define RRC 0x3a 16446 #define CST0 0x3c 16447 #define CST1 0x3d 16448 #define TCNT 0x60 16449 #define TCNTL 0x60 16450 #define TCNTH 0x61 16451 #define TCONR 0x62 16452 #define TCONRL 0x62 16453 #define TCONRH 0x63 16454 #define TMCS 0x64 16455 #define TEPR 0x65 16456 #define DARL 0x80 16457 #define DARH 0x81 16458 #define DARB 0x82 16459 #define BAR 0x80 16460 #define BARL 0x80 16461 #define BARH 0x81 16462 #define BARB 0x82 16463 #define SAR 0x84 16464 #define SARL 0x84 16465 #define SARH 0x85 16466 #define SARB 0x86 16467 #define CPB 0x86 16468 #define CDA 0x88 16469 #define CDAL 0x88 16470 #define CDAH 0x89 16471 #define EDA 0x8a 16472 #define EDAL 0x8a 16473 #define EDAH 0x8b 16474 #define BFL 0x8c 16475 #define BFLL 0x8c 16476 #define BFLH 0x8d 16477 #define BCR 0x8e 16478 #define BCRL 0x8e 16479 #define BCRH 0x8f 16480 #define DSR 0x90 16481 #define DMR 0x91 16482 #define FCT 0x93 16483 #define DIR 0x94 16484 #define DCMD 0x95 16485 #define TIMER0 0x00 16486 #define TIMER1 0x08 16487 #define TIMER2 0x10 16488 #define TIMER3 0x18 16489 #define RXDMA 0x00 16490 #define TXDMA 0x20 16491 #define NOOP 0x00 16492 #define TXRESET 0x01 16493 #define TXENABLE 0x02 16494 #define TXDISABLE 0x03 16495 #define TXCRCINIT 0x04 16496 #define TXCRCEXCL 0x05 16497 #define TXEOM 0x06 16498 #define TXABORT 0x07 16499 #define MPON 0x08 16500 #define TXBUFCLR 0x09 16501 #define RXRESET 0x11 16502 #define RXENABLE 0x12 16503 #define RXDISABLE 0x13 16504 #define RXCRCINIT 0x14 16505 #define RXREJECT 0x15 16506 #define SEARCHMP 0x16 16507 #define RXCRCEXCL 0x17 16508 #define RXCRCCALC 0x18 16509 #define CHRESET 0x21 16510 #define HUNT 0x31 16511 #define SWABORT 0x01 16512 #define FEICLEAR 0x02 16513 #define TXINTE BIT7 16514 #define RXINTE BIT6 16515 #define TXRDYE BIT1 16516 #define RXRDYE BIT0 16517 #define UDRN BIT7 16518 #define IDLE BIT6 16519 #define SYNCD BIT4 16520 #define FLGD BIT4 16521 #define CCTS BIT3 16522 #define CDCD BIT2 16523 #define BRKD BIT1 16524 #define ABTD BIT1 16525 #define GAPD BIT1 16526 #define BRKE BIT0 16527 #define IDLD BIT0 16528 #define EOM BIT7 16529 #define PMP BIT6 16530 #define SHRT BIT6 16531 #define PE BIT5 16532 #define ABT BIT5 16533 #define FRME BIT4 16534 #define RBIT BIT4 16535 #define OVRN BIT3 16536 #define CRCE BIT2 16537 #define WAKEUP_CHARS 256 16538 #if SYNCLINK_GENERIC_HDLC 16539 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16540 #endif 16541 #ifdef SANITY_CHECK 16542 #else 16543 #endif 16544 /* LDV_COMMENT_END_PREP */ 16545 /* LDV_COMMENT_FUNCTION_CALL Function from field "chars_in_buffer" from driver structure with callbacks "ops" */ 16546 ldv_handler_precall(); 16547 chars_in_buffer( var_group8); 16548 /* LDV_COMMENT_BEGIN_PREP */ 16549 #if SYNCLINK_GENERIC_HDLC 16550 #endif 16551 #if SYNCLINK_GENERIC_HDLC 16552 #endif 16553 #if SYNCLINK_GENERIC_HDLC 16554 #endif 16555 #ifdef CMSPAR 16556 #endif 16557 #if SYNCLINK_GENERIC_HDLC 16558 #endif 16559 #if SYNCLINK_GENERIC_HDLC 16560 #endif 16561 #if 0 16562 #endif 16563 #if SYNCLINK_GENERIC_HDLC 16564 #endif 16565 #if SYNCLINK_GENERIC_HDLC 16566 #endif 16567 #define TESTFRAMESIZE 20 16568 #if SYNCLINK_GENERIC_HDLC 16569 #endif 16570 #define CALC_REGADDR() \ 16571 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 16572 if (info->port_num > 1) \ 16573 RegAddr += 256; \ 16574 if ( info->port_num & 1) { \ 16575 if (Addr > 0x7f) \ 16576 RegAddr += 0x40; \ 16577 else if (Addr > 0x1f && Addr < 0x60) \ 16578 RegAddr += 0x20; \ 16579 } 16580 /* LDV_COMMENT_END_PREP */ 16581 16582 16583 16584 16585 } 16586 16587 break; 16588 case 17: { 16589 16590 /** STRUCT: struct type: tty_operations, struct name: ops **/ 16591 16592 16593 /* content: static void flush_buffer(struct tty_struct *tty)*/ 16594 /* LDV_COMMENT_BEGIN_PREP */ 16595 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 16596 #if defined(__i386__) 16597 # define BREAKPOINT() asm(" int $3"); 16598 #else 16599 # define BREAKPOINT() { } 16600 #endif 16601 #define MAX_DEVICES 12 16602 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 16603 #define SYNCLINK_GENERIC_HDLC 1 16604 #else 16605 #define SYNCLINK_GENERIC_HDLC 0 16606 #endif 16607 #define GET_USER(error,value,addr) error = get_user(value,addr) 16608 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 16609 #define PUT_USER(error,value,addr) error = put_user(value,addr) 16610 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 16611 #define SCABUFSIZE 1024 16612 #define SCA_MEM_SIZE 0x40000 16613 #define SCA_BASE_SIZE 512 16614 #define SCA_REG_SIZE 16 16615 #define SCA_MAX_PORTS 4 16616 #define SCAMAXDESC 128 16617 #define BUFFERLISTSIZE 4096 16618 #define BH_RECEIVE 1 16619 #define BH_TRANSMIT 2 16620 #define BH_STATUS 4 16621 #define IO_PIN_SHUTDOWN_LIMIT 100 16622 #if SYNCLINK_GENERIC_HDLC 16623 #endif 16624 #define MGSL_MAGIC 0x5401 16625 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 16626 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 16627 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 16628 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 16629 #define LPR 0x00 16630 #define PABR0 0x02 16631 #define PABR1 0x03 16632 #define WCRL 0x04 16633 #define WCRM 0x05 16634 #define WCRH 0x06 16635 #define DPCR 0x08 16636 #define DMER 0x09 16637 #define ISR0 0x10 16638 #define ISR1 0x11 16639 #define ISR2 0x12 16640 #define IER0 0x14 16641 #define IER1 0x15 16642 #define IER2 0x16 16643 #define ITCR 0x18 16644 #define INTVR 0x1a 16645 #define IMVR 0x1c 16646 #define TRB 0x20 16647 #define TRBL 0x20 16648 #define TRBH 0x21 16649 #define SR0 0x22 16650 #define SR1 0x23 16651 #define SR2 0x24 16652 #define SR3 0x25 16653 #define FST 0x26 16654 #define IE0 0x28 16655 #define IE1 0x29 16656 #define IE2 0x2a 16657 #define FIE 0x2b 16658 #define CMD 0x2c 16659 #define MD0 0x2e 16660 #define MD1 0x2f 16661 #define MD2 0x30 16662 #define CTL 0x31 16663 #define SA0 0x32 16664 #define SA1 0x33 16665 #define IDL 0x34 16666 #define TMC 0x35 16667 #define RXS 0x36 16668 #define TXS 0x37 16669 #define TRC0 0x38 16670 #define TRC1 0x39 16671 #define RRC 0x3a 16672 #define CST0 0x3c 16673 #define CST1 0x3d 16674 #define TCNT 0x60 16675 #define TCNTL 0x60 16676 #define TCNTH 0x61 16677 #define TCONR 0x62 16678 #define TCONRL 0x62 16679 #define TCONRH 0x63 16680 #define TMCS 0x64 16681 #define TEPR 0x65 16682 #define DARL 0x80 16683 #define DARH 0x81 16684 #define DARB 0x82 16685 #define BAR 0x80 16686 #define BARL 0x80 16687 #define BARH 0x81 16688 #define BARB 0x82 16689 #define SAR 0x84 16690 #define SARL 0x84 16691 #define SARH 0x85 16692 #define SARB 0x86 16693 #define CPB 0x86 16694 #define CDA 0x88 16695 #define CDAL 0x88 16696 #define CDAH 0x89 16697 #define EDA 0x8a 16698 #define EDAL 0x8a 16699 #define EDAH 0x8b 16700 #define BFL 0x8c 16701 #define BFLL 0x8c 16702 #define BFLH 0x8d 16703 #define BCR 0x8e 16704 #define BCRL 0x8e 16705 #define BCRH 0x8f 16706 #define DSR 0x90 16707 #define DMR 0x91 16708 #define FCT 0x93 16709 #define DIR 0x94 16710 #define DCMD 0x95 16711 #define TIMER0 0x00 16712 #define TIMER1 0x08 16713 #define TIMER2 0x10 16714 #define TIMER3 0x18 16715 #define RXDMA 0x00 16716 #define TXDMA 0x20 16717 #define NOOP 0x00 16718 #define TXRESET 0x01 16719 #define TXENABLE 0x02 16720 #define TXDISABLE 0x03 16721 #define TXCRCINIT 0x04 16722 #define TXCRCEXCL 0x05 16723 #define TXEOM 0x06 16724 #define TXABORT 0x07 16725 #define MPON 0x08 16726 #define TXBUFCLR 0x09 16727 #define RXRESET 0x11 16728 #define RXENABLE 0x12 16729 #define RXDISABLE 0x13 16730 #define RXCRCINIT 0x14 16731 #define RXREJECT 0x15 16732 #define SEARCHMP 0x16 16733 #define RXCRCEXCL 0x17 16734 #define RXCRCCALC 0x18 16735 #define CHRESET 0x21 16736 #define HUNT 0x31 16737 #define SWABORT 0x01 16738 #define FEICLEAR 0x02 16739 #define TXINTE BIT7 16740 #define RXINTE BIT6 16741 #define TXRDYE BIT1 16742 #define RXRDYE BIT0 16743 #define UDRN BIT7 16744 #define IDLE BIT6 16745 #define SYNCD BIT4 16746 #define FLGD BIT4 16747 #define CCTS BIT3 16748 #define CDCD BIT2 16749 #define BRKD BIT1 16750 #define ABTD BIT1 16751 #define GAPD BIT1 16752 #define BRKE BIT0 16753 #define IDLD BIT0 16754 #define EOM BIT7 16755 #define PMP BIT6 16756 #define SHRT BIT6 16757 #define PE BIT5 16758 #define ABT BIT5 16759 #define FRME BIT4 16760 #define RBIT BIT4 16761 #define OVRN BIT3 16762 #define CRCE BIT2 16763 #define WAKEUP_CHARS 256 16764 #if SYNCLINK_GENERIC_HDLC 16765 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16766 #endif 16767 #ifdef SANITY_CHECK 16768 #else 16769 #endif 16770 /* LDV_COMMENT_END_PREP */ 16771 /* LDV_COMMENT_FUNCTION_CALL Function from field "flush_buffer" from driver structure with callbacks "ops" */ 16772 ldv_handler_precall(); 16773 flush_buffer( var_group8); 16774 /* LDV_COMMENT_BEGIN_PREP */ 16775 #if SYNCLINK_GENERIC_HDLC 16776 #endif 16777 #if SYNCLINK_GENERIC_HDLC 16778 #endif 16779 #if SYNCLINK_GENERIC_HDLC 16780 #endif 16781 #ifdef CMSPAR 16782 #endif 16783 #if SYNCLINK_GENERIC_HDLC 16784 #endif 16785 #if SYNCLINK_GENERIC_HDLC 16786 #endif 16787 #if 0 16788 #endif 16789 #if SYNCLINK_GENERIC_HDLC 16790 #endif 16791 #if SYNCLINK_GENERIC_HDLC 16792 #endif 16793 #define TESTFRAMESIZE 20 16794 #if SYNCLINK_GENERIC_HDLC 16795 #endif 16796 #define CALC_REGADDR() \ 16797 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 16798 if (info->port_num > 1) \ 16799 RegAddr += 256; \ 16800 if ( info->port_num & 1) { \ 16801 if (Addr > 0x7f) \ 16802 RegAddr += 0x40; \ 16803 else if (Addr > 0x1f && Addr < 0x60) \ 16804 RegAddr += 0x20; \ 16805 } 16806 /* LDV_COMMENT_END_PREP */ 16807 16808 16809 16810 16811 } 16812 16813 break; 16814 case 18: { 16815 16816 /** STRUCT: struct type: tty_operations, struct name: ops **/ 16817 16818 16819 /* content: static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg)*/ 16820 /* LDV_COMMENT_BEGIN_PREP */ 16821 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 16822 #if defined(__i386__) 16823 # define BREAKPOINT() asm(" int $3"); 16824 #else 16825 # define BREAKPOINT() { } 16826 #endif 16827 #define MAX_DEVICES 12 16828 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 16829 #define SYNCLINK_GENERIC_HDLC 1 16830 #else 16831 #define SYNCLINK_GENERIC_HDLC 0 16832 #endif 16833 #define GET_USER(error,value,addr) error = get_user(value,addr) 16834 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 16835 #define PUT_USER(error,value,addr) error = put_user(value,addr) 16836 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 16837 #define SCABUFSIZE 1024 16838 #define SCA_MEM_SIZE 0x40000 16839 #define SCA_BASE_SIZE 512 16840 #define SCA_REG_SIZE 16 16841 #define SCA_MAX_PORTS 4 16842 #define SCAMAXDESC 128 16843 #define BUFFERLISTSIZE 4096 16844 #define BH_RECEIVE 1 16845 #define BH_TRANSMIT 2 16846 #define BH_STATUS 4 16847 #define IO_PIN_SHUTDOWN_LIMIT 100 16848 #if SYNCLINK_GENERIC_HDLC 16849 #endif 16850 #define MGSL_MAGIC 0x5401 16851 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 16852 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 16853 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 16854 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 16855 #define LPR 0x00 16856 #define PABR0 0x02 16857 #define PABR1 0x03 16858 #define WCRL 0x04 16859 #define WCRM 0x05 16860 #define WCRH 0x06 16861 #define DPCR 0x08 16862 #define DMER 0x09 16863 #define ISR0 0x10 16864 #define ISR1 0x11 16865 #define ISR2 0x12 16866 #define IER0 0x14 16867 #define IER1 0x15 16868 #define IER2 0x16 16869 #define ITCR 0x18 16870 #define INTVR 0x1a 16871 #define IMVR 0x1c 16872 #define TRB 0x20 16873 #define TRBL 0x20 16874 #define TRBH 0x21 16875 #define SR0 0x22 16876 #define SR1 0x23 16877 #define SR2 0x24 16878 #define SR3 0x25 16879 #define FST 0x26 16880 #define IE0 0x28 16881 #define IE1 0x29 16882 #define IE2 0x2a 16883 #define FIE 0x2b 16884 #define CMD 0x2c 16885 #define MD0 0x2e 16886 #define MD1 0x2f 16887 #define MD2 0x30 16888 #define CTL 0x31 16889 #define SA0 0x32 16890 #define SA1 0x33 16891 #define IDL 0x34 16892 #define TMC 0x35 16893 #define RXS 0x36 16894 #define TXS 0x37 16895 #define TRC0 0x38 16896 #define TRC1 0x39 16897 #define RRC 0x3a 16898 #define CST0 0x3c 16899 #define CST1 0x3d 16900 #define TCNT 0x60 16901 #define TCNTL 0x60 16902 #define TCNTH 0x61 16903 #define TCONR 0x62 16904 #define TCONRL 0x62 16905 #define TCONRH 0x63 16906 #define TMCS 0x64 16907 #define TEPR 0x65 16908 #define DARL 0x80 16909 #define DARH 0x81 16910 #define DARB 0x82 16911 #define BAR 0x80 16912 #define BARL 0x80 16913 #define BARH 0x81 16914 #define BARB 0x82 16915 #define SAR 0x84 16916 #define SARL 0x84 16917 #define SARH 0x85 16918 #define SARB 0x86 16919 #define CPB 0x86 16920 #define CDA 0x88 16921 #define CDAL 0x88 16922 #define CDAH 0x89 16923 #define EDA 0x8a 16924 #define EDAL 0x8a 16925 #define EDAH 0x8b 16926 #define BFL 0x8c 16927 #define BFLL 0x8c 16928 #define BFLH 0x8d 16929 #define BCR 0x8e 16930 #define BCRL 0x8e 16931 #define BCRH 0x8f 16932 #define DSR 0x90 16933 #define DMR 0x91 16934 #define FCT 0x93 16935 #define DIR 0x94 16936 #define DCMD 0x95 16937 #define TIMER0 0x00 16938 #define TIMER1 0x08 16939 #define TIMER2 0x10 16940 #define TIMER3 0x18 16941 #define RXDMA 0x00 16942 #define TXDMA 0x20 16943 #define NOOP 0x00 16944 #define TXRESET 0x01 16945 #define TXENABLE 0x02 16946 #define TXDISABLE 0x03 16947 #define TXCRCINIT 0x04 16948 #define TXCRCEXCL 0x05 16949 #define TXEOM 0x06 16950 #define TXABORT 0x07 16951 #define MPON 0x08 16952 #define TXBUFCLR 0x09 16953 #define RXRESET 0x11 16954 #define RXENABLE 0x12 16955 #define RXDISABLE 0x13 16956 #define RXCRCINIT 0x14 16957 #define RXREJECT 0x15 16958 #define SEARCHMP 0x16 16959 #define RXCRCEXCL 0x17 16960 #define RXCRCCALC 0x18 16961 #define CHRESET 0x21 16962 #define HUNT 0x31 16963 #define SWABORT 0x01 16964 #define FEICLEAR 0x02 16965 #define TXINTE BIT7 16966 #define RXINTE BIT6 16967 #define TXRDYE BIT1 16968 #define RXRDYE BIT0 16969 #define UDRN BIT7 16970 #define IDLE BIT6 16971 #define SYNCD BIT4 16972 #define FLGD BIT4 16973 #define CCTS BIT3 16974 #define CDCD BIT2 16975 #define BRKD BIT1 16976 #define ABTD BIT1 16977 #define GAPD BIT1 16978 #define BRKE BIT0 16979 #define IDLD BIT0 16980 #define EOM BIT7 16981 #define PMP BIT6 16982 #define SHRT BIT6 16983 #define PE BIT5 16984 #define ABT BIT5 16985 #define FRME BIT4 16986 #define RBIT BIT4 16987 #define OVRN BIT3 16988 #define CRCE BIT2 16989 #define WAKEUP_CHARS 256 16990 #if SYNCLINK_GENERIC_HDLC 16991 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 16992 #endif 16993 #ifdef SANITY_CHECK 16994 #else 16995 #endif 16996 /* LDV_COMMENT_END_PREP */ 16997 /* LDV_COMMENT_FUNCTION_CALL Function from field "ioctl" from driver structure with callbacks "ops" */ 16998 ldv_handler_precall(); 16999 ioctl( var_group8, var_ioctl_17_p1, var_ioctl_17_p2); 17000 /* LDV_COMMENT_BEGIN_PREP */ 17001 #if SYNCLINK_GENERIC_HDLC 17002 #endif 17003 #if SYNCLINK_GENERIC_HDLC 17004 #endif 17005 #if SYNCLINK_GENERIC_HDLC 17006 #endif 17007 #ifdef CMSPAR 17008 #endif 17009 #if SYNCLINK_GENERIC_HDLC 17010 #endif 17011 #if SYNCLINK_GENERIC_HDLC 17012 #endif 17013 #if 0 17014 #endif 17015 #if SYNCLINK_GENERIC_HDLC 17016 #endif 17017 #if SYNCLINK_GENERIC_HDLC 17018 #endif 17019 #define TESTFRAMESIZE 20 17020 #if SYNCLINK_GENERIC_HDLC 17021 #endif 17022 #define CALC_REGADDR() \ 17023 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17024 if (info->port_num > 1) \ 17025 RegAddr += 256; \ 17026 if ( info->port_num & 1) { \ 17027 if (Addr > 0x7f) \ 17028 RegAddr += 0x40; \ 17029 else if (Addr > 0x1f && Addr < 0x60) \ 17030 RegAddr += 0x20; \ 17031 } 17032 /* LDV_COMMENT_END_PREP */ 17033 17034 17035 17036 17037 } 17038 17039 break; 17040 case 19: { 17041 17042 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17043 17044 17045 /* content: static void throttle(struct tty_struct * tty)*/ 17046 /* LDV_COMMENT_BEGIN_PREP */ 17047 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17048 #if defined(__i386__) 17049 # define BREAKPOINT() asm(" int $3"); 17050 #else 17051 # define BREAKPOINT() { } 17052 #endif 17053 #define MAX_DEVICES 12 17054 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17055 #define SYNCLINK_GENERIC_HDLC 1 17056 #else 17057 #define SYNCLINK_GENERIC_HDLC 0 17058 #endif 17059 #define GET_USER(error,value,addr) error = get_user(value,addr) 17060 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17061 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17062 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17063 #define SCABUFSIZE 1024 17064 #define SCA_MEM_SIZE 0x40000 17065 #define SCA_BASE_SIZE 512 17066 #define SCA_REG_SIZE 16 17067 #define SCA_MAX_PORTS 4 17068 #define SCAMAXDESC 128 17069 #define BUFFERLISTSIZE 4096 17070 #define BH_RECEIVE 1 17071 #define BH_TRANSMIT 2 17072 #define BH_STATUS 4 17073 #define IO_PIN_SHUTDOWN_LIMIT 100 17074 #if SYNCLINK_GENERIC_HDLC 17075 #endif 17076 #define MGSL_MAGIC 0x5401 17077 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17078 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17079 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17080 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17081 #define LPR 0x00 17082 #define PABR0 0x02 17083 #define PABR1 0x03 17084 #define WCRL 0x04 17085 #define WCRM 0x05 17086 #define WCRH 0x06 17087 #define DPCR 0x08 17088 #define DMER 0x09 17089 #define ISR0 0x10 17090 #define ISR1 0x11 17091 #define ISR2 0x12 17092 #define IER0 0x14 17093 #define IER1 0x15 17094 #define IER2 0x16 17095 #define ITCR 0x18 17096 #define INTVR 0x1a 17097 #define IMVR 0x1c 17098 #define TRB 0x20 17099 #define TRBL 0x20 17100 #define TRBH 0x21 17101 #define SR0 0x22 17102 #define SR1 0x23 17103 #define SR2 0x24 17104 #define SR3 0x25 17105 #define FST 0x26 17106 #define IE0 0x28 17107 #define IE1 0x29 17108 #define IE2 0x2a 17109 #define FIE 0x2b 17110 #define CMD 0x2c 17111 #define MD0 0x2e 17112 #define MD1 0x2f 17113 #define MD2 0x30 17114 #define CTL 0x31 17115 #define SA0 0x32 17116 #define SA1 0x33 17117 #define IDL 0x34 17118 #define TMC 0x35 17119 #define RXS 0x36 17120 #define TXS 0x37 17121 #define TRC0 0x38 17122 #define TRC1 0x39 17123 #define RRC 0x3a 17124 #define CST0 0x3c 17125 #define CST1 0x3d 17126 #define TCNT 0x60 17127 #define TCNTL 0x60 17128 #define TCNTH 0x61 17129 #define TCONR 0x62 17130 #define TCONRL 0x62 17131 #define TCONRH 0x63 17132 #define TMCS 0x64 17133 #define TEPR 0x65 17134 #define DARL 0x80 17135 #define DARH 0x81 17136 #define DARB 0x82 17137 #define BAR 0x80 17138 #define BARL 0x80 17139 #define BARH 0x81 17140 #define BARB 0x82 17141 #define SAR 0x84 17142 #define SARL 0x84 17143 #define SARH 0x85 17144 #define SARB 0x86 17145 #define CPB 0x86 17146 #define CDA 0x88 17147 #define CDAL 0x88 17148 #define CDAH 0x89 17149 #define EDA 0x8a 17150 #define EDAL 0x8a 17151 #define EDAH 0x8b 17152 #define BFL 0x8c 17153 #define BFLL 0x8c 17154 #define BFLH 0x8d 17155 #define BCR 0x8e 17156 #define BCRL 0x8e 17157 #define BCRH 0x8f 17158 #define DSR 0x90 17159 #define DMR 0x91 17160 #define FCT 0x93 17161 #define DIR 0x94 17162 #define DCMD 0x95 17163 #define TIMER0 0x00 17164 #define TIMER1 0x08 17165 #define TIMER2 0x10 17166 #define TIMER3 0x18 17167 #define RXDMA 0x00 17168 #define TXDMA 0x20 17169 #define NOOP 0x00 17170 #define TXRESET 0x01 17171 #define TXENABLE 0x02 17172 #define TXDISABLE 0x03 17173 #define TXCRCINIT 0x04 17174 #define TXCRCEXCL 0x05 17175 #define TXEOM 0x06 17176 #define TXABORT 0x07 17177 #define MPON 0x08 17178 #define TXBUFCLR 0x09 17179 #define RXRESET 0x11 17180 #define RXENABLE 0x12 17181 #define RXDISABLE 0x13 17182 #define RXCRCINIT 0x14 17183 #define RXREJECT 0x15 17184 #define SEARCHMP 0x16 17185 #define RXCRCEXCL 0x17 17186 #define RXCRCCALC 0x18 17187 #define CHRESET 0x21 17188 #define HUNT 0x31 17189 #define SWABORT 0x01 17190 #define FEICLEAR 0x02 17191 #define TXINTE BIT7 17192 #define RXINTE BIT6 17193 #define TXRDYE BIT1 17194 #define RXRDYE BIT0 17195 #define UDRN BIT7 17196 #define IDLE BIT6 17197 #define SYNCD BIT4 17198 #define FLGD BIT4 17199 #define CCTS BIT3 17200 #define CDCD BIT2 17201 #define BRKD BIT1 17202 #define ABTD BIT1 17203 #define GAPD BIT1 17204 #define BRKE BIT0 17205 #define IDLD BIT0 17206 #define EOM BIT7 17207 #define PMP BIT6 17208 #define SHRT BIT6 17209 #define PE BIT5 17210 #define ABT BIT5 17211 #define FRME BIT4 17212 #define RBIT BIT4 17213 #define OVRN BIT3 17214 #define CRCE BIT2 17215 #define WAKEUP_CHARS 256 17216 #if SYNCLINK_GENERIC_HDLC 17217 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 17218 #endif 17219 #ifdef SANITY_CHECK 17220 #else 17221 #endif 17222 /* LDV_COMMENT_END_PREP */ 17223 /* LDV_COMMENT_FUNCTION_CALL Function from field "throttle" from driver structure with callbacks "ops" */ 17224 ldv_handler_precall(); 17225 throttle( var_group8); 17226 /* LDV_COMMENT_BEGIN_PREP */ 17227 #if SYNCLINK_GENERIC_HDLC 17228 #endif 17229 #if SYNCLINK_GENERIC_HDLC 17230 #endif 17231 #if SYNCLINK_GENERIC_HDLC 17232 #endif 17233 #ifdef CMSPAR 17234 #endif 17235 #if SYNCLINK_GENERIC_HDLC 17236 #endif 17237 #if SYNCLINK_GENERIC_HDLC 17238 #endif 17239 #if 0 17240 #endif 17241 #if SYNCLINK_GENERIC_HDLC 17242 #endif 17243 #if SYNCLINK_GENERIC_HDLC 17244 #endif 17245 #define TESTFRAMESIZE 20 17246 #if SYNCLINK_GENERIC_HDLC 17247 #endif 17248 #define CALC_REGADDR() \ 17249 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17250 if (info->port_num > 1) \ 17251 RegAddr += 256; \ 17252 if ( info->port_num & 1) { \ 17253 if (Addr > 0x7f) \ 17254 RegAddr += 0x40; \ 17255 else if (Addr > 0x1f && Addr < 0x60) \ 17256 RegAddr += 0x20; \ 17257 } 17258 /* LDV_COMMENT_END_PREP */ 17259 17260 17261 17262 17263 } 17264 17265 break; 17266 case 20: { 17267 17268 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17269 17270 17271 /* content: static void unthrottle(struct tty_struct * tty)*/ 17272 /* LDV_COMMENT_BEGIN_PREP */ 17273 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17274 #if defined(__i386__) 17275 # define BREAKPOINT() asm(" int $3"); 17276 #else 17277 # define BREAKPOINT() { } 17278 #endif 17279 #define MAX_DEVICES 12 17280 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17281 #define SYNCLINK_GENERIC_HDLC 1 17282 #else 17283 #define SYNCLINK_GENERIC_HDLC 0 17284 #endif 17285 #define GET_USER(error,value,addr) error = get_user(value,addr) 17286 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17287 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17288 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17289 #define SCABUFSIZE 1024 17290 #define SCA_MEM_SIZE 0x40000 17291 #define SCA_BASE_SIZE 512 17292 #define SCA_REG_SIZE 16 17293 #define SCA_MAX_PORTS 4 17294 #define SCAMAXDESC 128 17295 #define BUFFERLISTSIZE 4096 17296 #define BH_RECEIVE 1 17297 #define BH_TRANSMIT 2 17298 #define BH_STATUS 4 17299 #define IO_PIN_SHUTDOWN_LIMIT 100 17300 #if SYNCLINK_GENERIC_HDLC 17301 #endif 17302 #define MGSL_MAGIC 0x5401 17303 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17304 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17305 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17306 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17307 #define LPR 0x00 17308 #define PABR0 0x02 17309 #define PABR1 0x03 17310 #define WCRL 0x04 17311 #define WCRM 0x05 17312 #define WCRH 0x06 17313 #define DPCR 0x08 17314 #define DMER 0x09 17315 #define ISR0 0x10 17316 #define ISR1 0x11 17317 #define ISR2 0x12 17318 #define IER0 0x14 17319 #define IER1 0x15 17320 #define IER2 0x16 17321 #define ITCR 0x18 17322 #define INTVR 0x1a 17323 #define IMVR 0x1c 17324 #define TRB 0x20 17325 #define TRBL 0x20 17326 #define TRBH 0x21 17327 #define SR0 0x22 17328 #define SR1 0x23 17329 #define SR2 0x24 17330 #define SR3 0x25 17331 #define FST 0x26 17332 #define IE0 0x28 17333 #define IE1 0x29 17334 #define IE2 0x2a 17335 #define FIE 0x2b 17336 #define CMD 0x2c 17337 #define MD0 0x2e 17338 #define MD1 0x2f 17339 #define MD2 0x30 17340 #define CTL 0x31 17341 #define SA0 0x32 17342 #define SA1 0x33 17343 #define IDL 0x34 17344 #define TMC 0x35 17345 #define RXS 0x36 17346 #define TXS 0x37 17347 #define TRC0 0x38 17348 #define TRC1 0x39 17349 #define RRC 0x3a 17350 #define CST0 0x3c 17351 #define CST1 0x3d 17352 #define TCNT 0x60 17353 #define TCNTL 0x60 17354 #define TCNTH 0x61 17355 #define TCONR 0x62 17356 #define TCONRL 0x62 17357 #define TCONRH 0x63 17358 #define TMCS 0x64 17359 #define TEPR 0x65 17360 #define DARL 0x80 17361 #define DARH 0x81 17362 #define DARB 0x82 17363 #define BAR 0x80 17364 #define BARL 0x80 17365 #define BARH 0x81 17366 #define BARB 0x82 17367 #define SAR 0x84 17368 #define SARL 0x84 17369 #define SARH 0x85 17370 #define SARB 0x86 17371 #define CPB 0x86 17372 #define CDA 0x88 17373 #define CDAL 0x88 17374 #define CDAH 0x89 17375 #define EDA 0x8a 17376 #define EDAL 0x8a 17377 #define EDAH 0x8b 17378 #define BFL 0x8c 17379 #define BFLL 0x8c 17380 #define BFLH 0x8d 17381 #define BCR 0x8e 17382 #define BCRL 0x8e 17383 #define BCRH 0x8f 17384 #define DSR 0x90 17385 #define DMR 0x91 17386 #define FCT 0x93 17387 #define DIR 0x94 17388 #define DCMD 0x95 17389 #define TIMER0 0x00 17390 #define TIMER1 0x08 17391 #define TIMER2 0x10 17392 #define TIMER3 0x18 17393 #define RXDMA 0x00 17394 #define TXDMA 0x20 17395 #define NOOP 0x00 17396 #define TXRESET 0x01 17397 #define TXENABLE 0x02 17398 #define TXDISABLE 0x03 17399 #define TXCRCINIT 0x04 17400 #define TXCRCEXCL 0x05 17401 #define TXEOM 0x06 17402 #define TXABORT 0x07 17403 #define MPON 0x08 17404 #define TXBUFCLR 0x09 17405 #define RXRESET 0x11 17406 #define RXENABLE 0x12 17407 #define RXDISABLE 0x13 17408 #define RXCRCINIT 0x14 17409 #define RXREJECT 0x15 17410 #define SEARCHMP 0x16 17411 #define RXCRCEXCL 0x17 17412 #define RXCRCCALC 0x18 17413 #define CHRESET 0x21 17414 #define HUNT 0x31 17415 #define SWABORT 0x01 17416 #define FEICLEAR 0x02 17417 #define TXINTE BIT7 17418 #define RXINTE BIT6 17419 #define TXRDYE BIT1 17420 #define RXRDYE BIT0 17421 #define UDRN BIT7 17422 #define IDLE BIT6 17423 #define SYNCD BIT4 17424 #define FLGD BIT4 17425 #define CCTS BIT3 17426 #define CDCD BIT2 17427 #define BRKD BIT1 17428 #define ABTD BIT1 17429 #define GAPD BIT1 17430 #define BRKE BIT0 17431 #define IDLD BIT0 17432 #define EOM BIT7 17433 #define PMP BIT6 17434 #define SHRT BIT6 17435 #define PE BIT5 17436 #define ABT BIT5 17437 #define FRME BIT4 17438 #define RBIT BIT4 17439 #define OVRN BIT3 17440 #define CRCE BIT2 17441 #define WAKEUP_CHARS 256 17442 #if SYNCLINK_GENERIC_HDLC 17443 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 17444 #endif 17445 #ifdef SANITY_CHECK 17446 #else 17447 #endif 17448 /* LDV_COMMENT_END_PREP */ 17449 /* LDV_COMMENT_FUNCTION_CALL Function from field "unthrottle" from driver structure with callbacks "ops" */ 17450 ldv_handler_precall(); 17451 unthrottle( var_group8); 17452 /* LDV_COMMENT_BEGIN_PREP */ 17453 #if SYNCLINK_GENERIC_HDLC 17454 #endif 17455 #if SYNCLINK_GENERIC_HDLC 17456 #endif 17457 #if SYNCLINK_GENERIC_HDLC 17458 #endif 17459 #ifdef CMSPAR 17460 #endif 17461 #if SYNCLINK_GENERIC_HDLC 17462 #endif 17463 #if SYNCLINK_GENERIC_HDLC 17464 #endif 17465 #if 0 17466 #endif 17467 #if SYNCLINK_GENERIC_HDLC 17468 #endif 17469 #if SYNCLINK_GENERIC_HDLC 17470 #endif 17471 #define TESTFRAMESIZE 20 17472 #if SYNCLINK_GENERIC_HDLC 17473 #endif 17474 #define CALC_REGADDR() \ 17475 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17476 if (info->port_num > 1) \ 17477 RegAddr += 256; \ 17478 if ( info->port_num & 1) { \ 17479 if (Addr > 0x7f) \ 17480 RegAddr += 0x40; \ 17481 else if (Addr > 0x1f && Addr < 0x60) \ 17482 RegAddr += 0x20; \ 17483 } 17484 /* LDV_COMMENT_END_PREP */ 17485 17486 17487 17488 17489 } 17490 17491 break; 17492 case 21: { 17493 17494 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17495 17496 17497 /* content: static void send_xchar(struct tty_struct *tty, char ch)*/ 17498 /* LDV_COMMENT_BEGIN_PREP */ 17499 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17500 #if defined(__i386__) 17501 # define BREAKPOINT() asm(" int $3"); 17502 #else 17503 # define BREAKPOINT() { } 17504 #endif 17505 #define MAX_DEVICES 12 17506 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17507 #define SYNCLINK_GENERIC_HDLC 1 17508 #else 17509 #define SYNCLINK_GENERIC_HDLC 0 17510 #endif 17511 #define GET_USER(error,value,addr) error = get_user(value,addr) 17512 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17513 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17514 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17515 #define SCABUFSIZE 1024 17516 #define SCA_MEM_SIZE 0x40000 17517 #define SCA_BASE_SIZE 512 17518 #define SCA_REG_SIZE 16 17519 #define SCA_MAX_PORTS 4 17520 #define SCAMAXDESC 128 17521 #define BUFFERLISTSIZE 4096 17522 #define BH_RECEIVE 1 17523 #define BH_TRANSMIT 2 17524 #define BH_STATUS 4 17525 #define IO_PIN_SHUTDOWN_LIMIT 100 17526 #if SYNCLINK_GENERIC_HDLC 17527 #endif 17528 #define MGSL_MAGIC 0x5401 17529 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17530 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17531 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17532 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17533 #define LPR 0x00 17534 #define PABR0 0x02 17535 #define PABR1 0x03 17536 #define WCRL 0x04 17537 #define WCRM 0x05 17538 #define WCRH 0x06 17539 #define DPCR 0x08 17540 #define DMER 0x09 17541 #define ISR0 0x10 17542 #define ISR1 0x11 17543 #define ISR2 0x12 17544 #define IER0 0x14 17545 #define IER1 0x15 17546 #define IER2 0x16 17547 #define ITCR 0x18 17548 #define INTVR 0x1a 17549 #define IMVR 0x1c 17550 #define TRB 0x20 17551 #define TRBL 0x20 17552 #define TRBH 0x21 17553 #define SR0 0x22 17554 #define SR1 0x23 17555 #define SR2 0x24 17556 #define SR3 0x25 17557 #define FST 0x26 17558 #define IE0 0x28 17559 #define IE1 0x29 17560 #define IE2 0x2a 17561 #define FIE 0x2b 17562 #define CMD 0x2c 17563 #define MD0 0x2e 17564 #define MD1 0x2f 17565 #define MD2 0x30 17566 #define CTL 0x31 17567 #define SA0 0x32 17568 #define SA1 0x33 17569 #define IDL 0x34 17570 #define TMC 0x35 17571 #define RXS 0x36 17572 #define TXS 0x37 17573 #define TRC0 0x38 17574 #define TRC1 0x39 17575 #define RRC 0x3a 17576 #define CST0 0x3c 17577 #define CST1 0x3d 17578 #define TCNT 0x60 17579 #define TCNTL 0x60 17580 #define TCNTH 0x61 17581 #define TCONR 0x62 17582 #define TCONRL 0x62 17583 #define TCONRH 0x63 17584 #define TMCS 0x64 17585 #define TEPR 0x65 17586 #define DARL 0x80 17587 #define DARH 0x81 17588 #define DARB 0x82 17589 #define BAR 0x80 17590 #define BARL 0x80 17591 #define BARH 0x81 17592 #define BARB 0x82 17593 #define SAR 0x84 17594 #define SARL 0x84 17595 #define SARH 0x85 17596 #define SARB 0x86 17597 #define CPB 0x86 17598 #define CDA 0x88 17599 #define CDAL 0x88 17600 #define CDAH 0x89 17601 #define EDA 0x8a 17602 #define EDAL 0x8a 17603 #define EDAH 0x8b 17604 #define BFL 0x8c 17605 #define BFLL 0x8c 17606 #define BFLH 0x8d 17607 #define BCR 0x8e 17608 #define BCRL 0x8e 17609 #define BCRH 0x8f 17610 #define DSR 0x90 17611 #define DMR 0x91 17612 #define FCT 0x93 17613 #define DIR 0x94 17614 #define DCMD 0x95 17615 #define TIMER0 0x00 17616 #define TIMER1 0x08 17617 #define TIMER2 0x10 17618 #define TIMER3 0x18 17619 #define RXDMA 0x00 17620 #define TXDMA 0x20 17621 #define NOOP 0x00 17622 #define TXRESET 0x01 17623 #define TXENABLE 0x02 17624 #define TXDISABLE 0x03 17625 #define TXCRCINIT 0x04 17626 #define TXCRCEXCL 0x05 17627 #define TXEOM 0x06 17628 #define TXABORT 0x07 17629 #define MPON 0x08 17630 #define TXBUFCLR 0x09 17631 #define RXRESET 0x11 17632 #define RXENABLE 0x12 17633 #define RXDISABLE 0x13 17634 #define RXCRCINIT 0x14 17635 #define RXREJECT 0x15 17636 #define SEARCHMP 0x16 17637 #define RXCRCEXCL 0x17 17638 #define RXCRCCALC 0x18 17639 #define CHRESET 0x21 17640 #define HUNT 0x31 17641 #define SWABORT 0x01 17642 #define FEICLEAR 0x02 17643 #define TXINTE BIT7 17644 #define RXINTE BIT6 17645 #define TXRDYE BIT1 17646 #define RXRDYE BIT0 17647 #define UDRN BIT7 17648 #define IDLE BIT6 17649 #define SYNCD BIT4 17650 #define FLGD BIT4 17651 #define CCTS BIT3 17652 #define CDCD BIT2 17653 #define BRKD BIT1 17654 #define ABTD BIT1 17655 #define GAPD BIT1 17656 #define BRKE BIT0 17657 #define IDLD BIT0 17658 #define EOM BIT7 17659 #define PMP BIT6 17660 #define SHRT BIT6 17661 #define PE BIT5 17662 #define ABT BIT5 17663 #define FRME BIT4 17664 #define RBIT BIT4 17665 #define OVRN BIT3 17666 #define CRCE BIT2 17667 #define WAKEUP_CHARS 256 17668 #if SYNCLINK_GENERIC_HDLC 17669 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 17670 #endif 17671 #ifdef SANITY_CHECK 17672 #else 17673 #endif 17674 /* LDV_COMMENT_END_PREP */ 17675 /* LDV_COMMENT_FUNCTION_CALL Function from field "send_xchar" from driver structure with callbacks "ops" */ 17676 ldv_handler_precall(); 17677 send_xchar( var_group8, var_send_xchar_10_p1); 17678 /* LDV_COMMENT_BEGIN_PREP */ 17679 #if SYNCLINK_GENERIC_HDLC 17680 #endif 17681 #if SYNCLINK_GENERIC_HDLC 17682 #endif 17683 #if SYNCLINK_GENERIC_HDLC 17684 #endif 17685 #ifdef CMSPAR 17686 #endif 17687 #if SYNCLINK_GENERIC_HDLC 17688 #endif 17689 #if SYNCLINK_GENERIC_HDLC 17690 #endif 17691 #if 0 17692 #endif 17693 #if SYNCLINK_GENERIC_HDLC 17694 #endif 17695 #if SYNCLINK_GENERIC_HDLC 17696 #endif 17697 #define TESTFRAMESIZE 20 17698 #if SYNCLINK_GENERIC_HDLC 17699 #endif 17700 #define CALC_REGADDR() \ 17701 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17702 if (info->port_num > 1) \ 17703 RegAddr += 256; \ 17704 if ( info->port_num & 1) { \ 17705 if (Addr > 0x7f) \ 17706 RegAddr += 0x40; \ 17707 else if (Addr > 0x1f && Addr < 0x60) \ 17708 RegAddr += 0x20; \ 17709 } 17710 /* LDV_COMMENT_END_PREP */ 17711 17712 17713 17714 17715 } 17716 17717 break; 17718 case 22: { 17719 17720 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17721 17722 17723 /* content: static int set_break(struct tty_struct *tty, int break_state)*/ 17724 /* LDV_COMMENT_BEGIN_PREP */ 17725 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17726 #if defined(__i386__) 17727 # define BREAKPOINT() asm(" int $3"); 17728 #else 17729 # define BREAKPOINT() { } 17730 #endif 17731 #define MAX_DEVICES 12 17732 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17733 #define SYNCLINK_GENERIC_HDLC 1 17734 #else 17735 #define SYNCLINK_GENERIC_HDLC 0 17736 #endif 17737 #define GET_USER(error,value,addr) error = get_user(value,addr) 17738 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17739 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17740 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17741 #define SCABUFSIZE 1024 17742 #define SCA_MEM_SIZE 0x40000 17743 #define SCA_BASE_SIZE 512 17744 #define SCA_REG_SIZE 16 17745 #define SCA_MAX_PORTS 4 17746 #define SCAMAXDESC 128 17747 #define BUFFERLISTSIZE 4096 17748 #define BH_RECEIVE 1 17749 #define BH_TRANSMIT 2 17750 #define BH_STATUS 4 17751 #define IO_PIN_SHUTDOWN_LIMIT 100 17752 #if SYNCLINK_GENERIC_HDLC 17753 #endif 17754 #define MGSL_MAGIC 0x5401 17755 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17756 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17757 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17758 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17759 #define LPR 0x00 17760 #define PABR0 0x02 17761 #define PABR1 0x03 17762 #define WCRL 0x04 17763 #define WCRM 0x05 17764 #define WCRH 0x06 17765 #define DPCR 0x08 17766 #define DMER 0x09 17767 #define ISR0 0x10 17768 #define ISR1 0x11 17769 #define ISR2 0x12 17770 #define IER0 0x14 17771 #define IER1 0x15 17772 #define IER2 0x16 17773 #define ITCR 0x18 17774 #define INTVR 0x1a 17775 #define IMVR 0x1c 17776 #define TRB 0x20 17777 #define TRBL 0x20 17778 #define TRBH 0x21 17779 #define SR0 0x22 17780 #define SR1 0x23 17781 #define SR2 0x24 17782 #define SR3 0x25 17783 #define FST 0x26 17784 #define IE0 0x28 17785 #define IE1 0x29 17786 #define IE2 0x2a 17787 #define FIE 0x2b 17788 #define CMD 0x2c 17789 #define MD0 0x2e 17790 #define MD1 0x2f 17791 #define MD2 0x30 17792 #define CTL 0x31 17793 #define SA0 0x32 17794 #define SA1 0x33 17795 #define IDL 0x34 17796 #define TMC 0x35 17797 #define RXS 0x36 17798 #define TXS 0x37 17799 #define TRC0 0x38 17800 #define TRC1 0x39 17801 #define RRC 0x3a 17802 #define CST0 0x3c 17803 #define CST1 0x3d 17804 #define TCNT 0x60 17805 #define TCNTL 0x60 17806 #define TCNTH 0x61 17807 #define TCONR 0x62 17808 #define TCONRL 0x62 17809 #define TCONRH 0x63 17810 #define TMCS 0x64 17811 #define TEPR 0x65 17812 #define DARL 0x80 17813 #define DARH 0x81 17814 #define DARB 0x82 17815 #define BAR 0x80 17816 #define BARL 0x80 17817 #define BARH 0x81 17818 #define BARB 0x82 17819 #define SAR 0x84 17820 #define SARL 0x84 17821 #define SARH 0x85 17822 #define SARB 0x86 17823 #define CPB 0x86 17824 #define CDA 0x88 17825 #define CDAL 0x88 17826 #define CDAH 0x89 17827 #define EDA 0x8a 17828 #define EDAL 0x8a 17829 #define EDAH 0x8b 17830 #define BFL 0x8c 17831 #define BFLL 0x8c 17832 #define BFLH 0x8d 17833 #define BCR 0x8e 17834 #define BCRL 0x8e 17835 #define BCRH 0x8f 17836 #define DSR 0x90 17837 #define DMR 0x91 17838 #define FCT 0x93 17839 #define DIR 0x94 17840 #define DCMD 0x95 17841 #define TIMER0 0x00 17842 #define TIMER1 0x08 17843 #define TIMER2 0x10 17844 #define TIMER3 0x18 17845 #define RXDMA 0x00 17846 #define TXDMA 0x20 17847 #define NOOP 0x00 17848 #define TXRESET 0x01 17849 #define TXENABLE 0x02 17850 #define TXDISABLE 0x03 17851 #define TXCRCINIT 0x04 17852 #define TXCRCEXCL 0x05 17853 #define TXEOM 0x06 17854 #define TXABORT 0x07 17855 #define MPON 0x08 17856 #define TXBUFCLR 0x09 17857 #define RXRESET 0x11 17858 #define RXENABLE 0x12 17859 #define RXDISABLE 0x13 17860 #define RXCRCINIT 0x14 17861 #define RXREJECT 0x15 17862 #define SEARCHMP 0x16 17863 #define RXCRCEXCL 0x17 17864 #define RXCRCCALC 0x18 17865 #define CHRESET 0x21 17866 #define HUNT 0x31 17867 #define SWABORT 0x01 17868 #define FEICLEAR 0x02 17869 #define TXINTE BIT7 17870 #define RXINTE BIT6 17871 #define TXRDYE BIT1 17872 #define RXRDYE BIT0 17873 #define UDRN BIT7 17874 #define IDLE BIT6 17875 #define SYNCD BIT4 17876 #define FLGD BIT4 17877 #define CCTS BIT3 17878 #define CDCD BIT2 17879 #define BRKD BIT1 17880 #define ABTD BIT1 17881 #define GAPD BIT1 17882 #define BRKE BIT0 17883 #define IDLD BIT0 17884 #define EOM BIT7 17885 #define PMP BIT6 17886 #define SHRT BIT6 17887 #define PE BIT5 17888 #define ABT BIT5 17889 #define FRME BIT4 17890 #define RBIT BIT4 17891 #define OVRN BIT3 17892 #define CRCE BIT2 17893 #define WAKEUP_CHARS 256 17894 #if SYNCLINK_GENERIC_HDLC 17895 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 17896 #endif 17897 #ifdef SANITY_CHECK 17898 #else 17899 #endif 17900 /* LDV_COMMENT_END_PREP */ 17901 /* LDV_COMMENT_FUNCTION_CALL Function from field "break_ctl" from driver structure with callbacks "ops" */ 17902 ldv_handler_precall(); 17903 set_break( var_group8, var_set_break_25_p1); 17904 /* LDV_COMMENT_BEGIN_PREP */ 17905 #if SYNCLINK_GENERIC_HDLC 17906 #endif 17907 #if SYNCLINK_GENERIC_HDLC 17908 #endif 17909 #if SYNCLINK_GENERIC_HDLC 17910 #endif 17911 #ifdef CMSPAR 17912 #endif 17913 #if SYNCLINK_GENERIC_HDLC 17914 #endif 17915 #if SYNCLINK_GENERIC_HDLC 17916 #endif 17917 #if 0 17918 #endif 17919 #if SYNCLINK_GENERIC_HDLC 17920 #endif 17921 #if SYNCLINK_GENERIC_HDLC 17922 #endif 17923 #define TESTFRAMESIZE 20 17924 #if SYNCLINK_GENERIC_HDLC 17925 #endif 17926 #define CALC_REGADDR() \ 17927 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 17928 if (info->port_num > 1) \ 17929 RegAddr += 256; \ 17930 if ( info->port_num & 1) { \ 17931 if (Addr > 0x7f) \ 17932 RegAddr += 0x40; \ 17933 else if (Addr > 0x1f && Addr < 0x60) \ 17934 RegAddr += 0x20; \ 17935 } 17936 /* LDV_COMMENT_END_PREP */ 17937 17938 17939 17940 17941 } 17942 17943 break; 17944 case 23: { 17945 17946 /** STRUCT: struct type: tty_operations, struct name: ops **/ 17947 17948 17949 /* content: static void wait_until_sent(struct tty_struct *tty, int timeout)*/ 17950 /* LDV_COMMENT_BEGIN_PREP */ 17951 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 17952 #if defined(__i386__) 17953 # define BREAKPOINT() asm(" int $3"); 17954 #else 17955 # define BREAKPOINT() { } 17956 #endif 17957 #define MAX_DEVICES 12 17958 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 17959 #define SYNCLINK_GENERIC_HDLC 1 17960 #else 17961 #define SYNCLINK_GENERIC_HDLC 0 17962 #endif 17963 #define GET_USER(error,value,addr) error = get_user(value,addr) 17964 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 17965 #define PUT_USER(error,value,addr) error = put_user(value,addr) 17966 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 17967 #define SCABUFSIZE 1024 17968 #define SCA_MEM_SIZE 0x40000 17969 #define SCA_BASE_SIZE 512 17970 #define SCA_REG_SIZE 16 17971 #define SCA_MAX_PORTS 4 17972 #define SCAMAXDESC 128 17973 #define BUFFERLISTSIZE 4096 17974 #define BH_RECEIVE 1 17975 #define BH_TRANSMIT 2 17976 #define BH_STATUS 4 17977 #define IO_PIN_SHUTDOWN_LIMIT 100 17978 #if SYNCLINK_GENERIC_HDLC 17979 #endif 17980 #define MGSL_MAGIC 0x5401 17981 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 17982 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 17983 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 17984 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 17985 #define LPR 0x00 17986 #define PABR0 0x02 17987 #define PABR1 0x03 17988 #define WCRL 0x04 17989 #define WCRM 0x05 17990 #define WCRH 0x06 17991 #define DPCR 0x08 17992 #define DMER 0x09 17993 #define ISR0 0x10 17994 #define ISR1 0x11 17995 #define ISR2 0x12 17996 #define IER0 0x14 17997 #define IER1 0x15 17998 #define IER2 0x16 17999 #define ITCR 0x18 18000 #define INTVR 0x1a 18001 #define IMVR 0x1c 18002 #define TRB 0x20 18003 #define TRBL 0x20 18004 #define TRBH 0x21 18005 #define SR0 0x22 18006 #define SR1 0x23 18007 #define SR2 0x24 18008 #define SR3 0x25 18009 #define FST 0x26 18010 #define IE0 0x28 18011 #define IE1 0x29 18012 #define IE2 0x2a 18013 #define FIE 0x2b 18014 #define CMD 0x2c 18015 #define MD0 0x2e 18016 #define MD1 0x2f 18017 #define MD2 0x30 18018 #define CTL 0x31 18019 #define SA0 0x32 18020 #define SA1 0x33 18021 #define IDL 0x34 18022 #define TMC 0x35 18023 #define RXS 0x36 18024 #define TXS 0x37 18025 #define TRC0 0x38 18026 #define TRC1 0x39 18027 #define RRC 0x3a 18028 #define CST0 0x3c 18029 #define CST1 0x3d 18030 #define TCNT 0x60 18031 #define TCNTL 0x60 18032 #define TCNTH 0x61 18033 #define TCONR 0x62 18034 #define TCONRL 0x62 18035 #define TCONRH 0x63 18036 #define TMCS 0x64 18037 #define TEPR 0x65 18038 #define DARL 0x80 18039 #define DARH 0x81 18040 #define DARB 0x82 18041 #define BAR 0x80 18042 #define BARL 0x80 18043 #define BARH 0x81 18044 #define BARB 0x82 18045 #define SAR 0x84 18046 #define SARL 0x84 18047 #define SARH 0x85 18048 #define SARB 0x86 18049 #define CPB 0x86 18050 #define CDA 0x88 18051 #define CDAL 0x88 18052 #define CDAH 0x89 18053 #define EDA 0x8a 18054 #define EDAL 0x8a 18055 #define EDAH 0x8b 18056 #define BFL 0x8c 18057 #define BFLL 0x8c 18058 #define BFLH 0x8d 18059 #define BCR 0x8e 18060 #define BCRL 0x8e 18061 #define BCRH 0x8f 18062 #define DSR 0x90 18063 #define DMR 0x91 18064 #define FCT 0x93 18065 #define DIR 0x94 18066 #define DCMD 0x95 18067 #define TIMER0 0x00 18068 #define TIMER1 0x08 18069 #define TIMER2 0x10 18070 #define TIMER3 0x18 18071 #define RXDMA 0x00 18072 #define TXDMA 0x20 18073 #define NOOP 0x00 18074 #define TXRESET 0x01 18075 #define TXENABLE 0x02 18076 #define TXDISABLE 0x03 18077 #define TXCRCINIT 0x04 18078 #define TXCRCEXCL 0x05 18079 #define TXEOM 0x06 18080 #define TXABORT 0x07 18081 #define MPON 0x08 18082 #define TXBUFCLR 0x09 18083 #define RXRESET 0x11 18084 #define RXENABLE 0x12 18085 #define RXDISABLE 0x13 18086 #define RXCRCINIT 0x14 18087 #define RXREJECT 0x15 18088 #define SEARCHMP 0x16 18089 #define RXCRCEXCL 0x17 18090 #define RXCRCCALC 0x18 18091 #define CHRESET 0x21 18092 #define HUNT 0x31 18093 #define SWABORT 0x01 18094 #define FEICLEAR 0x02 18095 #define TXINTE BIT7 18096 #define RXINTE BIT6 18097 #define TXRDYE BIT1 18098 #define RXRDYE BIT0 18099 #define UDRN BIT7 18100 #define IDLE BIT6 18101 #define SYNCD BIT4 18102 #define FLGD BIT4 18103 #define CCTS BIT3 18104 #define CDCD BIT2 18105 #define BRKD BIT1 18106 #define ABTD BIT1 18107 #define GAPD BIT1 18108 #define BRKE BIT0 18109 #define IDLD BIT0 18110 #define EOM BIT7 18111 #define PMP BIT6 18112 #define SHRT BIT6 18113 #define PE BIT5 18114 #define ABT BIT5 18115 #define FRME BIT4 18116 #define RBIT BIT4 18117 #define OVRN BIT3 18118 #define CRCE BIT2 18119 #define WAKEUP_CHARS 256 18120 #if SYNCLINK_GENERIC_HDLC 18121 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 18122 #endif 18123 #ifdef SANITY_CHECK 18124 #else 18125 #endif 18126 /* LDV_COMMENT_END_PREP */ 18127 /* LDV_COMMENT_FUNCTION_CALL Function from field "wait_until_sent" from driver structure with callbacks "ops" */ 18128 ldv_handler_precall(); 18129 wait_until_sent( var_group8, var_wait_until_sent_11_p1); 18130 /* LDV_COMMENT_BEGIN_PREP */ 18131 #if SYNCLINK_GENERIC_HDLC 18132 #endif 18133 #if SYNCLINK_GENERIC_HDLC 18134 #endif 18135 #if SYNCLINK_GENERIC_HDLC 18136 #endif 18137 #ifdef CMSPAR 18138 #endif 18139 #if SYNCLINK_GENERIC_HDLC 18140 #endif 18141 #if SYNCLINK_GENERIC_HDLC 18142 #endif 18143 #if 0 18144 #endif 18145 #if SYNCLINK_GENERIC_HDLC 18146 #endif 18147 #if SYNCLINK_GENERIC_HDLC 18148 #endif 18149 #define TESTFRAMESIZE 20 18150 #if SYNCLINK_GENERIC_HDLC 18151 #endif 18152 #define CALC_REGADDR() \ 18153 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 18154 if (info->port_num > 1) \ 18155 RegAddr += 256; \ 18156 if ( info->port_num & 1) { \ 18157 if (Addr > 0x7f) \ 18158 RegAddr += 0x40; \ 18159 else if (Addr > 0x1f && Addr < 0x60) \ 18160 RegAddr += 0x20; \ 18161 } 18162 /* LDV_COMMENT_END_PREP */ 18163 18164 18165 18166 18167 } 18168 18169 break; 18170 case 24: { 18171 18172 /** STRUCT: struct type: tty_operations, struct name: ops **/ 18173 18174 18175 /* content: static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)*/ 18176 /* LDV_COMMENT_BEGIN_PREP */ 18177 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 18178 #if defined(__i386__) 18179 # define BREAKPOINT() asm(" int $3"); 18180 #else 18181 # define BREAKPOINT() { } 18182 #endif 18183 #define MAX_DEVICES 12 18184 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 18185 #define SYNCLINK_GENERIC_HDLC 1 18186 #else 18187 #define SYNCLINK_GENERIC_HDLC 0 18188 #endif 18189 #define GET_USER(error,value,addr) error = get_user(value,addr) 18190 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 18191 #define PUT_USER(error,value,addr) error = put_user(value,addr) 18192 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 18193 #define SCABUFSIZE 1024 18194 #define SCA_MEM_SIZE 0x40000 18195 #define SCA_BASE_SIZE 512 18196 #define SCA_REG_SIZE 16 18197 #define SCA_MAX_PORTS 4 18198 #define SCAMAXDESC 128 18199 #define BUFFERLISTSIZE 4096 18200 #define BH_RECEIVE 1 18201 #define BH_TRANSMIT 2 18202 #define BH_STATUS 4 18203 #define IO_PIN_SHUTDOWN_LIMIT 100 18204 #if SYNCLINK_GENERIC_HDLC 18205 #endif 18206 #define MGSL_MAGIC 0x5401 18207 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 18208 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 18209 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 18210 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 18211 #define LPR 0x00 18212 #define PABR0 0x02 18213 #define PABR1 0x03 18214 #define WCRL 0x04 18215 #define WCRM 0x05 18216 #define WCRH 0x06 18217 #define DPCR 0x08 18218 #define DMER 0x09 18219 #define ISR0 0x10 18220 #define ISR1 0x11 18221 #define ISR2 0x12 18222 #define IER0 0x14 18223 #define IER1 0x15 18224 #define IER2 0x16 18225 #define ITCR 0x18 18226 #define INTVR 0x1a 18227 #define IMVR 0x1c 18228 #define TRB 0x20 18229 #define TRBL 0x20 18230 #define TRBH 0x21 18231 #define SR0 0x22 18232 #define SR1 0x23 18233 #define SR2 0x24 18234 #define SR3 0x25 18235 #define FST 0x26 18236 #define IE0 0x28 18237 #define IE1 0x29 18238 #define IE2 0x2a 18239 #define FIE 0x2b 18240 #define CMD 0x2c 18241 #define MD0 0x2e 18242 #define MD1 0x2f 18243 #define MD2 0x30 18244 #define CTL 0x31 18245 #define SA0 0x32 18246 #define SA1 0x33 18247 #define IDL 0x34 18248 #define TMC 0x35 18249 #define RXS 0x36 18250 #define TXS 0x37 18251 #define TRC0 0x38 18252 #define TRC1 0x39 18253 #define RRC 0x3a 18254 #define CST0 0x3c 18255 #define CST1 0x3d 18256 #define TCNT 0x60 18257 #define TCNTL 0x60 18258 #define TCNTH 0x61 18259 #define TCONR 0x62 18260 #define TCONRL 0x62 18261 #define TCONRH 0x63 18262 #define TMCS 0x64 18263 #define TEPR 0x65 18264 #define DARL 0x80 18265 #define DARH 0x81 18266 #define DARB 0x82 18267 #define BAR 0x80 18268 #define BARL 0x80 18269 #define BARH 0x81 18270 #define BARB 0x82 18271 #define SAR 0x84 18272 #define SARL 0x84 18273 #define SARH 0x85 18274 #define SARB 0x86 18275 #define CPB 0x86 18276 #define CDA 0x88 18277 #define CDAL 0x88 18278 #define CDAH 0x89 18279 #define EDA 0x8a 18280 #define EDAL 0x8a 18281 #define EDAH 0x8b 18282 #define BFL 0x8c 18283 #define BFLL 0x8c 18284 #define BFLH 0x8d 18285 #define BCR 0x8e 18286 #define BCRL 0x8e 18287 #define BCRH 0x8f 18288 #define DSR 0x90 18289 #define DMR 0x91 18290 #define FCT 0x93 18291 #define DIR 0x94 18292 #define DCMD 0x95 18293 #define TIMER0 0x00 18294 #define TIMER1 0x08 18295 #define TIMER2 0x10 18296 #define TIMER3 0x18 18297 #define RXDMA 0x00 18298 #define TXDMA 0x20 18299 #define NOOP 0x00 18300 #define TXRESET 0x01 18301 #define TXENABLE 0x02 18302 #define TXDISABLE 0x03 18303 #define TXCRCINIT 0x04 18304 #define TXCRCEXCL 0x05 18305 #define TXEOM 0x06 18306 #define TXABORT 0x07 18307 #define MPON 0x08 18308 #define TXBUFCLR 0x09 18309 #define RXRESET 0x11 18310 #define RXENABLE 0x12 18311 #define RXDISABLE 0x13 18312 #define RXCRCINIT 0x14 18313 #define RXREJECT 0x15 18314 #define SEARCHMP 0x16 18315 #define RXCRCEXCL 0x17 18316 #define RXCRCCALC 0x18 18317 #define CHRESET 0x21 18318 #define HUNT 0x31 18319 #define SWABORT 0x01 18320 #define FEICLEAR 0x02 18321 #define TXINTE BIT7 18322 #define RXINTE BIT6 18323 #define TXRDYE BIT1 18324 #define RXRDYE BIT0 18325 #define UDRN BIT7 18326 #define IDLE BIT6 18327 #define SYNCD BIT4 18328 #define FLGD BIT4 18329 #define CCTS BIT3 18330 #define CDCD BIT2 18331 #define BRKD BIT1 18332 #define ABTD BIT1 18333 #define GAPD BIT1 18334 #define BRKE BIT0 18335 #define IDLD BIT0 18336 #define EOM BIT7 18337 #define PMP BIT6 18338 #define SHRT BIT6 18339 #define PE BIT5 18340 #define ABT BIT5 18341 #define FRME BIT4 18342 #define RBIT BIT4 18343 #define OVRN BIT3 18344 #define CRCE BIT2 18345 #define WAKEUP_CHARS 256 18346 #if SYNCLINK_GENERIC_HDLC 18347 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 18348 #endif 18349 #ifdef SANITY_CHECK 18350 #else 18351 #endif 18352 /* LDV_COMMENT_END_PREP */ 18353 /* LDV_COMMENT_FUNCTION_CALL Function from field "set_termios" from driver structure with callbacks "ops" */ 18354 ldv_handler_precall(); 18355 set_termios( var_group8, var_group9); 18356 /* LDV_COMMENT_BEGIN_PREP */ 18357 #if SYNCLINK_GENERIC_HDLC 18358 #endif 18359 #if SYNCLINK_GENERIC_HDLC 18360 #endif 18361 #if SYNCLINK_GENERIC_HDLC 18362 #endif 18363 #ifdef CMSPAR 18364 #endif 18365 #if SYNCLINK_GENERIC_HDLC 18366 #endif 18367 #if SYNCLINK_GENERIC_HDLC 18368 #endif 18369 #if 0 18370 #endif 18371 #if SYNCLINK_GENERIC_HDLC 18372 #endif 18373 #if SYNCLINK_GENERIC_HDLC 18374 #endif 18375 #define TESTFRAMESIZE 20 18376 #if SYNCLINK_GENERIC_HDLC 18377 #endif 18378 #define CALC_REGADDR() \ 18379 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 18380 if (info->port_num > 1) \ 18381 RegAddr += 256; \ 18382 if ( info->port_num & 1) { \ 18383 if (Addr > 0x7f) \ 18384 RegAddr += 0x40; \ 18385 else if (Addr > 0x1f && Addr < 0x60) \ 18386 RegAddr += 0x20; \ 18387 } 18388 /* LDV_COMMENT_END_PREP */ 18389 18390 18391 18392 18393 } 18394 18395 break; 18396 case 25: { 18397 18398 /** STRUCT: struct type: tty_operations, struct name: ops **/ 18399 18400 18401 /* content: static void tx_hold(struct tty_struct *tty)*/ 18402 /* LDV_COMMENT_BEGIN_PREP */ 18403 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 18404 #if defined(__i386__) 18405 # define BREAKPOINT() asm(" int $3"); 18406 #else 18407 # define BREAKPOINT() { } 18408 #endif 18409 #define MAX_DEVICES 12 18410 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 18411 #define SYNCLINK_GENERIC_HDLC 1 18412 #else 18413 #define SYNCLINK_GENERIC_HDLC 0 18414 #endif 18415 #define GET_USER(error,value,addr) error = get_user(value,addr) 18416 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 18417 #define PUT_USER(error,value,addr) error = put_user(value,addr) 18418 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 18419 #define SCABUFSIZE 1024 18420 #define SCA_MEM_SIZE 0x40000 18421 #define SCA_BASE_SIZE 512 18422 #define SCA_REG_SIZE 16 18423 #define SCA_MAX_PORTS 4 18424 #define SCAMAXDESC 128 18425 #define BUFFERLISTSIZE 4096 18426 #define BH_RECEIVE 1 18427 #define BH_TRANSMIT 2 18428 #define BH_STATUS 4 18429 #define IO_PIN_SHUTDOWN_LIMIT 100 18430 #if SYNCLINK_GENERIC_HDLC 18431 #endif 18432 #define MGSL_MAGIC 0x5401 18433 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 18434 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 18435 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 18436 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 18437 #define LPR 0x00 18438 #define PABR0 0x02 18439 #define PABR1 0x03 18440 #define WCRL 0x04 18441 #define WCRM 0x05 18442 #define WCRH 0x06 18443 #define DPCR 0x08 18444 #define DMER 0x09 18445 #define ISR0 0x10 18446 #define ISR1 0x11 18447 #define ISR2 0x12 18448 #define IER0 0x14 18449 #define IER1 0x15 18450 #define IER2 0x16 18451 #define ITCR 0x18 18452 #define INTVR 0x1a 18453 #define IMVR 0x1c 18454 #define TRB 0x20 18455 #define TRBL 0x20 18456 #define TRBH 0x21 18457 #define SR0 0x22 18458 #define SR1 0x23 18459 #define SR2 0x24 18460 #define SR3 0x25 18461 #define FST 0x26 18462 #define IE0 0x28 18463 #define IE1 0x29 18464 #define IE2 0x2a 18465 #define FIE 0x2b 18466 #define CMD 0x2c 18467 #define MD0 0x2e 18468 #define MD1 0x2f 18469 #define MD2 0x30 18470 #define CTL 0x31 18471 #define SA0 0x32 18472 #define SA1 0x33 18473 #define IDL 0x34 18474 #define TMC 0x35 18475 #define RXS 0x36 18476 #define TXS 0x37 18477 #define TRC0 0x38 18478 #define TRC1 0x39 18479 #define RRC 0x3a 18480 #define CST0 0x3c 18481 #define CST1 0x3d 18482 #define TCNT 0x60 18483 #define TCNTL 0x60 18484 #define TCNTH 0x61 18485 #define TCONR 0x62 18486 #define TCONRL 0x62 18487 #define TCONRH 0x63 18488 #define TMCS 0x64 18489 #define TEPR 0x65 18490 #define DARL 0x80 18491 #define DARH 0x81 18492 #define DARB 0x82 18493 #define BAR 0x80 18494 #define BARL 0x80 18495 #define BARH 0x81 18496 #define BARB 0x82 18497 #define SAR 0x84 18498 #define SARL 0x84 18499 #define SARH 0x85 18500 #define SARB 0x86 18501 #define CPB 0x86 18502 #define CDA 0x88 18503 #define CDAL 0x88 18504 #define CDAH 0x89 18505 #define EDA 0x8a 18506 #define EDAL 0x8a 18507 #define EDAH 0x8b 18508 #define BFL 0x8c 18509 #define BFLL 0x8c 18510 #define BFLH 0x8d 18511 #define BCR 0x8e 18512 #define BCRL 0x8e 18513 #define BCRH 0x8f 18514 #define DSR 0x90 18515 #define DMR 0x91 18516 #define FCT 0x93 18517 #define DIR 0x94 18518 #define DCMD 0x95 18519 #define TIMER0 0x00 18520 #define TIMER1 0x08 18521 #define TIMER2 0x10 18522 #define TIMER3 0x18 18523 #define RXDMA 0x00 18524 #define TXDMA 0x20 18525 #define NOOP 0x00 18526 #define TXRESET 0x01 18527 #define TXENABLE 0x02 18528 #define TXDISABLE 0x03 18529 #define TXCRCINIT 0x04 18530 #define TXCRCEXCL 0x05 18531 #define TXEOM 0x06 18532 #define TXABORT 0x07 18533 #define MPON 0x08 18534 #define TXBUFCLR 0x09 18535 #define RXRESET 0x11 18536 #define RXENABLE 0x12 18537 #define RXDISABLE 0x13 18538 #define RXCRCINIT 0x14 18539 #define RXREJECT 0x15 18540 #define SEARCHMP 0x16 18541 #define RXCRCEXCL 0x17 18542 #define RXCRCCALC 0x18 18543 #define CHRESET 0x21 18544 #define HUNT 0x31 18545 #define SWABORT 0x01 18546 #define FEICLEAR 0x02 18547 #define TXINTE BIT7 18548 #define RXINTE BIT6 18549 #define TXRDYE BIT1 18550 #define RXRDYE BIT0 18551 #define UDRN BIT7 18552 #define IDLE BIT6 18553 #define SYNCD BIT4 18554 #define FLGD BIT4 18555 #define CCTS BIT3 18556 #define CDCD BIT2 18557 #define BRKD BIT1 18558 #define ABTD BIT1 18559 #define GAPD BIT1 18560 #define BRKE BIT0 18561 #define IDLD BIT0 18562 #define EOM BIT7 18563 #define PMP BIT6 18564 #define SHRT BIT6 18565 #define PE BIT5 18566 #define ABT BIT5 18567 #define FRME BIT4 18568 #define RBIT BIT4 18569 #define OVRN BIT3 18570 #define CRCE BIT2 18571 #define WAKEUP_CHARS 256 18572 #if SYNCLINK_GENERIC_HDLC 18573 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 18574 #endif 18575 #ifdef SANITY_CHECK 18576 #else 18577 #endif 18578 /* LDV_COMMENT_END_PREP */ 18579 /* LDV_COMMENT_FUNCTION_CALL Function from field "stop" from driver structure with callbacks "ops" */ 18580 ldv_handler_precall(); 18581 tx_hold( var_group8); 18582 /* LDV_COMMENT_BEGIN_PREP */ 18583 #if SYNCLINK_GENERIC_HDLC 18584 #endif 18585 #if SYNCLINK_GENERIC_HDLC 18586 #endif 18587 #if SYNCLINK_GENERIC_HDLC 18588 #endif 18589 #ifdef CMSPAR 18590 #endif 18591 #if SYNCLINK_GENERIC_HDLC 18592 #endif 18593 #if SYNCLINK_GENERIC_HDLC 18594 #endif 18595 #if 0 18596 #endif 18597 #if SYNCLINK_GENERIC_HDLC 18598 #endif 18599 #if SYNCLINK_GENERIC_HDLC 18600 #endif 18601 #define TESTFRAMESIZE 20 18602 #if SYNCLINK_GENERIC_HDLC 18603 #endif 18604 #define CALC_REGADDR() \ 18605 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 18606 if (info->port_num > 1) \ 18607 RegAddr += 256; \ 18608 if ( info->port_num & 1) { \ 18609 if (Addr > 0x7f) \ 18610 RegAddr += 0x40; \ 18611 else if (Addr > 0x1f && Addr < 0x60) \ 18612 RegAddr += 0x20; \ 18613 } 18614 /* LDV_COMMENT_END_PREP */ 18615 18616 18617 18618 18619 } 18620 18621 break; 18622 case 26: { 18623 18624 /** STRUCT: struct type: tty_operations, struct name: ops **/ 18625 18626 18627 /* content: static void tx_release(struct tty_struct *tty)*/ 18628 /* LDV_COMMENT_BEGIN_PREP */ 18629 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 18630 #if defined(__i386__) 18631 # define BREAKPOINT() asm(" int $3"); 18632 #else 18633 # define BREAKPOINT() { } 18634 #endif 18635 #define MAX_DEVICES 12 18636 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 18637 #define SYNCLINK_GENERIC_HDLC 1 18638 #else 18639 #define SYNCLINK_GENERIC_HDLC 0 18640 #endif 18641 #define GET_USER(error,value,addr) error = get_user(value,addr) 18642 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 18643 #define PUT_USER(error,value,addr) error = put_user(value,addr) 18644 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 18645 #define SCABUFSIZE 1024 18646 #define SCA_MEM_SIZE 0x40000 18647 #define SCA_BASE_SIZE 512 18648 #define SCA_REG_SIZE 16 18649 #define SCA_MAX_PORTS 4 18650 #define SCAMAXDESC 128 18651 #define BUFFERLISTSIZE 4096 18652 #define BH_RECEIVE 1 18653 #define BH_TRANSMIT 2 18654 #define BH_STATUS 4 18655 #define IO_PIN_SHUTDOWN_LIMIT 100 18656 #if SYNCLINK_GENERIC_HDLC 18657 #endif 18658 #define MGSL_MAGIC 0x5401 18659 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 18660 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 18661 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 18662 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 18663 #define LPR 0x00 18664 #define PABR0 0x02 18665 #define PABR1 0x03 18666 #define WCRL 0x04 18667 #define WCRM 0x05 18668 #define WCRH 0x06 18669 #define DPCR 0x08 18670 #define DMER 0x09 18671 #define ISR0 0x10 18672 #define ISR1 0x11 18673 #define ISR2 0x12 18674 #define IER0 0x14 18675 #define IER1 0x15 18676 #define IER2 0x16 18677 #define ITCR 0x18 18678 #define INTVR 0x1a 18679 #define IMVR 0x1c 18680 #define TRB 0x20 18681 #define TRBL 0x20 18682 #define TRBH 0x21 18683 #define SR0 0x22 18684 #define SR1 0x23 18685 #define SR2 0x24 18686 #define SR3 0x25 18687 #define FST 0x26 18688 #define IE0 0x28 18689 #define IE1 0x29 18690 #define IE2 0x2a 18691 #define FIE 0x2b 18692 #define CMD 0x2c 18693 #define MD0 0x2e 18694 #define MD1 0x2f 18695 #define MD2 0x30 18696 #define CTL 0x31 18697 #define SA0 0x32 18698 #define SA1 0x33 18699 #define IDL 0x34 18700 #define TMC 0x35 18701 #define RXS 0x36 18702 #define TXS 0x37 18703 #define TRC0 0x38 18704 #define TRC1 0x39 18705 #define RRC 0x3a 18706 #define CST0 0x3c 18707 #define CST1 0x3d 18708 #define TCNT 0x60 18709 #define TCNTL 0x60 18710 #define TCNTH 0x61 18711 #define TCONR 0x62 18712 #define TCONRL 0x62 18713 #define TCONRH 0x63 18714 #define TMCS 0x64 18715 #define TEPR 0x65 18716 #define DARL 0x80 18717 #define DARH 0x81 18718 #define DARB 0x82 18719 #define BAR 0x80 18720 #define BARL 0x80 18721 #define BARH 0x81 18722 #define BARB 0x82 18723 #define SAR 0x84 18724 #define SARL 0x84 18725 #define SARH 0x85 18726 #define SARB 0x86 18727 #define CPB 0x86 18728 #define CDA 0x88 18729 #define CDAL 0x88 18730 #define CDAH 0x89 18731 #define EDA 0x8a 18732 #define EDAL 0x8a 18733 #define EDAH 0x8b 18734 #define BFL 0x8c 18735 #define BFLL 0x8c 18736 #define BFLH 0x8d 18737 #define BCR 0x8e 18738 #define BCRL 0x8e 18739 #define BCRH 0x8f 18740 #define DSR 0x90 18741 #define DMR 0x91 18742 #define FCT 0x93 18743 #define DIR 0x94 18744 #define DCMD 0x95 18745 #define TIMER0 0x00 18746 #define TIMER1 0x08 18747 #define TIMER2 0x10 18748 #define TIMER3 0x18 18749 #define RXDMA 0x00 18750 #define TXDMA 0x20 18751 #define NOOP 0x00 18752 #define TXRESET 0x01 18753 #define TXENABLE 0x02 18754 #define TXDISABLE 0x03 18755 #define TXCRCINIT 0x04 18756 #define TXCRCEXCL 0x05 18757 #define TXEOM 0x06 18758 #define TXABORT 0x07 18759 #define MPON 0x08 18760 #define TXBUFCLR 0x09 18761 #define RXRESET 0x11 18762 #define RXENABLE 0x12 18763 #define RXDISABLE 0x13 18764 #define RXCRCINIT 0x14 18765 #define RXREJECT 0x15 18766 #define SEARCHMP 0x16 18767 #define RXCRCEXCL 0x17 18768 #define RXCRCCALC 0x18 18769 #define CHRESET 0x21 18770 #define HUNT 0x31 18771 #define SWABORT 0x01 18772 #define FEICLEAR 0x02 18773 #define TXINTE BIT7 18774 #define RXINTE BIT6 18775 #define TXRDYE BIT1 18776 #define RXRDYE BIT0 18777 #define UDRN BIT7 18778 #define IDLE BIT6 18779 #define SYNCD BIT4 18780 #define FLGD BIT4 18781 #define CCTS BIT3 18782 #define CDCD BIT2 18783 #define BRKD BIT1 18784 #define ABTD BIT1 18785 #define GAPD BIT1 18786 #define BRKE BIT0 18787 #define IDLD BIT0 18788 #define EOM BIT7 18789 #define PMP BIT6 18790 #define SHRT BIT6 18791 #define PE BIT5 18792 #define ABT BIT5 18793 #define FRME BIT4 18794 #define RBIT BIT4 18795 #define OVRN BIT3 18796 #define CRCE BIT2 18797 #define WAKEUP_CHARS 256 18798 #if SYNCLINK_GENERIC_HDLC 18799 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 18800 #endif 18801 #ifdef SANITY_CHECK 18802 #else 18803 #endif 18804 /* LDV_COMMENT_END_PREP */ 18805 /* LDV_COMMENT_FUNCTION_CALL Function from field "start" from driver structure with callbacks "ops" */ 18806 ldv_handler_precall(); 18807 tx_release( var_group8); 18808 /* LDV_COMMENT_BEGIN_PREP */ 18809 #if SYNCLINK_GENERIC_HDLC 18810 #endif 18811 #if SYNCLINK_GENERIC_HDLC 18812 #endif 18813 #if SYNCLINK_GENERIC_HDLC 18814 #endif 18815 #ifdef CMSPAR 18816 #endif 18817 #if SYNCLINK_GENERIC_HDLC 18818 #endif 18819 #if SYNCLINK_GENERIC_HDLC 18820 #endif 18821 #if 0 18822 #endif 18823 #if SYNCLINK_GENERIC_HDLC 18824 #endif 18825 #if SYNCLINK_GENERIC_HDLC 18826 #endif 18827 #define TESTFRAMESIZE 20 18828 #if SYNCLINK_GENERIC_HDLC 18829 #endif 18830 #define CALC_REGADDR() \ 18831 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 18832 if (info->port_num > 1) \ 18833 RegAddr += 256; \ 18834 if ( info->port_num & 1) { \ 18835 if (Addr > 0x7f) \ 18836 RegAddr += 0x40; \ 18837 else if (Addr > 0x1f && Addr < 0x60) \ 18838 RegAddr += 0x20; \ 18839 } 18840 /* LDV_COMMENT_END_PREP */ 18841 18842 18843 18844 18845 } 18846 18847 break; 18848 case 27: { 18849 18850 /** STRUCT: struct type: tty_operations, struct name: ops **/ 18851 18852 18853 /* content: static void hangup(struct tty_struct *tty)*/ 18854 /* LDV_COMMENT_BEGIN_PREP */ 18855 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 18856 #if defined(__i386__) 18857 # define BREAKPOINT() asm(" int $3"); 18858 #else 18859 # define BREAKPOINT() { } 18860 #endif 18861 #define MAX_DEVICES 12 18862 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 18863 #define SYNCLINK_GENERIC_HDLC 1 18864 #else 18865 #define SYNCLINK_GENERIC_HDLC 0 18866 #endif 18867 #define GET_USER(error,value,addr) error = get_user(value,addr) 18868 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 18869 #define PUT_USER(error,value,addr) error = put_user(value,addr) 18870 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 18871 #define SCABUFSIZE 1024 18872 #define SCA_MEM_SIZE 0x40000 18873 #define SCA_BASE_SIZE 512 18874 #define SCA_REG_SIZE 16 18875 #define SCA_MAX_PORTS 4 18876 #define SCAMAXDESC 128 18877 #define BUFFERLISTSIZE 4096 18878 #define BH_RECEIVE 1 18879 #define BH_TRANSMIT 2 18880 #define BH_STATUS 4 18881 #define IO_PIN_SHUTDOWN_LIMIT 100 18882 #if SYNCLINK_GENERIC_HDLC 18883 #endif 18884 #define MGSL_MAGIC 0x5401 18885 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 18886 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 18887 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 18888 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 18889 #define LPR 0x00 18890 #define PABR0 0x02 18891 #define PABR1 0x03 18892 #define WCRL 0x04 18893 #define WCRM 0x05 18894 #define WCRH 0x06 18895 #define DPCR 0x08 18896 #define DMER 0x09 18897 #define ISR0 0x10 18898 #define ISR1 0x11 18899 #define ISR2 0x12 18900 #define IER0 0x14 18901 #define IER1 0x15 18902 #define IER2 0x16 18903 #define ITCR 0x18 18904 #define INTVR 0x1a 18905 #define IMVR 0x1c 18906 #define TRB 0x20 18907 #define TRBL 0x20 18908 #define TRBH 0x21 18909 #define SR0 0x22 18910 #define SR1 0x23 18911 #define SR2 0x24 18912 #define SR3 0x25 18913 #define FST 0x26 18914 #define IE0 0x28 18915 #define IE1 0x29 18916 #define IE2 0x2a 18917 #define FIE 0x2b 18918 #define CMD 0x2c 18919 #define MD0 0x2e 18920 #define MD1 0x2f 18921 #define MD2 0x30 18922 #define CTL 0x31 18923 #define SA0 0x32 18924 #define SA1 0x33 18925 #define IDL 0x34 18926 #define TMC 0x35 18927 #define RXS 0x36 18928 #define TXS 0x37 18929 #define TRC0 0x38 18930 #define TRC1 0x39 18931 #define RRC 0x3a 18932 #define CST0 0x3c 18933 #define CST1 0x3d 18934 #define TCNT 0x60 18935 #define TCNTL 0x60 18936 #define TCNTH 0x61 18937 #define TCONR 0x62 18938 #define TCONRL 0x62 18939 #define TCONRH 0x63 18940 #define TMCS 0x64 18941 #define TEPR 0x65 18942 #define DARL 0x80 18943 #define DARH 0x81 18944 #define DARB 0x82 18945 #define BAR 0x80 18946 #define BARL 0x80 18947 #define BARH 0x81 18948 #define BARB 0x82 18949 #define SAR 0x84 18950 #define SARL 0x84 18951 #define SARH 0x85 18952 #define SARB 0x86 18953 #define CPB 0x86 18954 #define CDA 0x88 18955 #define CDAL 0x88 18956 #define CDAH 0x89 18957 #define EDA 0x8a 18958 #define EDAL 0x8a 18959 #define EDAH 0x8b 18960 #define BFL 0x8c 18961 #define BFLL 0x8c 18962 #define BFLH 0x8d 18963 #define BCR 0x8e 18964 #define BCRL 0x8e 18965 #define BCRH 0x8f 18966 #define DSR 0x90 18967 #define DMR 0x91 18968 #define FCT 0x93 18969 #define DIR 0x94 18970 #define DCMD 0x95 18971 #define TIMER0 0x00 18972 #define TIMER1 0x08 18973 #define TIMER2 0x10 18974 #define TIMER3 0x18 18975 #define RXDMA 0x00 18976 #define TXDMA 0x20 18977 #define NOOP 0x00 18978 #define TXRESET 0x01 18979 #define TXENABLE 0x02 18980 #define TXDISABLE 0x03 18981 #define TXCRCINIT 0x04 18982 #define TXCRCEXCL 0x05 18983 #define TXEOM 0x06 18984 #define TXABORT 0x07 18985 #define MPON 0x08 18986 #define TXBUFCLR 0x09 18987 #define RXRESET 0x11 18988 #define RXENABLE 0x12 18989 #define RXDISABLE 0x13 18990 #define RXCRCINIT 0x14 18991 #define RXREJECT 0x15 18992 #define SEARCHMP 0x16 18993 #define RXCRCEXCL 0x17 18994 #define RXCRCCALC 0x18 18995 #define CHRESET 0x21 18996 #define HUNT 0x31 18997 #define SWABORT 0x01 18998 #define FEICLEAR 0x02 18999 #define TXINTE BIT7 19000 #define RXINTE BIT6 19001 #define TXRDYE BIT1 19002 #define RXRDYE BIT0 19003 #define UDRN BIT7 19004 #define IDLE BIT6 19005 #define SYNCD BIT4 19006 #define FLGD BIT4 19007 #define CCTS BIT3 19008 #define CDCD BIT2 19009 #define BRKD BIT1 19010 #define ABTD BIT1 19011 #define GAPD BIT1 19012 #define BRKE BIT0 19013 #define IDLD BIT0 19014 #define EOM BIT7 19015 #define PMP BIT6 19016 #define SHRT BIT6 19017 #define PE BIT5 19018 #define ABT BIT5 19019 #define FRME BIT4 19020 #define RBIT BIT4 19021 #define OVRN BIT3 19022 #define CRCE BIT2 19023 #define WAKEUP_CHARS 256 19024 #if SYNCLINK_GENERIC_HDLC 19025 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19026 #endif 19027 #ifdef SANITY_CHECK 19028 #else 19029 #endif 19030 /* LDV_COMMENT_END_PREP */ 19031 /* LDV_COMMENT_FUNCTION_CALL Function from field "hangup" from driver structure with callbacks "ops" */ 19032 ldv_handler_precall(); 19033 hangup( var_group8); 19034 /* LDV_COMMENT_BEGIN_PREP */ 19035 #if SYNCLINK_GENERIC_HDLC 19036 #endif 19037 #if SYNCLINK_GENERIC_HDLC 19038 #endif 19039 #if SYNCLINK_GENERIC_HDLC 19040 #endif 19041 #ifdef CMSPAR 19042 #endif 19043 #if SYNCLINK_GENERIC_HDLC 19044 #endif 19045 #if SYNCLINK_GENERIC_HDLC 19046 #endif 19047 #if 0 19048 #endif 19049 #if SYNCLINK_GENERIC_HDLC 19050 #endif 19051 #if SYNCLINK_GENERIC_HDLC 19052 #endif 19053 #define TESTFRAMESIZE 20 19054 #if SYNCLINK_GENERIC_HDLC 19055 #endif 19056 #define CALC_REGADDR() \ 19057 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19058 if (info->port_num > 1) \ 19059 RegAddr += 256; \ 19060 if ( info->port_num & 1) { \ 19061 if (Addr > 0x7f) \ 19062 RegAddr += 0x40; \ 19063 else if (Addr > 0x1f && Addr < 0x60) \ 19064 RegAddr += 0x20; \ 19065 } 19066 /* LDV_COMMENT_END_PREP */ 19067 19068 19069 19070 19071 } 19072 19073 break; 19074 case 28: { 19075 19076 /** STRUCT: struct type: tty_operations, struct name: ops **/ 19077 19078 19079 /* content: static int tiocmget(struct tty_struct *tty)*/ 19080 /* LDV_COMMENT_BEGIN_PREP */ 19081 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19082 #if defined(__i386__) 19083 # define BREAKPOINT() asm(" int $3"); 19084 #else 19085 # define BREAKPOINT() { } 19086 #endif 19087 #define MAX_DEVICES 12 19088 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19089 #define SYNCLINK_GENERIC_HDLC 1 19090 #else 19091 #define SYNCLINK_GENERIC_HDLC 0 19092 #endif 19093 #define GET_USER(error,value,addr) error = get_user(value,addr) 19094 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19095 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19096 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19097 #define SCABUFSIZE 1024 19098 #define SCA_MEM_SIZE 0x40000 19099 #define SCA_BASE_SIZE 512 19100 #define SCA_REG_SIZE 16 19101 #define SCA_MAX_PORTS 4 19102 #define SCAMAXDESC 128 19103 #define BUFFERLISTSIZE 4096 19104 #define BH_RECEIVE 1 19105 #define BH_TRANSMIT 2 19106 #define BH_STATUS 4 19107 #define IO_PIN_SHUTDOWN_LIMIT 100 19108 #if SYNCLINK_GENERIC_HDLC 19109 #endif 19110 #define MGSL_MAGIC 0x5401 19111 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 19112 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 19113 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 19114 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 19115 #define LPR 0x00 19116 #define PABR0 0x02 19117 #define PABR1 0x03 19118 #define WCRL 0x04 19119 #define WCRM 0x05 19120 #define WCRH 0x06 19121 #define DPCR 0x08 19122 #define DMER 0x09 19123 #define ISR0 0x10 19124 #define ISR1 0x11 19125 #define ISR2 0x12 19126 #define IER0 0x14 19127 #define IER1 0x15 19128 #define IER2 0x16 19129 #define ITCR 0x18 19130 #define INTVR 0x1a 19131 #define IMVR 0x1c 19132 #define TRB 0x20 19133 #define TRBL 0x20 19134 #define TRBH 0x21 19135 #define SR0 0x22 19136 #define SR1 0x23 19137 #define SR2 0x24 19138 #define SR3 0x25 19139 #define FST 0x26 19140 #define IE0 0x28 19141 #define IE1 0x29 19142 #define IE2 0x2a 19143 #define FIE 0x2b 19144 #define CMD 0x2c 19145 #define MD0 0x2e 19146 #define MD1 0x2f 19147 #define MD2 0x30 19148 #define CTL 0x31 19149 #define SA0 0x32 19150 #define SA1 0x33 19151 #define IDL 0x34 19152 #define TMC 0x35 19153 #define RXS 0x36 19154 #define TXS 0x37 19155 #define TRC0 0x38 19156 #define TRC1 0x39 19157 #define RRC 0x3a 19158 #define CST0 0x3c 19159 #define CST1 0x3d 19160 #define TCNT 0x60 19161 #define TCNTL 0x60 19162 #define TCNTH 0x61 19163 #define TCONR 0x62 19164 #define TCONRL 0x62 19165 #define TCONRH 0x63 19166 #define TMCS 0x64 19167 #define TEPR 0x65 19168 #define DARL 0x80 19169 #define DARH 0x81 19170 #define DARB 0x82 19171 #define BAR 0x80 19172 #define BARL 0x80 19173 #define BARH 0x81 19174 #define BARB 0x82 19175 #define SAR 0x84 19176 #define SARL 0x84 19177 #define SARH 0x85 19178 #define SARB 0x86 19179 #define CPB 0x86 19180 #define CDA 0x88 19181 #define CDAL 0x88 19182 #define CDAH 0x89 19183 #define EDA 0x8a 19184 #define EDAL 0x8a 19185 #define EDAH 0x8b 19186 #define BFL 0x8c 19187 #define BFLL 0x8c 19188 #define BFLH 0x8d 19189 #define BCR 0x8e 19190 #define BCRL 0x8e 19191 #define BCRH 0x8f 19192 #define DSR 0x90 19193 #define DMR 0x91 19194 #define FCT 0x93 19195 #define DIR 0x94 19196 #define DCMD 0x95 19197 #define TIMER0 0x00 19198 #define TIMER1 0x08 19199 #define TIMER2 0x10 19200 #define TIMER3 0x18 19201 #define RXDMA 0x00 19202 #define TXDMA 0x20 19203 #define NOOP 0x00 19204 #define TXRESET 0x01 19205 #define TXENABLE 0x02 19206 #define TXDISABLE 0x03 19207 #define TXCRCINIT 0x04 19208 #define TXCRCEXCL 0x05 19209 #define TXEOM 0x06 19210 #define TXABORT 0x07 19211 #define MPON 0x08 19212 #define TXBUFCLR 0x09 19213 #define RXRESET 0x11 19214 #define RXENABLE 0x12 19215 #define RXDISABLE 0x13 19216 #define RXCRCINIT 0x14 19217 #define RXREJECT 0x15 19218 #define SEARCHMP 0x16 19219 #define RXCRCEXCL 0x17 19220 #define RXCRCCALC 0x18 19221 #define CHRESET 0x21 19222 #define HUNT 0x31 19223 #define SWABORT 0x01 19224 #define FEICLEAR 0x02 19225 #define TXINTE BIT7 19226 #define RXINTE BIT6 19227 #define TXRDYE BIT1 19228 #define RXRDYE BIT0 19229 #define UDRN BIT7 19230 #define IDLE BIT6 19231 #define SYNCD BIT4 19232 #define FLGD BIT4 19233 #define CCTS BIT3 19234 #define CDCD BIT2 19235 #define BRKD BIT1 19236 #define ABTD BIT1 19237 #define GAPD BIT1 19238 #define BRKE BIT0 19239 #define IDLD BIT0 19240 #define EOM BIT7 19241 #define PMP BIT6 19242 #define SHRT BIT6 19243 #define PE BIT5 19244 #define ABT BIT5 19245 #define FRME BIT4 19246 #define RBIT BIT4 19247 #define OVRN BIT3 19248 #define CRCE BIT2 19249 #define WAKEUP_CHARS 256 19250 #if SYNCLINK_GENERIC_HDLC 19251 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19252 #endif 19253 #ifdef SANITY_CHECK 19254 #else 19255 #endif 19256 #if SYNCLINK_GENERIC_HDLC 19257 #endif 19258 #if SYNCLINK_GENERIC_HDLC 19259 #endif 19260 #if SYNCLINK_GENERIC_HDLC 19261 #endif 19262 #ifdef CMSPAR 19263 #endif 19264 /* LDV_COMMENT_END_PREP */ 19265 /* LDV_COMMENT_FUNCTION_CALL Function from field "tiocmget" from driver structure with callbacks "ops" */ 19266 ldv_handler_precall(); 19267 tiocmget( var_group8); 19268 /* LDV_COMMENT_BEGIN_PREP */ 19269 #if SYNCLINK_GENERIC_HDLC 19270 #endif 19271 #if SYNCLINK_GENERIC_HDLC 19272 #endif 19273 #if 0 19274 #endif 19275 #if SYNCLINK_GENERIC_HDLC 19276 #endif 19277 #if SYNCLINK_GENERIC_HDLC 19278 #endif 19279 #define TESTFRAMESIZE 20 19280 #if SYNCLINK_GENERIC_HDLC 19281 #endif 19282 #define CALC_REGADDR() \ 19283 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19284 if (info->port_num > 1) \ 19285 RegAddr += 256; \ 19286 if ( info->port_num & 1) { \ 19287 if (Addr > 0x7f) \ 19288 RegAddr += 0x40; \ 19289 else if (Addr > 0x1f && Addr < 0x60) \ 19290 RegAddr += 0x20; \ 19291 } 19292 /* LDV_COMMENT_END_PREP */ 19293 19294 19295 19296 19297 } 19298 19299 break; 19300 case 29: { 19301 19302 /** STRUCT: struct type: tty_operations, struct name: ops **/ 19303 19304 19305 /* content: static int tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)*/ 19306 /* LDV_COMMENT_BEGIN_PREP */ 19307 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19308 #if defined(__i386__) 19309 # define BREAKPOINT() asm(" int $3"); 19310 #else 19311 # define BREAKPOINT() { } 19312 #endif 19313 #define MAX_DEVICES 12 19314 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19315 #define SYNCLINK_GENERIC_HDLC 1 19316 #else 19317 #define SYNCLINK_GENERIC_HDLC 0 19318 #endif 19319 #define GET_USER(error,value,addr) error = get_user(value,addr) 19320 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19321 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19322 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19323 #define SCABUFSIZE 1024 19324 #define SCA_MEM_SIZE 0x40000 19325 #define SCA_BASE_SIZE 512 19326 #define SCA_REG_SIZE 16 19327 #define SCA_MAX_PORTS 4 19328 #define SCAMAXDESC 128 19329 #define BUFFERLISTSIZE 4096 19330 #define BH_RECEIVE 1 19331 #define BH_TRANSMIT 2 19332 #define BH_STATUS 4 19333 #define IO_PIN_SHUTDOWN_LIMIT 100 19334 #if SYNCLINK_GENERIC_HDLC 19335 #endif 19336 #define MGSL_MAGIC 0x5401 19337 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 19338 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 19339 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 19340 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 19341 #define LPR 0x00 19342 #define PABR0 0x02 19343 #define PABR1 0x03 19344 #define WCRL 0x04 19345 #define WCRM 0x05 19346 #define WCRH 0x06 19347 #define DPCR 0x08 19348 #define DMER 0x09 19349 #define ISR0 0x10 19350 #define ISR1 0x11 19351 #define ISR2 0x12 19352 #define IER0 0x14 19353 #define IER1 0x15 19354 #define IER2 0x16 19355 #define ITCR 0x18 19356 #define INTVR 0x1a 19357 #define IMVR 0x1c 19358 #define TRB 0x20 19359 #define TRBL 0x20 19360 #define TRBH 0x21 19361 #define SR0 0x22 19362 #define SR1 0x23 19363 #define SR2 0x24 19364 #define SR3 0x25 19365 #define FST 0x26 19366 #define IE0 0x28 19367 #define IE1 0x29 19368 #define IE2 0x2a 19369 #define FIE 0x2b 19370 #define CMD 0x2c 19371 #define MD0 0x2e 19372 #define MD1 0x2f 19373 #define MD2 0x30 19374 #define CTL 0x31 19375 #define SA0 0x32 19376 #define SA1 0x33 19377 #define IDL 0x34 19378 #define TMC 0x35 19379 #define RXS 0x36 19380 #define TXS 0x37 19381 #define TRC0 0x38 19382 #define TRC1 0x39 19383 #define RRC 0x3a 19384 #define CST0 0x3c 19385 #define CST1 0x3d 19386 #define TCNT 0x60 19387 #define TCNTL 0x60 19388 #define TCNTH 0x61 19389 #define TCONR 0x62 19390 #define TCONRL 0x62 19391 #define TCONRH 0x63 19392 #define TMCS 0x64 19393 #define TEPR 0x65 19394 #define DARL 0x80 19395 #define DARH 0x81 19396 #define DARB 0x82 19397 #define BAR 0x80 19398 #define BARL 0x80 19399 #define BARH 0x81 19400 #define BARB 0x82 19401 #define SAR 0x84 19402 #define SARL 0x84 19403 #define SARH 0x85 19404 #define SARB 0x86 19405 #define CPB 0x86 19406 #define CDA 0x88 19407 #define CDAL 0x88 19408 #define CDAH 0x89 19409 #define EDA 0x8a 19410 #define EDAL 0x8a 19411 #define EDAH 0x8b 19412 #define BFL 0x8c 19413 #define BFLL 0x8c 19414 #define BFLH 0x8d 19415 #define BCR 0x8e 19416 #define BCRL 0x8e 19417 #define BCRH 0x8f 19418 #define DSR 0x90 19419 #define DMR 0x91 19420 #define FCT 0x93 19421 #define DIR 0x94 19422 #define DCMD 0x95 19423 #define TIMER0 0x00 19424 #define TIMER1 0x08 19425 #define TIMER2 0x10 19426 #define TIMER3 0x18 19427 #define RXDMA 0x00 19428 #define TXDMA 0x20 19429 #define NOOP 0x00 19430 #define TXRESET 0x01 19431 #define TXENABLE 0x02 19432 #define TXDISABLE 0x03 19433 #define TXCRCINIT 0x04 19434 #define TXCRCEXCL 0x05 19435 #define TXEOM 0x06 19436 #define TXABORT 0x07 19437 #define MPON 0x08 19438 #define TXBUFCLR 0x09 19439 #define RXRESET 0x11 19440 #define RXENABLE 0x12 19441 #define RXDISABLE 0x13 19442 #define RXCRCINIT 0x14 19443 #define RXREJECT 0x15 19444 #define SEARCHMP 0x16 19445 #define RXCRCEXCL 0x17 19446 #define RXCRCCALC 0x18 19447 #define CHRESET 0x21 19448 #define HUNT 0x31 19449 #define SWABORT 0x01 19450 #define FEICLEAR 0x02 19451 #define TXINTE BIT7 19452 #define RXINTE BIT6 19453 #define TXRDYE BIT1 19454 #define RXRDYE BIT0 19455 #define UDRN BIT7 19456 #define IDLE BIT6 19457 #define SYNCD BIT4 19458 #define FLGD BIT4 19459 #define CCTS BIT3 19460 #define CDCD BIT2 19461 #define BRKD BIT1 19462 #define ABTD BIT1 19463 #define GAPD BIT1 19464 #define BRKE BIT0 19465 #define IDLD BIT0 19466 #define EOM BIT7 19467 #define PMP BIT6 19468 #define SHRT BIT6 19469 #define PE BIT5 19470 #define ABT BIT5 19471 #define FRME BIT4 19472 #define RBIT BIT4 19473 #define OVRN BIT3 19474 #define CRCE BIT2 19475 #define WAKEUP_CHARS 256 19476 #if SYNCLINK_GENERIC_HDLC 19477 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19478 #endif 19479 #ifdef SANITY_CHECK 19480 #else 19481 #endif 19482 #if SYNCLINK_GENERIC_HDLC 19483 #endif 19484 #if SYNCLINK_GENERIC_HDLC 19485 #endif 19486 #if SYNCLINK_GENERIC_HDLC 19487 #endif 19488 #ifdef CMSPAR 19489 #endif 19490 /* LDV_COMMENT_END_PREP */ 19491 /* LDV_COMMENT_FUNCTION_CALL Function from field "tiocmset" from driver structure with callbacks "ops" */ 19492 ldv_handler_precall(); 19493 tiocmset( var_group8, var_tiocmset_68_p1, var_tiocmset_68_p2); 19494 /* LDV_COMMENT_BEGIN_PREP */ 19495 #if SYNCLINK_GENERIC_HDLC 19496 #endif 19497 #if SYNCLINK_GENERIC_HDLC 19498 #endif 19499 #if 0 19500 #endif 19501 #if SYNCLINK_GENERIC_HDLC 19502 #endif 19503 #if SYNCLINK_GENERIC_HDLC 19504 #endif 19505 #define TESTFRAMESIZE 20 19506 #if SYNCLINK_GENERIC_HDLC 19507 #endif 19508 #define CALC_REGADDR() \ 19509 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19510 if (info->port_num > 1) \ 19511 RegAddr += 256; \ 19512 if ( info->port_num & 1) { \ 19513 if (Addr > 0x7f) \ 19514 RegAddr += 0x40; \ 19515 else if (Addr > 0x1f && Addr < 0x60) \ 19516 RegAddr += 0x20; \ 19517 } 19518 /* LDV_COMMENT_END_PREP */ 19519 19520 19521 19522 19523 } 19524 19525 break; 19526 case 30: { 19527 19528 /** STRUCT: struct type: tty_operations, struct name: ops **/ 19529 19530 19531 /* content: static int get_icount(struct tty_struct *tty, struct serial_icounter_struct *icount)*/ 19532 /* LDV_COMMENT_BEGIN_PREP */ 19533 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19534 #if defined(__i386__) 19535 # define BREAKPOINT() asm(" int $3"); 19536 #else 19537 # define BREAKPOINT() { } 19538 #endif 19539 #define MAX_DEVICES 12 19540 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19541 #define SYNCLINK_GENERIC_HDLC 1 19542 #else 19543 #define SYNCLINK_GENERIC_HDLC 0 19544 #endif 19545 #define GET_USER(error,value,addr) error = get_user(value,addr) 19546 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19547 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19548 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19549 #define SCABUFSIZE 1024 19550 #define SCA_MEM_SIZE 0x40000 19551 #define SCA_BASE_SIZE 512 19552 #define SCA_REG_SIZE 16 19553 #define SCA_MAX_PORTS 4 19554 #define SCAMAXDESC 128 19555 #define BUFFERLISTSIZE 4096 19556 #define BH_RECEIVE 1 19557 #define BH_TRANSMIT 2 19558 #define BH_STATUS 4 19559 #define IO_PIN_SHUTDOWN_LIMIT 100 19560 #if SYNCLINK_GENERIC_HDLC 19561 #endif 19562 #define MGSL_MAGIC 0x5401 19563 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 19564 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 19565 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 19566 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 19567 #define LPR 0x00 19568 #define PABR0 0x02 19569 #define PABR1 0x03 19570 #define WCRL 0x04 19571 #define WCRM 0x05 19572 #define WCRH 0x06 19573 #define DPCR 0x08 19574 #define DMER 0x09 19575 #define ISR0 0x10 19576 #define ISR1 0x11 19577 #define ISR2 0x12 19578 #define IER0 0x14 19579 #define IER1 0x15 19580 #define IER2 0x16 19581 #define ITCR 0x18 19582 #define INTVR 0x1a 19583 #define IMVR 0x1c 19584 #define TRB 0x20 19585 #define TRBL 0x20 19586 #define TRBH 0x21 19587 #define SR0 0x22 19588 #define SR1 0x23 19589 #define SR2 0x24 19590 #define SR3 0x25 19591 #define FST 0x26 19592 #define IE0 0x28 19593 #define IE1 0x29 19594 #define IE2 0x2a 19595 #define FIE 0x2b 19596 #define CMD 0x2c 19597 #define MD0 0x2e 19598 #define MD1 0x2f 19599 #define MD2 0x30 19600 #define CTL 0x31 19601 #define SA0 0x32 19602 #define SA1 0x33 19603 #define IDL 0x34 19604 #define TMC 0x35 19605 #define RXS 0x36 19606 #define TXS 0x37 19607 #define TRC0 0x38 19608 #define TRC1 0x39 19609 #define RRC 0x3a 19610 #define CST0 0x3c 19611 #define CST1 0x3d 19612 #define TCNT 0x60 19613 #define TCNTL 0x60 19614 #define TCNTH 0x61 19615 #define TCONR 0x62 19616 #define TCONRL 0x62 19617 #define TCONRH 0x63 19618 #define TMCS 0x64 19619 #define TEPR 0x65 19620 #define DARL 0x80 19621 #define DARH 0x81 19622 #define DARB 0x82 19623 #define BAR 0x80 19624 #define BARL 0x80 19625 #define BARH 0x81 19626 #define BARB 0x82 19627 #define SAR 0x84 19628 #define SARL 0x84 19629 #define SARH 0x85 19630 #define SARB 0x86 19631 #define CPB 0x86 19632 #define CDA 0x88 19633 #define CDAL 0x88 19634 #define CDAH 0x89 19635 #define EDA 0x8a 19636 #define EDAL 0x8a 19637 #define EDAH 0x8b 19638 #define BFL 0x8c 19639 #define BFLL 0x8c 19640 #define BFLH 0x8d 19641 #define BCR 0x8e 19642 #define BCRL 0x8e 19643 #define BCRH 0x8f 19644 #define DSR 0x90 19645 #define DMR 0x91 19646 #define FCT 0x93 19647 #define DIR 0x94 19648 #define DCMD 0x95 19649 #define TIMER0 0x00 19650 #define TIMER1 0x08 19651 #define TIMER2 0x10 19652 #define TIMER3 0x18 19653 #define RXDMA 0x00 19654 #define TXDMA 0x20 19655 #define NOOP 0x00 19656 #define TXRESET 0x01 19657 #define TXENABLE 0x02 19658 #define TXDISABLE 0x03 19659 #define TXCRCINIT 0x04 19660 #define TXCRCEXCL 0x05 19661 #define TXEOM 0x06 19662 #define TXABORT 0x07 19663 #define MPON 0x08 19664 #define TXBUFCLR 0x09 19665 #define RXRESET 0x11 19666 #define RXENABLE 0x12 19667 #define RXDISABLE 0x13 19668 #define RXCRCINIT 0x14 19669 #define RXREJECT 0x15 19670 #define SEARCHMP 0x16 19671 #define RXCRCEXCL 0x17 19672 #define RXCRCCALC 0x18 19673 #define CHRESET 0x21 19674 #define HUNT 0x31 19675 #define SWABORT 0x01 19676 #define FEICLEAR 0x02 19677 #define TXINTE BIT7 19678 #define RXINTE BIT6 19679 #define TXRDYE BIT1 19680 #define RXRDYE BIT0 19681 #define UDRN BIT7 19682 #define IDLE BIT6 19683 #define SYNCD BIT4 19684 #define FLGD BIT4 19685 #define CCTS BIT3 19686 #define CDCD BIT2 19687 #define BRKD BIT1 19688 #define ABTD BIT1 19689 #define GAPD BIT1 19690 #define BRKE BIT0 19691 #define IDLD BIT0 19692 #define EOM BIT7 19693 #define PMP BIT6 19694 #define SHRT BIT6 19695 #define PE BIT5 19696 #define ABT BIT5 19697 #define FRME BIT4 19698 #define RBIT BIT4 19699 #define OVRN BIT3 19700 #define CRCE BIT2 19701 #define WAKEUP_CHARS 256 19702 #if SYNCLINK_GENERIC_HDLC 19703 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19704 #endif 19705 #ifdef SANITY_CHECK 19706 #else 19707 #endif 19708 /* LDV_COMMENT_END_PREP */ 19709 /* LDV_COMMENT_FUNCTION_CALL Function from field "get_icount" from driver structure with callbacks "ops" */ 19710 ldv_handler_precall(); 19711 get_icount( var_group8, var_group10); 19712 /* LDV_COMMENT_BEGIN_PREP */ 19713 #if SYNCLINK_GENERIC_HDLC 19714 #endif 19715 #if SYNCLINK_GENERIC_HDLC 19716 #endif 19717 #if SYNCLINK_GENERIC_HDLC 19718 #endif 19719 #ifdef CMSPAR 19720 #endif 19721 #if SYNCLINK_GENERIC_HDLC 19722 #endif 19723 #if SYNCLINK_GENERIC_HDLC 19724 #endif 19725 #if 0 19726 #endif 19727 #if SYNCLINK_GENERIC_HDLC 19728 #endif 19729 #if SYNCLINK_GENERIC_HDLC 19730 #endif 19731 #define TESTFRAMESIZE 20 19732 #if SYNCLINK_GENERIC_HDLC 19733 #endif 19734 #define CALC_REGADDR() \ 19735 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19736 if (info->port_num > 1) \ 19737 RegAddr += 256; \ 19738 if ( info->port_num & 1) { \ 19739 if (Addr > 0x7f) \ 19740 RegAddr += 0x40; \ 19741 else if (Addr > 0x1f && Addr < 0x60) \ 19742 RegAddr += 0x20; \ 19743 } 19744 /* LDV_COMMENT_END_PREP */ 19745 19746 19747 19748 19749 } 19750 19751 break; 19752 case 31: { 19753 19754 /** CALLBACK SECTION request_irq **/ 19755 LDV_IN_INTERRUPT=2; 19756 19757 /* content: static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)*/ 19758 /* LDV_COMMENT_BEGIN_PREP */ 19759 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19760 #if defined(__i386__) 19761 # define BREAKPOINT() asm(" int $3"); 19762 #else 19763 # define BREAKPOINT() { } 19764 #endif 19765 #define MAX_DEVICES 12 19766 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19767 #define SYNCLINK_GENERIC_HDLC 1 19768 #else 19769 #define SYNCLINK_GENERIC_HDLC 0 19770 #endif 19771 #define GET_USER(error,value,addr) error = get_user(value,addr) 19772 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 19773 #define PUT_USER(error,value,addr) error = put_user(value,addr) 19774 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 19775 #define SCABUFSIZE 1024 19776 #define SCA_MEM_SIZE 0x40000 19777 #define SCA_BASE_SIZE 512 19778 #define SCA_REG_SIZE 16 19779 #define SCA_MAX_PORTS 4 19780 #define SCAMAXDESC 128 19781 #define BUFFERLISTSIZE 4096 19782 #define BH_RECEIVE 1 19783 #define BH_TRANSMIT 2 19784 #define BH_STATUS 4 19785 #define IO_PIN_SHUTDOWN_LIMIT 100 19786 #if SYNCLINK_GENERIC_HDLC 19787 #endif 19788 #define MGSL_MAGIC 0x5401 19789 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 19790 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 19791 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 19792 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 19793 #define LPR 0x00 19794 #define PABR0 0x02 19795 #define PABR1 0x03 19796 #define WCRL 0x04 19797 #define WCRM 0x05 19798 #define WCRH 0x06 19799 #define DPCR 0x08 19800 #define DMER 0x09 19801 #define ISR0 0x10 19802 #define ISR1 0x11 19803 #define ISR2 0x12 19804 #define IER0 0x14 19805 #define IER1 0x15 19806 #define IER2 0x16 19807 #define ITCR 0x18 19808 #define INTVR 0x1a 19809 #define IMVR 0x1c 19810 #define TRB 0x20 19811 #define TRBL 0x20 19812 #define TRBH 0x21 19813 #define SR0 0x22 19814 #define SR1 0x23 19815 #define SR2 0x24 19816 #define SR3 0x25 19817 #define FST 0x26 19818 #define IE0 0x28 19819 #define IE1 0x29 19820 #define IE2 0x2a 19821 #define FIE 0x2b 19822 #define CMD 0x2c 19823 #define MD0 0x2e 19824 #define MD1 0x2f 19825 #define MD2 0x30 19826 #define CTL 0x31 19827 #define SA0 0x32 19828 #define SA1 0x33 19829 #define IDL 0x34 19830 #define TMC 0x35 19831 #define RXS 0x36 19832 #define TXS 0x37 19833 #define TRC0 0x38 19834 #define TRC1 0x39 19835 #define RRC 0x3a 19836 #define CST0 0x3c 19837 #define CST1 0x3d 19838 #define TCNT 0x60 19839 #define TCNTL 0x60 19840 #define TCNTH 0x61 19841 #define TCONR 0x62 19842 #define TCONRL 0x62 19843 #define TCONRH 0x63 19844 #define TMCS 0x64 19845 #define TEPR 0x65 19846 #define DARL 0x80 19847 #define DARH 0x81 19848 #define DARB 0x82 19849 #define BAR 0x80 19850 #define BARL 0x80 19851 #define BARH 0x81 19852 #define BARB 0x82 19853 #define SAR 0x84 19854 #define SARL 0x84 19855 #define SARH 0x85 19856 #define SARB 0x86 19857 #define CPB 0x86 19858 #define CDA 0x88 19859 #define CDAL 0x88 19860 #define CDAH 0x89 19861 #define EDA 0x8a 19862 #define EDAL 0x8a 19863 #define EDAH 0x8b 19864 #define BFL 0x8c 19865 #define BFLL 0x8c 19866 #define BFLH 0x8d 19867 #define BCR 0x8e 19868 #define BCRL 0x8e 19869 #define BCRH 0x8f 19870 #define DSR 0x90 19871 #define DMR 0x91 19872 #define FCT 0x93 19873 #define DIR 0x94 19874 #define DCMD 0x95 19875 #define TIMER0 0x00 19876 #define TIMER1 0x08 19877 #define TIMER2 0x10 19878 #define TIMER3 0x18 19879 #define RXDMA 0x00 19880 #define TXDMA 0x20 19881 #define NOOP 0x00 19882 #define TXRESET 0x01 19883 #define TXENABLE 0x02 19884 #define TXDISABLE 0x03 19885 #define TXCRCINIT 0x04 19886 #define TXCRCEXCL 0x05 19887 #define TXEOM 0x06 19888 #define TXABORT 0x07 19889 #define MPON 0x08 19890 #define TXBUFCLR 0x09 19891 #define RXRESET 0x11 19892 #define RXENABLE 0x12 19893 #define RXDISABLE 0x13 19894 #define RXCRCINIT 0x14 19895 #define RXREJECT 0x15 19896 #define SEARCHMP 0x16 19897 #define RXCRCEXCL 0x17 19898 #define RXCRCCALC 0x18 19899 #define CHRESET 0x21 19900 #define HUNT 0x31 19901 #define SWABORT 0x01 19902 #define FEICLEAR 0x02 19903 #define TXINTE BIT7 19904 #define RXINTE BIT6 19905 #define TXRDYE BIT1 19906 #define RXRDYE BIT0 19907 #define UDRN BIT7 19908 #define IDLE BIT6 19909 #define SYNCD BIT4 19910 #define FLGD BIT4 19911 #define CCTS BIT3 19912 #define CDCD BIT2 19913 #define BRKD BIT1 19914 #define ABTD BIT1 19915 #define GAPD BIT1 19916 #define BRKE BIT0 19917 #define IDLD BIT0 19918 #define EOM BIT7 19919 #define PMP BIT6 19920 #define SHRT BIT6 19921 #define PE BIT5 19922 #define ABT BIT5 19923 #define FRME BIT4 19924 #define RBIT BIT4 19925 #define OVRN BIT3 19926 #define CRCE BIT2 19927 #define WAKEUP_CHARS 256 19928 #if SYNCLINK_GENERIC_HDLC 19929 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 19930 #endif 19931 #ifdef SANITY_CHECK 19932 #else 19933 #endif 19934 #if SYNCLINK_GENERIC_HDLC 19935 #endif 19936 #if SYNCLINK_GENERIC_HDLC 19937 #endif 19938 #if SYNCLINK_GENERIC_HDLC 19939 #endif 19940 /* LDV_COMMENT_END_PREP */ 19941 /* LDV_COMMENT_FUNCTION_CALL */ 19942 ldv_handler_precall(); 19943 synclinkmp_interrupt( var_synclinkmp_interrupt_52_p0, var_synclinkmp_interrupt_52_p1); 19944 /* LDV_COMMENT_BEGIN_PREP */ 19945 #ifdef CMSPAR 19946 #endif 19947 #if SYNCLINK_GENERIC_HDLC 19948 #endif 19949 #if SYNCLINK_GENERIC_HDLC 19950 #endif 19951 #if 0 19952 #endif 19953 #if SYNCLINK_GENERIC_HDLC 19954 #endif 19955 #if SYNCLINK_GENERIC_HDLC 19956 #endif 19957 #define TESTFRAMESIZE 20 19958 #if SYNCLINK_GENERIC_HDLC 19959 #endif 19960 #define CALC_REGADDR() \ 19961 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 19962 if (info->port_num > 1) \ 19963 RegAddr += 256; \ 19964 if ( info->port_num & 1) { \ 19965 if (Addr > 0x7f) \ 19966 RegAddr += 0x40; \ 19967 else if (Addr > 0x1f && Addr < 0x60) \ 19968 RegAddr += 0x20; \ 19969 } 19970 /* LDV_COMMENT_END_PREP */ 19971 LDV_IN_INTERRUPT=1; 19972 19973 19974 19975 } 19976 19977 break; 19978 default: break; 19979 19980 } 19981 19982 } 19983 19984 ldv_module_exit: 19985 19986 /** INIT: init_type: ST_MODULE_EXIT **/ 19987 /* content: static void __exit synclinkmp_exit(void)*/ 19988 /* LDV_COMMENT_BEGIN_PREP */ 19989 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 19990 #if defined(__i386__) 19991 # define BREAKPOINT() asm(" int $3"); 19992 #else 19993 # define BREAKPOINT() { } 19994 #endif 19995 #define MAX_DEVICES 12 19996 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) 19997 #define SYNCLINK_GENERIC_HDLC 1 19998 #else 19999 #define SYNCLINK_GENERIC_HDLC 0 20000 #endif 20001 #define GET_USER(error,value,addr) error = get_user(value,addr) 20002 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 20003 #define PUT_USER(error,value,addr) error = put_user(value,addr) 20004 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 20005 #define SCABUFSIZE 1024 20006 #define SCA_MEM_SIZE 0x40000 20007 #define SCA_BASE_SIZE 512 20008 #define SCA_REG_SIZE 16 20009 #define SCA_MAX_PORTS 4 20010 #define SCAMAXDESC 128 20011 #define BUFFERLISTSIZE 4096 20012 #define BH_RECEIVE 1 20013 #define BH_TRANSMIT 2 20014 #define BH_STATUS 4 20015 #define IO_PIN_SHUTDOWN_LIMIT 100 20016 #if SYNCLINK_GENERIC_HDLC 20017 #endif 20018 #define MGSL_MAGIC 0x5401 20019 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) 20020 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) 20021 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) 20022 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) 20023 #define LPR 0x00 20024 #define PABR0 0x02 20025 #define PABR1 0x03 20026 #define WCRL 0x04 20027 #define WCRM 0x05 20028 #define WCRH 0x06 20029 #define DPCR 0x08 20030 #define DMER 0x09 20031 #define ISR0 0x10 20032 #define ISR1 0x11 20033 #define ISR2 0x12 20034 #define IER0 0x14 20035 #define IER1 0x15 20036 #define IER2 0x16 20037 #define ITCR 0x18 20038 #define INTVR 0x1a 20039 #define IMVR 0x1c 20040 #define TRB 0x20 20041 #define TRBL 0x20 20042 #define TRBH 0x21 20043 #define SR0 0x22 20044 #define SR1 0x23 20045 #define SR2 0x24 20046 #define SR3 0x25 20047 #define FST 0x26 20048 #define IE0 0x28 20049 #define IE1 0x29 20050 #define IE2 0x2a 20051 #define FIE 0x2b 20052 #define CMD 0x2c 20053 #define MD0 0x2e 20054 #define MD1 0x2f 20055 #define MD2 0x30 20056 #define CTL 0x31 20057 #define SA0 0x32 20058 #define SA1 0x33 20059 #define IDL 0x34 20060 #define TMC 0x35 20061 #define RXS 0x36 20062 #define TXS 0x37 20063 #define TRC0 0x38 20064 #define TRC1 0x39 20065 #define RRC 0x3a 20066 #define CST0 0x3c 20067 #define CST1 0x3d 20068 #define TCNT 0x60 20069 #define TCNTL 0x60 20070 #define TCNTH 0x61 20071 #define TCONR 0x62 20072 #define TCONRL 0x62 20073 #define TCONRH 0x63 20074 #define TMCS 0x64 20075 #define TEPR 0x65 20076 #define DARL 0x80 20077 #define DARH 0x81 20078 #define DARB 0x82 20079 #define BAR 0x80 20080 #define BARL 0x80 20081 #define BARH 0x81 20082 #define BARB 0x82 20083 #define SAR 0x84 20084 #define SARL 0x84 20085 #define SARH 0x85 20086 #define SARB 0x86 20087 #define CPB 0x86 20088 #define CDA 0x88 20089 #define CDAL 0x88 20090 #define CDAH 0x89 20091 #define EDA 0x8a 20092 #define EDAL 0x8a 20093 #define EDAH 0x8b 20094 #define BFL 0x8c 20095 #define BFLL 0x8c 20096 #define BFLH 0x8d 20097 #define BCR 0x8e 20098 #define BCRL 0x8e 20099 #define BCRH 0x8f 20100 #define DSR 0x90 20101 #define DMR 0x91 20102 #define FCT 0x93 20103 #define DIR 0x94 20104 #define DCMD 0x95 20105 #define TIMER0 0x00 20106 #define TIMER1 0x08 20107 #define TIMER2 0x10 20108 #define TIMER3 0x18 20109 #define RXDMA 0x00 20110 #define TXDMA 0x20 20111 #define NOOP 0x00 20112 #define TXRESET 0x01 20113 #define TXENABLE 0x02 20114 #define TXDISABLE 0x03 20115 #define TXCRCINIT 0x04 20116 #define TXCRCEXCL 0x05 20117 #define TXEOM 0x06 20118 #define TXABORT 0x07 20119 #define MPON 0x08 20120 #define TXBUFCLR 0x09 20121 #define RXRESET 0x11 20122 #define RXENABLE 0x12 20123 #define RXDISABLE 0x13 20124 #define RXCRCINIT 0x14 20125 #define RXREJECT 0x15 20126 #define SEARCHMP 0x16 20127 #define RXCRCEXCL 0x17 20128 #define RXCRCCALC 0x18 20129 #define CHRESET 0x21 20130 #define HUNT 0x31 20131 #define SWABORT 0x01 20132 #define FEICLEAR 0x02 20133 #define TXINTE BIT7 20134 #define RXINTE BIT6 20135 #define TXRDYE BIT1 20136 #define RXRDYE BIT0 20137 #define UDRN BIT7 20138 #define IDLE BIT6 20139 #define SYNCD BIT4 20140 #define FLGD BIT4 20141 #define CCTS BIT3 20142 #define CDCD BIT2 20143 #define BRKD BIT1 20144 #define ABTD BIT1 20145 #define GAPD BIT1 20146 #define BRKE BIT0 20147 #define IDLD BIT0 20148 #define EOM BIT7 20149 #define PMP BIT6 20150 #define SHRT BIT6 20151 #define PE BIT5 20152 #define ABT BIT5 20153 #define FRME BIT4 20154 #define RBIT BIT4 20155 #define OVRN BIT3 20156 #define CRCE BIT2 20157 #define WAKEUP_CHARS 256 20158 #if SYNCLINK_GENERIC_HDLC 20159 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 20160 #endif 20161 #ifdef SANITY_CHECK 20162 #else 20163 #endif 20164 #if SYNCLINK_GENERIC_HDLC 20165 #endif 20166 #if SYNCLINK_GENERIC_HDLC 20167 #endif 20168 #if SYNCLINK_GENERIC_HDLC 20169 #endif 20170 #ifdef CMSPAR 20171 #endif 20172 #if SYNCLINK_GENERIC_HDLC 20173 #endif 20174 #if SYNCLINK_GENERIC_HDLC 20175 #endif 20176 /* LDV_COMMENT_END_PREP */ 20177 /* LDV_COMMENT_FUNCTION_CALL Kernel calls driver release function before driver will be uploaded from kernel. This function declared as "MODULE_EXIT(function name)". */ 20178 ldv_handler_precall(); 20179 synclinkmp_exit(); 20180 /* LDV_COMMENT_BEGIN_PREP */ 20181 #if 0 20182 #endif 20183 #if SYNCLINK_GENERIC_HDLC 20184 #endif 20185 #if SYNCLINK_GENERIC_HDLC 20186 #endif 20187 #define TESTFRAMESIZE 20 20188 #if SYNCLINK_GENERIC_HDLC 20189 #endif 20190 #define CALC_REGADDR() \ 20191 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 20192 if (info->port_num > 1) \ 20193 RegAddr += 256; \ 20194 if ( info->port_num & 1) { \ 20195 if (Addr > 0x7f) \ 20196 RegAddr += 0x40; \ 20197 else if (Addr > 0x1f && Addr < 0x60) \ 20198 RegAddr += 0x20; \ 20199 } 20200 /* LDV_COMMENT_END_PREP */ 20201 20202 /* LDV_COMMENT_FUNCTION_CALL Checks that all resources and locks are correctly released before the driver will be unloaded. */ 20203 ldv_final: ldv_check_final_state(); 20204 20205 /* LDV_COMMENT_END_FUNCTION_CALL_SECTION */ 20206 return; 20207 20208 } 20209 #endif 20210 20211 /* LDV_COMMENT_END_MAIN */ 20212 20213 #line 14 "/home/ldvuser/ref_launch/work/current--X--drivers--X--defaultlinux-4.5-rc1.tar.xz--X--134_1a--X--cpachecker/linux-4.5-rc1.tar.xz/csd_deg_dscv/8588/dscv_tempdir/dscv/ri/134_1a/drivers/tty/synclinkmp.o.c.prepared"
1 2 #include <linux/kernel.h> 3 #include <verifier/rcv.h> // For LDV auxiliary routines. 4 #include <kernel-model/ERR.inc> 5 6 // There are 3 possible model states 7 enum 8 { 9 LDV_PROBE_ZERO_STATE = 0, // No error occured 10 LDV_PROBE_ERROR = 1, // Error occured. probe() should return error an code (or at least not zero) 11 }; 12 13 /* LDV_COMMENT_OTHER The model automaton state (one of thee possible ones). */ 14 int ldv_probe_state = LDV_PROBE_ZERO_STATE; 15 16 /* LDV_COMMENT_MODEL_FUNCTION_DEFINITION(name='ldv_usb_register') Non-deterministically change state after call to usb_register. */ 17 int ldv_usb_register(void) 18 { 19 int nondet; 20 21 /* LDV_COMMENT_OTHER Nondeterministically report an error. */ 22 if (nondet < 0) { 23 /* LDV_COMMENT_CHANGE_STATE Error occured. */ 24 ldv_probe_state = LDV_PROBE_ERROR; 25 /* LDV_COMMENT_RETURN Return an error. */ 26 return nondet; 27 } else if (nondet >= 0) { 28 /* LDV_COMMENT_RETURN Assume no error occured. */ 29 return 0; 30 } 31 } 32 33 /* LDV_COMMENT_MODEL_FUNCTION_DEFINITION(name='register_netdev') Non-deterministically change state after call to register_netdev. */ 34 int ldv_register_netdev(void) 35 { 36 int nondet; 37 38 /* LDV_COMMENT_OTHER Nondeterministically report an error. */ 39 if (nondet < 0) { 40 /* LDV_COMMENT_CHANGE_STATE Error occured. */ 41 ldv_probe_state = LDV_PROBE_ERROR; 42 /* LDV_COMMENT_RETURN Return an error. */ 43 return nondet; 44 } else if (nondet >= 0) { 45 /* LDV_COMMENT_RETURN Assume no error occured. */ 46 return 0; 47 } 48 } 49 50 /* LDV_COMMENT_MODEL_FUNCTION_DEFINITION(name='ldv_check_return_value_probe') Check the error code was properly propagated in probe . */ 51 void ldv_check_return_value_probe(int retval) 52 { 53 if (ldv_probe_state == LDV_PROBE_ERROR) 54 ldv_assert(retval != 0); 55 }
1 #ifndef _LDV_ERR_ 2 #define _LDV_ERR_ 3 4 #include <linux/kernel.h> 5 6 /* LDV_COMMENT_MODEL_FUNCTION_DEFENITION(name='ldv_is_err') This function return result of checking if pointer is impossible. */ 7 bool ldv_is_err(const void *ptr) 8 { 9 /*LDV_COMMENT_RETURN Return value of function ldv_is_err_val().*/ 10 return ((unsigned long)ptr > LDV_PTR_MAX); 11 } 12 13 /* LDV_COMMENT_MODEL_FUNCTION_DEFENITION(name='ldv_err_ptr') This function return pointer. */ 14 void* ldv_err_ptr(long error) 15 { 16 /*LDV_COMMENT_RETURN Return error pointer.*/ 17 return (void *)(LDV_PTR_MAX - error); 18 } 19 20 /* LDV_COMMENT_MODEL_FUNCTION_DEFENITION(name='ldv_ptr_err') This function return error if pointer is impossible. */ 21 long ldv_ptr_err(const void *ptr) 22 { 23 /*LDV_COMMENT_RETURN Return error code.*/ 24 return (long)(LDV_PTR_MAX - (unsigned long)ptr); 25 } 26 27 /* LDV_COMMENT_MODEL_FUNCTION_DEFENITION(name='ldv_is_err_or_null') This function check if pointer is impossible or null. */ 28 bool ldv_is_err_or_null(const void *ptr) 29 { 30 /*LDV_COMMENT_RETURN Return 0 if pointer is possible and not zero, and 1 in other cases*/ 31 return !ptr || ldv_is_err((unsigned long)ptr); 32 } 33 34 #endif /* _LDV_ERR_ */
1 #ifndef _LDV_RCV_H_ 2 #define _LDV_RCV_H_ 3 4 /* If expr evaluates to zero, ldv_assert() causes a program to reach the error 5 label like the standard assert(). */ 6 #define ldv_assert(expr) ((expr) ? 0 : ldv_error()) 7 8 /* The error label wrapper. It is used because of some static verifiers (like 9 BLAST) don't accept multiple error labels through a program. */ 10 static inline void ldv_error(void) 11 { 12 LDV_ERROR: goto LDV_ERROR; 13 } 14 15 /* If expr evaluates to zero, ldv_assume() causes an infinite loop that is 16 avoided by verifiers. */ 17 #define ldv_assume(expr) ((expr) ? 0 : ldv_stop()) 18 19 /* Infinite loop, that causes verifiers to skip such paths. */ 20 static inline void ldv_stop(void) { 21 LDV_STOP: goto LDV_STOP; 22 } 23 24 /* Special nondeterministic functions. */ 25 int ldv_undef_int(void); 26 void *ldv_undef_ptr(void); 27 unsigned long ldv_undef_ulong(void); 28 long ldv_undef_long(void); 29 /* Return nondeterministic negative integer number. */ 30 static inline int ldv_undef_int_negative(void) 31 { 32 int ret = ldv_undef_int(); 33 34 ldv_assume(ret < 0); 35 36 return ret; 37 } 38 /* Return nondeterministic nonpositive integer number. */ 39 static inline int ldv_undef_int_nonpositive(void) 40 { 41 int ret = ldv_undef_int(); 42 43 ldv_assume(ret <= 0); 44 45 return ret; 46 } 47 48 /* Add explicit model for __builin_expect GCC function. Without the model a 49 return value will be treated as nondetermined by verifiers. */ 50 static inline long __builtin_expect(long exp, long c) 51 { 52 return exp; 53 } 54 55 /* This function causes the program to exit abnormally. GCC implements this 56 function by using a target-dependent mechanism (such as intentionally executing 57 an illegal instruction) or by calling abort. The mechanism used may vary from 58 release to release so you should not rely on any particular implementation. 59 http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html */ 60 static inline void __builtin_trap(void) 61 { 62 ldv_assert(0); 63 } 64 65 /* The constant is for simulating an error of ldv_undef_ptr() function. */ 66 #define LDV_PTR_MAX 2012 67 68 #endif /* _LDV_RCV_H_ */
1 #ifndef __LINUX_COMPILER_H 2 #define __LINUX_COMPILER_H 3 4 #ifndef __ASSEMBLY__ 5 6 #ifdef __CHECKER__ 7 # define __user __attribute__((noderef, address_space(1))) 8 # define __kernel __attribute__((address_space(0))) 9 # define __safe __attribute__((safe)) 10 # define __force __attribute__((force)) 11 # define __nocast __attribute__((nocast)) 12 # define __iomem __attribute__((noderef, address_space(2))) 13 # define __must_hold(x) __attribute__((context(x,1,1))) 14 # define __acquires(x) __attribute__((context(x,0,1))) 15 # define __releases(x) __attribute__((context(x,1,0))) 16 # define __acquire(x) __context__(x,1) 17 # define __release(x) __context__(x,-1) 18 # define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) 19 # define __percpu __attribute__((noderef, address_space(3))) 20 # define __pmem __attribute__((noderef, address_space(5))) 21 #ifdef CONFIG_SPARSE_RCU_POINTER 22 # define __rcu __attribute__((noderef, address_space(4))) 23 #else 24 # define __rcu 25 #endif 26 extern void __chk_user_ptr(const volatile void __user *); 27 extern void __chk_io_ptr(const volatile void __iomem *); 28 #else 29 # define __user 30 # define __kernel 31 # define __safe 32 # define __force 33 # define __nocast 34 # define __iomem 35 # define __chk_user_ptr(x) (void)0 36 # define __chk_io_ptr(x) (void)0 37 # define __builtin_warning(x, y...) (1) 38 # define __must_hold(x) 39 # define __acquires(x) 40 # define __releases(x) 41 # define __acquire(x) (void)0 42 # define __release(x) (void)0 43 # define __cond_lock(x,c) (c) 44 # define __percpu 45 # define __rcu 46 # define __pmem 47 #endif 48 49 /* Indirect macros required for expanded argument pasting, eg. __LINE__. */ 50 #define ___PASTE(a,b) a##b 51 #define __PASTE(a,b) ___PASTE(a,b) 52 53 #ifdef __KERNEL__ 54 55 #ifdef __GNUC__ 56 #include <linux/compiler-gcc.h> 57 #endif 58 59 #if defined(CC_USING_HOTPATCH) && !defined(__CHECKER__) 60 #define notrace __attribute__((hotpatch(0,0))) 61 #else 62 #define notrace __attribute__((no_instrument_function)) 63 #endif 64 65 /* Intel compiler defines __GNUC__. So we will overwrite implementations 66 * coming from above header files here 67 */ 68 #ifdef __INTEL_COMPILER 69 # include <linux/compiler-intel.h> 70 #endif 71 72 /* Clang compiler defines __GNUC__. So we will overwrite implementations 73 * coming from above header files here 74 */ 75 #ifdef __clang__ 76 #include <linux/compiler-clang.h> 77 #endif 78 79 /* 80 * Generic compiler-dependent macros required for kernel 81 * build go below this comment. Actual compiler/compiler version 82 * specific implementations come from the above header files 83 */ 84 85 struct ftrace_branch_data { 86 const char *func; 87 const char *file; 88 unsigned line; 89 union { 90 struct { 91 unsigned long correct; 92 unsigned long incorrect; 93 }; 94 struct { 95 unsigned long miss; 96 unsigned long hit; 97 }; 98 unsigned long miss_hit[2]; 99 }; 100 }; 101 102 /* 103 * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code 104 * to disable branch tracing on a per file basis. 105 */ 106 #if defined(CONFIG_TRACE_BRANCH_PROFILING) \ 107 && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__) 108 void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); 109 110 #define likely_notrace(x) __builtin_expect(!!(x), 1) 111 #define unlikely_notrace(x) __builtin_expect(!!(x), 0) 112 113 #define __branch_check__(x, expect) ({ \ 114 int ______r; \ 115 static struct ftrace_branch_data \ 116 __attribute__((__aligned__(4))) \ 117 __attribute__((section("_ftrace_annotated_branch"))) \ 118 ______f = { \ 119 .func = __func__, \ 120 .file = __FILE__, \ 121 .line = __LINE__, \ 122 }; \ 123 ______r = likely_notrace(x); \ 124 ftrace_likely_update(&______f, ______r, expect); \ 125 ______r; \ 126 }) 127 128 /* 129 * Using __builtin_constant_p(x) to ignore cases where the return 130 * value is always the same. This idea is taken from a similar patch 131 * written by Daniel Walker. 132 */ 133 # ifndef likely 134 # define likely(x) (__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1)) 135 # endif 136 # ifndef unlikely 137 # define unlikely(x) (__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0)) 138 # endif 139 140 #ifdef CONFIG_PROFILE_ALL_BRANCHES 141 /* 142 * "Define 'is'", Bill Clinton 143 * "Define 'if'", Steven Rostedt 144 */ 145 #define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) ) 146 #define __trace_if(cond) \ 147 if (__builtin_constant_p((cond)) ? !!(cond) : \ 148 ({ \ 149 int ______r; \ 150 static struct ftrace_branch_data \ 151 __attribute__((__aligned__(4))) \ 152 __attribute__((section("_ftrace_branch"))) \ 153 ______f = { \ 154 .func = __func__, \ 155 .file = __FILE__, \ 156 .line = __LINE__, \ 157 }; \ 158 ______r = !!(cond); \ 159 ______f.miss_hit[______r]++; \ 160 ______r; \ 161 })) 162 #endif /* CONFIG_PROFILE_ALL_BRANCHES */ 163 164 #else 165 # define likely(x) __builtin_expect(!!(x), 1) 166 # define unlikely(x) __builtin_expect(!!(x), 0) 167 #endif 168 169 /* Optimization barrier */ 170 #ifndef barrier 171 # define barrier() __memory_barrier() 172 #endif 173 174 #ifndef barrier_data 175 # define barrier_data(ptr) barrier() 176 #endif 177 178 /* Unreachable code */ 179 #ifndef unreachable 180 # define unreachable() do { } while (1) 181 #endif 182 183 #ifndef RELOC_HIDE 184 # define RELOC_HIDE(ptr, off) \ 185 ({ unsigned long __ptr; \ 186 __ptr = (unsigned long) (ptr); \ 187 (typeof(ptr)) (__ptr + (off)); }) 188 #endif 189 190 #ifndef OPTIMIZER_HIDE_VAR 191 #define OPTIMIZER_HIDE_VAR(var) barrier() 192 #endif 193 194 /* Not-quite-unique ID. */ 195 #ifndef __UNIQUE_ID 196 # define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__) 197 #endif 198 199 #include <uapi/linux/types.h> 200 201 #define __READ_ONCE_SIZE \ 202 ({ \ 203 switch (size) { \ 204 case 1: *(__u8 *)res = *(volatile __u8 *)p; break; \ 205 case 2: *(__u16 *)res = *(volatile __u16 *)p; break; \ 206 case 4: *(__u32 *)res = *(volatile __u32 *)p; break; \ 207 case 8: *(__u64 *)res = *(volatile __u64 *)p; break; \ 208 default: \ 209 barrier(); \ 210 __builtin_memcpy((void *)res, (const void *)p, size); \ 211 barrier(); \ 212 } \ 213 }) 214 215 static __always_inline 216 void __read_once_size(const volatile void *p, void *res, int size) 217 { 218 __READ_ONCE_SIZE; 219 } 220 221 #ifdef CONFIG_KASAN 222 /* 223 * This function is not 'inline' because __no_sanitize_address confilcts 224 * with inlining. Attempt to inline it may cause a build failure. 225 * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 226 * '__maybe_unused' allows us to avoid defined-but-not-used warnings. 227 */ 228 static __no_sanitize_address __maybe_unused 229 void __read_once_size_nocheck(const volatile void *p, void *res, int size) 230 { 231 __READ_ONCE_SIZE; 232 } 233 #else 234 static __always_inline 235 void __read_once_size_nocheck(const volatile void *p, void *res, int size) 236 { 237 __READ_ONCE_SIZE; 238 } 239 #endif 240 241 static __always_inline void __write_once_size(volatile void *p, void *res, int size) 242 { 243 switch (size) { 244 case 1: *(volatile __u8 *)p = *(__u8 *)res; break; 245 case 2: *(volatile __u16 *)p = *(__u16 *)res; break; 246 case 4: *(volatile __u32 *)p = *(__u32 *)res; break; 247 case 8: *(volatile __u64 *)p = *(__u64 *)res; break; 248 default: 249 barrier(); 250 __builtin_memcpy((void *)p, (const void *)res, size); 251 barrier(); 252 } 253 } 254 255 /* 256 * Prevent the compiler from merging or refetching reads or writes. The 257 * compiler is also forbidden from reordering successive instances of 258 * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the 259 * compiler is aware of some particular ordering. One way to make the 260 * compiler aware of ordering is to put the two invocations of READ_ONCE, 261 * WRITE_ONCE or ACCESS_ONCE() in different C statements. 262 * 263 * In contrast to ACCESS_ONCE these two macros will also work on aggregate 264 * data types like structs or unions. If the size of the accessed data 265 * type exceeds the word size of the machine (e.g., 32 bits or 64 bits) 266 * READ_ONCE() and WRITE_ONCE() will fall back to memcpy and print a 267 * compile-time warning. 268 * 269 * Their two major use cases are: (1) Mediating communication between 270 * process-level code and irq/NMI handlers, all running on the same CPU, 271 * and (2) Ensuring that the compiler does not fold, spindle, or otherwise 272 * mutilate accesses that either do not require ordering or that interact 273 * with an explicit memory barrier or atomic instruction that provides the 274 * required ordering. 275 */ 276 277 #define __READ_ONCE(x, check) \ 278 ({ \ 279 union { typeof(x) __val; char __c[1]; } __u; \ 280 if (check) \ 281 __read_once_size(&(x), __u.__c, sizeof(x)); \ 282 else \ 283 __read_once_size_nocheck(&(x), __u.__c, sizeof(x)); \ 284 __u.__val; \ 285 }) 286 #define READ_ONCE(x) __READ_ONCE(x, 1) 287 288 /* 289 * Use READ_ONCE_NOCHECK() instead of READ_ONCE() if you need 290 * to hide memory access from KASAN. 291 */ 292 #define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0) 293 294 #define WRITE_ONCE(x, val) \ 295 ({ \ 296 union { typeof(x) __val; char __c[1]; } __u = \ 297 { .__val = (__force typeof(x)) (val) }; \ 298 __write_once_size(&(x), __u.__c, sizeof(x)); \ 299 __u.__val; \ 300 }) 301 302 /** 303 * smp_cond_acquire() - Spin wait for cond with ACQUIRE ordering 304 * @cond: boolean expression to wait for 305 * 306 * Equivalent to using smp_load_acquire() on the condition variable but employs 307 * the control dependency of the wait to reduce the barrier on many platforms. 308 * 309 * The control dependency provides a LOAD->STORE order, the additional RMB 310 * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order, 311 * aka. ACQUIRE. 312 */ 313 #define smp_cond_acquire(cond) do { \ 314 while (!(cond)) \ 315 cpu_relax(); \ 316 smp_rmb(); /* ctrl + rmb := acquire */ \ 317 } while (0) 318 319 #endif /* __KERNEL__ */ 320 321 #endif /* __ASSEMBLY__ */ 322 323 #ifdef __KERNEL__ 324 /* 325 * Allow us to mark functions as 'deprecated' and have gcc emit a nice 326 * warning for each use, in hopes of speeding the functions removal. 327 * Usage is: 328 * int __deprecated foo(void) 329 */ 330 #ifndef __deprecated 331 # define __deprecated /* unimplemented */ 332 #endif 333 334 #ifdef MODULE 335 #define __deprecated_for_modules __deprecated 336 #else 337 #define __deprecated_for_modules 338 #endif 339 340 #ifndef __must_check 341 #define __must_check 342 #endif 343 344 #ifndef CONFIG_ENABLE_MUST_CHECK 345 #undef __must_check 346 #define __must_check 347 #endif 348 #ifndef CONFIG_ENABLE_WARN_DEPRECATED 349 #undef __deprecated 350 #undef __deprecated_for_modules 351 #define __deprecated 352 #define __deprecated_for_modules 353 #endif 354 355 /* 356 * Allow us to avoid 'defined but not used' warnings on functions and data, 357 * as well as force them to be emitted to the assembly file. 358 * 359 * As of gcc 3.4, static functions that are not marked with attribute((used)) 360 * may be elided from the assembly file. As of gcc 3.4, static data not so 361 * marked will not be elided, but this may change in a future gcc version. 362 * 363 * NOTE: Because distributions shipped with a backported unit-at-a-time 364 * compiler in gcc 3.3, we must define __used to be __attribute__((used)) 365 * for gcc >=3.3 instead of 3.4. 366 * 367 * In prior versions of gcc, such functions and data would be emitted, but 368 * would be warned about except with attribute((unused)). 369 * 370 * Mark functions that are referenced only in inline assembly as __used so 371 * the code is emitted even though it appears to be unreferenced. 372 */ 373 #ifndef __used 374 # define __used /* unimplemented */ 375 #endif 376 377 #ifndef __maybe_unused 378 # define __maybe_unused /* unimplemented */ 379 #endif 380 381 #ifndef __always_unused 382 # define __always_unused /* unimplemented */ 383 #endif 384 385 #ifndef noinline 386 #define noinline 387 #endif 388 389 /* 390 * Rather then using noinline to prevent stack consumption, use 391 * noinline_for_stack instead. For documentation reasons. 392 */ 393 #define noinline_for_stack noinline 394 395 #ifndef __always_inline 396 #define __always_inline inline 397 #endif 398 399 #endif /* __KERNEL__ */ 400 401 /* 402 * From the GCC manual: 403 * 404 * Many functions do not examine any values except their arguments, 405 * and have no effects except the return value. Basically this is 406 * just slightly more strict class than the `pure' attribute above, 407 * since function is not allowed to read global memory. 408 * 409 * Note that a function that has pointer arguments and examines the 410 * data pointed to must _not_ be declared `const'. Likewise, a 411 * function that calls a non-`const' function usually must not be 412 * `const'. It does not make sense for a `const' function to return 413 * `void'. 414 */ 415 #ifndef __attribute_const__ 416 # define __attribute_const__ /* unimplemented */ 417 #endif 418 419 /* 420 * Tell gcc if a function is cold. The compiler will assume any path 421 * directly leading to the call is unlikely. 422 */ 423 424 #ifndef __cold 425 #define __cold 426 #endif 427 428 /* Simple shorthand for a section definition */ 429 #ifndef __section 430 # define __section(S) __attribute__ ((__section__(#S))) 431 #endif 432 433 #ifndef __visible 434 #define __visible 435 #endif 436 437 /* 438 * Assume alignment of return value. 439 */ 440 #ifndef __assume_aligned 441 #define __assume_aligned(a, ...) 442 #endif 443 444 445 /* Are two types/vars the same type (ignoring qualifiers)? */ 446 #ifndef __same_type 447 # define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) 448 #endif 449 450 /* Is this type a native word size -- useful for atomic operations */ 451 #ifndef __native_word 452 # define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) 453 #endif 454 455 /* Compile time object size, -1 for unknown */ 456 #ifndef __compiletime_object_size 457 # define __compiletime_object_size(obj) -1 458 #endif 459 #ifndef __compiletime_warning 460 # define __compiletime_warning(message) 461 #endif 462 #ifndef __compiletime_error 463 # define __compiletime_error(message) 464 /* 465 * Sparse complains of variable sized arrays due to the temporary variable in 466 * __compiletime_assert. Unfortunately we can't just expand it out to make 467 * sparse see a constant array size without breaking compiletime_assert on old 468 * versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether. 469 */ 470 # ifndef __CHECKER__ 471 # define __compiletime_error_fallback(condition) \ 472 do { } while (0) 473 # endif 474 #endif 475 #ifndef __compiletime_error_fallback 476 # define __compiletime_error_fallback(condition) do { } while (0) 477 #endif 478 479 #define __compiletime_assert(condition, msg, prefix, suffix) \ 480 do { \ 481 bool __cond = !(condition); \ 482 extern void prefix ## suffix(void) __compiletime_error(msg); \ 483 if (__cond) \ 484 prefix ## suffix(); \ 485 __compiletime_error_fallback(__cond); \ 486 } while (0) 487 488 #define _compiletime_assert(condition, msg, prefix, suffix) \ 489 __compiletime_assert(condition, msg, prefix, suffix) 490 491 /** 492 * compiletime_assert - break build and emit msg if condition is false 493 * @condition: a compile-time constant condition to check 494 * @msg: a message to emit if condition is false 495 * 496 * In tradition of POSIX assert, this macro will break the build if the 497 * supplied condition is *false*, emitting the supplied error message if the 498 * compiler has support to do so. 499 */ 500 #define compiletime_assert(condition, msg) \ 501 _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__) 502 503 #define compiletime_assert_atomic_type(t) \ 504 compiletime_assert(__native_word(t), \ 505 "Need native word sized stores/loads for atomicity.") 506 507 /* 508 * Prevent the compiler from merging or refetching accesses. The compiler 509 * is also forbidden from reordering successive instances of ACCESS_ONCE(), 510 * but only when the compiler is aware of some particular ordering. One way 511 * to make the compiler aware of ordering is to put the two invocations of 512 * ACCESS_ONCE() in different C statements. 513 * 514 * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE 515 * on a union member will work as long as the size of the member matches the 516 * size of the union and the size is smaller than word size. 517 * 518 * The major use cases of ACCESS_ONCE used to be (1) Mediating communication 519 * between process-level code and irq/NMI handlers, all running on the same CPU, 520 * and (2) Ensuring that the compiler does not fold, spindle, or otherwise 521 * mutilate accesses that either do not require ordering or that interact 522 * with an explicit memory barrier or atomic instruction that provides the 523 * required ordering. 524 * 525 * If possible use READ_ONCE()/WRITE_ONCE() instead. 526 */ 527 #define __ACCESS_ONCE(x) ({ \ 528 __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \ 529 (volatile typeof(x) *)&(x); }) 530 #define ACCESS_ONCE(x) (*__ACCESS_ONCE(x)) 531 532 /** 533 * lockless_dereference() - safely load a pointer for later dereference 534 * @p: The pointer to load 535 * 536 * Similar to rcu_dereference(), but for situations where the pointed-to 537 * object's lifetime is managed by something other than RCU. That 538 * "something other" might be reference counting or simple immortality. 539 */ 540 #define lockless_dereference(p) \ 541 ({ \ 542 typeof(p) _________p1 = READ_ONCE(p); \ 543 smp_read_barrier_depends(); /* Dependency order vs. p above. */ \ 544 (_________p1); \ 545 }) 546 547 /* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */ 548 #ifdef CONFIG_KPROBES 549 # define __kprobes __attribute__((__section__(".kprobes.text"))) 550 # define nokprobe_inline __always_inline 551 #else 552 # define __kprobes 553 # define nokprobe_inline inline 554 #endif 555 #endif /* __LINUX_COMPILER_H */
1 /* 2 * Generic HDLC support routines for Linux 3 * 4 * Copyright (C) 1999-2005 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 */ 10 #ifndef __HDLC_H 11 #define __HDLC_H 12 13 14 #include <linux/skbuff.h> 15 #include <linux/netdevice.h> 16 #include <linux/hdlc/ioctl.h> 17 #include <uapi/linux/hdlc.h> 18 19 /* This structure is a private property of HDLC protocols. 20 Hardware drivers have no interest here */ 21 22 struct hdlc_proto { 23 int (*open)(struct net_device *dev); 24 void (*close)(struct net_device *dev); 25 void (*start)(struct net_device *dev); /* if open & DCD */ 26 void (*stop)(struct net_device *dev); /* if open & !DCD */ 27 void (*detach)(struct net_device *dev); 28 int (*ioctl)(struct net_device *dev, struct ifreq *ifr); 29 __be16 (*type_trans)(struct sk_buff *skb, struct net_device *dev); 30 int (*netif_rx)(struct sk_buff *skb); 31 netdev_tx_t (*xmit)(struct sk_buff *skb, struct net_device *dev); 32 struct module *module; 33 struct hdlc_proto *next; /* next protocol in the list */ 34 }; 35 36 37 /* Pointed to by netdev_priv(dev) */ 38 typedef struct hdlc_device { 39 /* used by HDLC layer to take control over HDLC device from hw driver*/ 40 int (*attach)(struct net_device *dev, 41 unsigned short encoding, unsigned short parity); 42 43 /* hardware driver must handle this instead of dev->hard_start_xmit */ 44 netdev_tx_t (*xmit)(struct sk_buff *skb, struct net_device *dev); 45 46 /* Things below are for HDLC layer internal use only */ 47 const struct hdlc_proto *proto; 48 int carrier; 49 int open; 50 spinlock_t state_lock; 51 void *state; 52 void *priv; 53 } hdlc_device; 54 55 56 57 /* Exported from hdlc module */ 58 59 /* Called by hardware driver when a user requests HDLC service */ 60 int hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); 61 62 /* Must be used by hardware driver on module startup/exit */ 63 #define register_hdlc_device(dev) register_netdev(dev) 64 void unregister_hdlc_device(struct net_device *dev); 65 66 67 void register_hdlc_protocol(struct hdlc_proto *proto); 68 void unregister_hdlc_protocol(struct hdlc_proto *proto); 69 70 struct net_device *alloc_hdlcdev(void *priv); 71 72 static inline struct hdlc_device* dev_to_hdlc(struct net_device *dev) 73 { 74 return netdev_priv(dev); 75 } 76 77 static __inline__ void debug_frame(const struct sk_buff *skb) 78 { 79 int i; 80 81 for (i=0; i < skb->len; i++) { 82 if (i == 100) { 83 printk("...\n"); 84 return; 85 } 86 printk(" %02X", skb->data[i]); 87 } 88 printk("\n"); 89 } 90 91 92 /* Must be called by hardware driver when HDLC device is being opened */ 93 int hdlc_open(struct net_device *dev); 94 /* Must be called by hardware driver when HDLC device is being closed */ 95 void hdlc_close(struct net_device *dev); 96 /* May be used by hardware driver */ 97 int hdlc_change_mtu(struct net_device *dev, int new_mtu); 98 /* Must be pointed to by hw driver's dev->netdev_ops->ndo_start_xmit */ 99 netdev_tx_t hdlc_start_xmit(struct sk_buff *skb, struct net_device *dev); 100 101 int attach_hdlc_protocol(struct net_device *dev, struct hdlc_proto *proto, 102 size_t size); 103 /* May be used by hardware driver to gain control over HDLC device */ 104 int detach_hdlc_protocol(struct net_device *dev); 105 106 static __inline__ __be16 hdlc_type_trans(struct sk_buff *skb, 107 struct net_device *dev) 108 { 109 hdlc_device *hdlc = dev_to_hdlc(dev); 110 111 skb->dev = dev; 112 skb_reset_mac_header(skb); 113 114 if (hdlc->proto->type_trans) 115 return hdlc->proto->type_trans(skb, dev); 116 else 117 return htons(ETH_P_HDLC); 118 } 119 120 #endif /* __HDLC_H */
1 #ifndef _LINUX_LIST_H 2 #define _LINUX_LIST_H 3 4 #include <linux/types.h> 5 #include <linux/stddef.h> 6 #include <linux/poison.h> 7 #include <linux/const.h> 8 #include <linux/kernel.h> 9 10 /* 11 * Simple doubly linked list implementation. 12 * 13 * Some of the internal functions ("__xxx") are useful when 14 * manipulating whole lists rather than single entries, as 15 * sometimes we already know the next/prev entries and we can 16 * generate better code by using them directly rather than 17 * using the generic single-entry routines. 18 */ 19 20 #define LIST_HEAD_INIT(name) { &(name), &(name) } 21 22 #define LIST_HEAD(name) \ 23 struct list_head name = LIST_HEAD_INIT(name) 24 25 static inline void INIT_LIST_HEAD(struct list_head *list) 26 { 27 WRITE_ONCE(list->next, list); 28 list->prev = list; 29 } 30 31 /* 32 * Insert a new entry between two known consecutive entries. 33 * 34 * This is only for internal list manipulation where we know 35 * the prev/next entries already! 36 */ 37 #ifndef CONFIG_DEBUG_LIST 38 static inline void __list_add(struct list_head *new, 39 struct list_head *prev, 40 struct list_head *next) 41 { 42 next->prev = new; 43 new->next = next; 44 new->prev = prev; 45 WRITE_ONCE(prev->next, new); 46 } 47 #else 48 extern void __list_add(struct list_head *new, 49 struct list_head *prev, 50 struct list_head *next); 51 #endif 52 53 /** 54 * list_add - add a new entry 55 * @new: new entry to be added 56 * @head: list head to add it after 57 * 58 * Insert a new entry after the specified head. 59 * This is good for implementing stacks. 60 */ 61 static inline void list_add(struct list_head *new, struct list_head *head) 62 { 63 __list_add(new, head, head->next); 64 } 65 66 67 /** 68 * list_add_tail - add a new entry 69 * @new: new entry to be added 70 * @head: list head to add it before 71 * 72 * Insert a new entry before the specified head. 73 * This is useful for implementing queues. 74 */ 75 static inline void list_add_tail(struct list_head *new, struct list_head *head) 76 { 77 __list_add(new, head->prev, head); 78 } 79 80 /* 81 * Delete a list entry by making the prev/next entries 82 * point to each other. 83 * 84 * This is only for internal list manipulation where we know 85 * the prev/next entries already! 86 */ 87 static inline void __list_del(struct list_head * prev, struct list_head * next) 88 { 89 next->prev = prev; 90 WRITE_ONCE(prev->next, next); 91 } 92 93 /** 94 * list_del - deletes entry from list. 95 * @entry: the element to delete from the list. 96 * Note: list_empty() on entry does not return true after this, the entry is 97 * in an undefined state. 98 */ 99 #ifndef CONFIG_DEBUG_LIST 100 static inline void __list_del_entry(struct list_head *entry) 101 { 102 __list_del(entry->prev, entry->next); 103 } 104 105 static inline void list_del(struct list_head *entry) 106 { 107 __list_del(entry->prev, entry->next); 108 entry->next = LIST_POISON1; 109 entry->prev = LIST_POISON2; 110 } 111 #else 112 extern void __list_del_entry(struct list_head *entry); 113 extern void list_del(struct list_head *entry); 114 #endif 115 116 #ifdef CONFIG_DEBUG_LIST 117 /* 118 * See devm_memremap_pages() which wants DEBUG_LIST=y to assert if one 119 * of the pages it allocates is ever passed to list_add() 120 */ 121 extern void list_force_poison(struct list_head *entry); 122 #else 123 /* fallback to the less strict LIST_POISON* definitions */ 124 #define list_force_poison list_del 125 #endif 126 127 /** 128 * list_replace - replace old entry by new one 129 * @old : the element to be replaced 130 * @new : the new element to insert 131 * 132 * If @old was empty, it will be overwritten. 133 */ 134 static inline void list_replace(struct list_head *old, 135 struct list_head *new) 136 { 137 new->next = old->next; 138 new->next->prev = new; 139 new->prev = old->prev; 140 new->prev->next = new; 141 } 142 143 static inline void list_replace_init(struct list_head *old, 144 struct list_head *new) 145 { 146 list_replace(old, new); 147 INIT_LIST_HEAD(old); 148 } 149 150 /** 151 * list_del_init - deletes entry from list and reinitialize it. 152 * @entry: the element to delete from the list. 153 */ 154 static inline void list_del_init(struct list_head *entry) 155 { 156 __list_del_entry(entry); 157 INIT_LIST_HEAD(entry); 158 } 159 160 /** 161 * list_move - delete from one list and add as another's head 162 * @list: the entry to move 163 * @head: the head that will precede our entry 164 */ 165 static inline void list_move(struct list_head *list, struct list_head *head) 166 { 167 __list_del_entry(list); 168 list_add(list, head); 169 } 170 171 /** 172 * list_move_tail - delete from one list and add as another's tail 173 * @list: the entry to move 174 * @head: the head that will follow our entry 175 */ 176 static inline void list_move_tail(struct list_head *list, 177 struct list_head *head) 178 { 179 __list_del_entry(list); 180 list_add_tail(list, head); 181 } 182 183 /** 184 * list_is_last - tests whether @list is the last entry in list @head 185 * @list: the entry to test 186 * @head: the head of the list 187 */ 188 static inline int list_is_last(const struct list_head *list, 189 const struct list_head *head) 190 { 191 return list->next == head; 192 } 193 194 /** 195 * list_empty - tests whether a list is empty 196 * @head: the list to test. 197 */ 198 static inline int list_empty(const struct list_head *head) 199 { 200 return READ_ONCE(head->next) == head; 201 } 202 203 /** 204 * list_empty_careful - tests whether a list is empty and not being modified 205 * @head: the list to test 206 * 207 * Description: 208 * tests whether a list is empty _and_ checks that no other CPU might be 209 * in the process of modifying either member (next or prev) 210 * 211 * NOTE: using list_empty_careful() without synchronization 212 * can only be safe if the only activity that can happen 213 * to the list entry is list_del_init(). Eg. it cannot be used 214 * if another CPU could re-list_add() it. 215 */ 216 static inline int list_empty_careful(const struct list_head *head) 217 { 218 struct list_head *next = head->next; 219 return (next == head) && (next == head->prev); 220 } 221 222 /** 223 * list_rotate_left - rotate the list to the left 224 * @head: the head of the list 225 */ 226 static inline void list_rotate_left(struct list_head *head) 227 { 228 struct list_head *first; 229 230 if (!list_empty(head)) { 231 first = head->next; 232 list_move_tail(first, head); 233 } 234 } 235 236 /** 237 * list_is_singular - tests whether a list has just one entry. 238 * @head: the list to test. 239 */ 240 static inline int list_is_singular(const struct list_head *head) 241 { 242 return !list_empty(head) && (head->next == head->prev); 243 } 244 245 static inline void __list_cut_position(struct list_head *list, 246 struct list_head *head, struct list_head *entry) 247 { 248 struct list_head *new_first = entry->next; 249 list->next = head->next; 250 list->next->prev = list; 251 list->prev = entry; 252 entry->next = list; 253 head->next = new_first; 254 new_first->prev = head; 255 } 256 257 /** 258 * list_cut_position - cut a list into two 259 * @list: a new list to add all removed entries 260 * @head: a list with entries 261 * @entry: an entry within head, could be the head itself 262 * and if so we won't cut the list 263 * 264 * This helper moves the initial part of @head, up to and 265 * including @entry, from @head to @list. You should 266 * pass on @entry an element you know is on @head. @list 267 * should be an empty list or a list you do not care about 268 * losing its data. 269 * 270 */ 271 static inline void list_cut_position(struct list_head *list, 272 struct list_head *head, struct list_head *entry) 273 { 274 if (list_empty(head)) 275 return; 276 if (list_is_singular(head) && 277 (head->next != entry && head != entry)) 278 return; 279 if (entry == head) 280 INIT_LIST_HEAD(list); 281 else 282 __list_cut_position(list, head, entry); 283 } 284 285 static inline void __list_splice(const struct list_head *list, 286 struct list_head *prev, 287 struct list_head *next) 288 { 289 struct list_head *first = list->next; 290 struct list_head *last = list->prev; 291 292 first->prev = prev; 293 prev->next = first; 294 295 last->next = next; 296 next->prev = last; 297 } 298 299 /** 300 * list_splice - join two lists, this is designed for stacks 301 * @list: the new list to add. 302 * @head: the place to add it in the first list. 303 */ 304 static inline void list_splice(const struct list_head *list, 305 struct list_head *head) 306 { 307 if (!list_empty(list)) 308 __list_splice(list, head, head->next); 309 } 310 311 /** 312 * list_splice_tail - join two lists, each list being a queue 313 * @list: the new list to add. 314 * @head: the place to add it in the first list. 315 */ 316 static inline void list_splice_tail(struct list_head *list, 317 struct list_head *head) 318 { 319 if (!list_empty(list)) 320 __list_splice(list, head->prev, head); 321 } 322 323 /** 324 * list_splice_init - join two lists and reinitialise the emptied list. 325 * @list: the new list to add. 326 * @head: the place to add it in the first list. 327 * 328 * The list at @list is reinitialised 329 */ 330 static inline void list_splice_init(struct list_head *list, 331 struct list_head *head) 332 { 333 if (!list_empty(list)) { 334 __list_splice(list, head, head->next); 335 INIT_LIST_HEAD(list); 336 } 337 } 338 339 /** 340 * list_splice_tail_init - join two lists and reinitialise the emptied list 341 * @list: the new list to add. 342 * @head: the place to add it in the first list. 343 * 344 * Each of the lists is a queue. 345 * The list at @list is reinitialised 346 */ 347 static inline void list_splice_tail_init(struct list_head *list, 348 struct list_head *head) 349 { 350 if (!list_empty(list)) { 351 __list_splice(list, head->prev, head); 352 INIT_LIST_HEAD(list); 353 } 354 } 355 356 /** 357 * list_entry - get the struct for this entry 358 * @ptr: the &struct list_head pointer. 359 * @type: the type of the struct this is embedded in. 360 * @member: the name of the list_head within the struct. 361 */ 362 #define list_entry(ptr, type, member) \ 363 container_of(ptr, type, member) 364 365 /** 366 * list_first_entry - get the first element from a list 367 * @ptr: the list head to take the element from. 368 * @type: the type of the struct this is embedded in. 369 * @member: the name of the list_head within the struct. 370 * 371 * Note, that list is expected to be not empty. 372 */ 373 #define list_first_entry(ptr, type, member) \ 374 list_entry((ptr)->next, type, member) 375 376 /** 377 * list_last_entry - get the last element from a list 378 * @ptr: the list head to take the element from. 379 * @type: the type of the struct this is embedded in. 380 * @member: the name of the list_head within the struct. 381 * 382 * Note, that list is expected to be not empty. 383 */ 384 #define list_last_entry(ptr, type, member) \ 385 list_entry((ptr)->prev, type, member) 386 387 /** 388 * list_first_entry_or_null - get the first element from a list 389 * @ptr: the list head to take the element from. 390 * @type: the type of the struct this is embedded in. 391 * @member: the name of the list_head within the struct. 392 * 393 * Note that if the list is empty, it returns NULL. 394 */ 395 #define list_first_entry_or_null(ptr, type, member) \ 396 (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL) 397 398 /** 399 * list_next_entry - get the next element in list 400 * @pos: the type * to cursor 401 * @member: the name of the list_head within the struct. 402 */ 403 #define list_next_entry(pos, member) \ 404 list_entry((pos)->member.next, typeof(*(pos)), member) 405 406 /** 407 * list_prev_entry - get the prev element in list 408 * @pos: the type * to cursor 409 * @member: the name of the list_head within the struct. 410 */ 411 #define list_prev_entry(pos, member) \ 412 list_entry((pos)->member.prev, typeof(*(pos)), member) 413 414 /** 415 * list_for_each - iterate over a list 416 * @pos: the &struct list_head to use as a loop cursor. 417 * @head: the head for your list. 418 */ 419 #define list_for_each(pos, head) \ 420 for (pos = (head)->next; pos != (head); pos = pos->next) 421 422 /** 423 * list_for_each_prev - iterate over a list backwards 424 * @pos: the &struct list_head to use as a loop cursor. 425 * @head: the head for your list. 426 */ 427 #define list_for_each_prev(pos, head) \ 428 for (pos = (head)->prev; pos != (head); pos = pos->prev) 429 430 /** 431 * list_for_each_safe - iterate over a list safe against removal of list entry 432 * @pos: the &struct list_head to use as a loop cursor. 433 * @n: another &struct list_head to use as temporary storage 434 * @head: the head for your list. 435 */ 436 #define list_for_each_safe(pos, n, head) \ 437 for (pos = (head)->next, n = pos->next; pos != (head); \ 438 pos = n, n = pos->next) 439 440 /** 441 * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry 442 * @pos: the &struct list_head to use as a loop cursor. 443 * @n: another &struct list_head to use as temporary storage 444 * @head: the head for your list. 445 */ 446 #define list_for_each_prev_safe(pos, n, head) \ 447 for (pos = (head)->prev, n = pos->prev; \ 448 pos != (head); \ 449 pos = n, n = pos->prev) 450 451 /** 452 * list_for_each_entry - iterate over list of given type 453 * @pos: the type * to use as a loop cursor. 454 * @head: the head for your list. 455 * @member: the name of the list_head within the struct. 456 */ 457 #define list_for_each_entry(pos, head, member) \ 458 for (pos = list_first_entry(head, typeof(*pos), member); \ 459 &pos->member != (head); \ 460 pos = list_next_entry(pos, member)) 461 462 /** 463 * list_for_each_entry_reverse - iterate backwards over list of given type. 464 * @pos: the type * to use as a loop cursor. 465 * @head: the head for your list. 466 * @member: the name of the list_head within the struct. 467 */ 468 #define list_for_each_entry_reverse(pos, head, member) \ 469 for (pos = list_last_entry(head, typeof(*pos), member); \ 470 &pos->member != (head); \ 471 pos = list_prev_entry(pos, member)) 472 473 /** 474 * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() 475 * @pos: the type * to use as a start point 476 * @head: the head of the list 477 * @member: the name of the list_head within the struct. 478 * 479 * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). 480 */ 481 #define list_prepare_entry(pos, head, member) \ 482 ((pos) ? : list_entry(head, typeof(*pos), member)) 483 484 /** 485 * list_for_each_entry_continue - continue iteration over list of given type 486 * @pos: the type * to use as a loop cursor. 487 * @head: the head for your list. 488 * @member: the name of the list_head within the struct. 489 * 490 * Continue to iterate over list of given type, continuing after 491 * the current position. 492 */ 493 #define list_for_each_entry_continue(pos, head, member) \ 494 for (pos = list_next_entry(pos, member); \ 495 &pos->member != (head); \ 496 pos = list_next_entry(pos, member)) 497 498 /** 499 * list_for_each_entry_continue_reverse - iterate backwards from the given point 500 * @pos: the type * to use as a loop cursor. 501 * @head: the head for your list. 502 * @member: the name of the list_head within the struct. 503 * 504 * Start to iterate over list of given type backwards, continuing after 505 * the current position. 506 */ 507 #define list_for_each_entry_continue_reverse(pos, head, member) \ 508 for (pos = list_prev_entry(pos, member); \ 509 &pos->member != (head); \ 510 pos = list_prev_entry(pos, member)) 511 512 /** 513 * list_for_each_entry_from - iterate over list of given type from the current point 514 * @pos: the type * to use as a loop cursor. 515 * @head: the head for your list. 516 * @member: the name of the list_head within the struct. 517 * 518 * Iterate over list of given type, continuing from current position. 519 */ 520 #define list_for_each_entry_from(pos, head, member) \ 521 for (; &pos->member != (head); \ 522 pos = list_next_entry(pos, member)) 523 524 /** 525 * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry 526 * @pos: the type * to use as a loop cursor. 527 * @n: another type * to use as temporary storage 528 * @head: the head for your list. 529 * @member: the name of the list_head within the struct. 530 */ 531 #define list_for_each_entry_safe(pos, n, head, member) \ 532 for (pos = list_first_entry(head, typeof(*pos), member), \ 533 n = list_next_entry(pos, member); \ 534 &pos->member != (head); \ 535 pos = n, n = list_next_entry(n, member)) 536 537 /** 538 * list_for_each_entry_safe_continue - continue list iteration safe against removal 539 * @pos: the type * to use as a loop cursor. 540 * @n: another type * to use as temporary storage 541 * @head: the head for your list. 542 * @member: the name of the list_head within the struct. 543 * 544 * Iterate over list of given type, continuing after current point, 545 * safe against removal of list entry. 546 */ 547 #define list_for_each_entry_safe_continue(pos, n, head, member) \ 548 for (pos = list_next_entry(pos, member), \ 549 n = list_next_entry(pos, member); \ 550 &pos->member != (head); \ 551 pos = n, n = list_next_entry(n, member)) 552 553 /** 554 * list_for_each_entry_safe_from - iterate over list from current point safe against removal 555 * @pos: the type * to use as a loop cursor. 556 * @n: another type * to use as temporary storage 557 * @head: the head for your list. 558 * @member: the name of the list_head within the struct. 559 * 560 * Iterate over list of given type from current point, safe against 561 * removal of list entry. 562 */ 563 #define list_for_each_entry_safe_from(pos, n, head, member) \ 564 for (n = list_next_entry(pos, member); \ 565 &pos->member != (head); \ 566 pos = n, n = list_next_entry(n, member)) 567 568 /** 569 * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal 570 * @pos: the type * to use as a loop cursor. 571 * @n: another type * to use as temporary storage 572 * @head: the head for your list. 573 * @member: the name of the list_head within the struct. 574 * 575 * Iterate backwards over list of given type, safe against removal 576 * of list entry. 577 */ 578 #define list_for_each_entry_safe_reverse(pos, n, head, member) \ 579 for (pos = list_last_entry(head, typeof(*pos), member), \ 580 n = list_prev_entry(pos, member); \ 581 &pos->member != (head); \ 582 pos = n, n = list_prev_entry(n, member)) 583 584 /** 585 * list_safe_reset_next - reset a stale list_for_each_entry_safe loop 586 * @pos: the loop cursor used in the list_for_each_entry_safe loop 587 * @n: temporary storage used in list_for_each_entry_safe 588 * @member: the name of the list_head within the struct. 589 * 590 * list_safe_reset_next is not safe to use in general if the list may be 591 * modified concurrently (eg. the lock is dropped in the loop body). An 592 * exception to this is if the cursor element (pos) is pinned in the list, 593 * and list_safe_reset_next is called after re-taking the lock and before 594 * completing the current iteration of the loop body. 595 */ 596 #define list_safe_reset_next(pos, n, member) \ 597 n = list_next_entry(pos, member) 598 599 /* 600 * Double linked lists with a single pointer list head. 601 * Mostly useful for hash tables where the two pointer list head is 602 * too wasteful. 603 * You lose the ability to access the tail in O(1). 604 */ 605 606 #define HLIST_HEAD_INIT { .first = NULL } 607 #define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } 608 #define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) 609 static inline void INIT_HLIST_NODE(struct hlist_node *h) 610 { 611 h->next = NULL; 612 h->pprev = NULL; 613 } 614 615 static inline int hlist_unhashed(const struct hlist_node *h) 616 { 617 return !h->pprev; 618 } 619 620 static inline int hlist_empty(const struct hlist_head *h) 621 { 622 return !READ_ONCE(h->first); 623 } 624 625 static inline void __hlist_del(struct hlist_node *n) 626 { 627 struct hlist_node *next = n->next; 628 struct hlist_node **pprev = n->pprev; 629 630 WRITE_ONCE(*pprev, next); 631 if (next) 632 next->pprev = pprev; 633 } 634 635 static inline void hlist_del(struct hlist_node *n) 636 { 637 __hlist_del(n); 638 n->next = LIST_POISON1; 639 n->pprev = LIST_POISON2; 640 } 641 642 static inline void hlist_del_init(struct hlist_node *n) 643 { 644 if (!hlist_unhashed(n)) { 645 __hlist_del(n); 646 INIT_HLIST_NODE(n); 647 } 648 } 649 650 static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) 651 { 652 struct hlist_node *first = h->first; 653 n->next = first; 654 if (first) 655 first->pprev = &n->next; 656 WRITE_ONCE(h->first, n); 657 n->pprev = &h->first; 658 } 659 660 /* next must be != NULL */ 661 static inline void hlist_add_before(struct hlist_node *n, 662 struct hlist_node *next) 663 { 664 n->pprev = next->pprev; 665 n->next = next; 666 next->pprev = &n->next; 667 WRITE_ONCE(*(n->pprev), n); 668 } 669 670 static inline void hlist_add_behind(struct hlist_node *n, 671 struct hlist_node *prev) 672 { 673 n->next = prev->next; 674 WRITE_ONCE(prev->next, n); 675 n->pprev = &prev->next; 676 677 if (n->next) 678 n->next->pprev = &n->next; 679 } 680 681 /* after that we'll appear to be on some hlist and hlist_del will work */ 682 static inline void hlist_add_fake(struct hlist_node *n) 683 { 684 n->pprev = &n->next; 685 } 686 687 static inline bool hlist_fake(struct hlist_node *h) 688 { 689 return h->pprev == &h->next; 690 } 691 692 /* 693 * Move a list from one list head to another. Fixup the pprev 694 * reference of the first entry if it exists. 695 */ 696 static inline void hlist_move_list(struct hlist_head *old, 697 struct hlist_head *new) 698 { 699 new->first = old->first; 700 if (new->first) 701 new->first->pprev = &new->first; 702 old->first = NULL; 703 } 704 705 #define hlist_entry(ptr, type, member) container_of(ptr,type,member) 706 707 #define hlist_for_each(pos, head) \ 708 for (pos = (head)->first; pos ; pos = pos->next) 709 710 #define hlist_for_each_safe(pos, n, head) \ 711 for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \ 712 pos = n) 713 714 #define hlist_entry_safe(ptr, type, member) \ 715 ({ typeof(ptr) ____ptr = (ptr); \ 716 ____ptr ? hlist_entry(____ptr, type, member) : NULL; \ 717 }) 718 719 /** 720 * hlist_for_each_entry - iterate over list of given type 721 * @pos: the type * to use as a loop cursor. 722 * @head: the head for your list. 723 * @member: the name of the hlist_node within the struct. 724 */ 725 #define hlist_for_each_entry(pos, head, member) \ 726 for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member);\ 727 pos; \ 728 pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) 729 730 /** 731 * hlist_for_each_entry_continue - iterate over a hlist continuing after current point 732 * @pos: the type * to use as a loop cursor. 733 * @member: the name of the hlist_node within the struct. 734 */ 735 #define hlist_for_each_entry_continue(pos, member) \ 736 for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member);\ 737 pos; \ 738 pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) 739 740 /** 741 * hlist_for_each_entry_from - iterate over a hlist continuing from current point 742 * @pos: the type * to use as a loop cursor. 743 * @member: the name of the hlist_node within the struct. 744 */ 745 #define hlist_for_each_entry_from(pos, member) \ 746 for (; pos; \ 747 pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) 748 749 /** 750 * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry 751 * @pos: the type * to use as a loop cursor. 752 * @n: another &struct hlist_node to use as temporary storage 753 * @head: the head for your list. 754 * @member: the name of the hlist_node within the struct. 755 */ 756 #define hlist_for_each_entry_safe(pos, n, head, member) \ 757 for (pos = hlist_entry_safe((head)->first, typeof(*pos), member);\ 758 pos && ({ n = pos->member.next; 1; }); \ 759 pos = hlist_entry_safe(n, typeof(*pos), member)) 760 761 #endif
1 /* 2 * INET An implementation of the TCP/IP protocol suite for the LINUX 3 * operating system. INET is implemented using the BSD Socket 4 * interface as the means of communication with the user level. 5 * 6 * Definitions for the Interfaces handler. 7 * 8 * Version: @(#)dev.h 1.0.10 08/12/93 9 * 10 * Authors: Ross Biro 11 * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> 12 * Corey Minyard <wf-rch!minyard@relay.EU.net> 13 * Donald J. Becker, <becker@cesdis.gsfc.nasa.gov> 14 * Alan Cox, <alan@lxorguk.ukuu.org.uk> 15 * Bjorn Ekwall. <bj0rn@blox.se> 16 * Pekka Riikonen <priikone@poseidon.pspt.fi> 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License 20 * as published by the Free Software Foundation; either version 21 * 2 of the License, or (at your option) any later version. 22 * 23 * Moved to /usr/include/linux for NET3 24 */ 25 #ifndef _LINUX_NETDEVICE_H 26 #define _LINUX_NETDEVICE_H 27 28 #include <linux/timer.h> 29 #include <linux/bug.h> 30 #include <linux/delay.h> 31 #include <linux/atomic.h> 32 #include <linux/prefetch.h> 33 #include <asm/cache.h> 34 #include <asm/byteorder.h> 35 36 #include <linux/percpu.h> 37 #include <linux/rculist.h> 38 #include <linux/dmaengine.h> 39 #include <linux/workqueue.h> 40 #include <linux/dynamic_queue_limits.h> 41 42 #include <linux/ethtool.h> 43 #include <net/net_namespace.h> 44 #include <net/dsa.h> 45 #ifdef CONFIG_DCB 46 #include <net/dcbnl.h> 47 #endif 48 #include <net/netprio_cgroup.h> 49 50 #include <linux/netdev_features.h> 51 #include <linux/neighbour.h> 52 #include <uapi/linux/netdevice.h> 53 #include <uapi/linux/if_bonding.h> 54 55 struct netpoll_info; 56 struct device; 57 struct phy_device; 58 /* 802.11 specific */ 59 struct wireless_dev; 60 /* 802.15.4 specific */ 61 struct wpan_dev; 62 struct mpls_dev; 63 64 void netdev_set_default_ethtool_ops(struct net_device *dev, 65 const struct ethtool_ops *ops); 66 67 /* Backlog congestion levels */ 68 #define NET_RX_SUCCESS 0 /* keep 'em coming, baby */ 69 #define NET_RX_DROP 1 /* packet dropped */ 70 71 /* 72 * Transmit return codes: transmit return codes originate from three different 73 * namespaces: 74 * 75 * - qdisc return codes 76 * - driver transmit return codes 77 * - errno values 78 * 79 * Drivers are allowed to return any one of those in their hard_start_xmit() 80 * function. Real network devices commonly used with qdiscs should only return 81 * the driver transmit return codes though - when qdiscs are used, the actual 82 * transmission happens asynchronously, so the value is not propagated to 83 * higher layers. Virtual network devices transmit synchronously, in this case 84 * the driver transmit return codes are consumed by dev_queue_xmit(), all 85 * others are propagated to higher layers. 86 */ 87 88 /* qdisc ->enqueue() return codes. */ 89 #define NET_XMIT_SUCCESS 0x00 90 #define NET_XMIT_DROP 0x01 /* skb dropped */ 91 #define NET_XMIT_CN 0x02 /* congestion notification */ 92 #define NET_XMIT_POLICED 0x03 /* skb is shot by police */ 93 #define NET_XMIT_MASK 0x0f /* qdisc flags in net/sch_generic.h */ 94 95 /* NET_XMIT_CN is special. It does not guarantee that this packet is lost. It 96 * indicates that the device will soon be dropping packets, or already drops 97 * some packets of the same priority; prompting us to send less aggressively. */ 98 #define net_xmit_eval(e) ((e) == NET_XMIT_CN ? 0 : (e)) 99 #define net_xmit_errno(e) ((e) != NET_XMIT_CN ? -ENOBUFS : 0) 100 101 /* Driver transmit return codes */ 102 #define NETDEV_TX_MASK 0xf0 103 104 enum netdev_tx { 105 __NETDEV_TX_MIN = INT_MIN, /* make sure enum is signed */ 106 NETDEV_TX_OK = 0x00, /* driver took care of packet */ 107 NETDEV_TX_BUSY = 0x10, /* driver tx path was busy*/ 108 NETDEV_TX_LOCKED = 0x20, /* driver tx lock was already taken */ 109 }; 110 typedef enum netdev_tx netdev_tx_t; 111 112 /* 113 * Current order: NETDEV_TX_MASK > NET_XMIT_MASK >= 0 is significant; 114 * hard_start_xmit() return < NET_XMIT_MASK means skb was consumed. 115 */ 116 static inline bool dev_xmit_complete(int rc) 117 { 118 /* 119 * Positive cases with an skb consumed by a driver: 120 * - successful transmission (rc == NETDEV_TX_OK) 121 * - error while transmitting (rc < 0) 122 * - error while queueing to a different device (rc & NET_XMIT_MASK) 123 */ 124 if (likely(rc < NET_XMIT_MASK)) 125 return true; 126 127 return false; 128 } 129 130 /* 131 * Compute the worst case header length according to the protocols 132 * used. 133 */ 134 135 #if defined(CONFIG_HYPERV_NET) 136 # define LL_MAX_HEADER 128 137 #elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) 138 # if defined(CONFIG_MAC80211_MESH) 139 # define LL_MAX_HEADER 128 140 # else 141 # define LL_MAX_HEADER 96 142 # endif 143 #else 144 # define LL_MAX_HEADER 32 145 #endif 146 147 #if !IS_ENABLED(CONFIG_NET_IPIP) && !IS_ENABLED(CONFIG_NET_IPGRE) && \ 148 !IS_ENABLED(CONFIG_IPV6_SIT) && !IS_ENABLED(CONFIG_IPV6_TUNNEL) 149 #define MAX_HEADER LL_MAX_HEADER 150 #else 151 #define MAX_HEADER (LL_MAX_HEADER + 48) 152 #endif 153 154 /* 155 * Old network device statistics. Fields are native words 156 * (unsigned long) so they can be read and written atomically. 157 */ 158 159 struct net_device_stats { 160 unsigned long rx_packets; 161 unsigned long tx_packets; 162 unsigned long rx_bytes; 163 unsigned long tx_bytes; 164 unsigned long rx_errors; 165 unsigned long tx_errors; 166 unsigned long rx_dropped; 167 unsigned long tx_dropped; 168 unsigned long multicast; 169 unsigned long collisions; 170 unsigned long rx_length_errors; 171 unsigned long rx_over_errors; 172 unsigned long rx_crc_errors; 173 unsigned long rx_frame_errors; 174 unsigned long rx_fifo_errors; 175 unsigned long rx_missed_errors; 176 unsigned long tx_aborted_errors; 177 unsigned long tx_carrier_errors; 178 unsigned long tx_fifo_errors; 179 unsigned long tx_heartbeat_errors; 180 unsigned long tx_window_errors; 181 unsigned long rx_compressed; 182 unsigned long tx_compressed; 183 }; 184 185 186 #include <linux/cache.h> 187 #include <linux/skbuff.h> 188 189 #ifdef CONFIG_RPS 190 #include <linux/static_key.h> 191 extern struct static_key rps_needed; 192 #endif 193 194 struct neighbour; 195 struct neigh_parms; 196 struct sk_buff; 197 198 struct netdev_hw_addr { 199 struct list_head list; 200 unsigned char addr[MAX_ADDR_LEN]; 201 unsigned char type; 202 #define NETDEV_HW_ADDR_T_LAN 1 203 #define NETDEV_HW_ADDR_T_SAN 2 204 #define NETDEV_HW_ADDR_T_SLAVE 3 205 #define NETDEV_HW_ADDR_T_UNICAST 4 206 #define NETDEV_HW_ADDR_T_MULTICAST 5 207 bool global_use; 208 int sync_cnt; 209 int refcount; 210 int synced; 211 struct rcu_head rcu_head; 212 }; 213 214 struct netdev_hw_addr_list { 215 struct list_head list; 216 int count; 217 }; 218 219 #define netdev_hw_addr_list_count(l) ((l)->count) 220 #define netdev_hw_addr_list_empty(l) (netdev_hw_addr_list_count(l) == 0) 221 #define netdev_hw_addr_list_for_each(ha, l) \ 222 list_for_each_entry(ha, &(l)->list, list) 223 224 #define netdev_uc_count(dev) netdev_hw_addr_list_count(&(dev)->uc) 225 #define netdev_uc_empty(dev) netdev_hw_addr_list_empty(&(dev)->uc) 226 #define netdev_for_each_uc_addr(ha, dev) \ 227 netdev_hw_addr_list_for_each(ha, &(dev)->uc) 228 229 #define netdev_mc_count(dev) netdev_hw_addr_list_count(&(dev)->mc) 230 #define netdev_mc_empty(dev) netdev_hw_addr_list_empty(&(dev)->mc) 231 #define netdev_for_each_mc_addr(ha, dev) \ 232 netdev_hw_addr_list_for_each(ha, &(dev)->mc) 233 234 struct hh_cache { 235 u16 hh_len; 236 u16 __pad; 237 seqlock_t hh_lock; 238 239 /* cached hardware header; allow for machine alignment needs. */ 240 #define HH_DATA_MOD 16 241 #define HH_DATA_OFF(__len) \ 242 (HH_DATA_MOD - (((__len - 1) & (HH_DATA_MOD - 1)) + 1)) 243 #define HH_DATA_ALIGN(__len) \ 244 (((__len)+(HH_DATA_MOD-1))&~(HH_DATA_MOD - 1)) 245 unsigned long hh_data[HH_DATA_ALIGN(LL_MAX_HEADER) / sizeof(long)]; 246 }; 247 248 /* Reserve HH_DATA_MOD byte aligned hard_header_len, but at least that much. 249 * Alternative is: 250 * dev->hard_header_len ? (dev->hard_header_len + 251 * (HH_DATA_MOD - 1)) & ~(HH_DATA_MOD - 1) : 0 252 * 253 * We could use other alignment values, but we must maintain the 254 * relationship HH alignment <= LL alignment. 255 */ 256 #define LL_RESERVED_SPACE(dev) \ 257 ((((dev)->hard_header_len+(dev)->needed_headroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) 258 #define LL_RESERVED_SPACE_EXTRA(dev,extra) \ 259 ((((dev)->hard_header_len+(dev)->needed_headroom+(extra))&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) 260 261 struct header_ops { 262 int (*create) (struct sk_buff *skb, struct net_device *dev, 263 unsigned short type, const void *daddr, 264 const void *saddr, unsigned int len); 265 int (*parse)(const struct sk_buff *skb, unsigned char *haddr); 266 int (*cache)(const struct neighbour *neigh, struct hh_cache *hh, __be16 type); 267 void (*cache_update)(struct hh_cache *hh, 268 const struct net_device *dev, 269 const unsigned char *haddr); 270 }; 271 272 /* These flag bits are private to the generic network queueing 273 * layer, they may not be explicitly referenced by any other 274 * code. 275 */ 276 277 enum netdev_state_t { 278 __LINK_STATE_START, 279 __LINK_STATE_PRESENT, 280 __LINK_STATE_NOCARRIER, 281 __LINK_STATE_LINKWATCH_PENDING, 282 __LINK_STATE_DORMANT, 283 }; 284 285 286 /* 287 * This structure holds at boot time configured netdevice settings. They 288 * are then used in the device probing. 289 */ 290 struct netdev_boot_setup { 291 char name[IFNAMSIZ]; 292 struct ifmap map; 293 }; 294 #define NETDEV_BOOT_SETUP_MAX 8 295 296 int __init netdev_boot_setup(char *str); 297 298 /* 299 * Structure for NAPI scheduling similar to tasklet but with weighting 300 */ 301 struct napi_struct { 302 /* The poll_list must only be managed by the entity which 303 * changes the state of the NAPI_STATE_SCHED bit. This means 304 * whoever atomically sets that bit can add this napi_struct 305 * to the per-cpu poll_list, and whoever clears that bit 306 * can remove from the list right before clearing the bit. 307 */ 308 struct list_head poll_list; 309 310 unsigned long state; 311 int weight; 312 unsigned int gro_count; 313 int (*poll)(struct napi_struct *, int); 314 #ifdef CONFIG_NETPOLL 315 spinlock_t poll_lock; 316 int poll_owner; 317 #endif 318 struct net_device *dev; 319 struct sk_buff *gro_list; 320 struct sk_buff *skb; 321 struct hrtimer timer; 322 struct list_head dev_list; 323 struct hlist_node napi_hash_node; 324 unsigned int napi_id; 325 }; 326 327 enum { 328 NAPI_STATE_SCHED, /* Poll is scheduled */ 329 NAPI_STATE_DISABLE, /* Disable pending */ 330 NAPI_STATE_NPSVC, /* Netpoll - don't dequeue from poll_list */ 331 NAPI_STATE_HASHED, /* In NAPI hash (busy polling possible) */ 332 NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */ 333 }; 334 335 enum gro_result { 336 GRO_MERGED, 337 GRO_MERGED_FREE, 338 GRO_HELD, 339 GRO_NORMAL, 340 GRO_DROP, 341 }; 342 typedef enum gro_result gro_result_t; 343 344 /* 345 * enum rx_handler_result - Possible return values for rx_handlers. 346 * @RX_HANDLER_CONSUMED: skb was consumed by rx_handler, do not process it 347 * further. 348 * @RX_HANDLER_ANOTHER: Do another round in receive path. This is indicated in 349 * case skb->dev was changed by rx_handler. 350 * @RX_HANDLER_EXACT: Force exact delivery, no wildcard. 351 * @RX_HANDLER_PASS: Do nothing, passe the skb as if no rx_handler was called. 352 * 353 * rx_handlers are functions called from inside __netif_receive_skb(), to do 354 * special processing of the skb, prior to delivery to protocol handlers. 355 * 356 * Currently, a net_device can only have a single rx_handler registered. Trying 357 * to register a second rx_handler will return -EBUSY. 358 * 359 * To register a rx_handler on a net_device, use netdev_rx_handler_register(). 360 * To unregister a rx_handler on a net_device, use 361 * netdev_rx_handler_unregister(). 362 * 363 * Upon return, rx_handler is expected to tell __netif_receive_skb() what to 364 * do with the skb. 365 * 366 * If the rx_handler consumed to skb in some way, it should return 367 * RX_HANDLER_CONSUMED. This is appropriate when the rx_handler arranged for 368 * the skb to be delivered in some other ways. 369 * 370 * If the rx_handler changed skb->dev, to divert the skb to another 371 * net_device, it should return RX_HANDLER_ANOTHER. The rx_handler for the 372 * new device will be called if it exists. 373 * 374 * If the rx_handler consider the skb should be ignored, it should return 375 * RX_HANDLER_EXACT. The skb will only be delivered to protocol handlers that 376 * are registered on exact device (ptype->dev == skb->dev). 377 * 378 * If the rx_handler didn't changed skb->dev, but want the skb to be normally 379 * delivered, it should return RX_HANDLER_PASS. 380 * 381 * A device without a registered rx_handler will behave as if rx_handler 382 * returned RX_HANDLER_PASS. 383 */ 384 385 enum rx_handler_result { 386 RX_HANDLER_CONSUMED, 387 RX_HANDLER_ANOTHER, 388 RX_HANDLER_EXACT, 389 RX_HANDLER_PASS, 390 }; 391 typedef enum rx_handler_result rx_handler_result_t; 392 typedef rx_handler_result_t rx_handler_func_t(struct sk_buff **pskb); 393 394 void __napi_schedule(struct napi_struct *n); 395 void __napi_schedule_irqoff(struct napi_struct *n); 396 397 static inline bool napi_disable_pending(struct napi_struct *n) 398 { 399 return test_bit(NAPI_STATE_DISABLE, &n->state); 400 } 401 402 /** 403 * napi_schedule_prep - check if napi can be scheduled 404 * @n: napi context 405 * 406 * Test if NAPI routine is already running, and if not mark 407 * it as running. This is used as a condition variable 408 * insure only one NAPI poll instance runs. We also make 409 * sure there is no pending NAPI disable. 410 */ 411 static inline bool napi_schedule_prep(struct napi_struct *n) 412 { 413 return !napi_disable_pending(n) && 414 !test_and_set_bit(NAPI_STATE_SCHED, &n->state); 415 } 416 417 /** 418 * napi_schedule - schedule NAPI poll 419 * @n: napi context 420 * 421 * Schedule NAPI poll routine to be called if it is not already 422 * running. 423 */ 424 static inline void napi_schedule(struct napi_struct *n) 425 { 426 if (napi_schedule_prep(n)) 427 __napi_schedule(n); 428 } 429 430 /** 431 * napi_schedule_irqoff - schedule NAPI poll 432 * @n: napi context 433 * 434 * Variant of napi_schedule(), assuming hard irqs are masked. 435 */ 436 static inline void napi_schedule_irqoff(struct napi_struct *n) 437 { 438 if (napi_schedule_prep(n)) 439 __napi_schedule_irqoff(n); 440 } 441 442 /* Try to reschedule poll. Called by dev->poll() after napi_complete(). */ 443 static inline bool napi_reschedule(struct napi_struct *napi) 444 { 445 if (napi_schedule_prep(napi)) { 446 __napi_schedule(napi); 447 return true; 448 } 449 return false; 450 } 451 452 void __napi_complete(struct napi_struct *n); 453 void napi_complete_done(struct napi_struct *n, int work_done); 454 /** 455 * napi_complete - NAPI processing complete 456 * @n: napi context 457 * 458 * Mark NAPI processing as complete. 459 * Consider using napi_complete_done() instead. 460 */ 461 static inline void napi_complete(struct napi_struct *n) 462 { 463 return napi_complete_done(n, 0); 464 } 465 466 /** 467 * napi_hash_add - add a NAPI to global hashtable 468 * @napi: napi context 469 * 470 * generate a new napi_id and store a @napi under it in napi_hash 471 * Used for busy polling (CONFIG_NET_RX_BUSY_POLL) 472 * Note: This is normally automatically done from netif_napi_add(), 473 * so might disappear in a future linux version. 474 */ 475 void napi_hash_add(struct napi_struct *napi); 476 477 /** 478 * napi_hash_del - remove a NAPI from global table 479 * @napi: napi context 480 * 481 * Warning: caller must observe rcu grace period 482 * before freeing memory containing @napi, if 483 * this function returns true. 484 * Note: core networking stack automatically calls it 485 * from netif_napi_del() 486 * Drivers might want to call this helper to combine all 487 * the needed rcu grace periods into a single one. 488 */ 489 bool napi_hash_del(struct napi_struct *napi); 490 491 /** 492 * napi_disable - prevent NAPI from scheduling 493 * @n: napi context 494 * 495 * Stop NAPI from being scheduled on this context. 496 * Waits till any outstanding processing completes. 497 */ 498 void napi_disable(struct napi_struct *n); 499 500 /** 501 * napi_enable - enable NAPI scheduling 502 * @n: napi context 503 * 504 * Resume NAPI from being scheduled on this context. 505 * Must be paired with napi_disable. 506 */ 507 static inline void napi_enable(struct napi_struct *n) 508 { 509 BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); 510 smp_mb__before_atomic(); 511 clear_bit(NAPI_STATE_SCHED, &n->state); 512 clear_bit(NAPI_STATE_NPSVC, &n->state); 513 } 514 515 #ifdef CONFIG_SMP 516 /** 517 * napi_synchronize - wait until NAPI is not running 518 * @n: napi context 519 * 520 * Wait until NAPI is done being scheduled on this context. 521 * Waits till any outstanding processing completes but 522 * does not disable future activations. 523 */ 524 static inline void napi_synchronize(const struct napi_struct *n) 525 { 526 while (test_bit(NAPI_STATE_SCHED, &n->state)) 527 msleep(1); 528 } 529 #else 530 # define napi_synchronize(n) barrier() 531 #endif 532 533 enum netdev_queue_state_t { 534 __QUEUE_STATE_DRV_XOFF, 535 __QUEUE_STATE_STACK_XOFF, 536 __QUEUE_STATE_FROZEN, 537 }; 538 539 #define QUEUE_STATE_DRV_XOFF (1 << __QUEUE_STATE_DRV_XOFF) 540 #define QUEUE_STATE_STACK_XOFF (1 << __QUEUE_STATE_STACK_XOFF) 541 #define QUEUE_STATE_FROZEN (1 << __QUEUE_STATE_FROZEN) 542 543 #define QUEUE_STATE_ANY_XOFF (QUEUE_STATE_DRV_XOFF | QUEUE_STATE_STACK_XOFF) 544 #define QUEUE_STATE_ANY_XOFF_OR_FROZEN (QUEUE_STATE_ANY_XOFF | \ 545 QUEUE_STATE_FROZEN) 546 #define QUEUE_STATE_DRV_XOFF_OR_FROZEN (QUEUE_STATE_DRV_XOFF | \ 547 QUEUE_STATE_FROZEN) 548 549 /* 550 * __QUEUE_STATE_DRV_XOFF is used by drivers to stop the transmit queue. The 551 * netif_tx_* functions below are used to manipulate this flag. The 552 * __QUEUE_STATE_STACK_XOFF flag is used by the stack to stop the transmit 553 * queue independently. The netif_xmit_*stopped functions below are called 554 * to check if the queue has been stopped by the driver or stack (either 555 * of the XOFF bits are set in the state). Drivers should not need to call 556 * netif_xmit*stopped functions, they should only be using netif_tx_*. 557 */ 558 559 struct netdev_queue { 560 /* 561 * read mostly part 562 */ 563 struct net_device *dev; 564 struct Qdisc __rcu *qdisc; 565 struct Qdisc *qdisc_sleeping; 566 #ifdef CONFIG_SYSFS 567 struct kobject kobj; 568 #endif 569 #if defined(CONFIG_XPS) && defined(CONFIG_NUMA) 570 int numa_node; 571 #endif 572 /* 573 * write mostly part 574 */ 575 spinlock_t _xmit_lock ____cacheline_aligned_in_smp; 576 int xmit_lock_owner; 577 /* 578 * please use this field instead of dev->trans_start 579 */ 580 unsigned long trans_start; 581 582 /* 583 * Number of TX timeouts for this queue 584 * (/sys/class/net/DEV/Q/trans_timeout) 585 */ 586 unsigned long trans_timeout; 587 588 unsigned long state; 589 590 #ifdef CONFIG_BQL 591 struct dql dql; 592 #endif 593 unsigned long tx_maxrate; 594 } ____cacheline_aligned_in_smp; 595 596 static inline int netdev_queue_numa_node_read(const struct netdev_queue *q) 597 { 598 #if defined(CONFIG_XPS) && defined(CONFIG_NUMA) 599 return q->numa_node; 600 #else 601 return NUMA_NO_NODE; 602 #endif 603 } 604 605 static inline void netdev_queue_numa_node_write(struct netdev_queue *q, int node) 606 { 607 #if defined(CONFIG_XPS) && defined(CONFIG_NUMA) 608 q->numa_node = node; 609 #endif 610 } 611 612 #ifdef CONFIG_RPS 613 /* 614 * This structure holds an RPS map which can be of variable length. The 615 * map is an array of CPUs. 616 */ 617 struct rps_map { 618 unsigned int len; 619 struct rcu_head rcu; 620 u16 cpus[0]; 621 }; 622 #define RPS_MAP_SIZE(_num) (sizeof(struct rps_map) + ((_num) * sizeof(u16))) 623 624 /* 625 * The rps_dev_flow structure contains the mapping of a flow to a CPU, the 626 * tail pointer for that CPU's input queue at the time of last enqueue, and 627 * a hardware filter index. 628 */ 629 struct rps_dev_flow { 630 u16 cpu; 631 u16 filter; 632 unsigned int last_qtail; 633 }; 634 #define RPS_NO_FILTER 0xffff 635 636 /* 637 * The rps_dev_flow_table structure contains a table of flow mappings. 638 */ 639 struct rps_dev_flow_table { 640 unsigned int mask; 641 struct rcu_head rcu; 642 struct rps_dev_flow flows[0]; 643 }; 644 #define RPS_DEV_FLOW_TABLE_SIZE(_num) (sizeof(struct rps_dev_flow_table) + \ 645 ((_num) * sizeof(struct rps_dev_flow))) 646 647 /* 648 * The rps_sock_flow_table contains mappings of flows to the last CPU 649 * on which they were processed by the application (set in recvmsg). 650 * Each entry is a 32bit value. Upper part is the high order bits 651 * of flow hash, lower part is cpu number. 652 * rps_cpu_mask is used to partition the space, depending on number of 653 * possible cpus : rps_cpu_mask = roundup_pow_of_two(nr_cpu_ids) - 1 654 * For example, if 64 cpus are possible, rps_cpu_mask = 0x3f, 655 * meaning we use 32-6=26 bits for the hash. 656 */ 657 struct rps_sock_flow_table { 658 u32 mask; 659 660 u32 ents[0] ____cacheline_aligned_in_smp; 661 }; 662 #define RPS_SOCK_FLOW_TABLE_SIZE(_num) (offsetof(struct rps_sock_flow_table, ents[_num])) 663 664 #define RPS_NO_CPU 0xffff 665 666 extern u32 rps_cpu_mask; 667 extern struct rps_sock_flow_table __rcu *rps_sock_flow_table; 668 669 static inline void rps_record_sock_flow(struct rps_sock_flow_table *table, 670 u32 hash) 671 { 672 if (table && hash) { 673 unsigned int index = hash & table->mask; 674 u32 val = hash & ~rps_cpu_mask; 675 676 /* We only give a hint, preemption can change cpu under us */ 677 val |= raw_smp_processor_id(); 678 679 if (table->ents[index] != val) 680 table->ents[index] = val; 681 } 682 } 683 684 #ifdef CONFIG_RFS_ACCEL 685 bool rps_may_expire_flow(struct net_device *dev, u16 rxq_index, u32 flow_id, 686 u16 filter_id); 687 #endif 688 #endif /* CONFIG_RPS */ 689 690 /* This structure contains an instance of an RX queue. */ 691 struct netdev_rx_queue { 692 #ifdef CONFIG_RPS 693 struct rps_map __rcu *rps_map; 694 struct rps_dev_flow_table __rcu *rps_flow_table; 695 #endif 696 struct kobject kobj; 697 struct net_device *dev; 698 } ____cacheline_aligned_in_smp; 699 700 /* 701 * RX queue sysfs structures and functions. 702 */ 703 struct rx_queue_attribute { 704 struct attribute attr; 705 ssize_t (*show)(struct netdev_rx_queue *queue, 706 struct rx_queue_attribute *attr, char *buf); 707 ssize_t (*store)(struct netdev_rx_queue *queue, 708 struct rx_queue_attribute *attr, const char *buf, size_t len); 709 }; 710 711 #ifdef CONFIG_XPS 712 /* 713 * This structure holds an XPS map which can be of variable length. The 714 * map is an array of queues. 715 */ 716 struct xps_map { 717 unsigned int len; 718 unsigned int alloc_len; 719 struct rcu_head rcu; 720 u16 queues[0]; 721 }; 722 #define XPS_MAP_SIZE(_num) (sizeof(struct xps_map) + ((_num) * sizeof(u16))) 723 #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \ 724 - sizeof(struct xps_map)) / sizeof(u16)) 725 726 /* 727 * This structure holds all XPS maps for device. Maps are indexed by CPU. 728 */ 729 struct xps_dev_maps { 730 struct rcu_head rcu; 731 struct xps_map __rcu *cpu_map[0]; 732 }; 733 #define XPS_DEV_MAPS_SIZE (sizeof(struct xps_dev_maps) + \ 734 (nr_cpu_ids * sizeof(struct xps_map *))) 735 #endif /* CONFIG_XPS */ 736 737 #define TC_MAX_QUEUE 16 738 #define TC_BITMASK 15 739 /* HW offloaded queuing disciplines txq count and offset maps */ 740 struct netdev_tc_txq { 741 u16 count; 742 u16 offset; 743 }; 744 745 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 746 /* 747 * This structure is to hold information about the device 748 * configured to run FCoE protocol stack. 749 */ 750 struct netdev_fcoe_hbainfo { 751 char manufacturer[64]; 752 char serial_number[64]; 753 char hardware_version[64]; 754 char driver_version[64]; 755 char optionrom_version[64]; 756 char firmware_version[64]; 757 char model[256]; 758 char model_description[256]; 759 }; 760 #endif 761 762 #define MAX_PHYS_ITEM_ID_LEN 32 763 764 /* This structure holds a unique identifier to identify some 765 * physical item (port for example) used by a netdevice. 766 */ 767 struct netdev_phys_item_id { 768 unsigned char id[MAX_PHYS_ITEM_ID_LEN]; 769 unsigned char id_len; 770 }; 771 772 static inline bool netdev_phys_item_id_same(struct netdev_phys_item_id *a, 773 struct netdev_phys_item_id *b) 774 { 775 return a->id_len == b->id_len && 776 memcmp(a->id, b->id, a->id_len) == 0; 777 } 778 779 typedef u16 (*select_queue_fallback_t)(struct net_device *dev, 780 struct sk_buff *skb); 781 782 /* 783 * This structure defines the management hooks for network devices. 784 * The following hooks can be defined; unless noted otherwise, they are 785 * optional and can be filled with a null pointer. 786 * 787 * int (*ndo_init)(struct net_device *dev); 788 * This function is called once when network device is registered. 789 * The network device can use this to any late stage initializaton 790 * or semantic validattion. It can fail with an error code which will 791 * be propogated back to register_netdev 792 * 793 * void (*ndo_uninit)(struct net_device *dev); 794 * This function is called when device is unregistered or when registration 795 * fails. It is not called if init fails. 796 * 797 * int (*ndo_open)(struct net_device *dev); 798 * This function is called when network device transistions to the up 799 * state. 800 * 801 * int (*ndo_stop)(struct net_device *dev); 802 * This function is called when network device transistions to the down 803 * state. 804 * 805 * netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, 806 * struct net_device *dev); 807 * Called when a packet needs to be transmitted. 808 * Returns NETDEV_TX_OK. Can return NETDEV_TX_BUSY, but you should stop 809 * the queue before that can happen; it's for obsolete devices and weird 810 * corner cases, but the stack really does a non-trivial amount 811 * of useless work if you return NETDEV_TX_BUSY. 812 * (can also return NETDEV_TX_LOCKED iff NETIF_F_LLTX) 813 * Required can not be NULL. 814 * 815 * netdev_features_t (*ndo_fix_features)(struct net_device *dev, 816 * netdev_features_t features); 817 * Adjusts the requested feature flags according to device-specific 818 * constraints, and returns the resulting flags. Must not modify 819 * the device state. 820 * 821 * u16 (*ndo_select_queue)(struct net_device *dev, struct sk_buff *skb, 822 * void *accel_priv, select_queue_fallback_t fallback); 823 * Called to decide which queue to when device supports multiple 824 * transmit queues. 825 * 826 * void (*ndo_change_rx_flags)(struct net_device *dev, int flags); 827 * This function is called to allow device receiver to make 828 * changes to configuration when multicast or promiscious is enabled. 829 * 830 * void (*ndo_set_rx_mode)(struct net_device *dev); 831 * This function is called device changes address list filtering. 832 * If driver handles unicast address filtering, it should set 833 * IFF_UNICAST_FLT to its priv_flags. 834 * 835 * int (*ndo_set_mac_address)(struct net_device *dev, void *addr); 836 * This function is called when the Media Access Control address 837 * needs to be changed. If this interface is not defined, the 838 * mac address can not be changed. 839 * 840 * int (*ndo_validate_addr)(struct net_device *dev); 841 * Test if Media Access Control address is valid for the device. 842 * 843 * int (*ndo_do_ioctl)(struct net_device *dev, struct ifreq *ifr, int cmd); 844 * Called when a user request an ioctl which can't be handled by 845 * the generic interface code. If not defined ioctl's return 846 * not supported error code. 847 * 848 * int (*ndo_set_config)(struct net_device *dev, struct ifmap *map); 849 * Used to set network devices bus interface parameters. This interface 850 * is retained for legacy reason, new devices should use the bus 851 * interface (PCI) for low level management. 852 * 853 * int (*ndo_change_mtu)(struct net_device *dev, int new_mtu); 854 * Called when a user wants to change the Maximum Transfer Unit 855 * of a device. If not defined, any request to change MTU will 856 * will return an error. 857 * 858 * void (*ndo_tx_timeout)(struct net_device *dev); 859 * Callback uses when the transmitter has not made any progress 860 * for dev->watchdog ticks. 861 * 862 * struct rtnl_link_stats64* (*ndo_get_stats64)(struct net_device *dev, 863 * struct rtnl_link_stats64 *storage); 864 * struct net_device_stats* (*ndo_get_stats)(struct net_device *dev); 865 * Called when a user wants to get the network device usage 866 * statistics. Drivers must do one of the following: 867 * 1. Define @ndo_get_stats64 to fill in a zero-initialised 868 * rtnl_link_stats64 structure passed by the caller. 869 * 2. Define @ndo_get_stats to update a net_device_stats structure 870 * (which should normally be dev->stats) and return a pointer to 871 * it. The structure may be changed asynchronously only if each 872 * field is written atomically. 873 * 3. Update dev->stats asynchronously and atomically, and define 874 * neither operation. 875 * 876 * int (*ndo_vlan_rx_add_vid)(struct net_device *dev, __be16 proto, u16 vid); 877 * If device support VLAN filtering this function is called when a 878 * VLAN id is registered. 879 * 880 * int (*ndo_vlan_rx_kill_vid)(struct net_device *dev, __be16 proto, u16 vid); 881 * If device support VLAN filtering this function is called when a 882 * VLAN id is unregistered. 883 * 884 * void (*ndo_poll_controller)(struct net_device *dev); 885 * 886 * SR-IOV management functions. 887 * int (*ndo_set_vf_mac)(struct net_device *dev, int vf, u8* mac); 888 * int (*ndo_set_vf_vlan)(struct net_device *dev, int vf, u16 vlan, u8 qos); 889 * int (*ndo_set_vf_rate)(struct net_device *dev, int vf, int min_tx_rate, 890 * int max_tx_rate); 891 * int (*ndo_set_vf_spoofchk)(struct net_device *dev, int vf, bool setting); 892 * int (*ndo_set_vf_trust)(struct net_device *dev, int vf, bool setting); 893 * int (*ndo_get_vf_config)(struct net_device *dev, 894 * int vf, struct ifla_vf_info *ivf); 895 * int (*ndo_set_vf_link_state)(struct net_device *dev, int vf, int link_state); 896 * int (*ndo_set_vf_port)(struct net_device *dev, int vf, 897 * struct nlattr *port[]); 898 * 899 * Enable or disable the VF ability to query its RSS Redirection Table and 900 * Hash Key. This is needed since on some devices VF share this information 901 * with PF and querying it may adduce a theoretical security risk. 902 * int (*ndo_set_vf_rss_query_en)(struct net_device *dev, int vf, bool setting); 903 * int (*ndo_get_vf_port)(struct net_device *dev, int vf, struct sk_buff *skb); 904 * int (*ndo_setup_tc)(struct net_device *dev, u8 tc) 905 * Called to setup 'tc' number of traffic classes in the net device. This 906 * is always called from the stack with the rtnl lock held and netif tx 907 * queues stopped. This allows the netdevice to perform queue management 908 * safely. 909 * 910 * Fiber Channel over Ethernet (FCoE) offload functions. 911 * int (*ndo_fcoe_enable)(struct net_device *dev); 912 * Called when the FCoE protocol stack wants to start using LLD for FCoE 913 * so the underlying device can perform whatever needed configuration or 914 * initialization to support acceleration of FCoE traffic. 915 * 916 * int (*ndo_fcoe_disable)(struct net_device *dev); 917 * Called when the FCoE protocol stack wants to stop using LLD for FCoE 918 * so the underlying device can perform whatever needed clean-ups to 919 * stop supporting acceleration of FCoE traffic. 920 * 921 * int (*ndo_fcoe_ddp_setup)(struct net_device *dev, u16 xid, 922 * struct scatterlist *sgl, unsigned int sgc); 923 * Called when the FCoE Initiator wants to initialize an I/O that 924 * is a possible candidate for Direct Data Placement (DDP). The LLD can 925 * perform necessary setup and returns 1 to indicate the device is set up 926 * successfully to perform DDP on this I/O, otherwise this returns 0. 927 * 928 * int (*ndo_fcoe_ddp_done)(struct net_device *dev, u16 xid); 929 * Called when the FCoE Initiator/Target is done with the DDPed I/O as 930 * indicated by the FC exchange id 'xid', so the underlying device can 931 * clean up and reuse resources for later DDP requests. 932 * 933 * int (*ndo_fcoe_ddp_target)(struct net_device *dev, u16 xid, 934 * struct scatterlist *sgl, unsigned int sgc); 935 * Called when the FCoE Target wants to initialize an I/O that 936 * is a possible candidate for Direct Data Placement (DDP). The LLD can 937 * perform necessary setup and returns 1 to indicate the device is set up 938 * successfully to perform DDP on this I/O, otherwise this returns 0. 939 * 940 * int (*ndo_fcoe_get_hbainfo)(struct net_device *dev, 941 * struct netdev_fcoe_hbainfo *hbainfo); 942 * Called when the FCoE Protocol stack wants information on the underlying 943 * device. This information is utilized by the FCoE protocol stack to 944 * register attributes with Fiber Channel management service as per the 945 * FC-GS Fabric Device Management Information(FDMI) specification. 946 * 947 * int (*ndo_fcoe_get_wwn)(struct net_device *dev, u64 *wwn, int type); 948 * Called when the underlying device wants to override default World Wide 949 * Name (WWN) generation mechanism in FCoE protocol stack to pass its own 950 * World Wide Port Name (WWPN) or World Wide Node Name (WWNN) to the FCoE 951 * protocol stack to use. 952 * 953 * RFS acceleration. 954 * int (*ndo_rx_flow_steer)(struct net_device *dev, const struct sk_buff *skb, 955 * u16 rxq_index, u32 flow_id); 956 * Set hardware filter for RFS. rxq_index is the target queue index; 957 * flow_id is a flow ID to be passed to rps_may_expire_flow() later. 958 * Return the filter ID on success, or a negative error code. 959 * 960 * Slave management functions (for bridge, bonding, etc). 961 * int (*ndo_add_slave)(struct net_device *dev, struct net_device *slave_dev); 962 * Called to make another netdev an underling. 963 * 964 * int (*ndo_del_slave)(struct net_device *dev, struct net_device *slave_dev); 965 * Called to release previously enslaved netdev. 966 * 967 * Feature/offload setting functions. 968 * int (*ndo_set_features)(struct net_device *dev, netdev_features_t features); 969 * Called to update device configuration to new features. Passed 970 * feature set might be less than what was returned by ndo_fix_features()). 971 * Must return >0 or -errno if it changed dev->features itself. 972 * 973 * int (*ndo_fdb_add)(struct ndmsg *ndm, struct nlattr *tb[], 974 * struct net_device *dev, 975 * const unsigned char *addr, u16 vid, u16 flags) 976 * Adds an FDB entry to dev for addr. 977 * int (*ndo_fdb_del)(struct ndmsg *ndm, struct nlattr *tb[], 978 * struct net_device *dev, 979 * const unsigned char *addr, u16 vid) 980 * Deletes the FDB entry from dev coresponding to addr. 981 * int (*ndo_fdb_dump)(struct sk_buff *skb, struct netlink_callback *cb, 982 * struct net_device *dev, struct net_device *filter_dev, 983 * int idx) 984 * Used to add FDB entries to dump requests. Implementers should add 985 * entries to skb and update idx with the number of entries. 986 * 987 * int (*ndo_bridge_setlink)(struct net_device *dev, struct nlmsghdr *nlh, 988 * u16 flags) 989 * int (*ndo_bridge_getlink)(struct sk_buff *skb, u32 pid, u32 seq, 990 * struct net_device *dev, u32 filter_mask, 991 * int nlflags) 992 * int (*ndo_bridge_dellink)(struct net_device *dev, struct nlmsghdr *nlh, 993 * u16 flags); 994 * 995 * int (*ndo_change_carrier)(struct net_device *dev, bool new_carrier); 996 * Called to change device carrier. Soft-devices (like dummy, team, etc) 997 * which do not represent real hardware may define this to allow their 998 * userspace components to manage their virtual carrier state. Devices 999 * that determine carrier state from physical hardware properties (eg 1000 * network cables) or protocol-dependent mechanisms (eg 1001 * USB_CDC_NOTIFY_NETWORK_CONNECTION) should NOT implement this function. 1002 * 1003 * int (*ndo_get_phys_port_id)(struct net_device *dev, 1004 * struct netdev_phys_item_id *ppid); 1005 * Called to get ID of physical port of this device. If driver does 1006 * not implement this, it is assumed that the hw is not able to have 1007 * multiple net devices on single physical port. 1008 * 1009 * void (*ndo_add_vxlan_port)(struct net_device *dev, 1010 * sa_family_t sa_family, __be16 port); 1011 * Called by vxlan to notiy a driver about the UDP port and socket 1012 * address family that vxlan is listnening to. It is called only when 1013 * a new port starts listening. The operation is protected by the 1014 * vxlan_net->sock_lock. 1015 * 1016 * void (*ndo_add_geneve_port)(struct net_device *dev, 1017 * sa_family_t sa_family, __be16 port); 1018 * Called by geneve to notify a driver about the UDP port and socket 1019 * address family that geneve is listnening to. It is called only when 1020 * a new port starts listening. The operation is protected by the 1021 * geneve_net->sock_lock. 1022 * 1023 * void (*ndo_del_geneve_port)(struct net_device *dev, 1024 * sa_family_t sa_family, __be16 port); 1025 * Called by geneve to notify the driver about a UDP port and socket 1026 * address family that geneve is not listening to anymore. The operation 1027 * is protected by the geneve_net->sock_lock. 1028 * 1029 * void (*ndo_del_vxlan_port)(struct net_device *dev, 1030 * sa_family_t sa_family, __be16 port); 1031 * Called by vxlan to notify the driver about a UDP port and socket 1032 * address family that vxlan is not listening to anymore. The operation 1033 * is protected by the vxlan_net->sock_lock. 1034 * 1035 * void* (*ndo_dfwd_add_station)(struct net_device *pdev, 1036 * struct net_device *dev) 1037 * Called by upper layer devices to accelerate switching or other 1038 * station functionality into hardware. 'pdev is the lowerdev 1039 * to use for the offload and 'dev' is the net device that will 1040 * back the offload. Returns a pointer to the private structure 1041 * the upper layer will maintain. 1042 * void (*ndo_dfwd_del_station)(struct net_device *pdev, void *priv) 1043 * Called by upper layer device to delete the station created 1044 * by 'ndo_dfwd_add_station'. 'pdev' is the net device backing 1045 * the station and priv is the structure returned by the add 1046 * operation. 1047 * netdev_tx_t (*ndo_dfwd_start_xmit)(struct sk_buff *skb, 1048 * struct net_device *dev, 1049 * void *priv); 1050 * Callback to use for xmit over the accelerated station. This 1051 * is used in place of ndo_start_xmit on accelerated net 1052 * devices. 1053 * netdev_features_t (*ndo_features_check) (struct sk_buff *skb, 1054 * struct net_device *dev 1055 * netdev_features_t features); 1056 * Called by core transmit path to determine if device is capable of 1057 * performing offload operations on a given packet. This is to give 1058 * the device an opportunity to implement any restrictions that cannot 1059 * be otherwise expressed by feature flags. The check is called with 1060 * the set of features that the stack has calculated and it returns 1061 * those the driver believes to be appropriate. 1062 * int (*ndo_set_tx_maxrate)(struct net_device *dev, 1063 * int queue_index, u32 maxrate); 1064 * Called when a user wants to set a max-rate limitation of specific 1065 * TX queue. 1066 * int (*ndo_get_iflink)(const struct net_device *dev); 1067 * Called to get the iflink value of this device. 1068 * void (*ndo_change_proto_down)(struct net_device *dev, 1069 * bool proto_down); 1070 * This function is used to pass protocol port error state information 1071 * to the switch driver. The switch driver can react to the proto_down 1072 * by doing a phys down on the associated switch port. 1073 * int (*ndo_fill_metadata_dst)(struct net_device *dev, struct sk_buff *skb); 1074 * This function is used to get egress tunnel information for given skb. 1075 * This is useful for retrieving outer tunnel header parameters while 1076 * sampling packet. 1077 * 1078 */ 1079 struct net_device_ops { 1080 int (*ndo_init)(struct net_device *dev); 1081 void (*ndo_uninit)(struct net_device *dev); 1082 int (*ndo_open)(struct net_device *dev); 1083 int (*ndo_stop)(struct net_device *dev); 1084 netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, 1085 struct net_device *dev); 1086 netdev_features_t (*ndo_features_check)(struct sk_buff *skb, 1087 struct net_device *dev, 1088 netdev_features_t features); 1089 u16 (*ndo_select_queue)(struct net_device *dev, 1090 struct sk_buff *skb, 1091 void *accel_priv, 1092 select_queue_fallback_t fallback); 1093 void (*ndo_change_rx_flags)(struct net_device *dev, 1094 int flags); 1095 void (*ndo_set_rx_mode)(struct net_device *dev); 1096 int (*ndo_set_mac_address)(struct net_device *dev, 1097 void *addr); 1098 int (*ndo_validate_addr)(struct net_device *dev); 1099 int (*ndo_do_ioctl)(struct net_device *dev, 1100 struct ifreq *ifr, int cmd); 1101 int (*ndo_set_config)(struct net_device *dev, 1102 struct ifmap *map); 1103 int (*ndo_change_mtu)(struct net_device *dev, 1104 int new_mtu); 1105 int (*ndo_neigh_setup)(struct net_device *dev, 1106 struct neigh_parms *); 1107 void (*ndo_tx_timeout) (struct net_device *dev); 1108 1109 struct rtnl_link_stats64* (*ndo_get_stats64)(struct net_device *dev, 1110 struct rtnl_link_stats64 *storage); 1111 struct net_device_stats* (*ndo_get_stats)(struct net_device *dev); 1112 1113 int (*ndo_vlan_rx_add_vid)(struct net_device *dev, 1114 __be16 proto, u16 vid); 1115 int (*ndo_vlan_rx_kill_vid)(struct net_device *dev, 1116 __be16 proto, u16 vid); 1117 #ifdef CONFIG_NET_POLL_CONTROLLER 1118 void (*ndo_poll_controller)(struct net_device *dev); 1119 int (*ndo_netpoll_setup)(struct net_device *dev, 1120 struct netpoll_info *info); 1121 void (*ndo_netpoll_cleanup)(struct net_device *dev); 1122 #endif 1123 #ifdef CONFIG_NET_RX_BUSY_POLL 1124 int (*ndo_busy_poll)(struct napi_struct *dev); 1125 #endif 1126 int (*ndo_set_vf_mac)(struct net_device *dev, 1127 int queue, u8 *mac); 1128 int (*ndo_set_vf_vlan)(struct net_device *dev, 1129 int queue, u16 vlan, u8 qos); 1130 int (*ndo_set_vf_rate)(struct net_device *dev, 1131 int vf, int min_tx_rate, 1132 int max_tx_rate); 1133 int (*ndo_set_vf_spoofchk)(struct net_device *dev, 1134 int vf, bool setting); 1135 int (*ndo_set_vf_trust)(struct net_device *dev, 1136 int vf, bool setting); 1137 int (*ndo_get_vf_config)(struct net_device *dev, 1138 int vf, 1139 struct ifla_vf_info *ivf); 1140 int (*ndo_set_vf_link_state)(struct net_device *dev, 1141 int vf, int link_state); 1142 int (*ndo_get_vf_stats)(struct net_device *dev, 1143 int vf, 1144 struct ifla_vf_stats 1145 *vf_stats); 1146 int (*ndo_set_vf_port)(struct net_device *dev, 1147 int vf, 1148 struct nlattr *port[]); 1149 int (*ndo_get_vf_port)(struct net_device *dev, 1150 int vf, struct sk_buff *skb); 1151 int (*ndo_set_vf_rss_query_en)( 1152 struct net_device *dev, 1153 int vf, bool setting); 1154 int (*ndo_setup_tc)(struct net_device *dev, u8 tc); 1155 #if IS_ENABLED(CONFIG_FCOE) 1156 int (*ndo_fcoe_enable)(struct net_device *dev); 1157 int (*ndo_fcoe_disable)(struct net_device *dev); 1158 int (*ndo_fcoe_ddp_setup)(struct net_device *dev, 1159 u16 xid, 1160 struct scatterlist *sgl, 1161 unsigned int sgc); 1162 int (*ndo_fcoe_ddp_done)(struct net_device *dev, 1163 u16 xid); 1164 int (*ndo_fcoe_ddp_target)(struct net_device *dev, 1165 u16 xid, 1166 struct scatterlist *sgl, 1167 unsigned int sgc); 1168 int (*ndo_fcoe_get_hbainfo)(struct net_device *dev, 1169 struct netdev_fcoe_hbainfo *hbainfo); 1170 #endif 1171 1172 #if IS_ENABLED(CONFIG_LIBFCOE) 1173 #define NETDEV_FCOE_WWNN 0 1174 #define NETDEV_FCOE_WWPN 1 1175 int (*ndo_fcoe_get_wwn)(struct net_device *dev, 1176 u64 *wwn, int type); 1177 #endif 1178 1179 #ifdef CONFIG_RFS_ACCEL 1180 int (*ndo_rx_flow_steer)(struct net_device *dev, 1181 const struct sk_buff *skb, 1182 u16 rxq_index, 1183 u32 flow_id); 1184 #endif 1185 int (*ndo_add_slave)(struct net_device *dev, 1186 struct net_device *slave_dev); 1187 int (*ndo_del_slave)(struct net_device *dev, 1188 struct net_device *slave_dev); 1189 netdev_features_t (*ndo_fix_features)(struct net_device *dev, 1190 netdev_features_t features); 1191 int (*ndo_set_features)(struct net_device *dev, 1192 netdev_features_t features); 1193 int (*ndo_neigh_construct)(struct neighbour *n); 1194 void (*ndo_neigh_destroy)(struct neighbour *n); 1195 1196 int (*ndo_fdb_add)(struct ndmsg *ndm, 1197 struct nlattr *tb[], 1198 struct net_device *dev, 1199 const unsigned char *addr, 1200 u16 vid, 1201 u16 flags); 1202 int (*ndo_fdb_del)(struct ndmsg *ndm, 1203 struct nlattr *tb[], 1204 struct net_device *dev, 1205 const unsigned char *addr, 1206 u16 vid); 1207 int (*ndo_fdb_dump)(struct sk_buff *skb, 1208 struct netlink_callback *cb, 1209 struct net_device *dev, 1210 struct net_device *filter_dev, 1211 int idx); 1212 1213 int (*ndo_bridge_setlink)(struct net_device *dev, 1214 struct nlmsghdr *nlh, 1215 u16 flags); 1216 int (*ndo_bridge_getlink)(struct sk_buff *skb, 1217 u32 pid, u32 seq, 1218 struct net_device *dev, 1219 u32 filter_mask, 1220 int nlflags); 1221 int (*ndo_bridge_dellink)(struct net_device *dev, 1222 struct nlmsghdr *nlh, 1223 u16 flags); 1224 int (*ndo_change_carrier)(struct net_device *dev, 1225 bool new_carrier); 1226 int (*ndo_get_phys_port_id)(struct net_device *dev, 1227 struct netdev_phys_item_id *ppid); 1228 int (*ndo_get_phys_port_name)(struct net_device *dev, 1229 char *name, size_t len); 1230 void (*ndo_add_vxlan_port)(struct net_device *dev, 1231 sa_family_t sa_family, 1232 __be16 port); 1233 void (*ndo_del_vxlan_port)(struct net_device *dev, 1234 sa_family_t sa_family, 1235 __be16 port); 1236 void (*ndo_add_geneve_port)(struct net_device *dev, 1237 sa_family_t sa_family, 1238 __be16 port); 1239 void (*ndo_del_geneve_port)(struct net_device *dev, 1240 sa_family_t sa_family, 1241 __be16 port); 1242 void* (*ndo_dfwd_add_station)(struct net_device *pdev, 1243 struct net_device *dev); 1244 void (*ndo_dfwd_del_station)(struct net_device *pdev, 1245 void *priv); 1246 1247 netdev_tx_t (*ndo_dfwd_start_xmit) (struct sk_buff *skb, 1248 struct net_device *dev, 1249 void *priv); 1250 int (*ndo_get_lock_subclass)(struct net_device *dev); 1251 int (*ndo_set_tx_maxrate)(struct net_device *dev, 1252 int queue_index, 1253 u32 maxrate); 1254 int (*ndo_get_iflink)(const struct net_device *dev); 1255 int (*ndo_change_proto_down)(struct net_device *dev, 1256 bool proto_down); 1257 int (*ndo_fill_metadata_dst)(struct net_device *dev, 1258 struct sk_buff *skb); 1259 }; 1260 1261 /** 1262 * enum net_device_priv_flags - &struct net_device priv_flags 1263 * 1264 * These are the &struct net_device, they are only set internally 1265 * by drivers and used in the kernel. These flags are invisible to 1266 * userspace, this means that the order of these flags can change 1267 * during any kernel release. 1268 * 1269 * You should have a pretty good reason to be extending these flags. 1270 * 1271 * @IFF_802_1Q_VLAN: 802.1Q VLAN device 1272 * @IFF_EBRIDGE: Ethernet bridging device 1273 * @IFF_BONDING: bonding master or slave 1274 * @IFF_ISATAP: ISATAP interface (RFC4214) 1275 * @IFF_WAN_HDLC: WAN HDLC device 1276 * @IFF_XMIT_DST_RELEASE: dev_hard_start_xmit() is allowed to 1277 * release skb->dst 1278 * @IFF_DONT_BRIDGE: disallow bridging this ether dev 1279 * @IFF_DISABLE_NETPOLL: disable netpoll at run-time 1280 * @IFF_MACVLAN_PORT: device used as macvlan port 1281 * @IFF_BRIDGE_PORT: device used as bridge port 1282 * @IFF_OVS_DATAPATH: device used as Open vSwitch datapath port 1283 * @IFF_TX_SKB_SHARING: The interface supports sharing skbs on transmit 1284 * @IFF_UNICAST_FLT: Supports unicast filtering 1285 * @IFF_TEAM_PORT: device used as team port 1286 * @IFF_SUPP_NOFCS: device supports sending custom FCS 1287 * @IFF_LIVE_ADDR_CHANGE: device supports hardware address 1288 * change when it's running 1289 * @IFF_MACVLAN: Macvlan device 1290 * @IFF_L3MDEV_MASTER: device is an L3 master device 1291 * @IFF_NO_QUEUE: device can run without qdisc attached 1292 * @IFF_OPENVSWITCH: device is a Open vSwitch master 1293 * @IFF_L3MDEV_SLAVE: device is enslaved to an L3 master device 1294 * @IFF_TEAM: device is a team device 1295 */ 1296 enum netdev_priv_flags { 1297 IFF_802_1Q_VLAN = 1<<0, 1298 IFF_EBRIDGE = 1<<1, 1299 IFF_BONDING = 1<<2, 1300 IFF_ISATAP = 1<<3, 1301 IFF_WAN_HDLC = 1<<4, 1302 IFF_XMIT_DST_RELEASE = 1<<5, 1303 IFF_DONT_BRIDGE = 1<<6, 1304 IFF_DISABLE_NETPOLL = 1<<7, 1305 IFF_MACVLAN_PORT = 1<<8, 1306 IFF_BRIDGE_PORT = 1<<9, 1307 IFF_OVS_DATAPATH = 1<<10, 1308 IFF_TX_SKB_SHARING = 1<<11, 1309 IFF_UNICAST_FLT = 1<<12, 1310 IFF_TEAM_PORT = 1<<13, 1311 IFF_SUPP_NOFCS = 1<<14, 1312 IFF_LIVE_ADDR_CHANGE = 1<<15, 1313 IFF_MACVLAN = 1<<16, 1314 IFF_XMIT_DST_RELEASE_PERM = 1<<17, 1315 IFF_IPVLAN_MASTER = 1<<18, 1316 IFF_IPVLAN_SLAVE = 1<<19, 1317 IFF_L3MDEV_MASTER = 1<<20, 1318 IFF_NO_QUEUE = 1<<21, 1319 IFF_OPENVSWITCH = 1<<22, 1320 IFF_L3MDEV_SLAVE = 1<<23, 1321 IFF_TEAM = 1<<24, 1322 }; 1323 1324 #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN 1325 #define IFF_EBRIDGE IFF_EBRIDGE 1326 #define IFF_BONDING IFF_BONDING 1327 #define IFF_ISATAP IFF_ISATAP 1328 #define IFF_WAN_HDLC IFF_WAN_HDLC 1329 #define IFF_XMIT_DST_RELEASE IFF_XMIT_DST_RELEASE 1330 #define IFF_DONT_BRIDGE IFF_DONT_BRIDGE 1331 #define IFF_DISABLE_NETPOLL IFF_DISABLE_NETPOLL 1332 #define IFF_MACVLAN_PORT IFF_MACVLAN_PORT 1333 #define IFF_BRIDGE_PORT IFF_BRIDGE_PORT 1334 #define IFF_OVS_DATAPATH IFF_OVS_DATAPATH 1335 #define IFF_TX_SKB_SHARING IFF_TX_SKB_SHARING 1336 #define IFF_UNICAST_FLT IFF_UNICAST_FLT 1337 #define IFF_TEAM_PORT IFF_TEAM_PORT 1338 #define IFF_SUPP_NOFCS IFF_SUPP_NOFCS 1339 #define IFF_LIVE_ADDR_CHANGE IFF_LIVE_ADDR_CHANGE 1340 #define IFF_MACVLAN IFF_MACVLAN 1341 #define IFF_XMIT_DST_RELEASE_PERM IFF_XMIT_DST_RELEASE_PERM 1342 #define IFF_IPVLAN_MASTER IFF_IPVLAN_MASTER 1343 #define IFF_IPVLAN_SLAVE IFF_IPVLAN_SLAVE 1344 #define IFF_L3MDEV_MASTER IFF_L3MDEV_MASTER 1345 #define IFF_NO_QUEUE IFF_NO_QUEUE 1346 #define IFF_OPENVSWITCH IFF_OPENVSWITCH 1347 #define IFF_L3MDEV_SLAVE IFF_L3MDEV_SLAVE 1348 #define IFF_TEAM IFF_TEAM 1349 1350 /** 1351 * struct net_device - The DEVICE structure. 1352 * Actually, this whole structure is a big mistake. It mixes I/O 1353 * data with strictly "high-level" data, and it has to know about 1354 * almost every data structure used in the INET module. 1355 * 1356 * @name: This is the first field of the "visible" part of this structure 1357 * (i.e. as seen by users in the "Space.c" file). It is the name 1358 * of the interface. 1359 * 1360 * @name_hlist: Device name hash chain, please keep it close to name[] 1361 * @ifalias: SNMP alias 1362 * @mem_end: Shared memory end 1363 * @mem_start: Shared memory start 1364 * @base_addr: Device I/O address 1365 * @irq: Device IRQ number 1366 * 1367 * @carrier_changes: Stats to monitor carrier on<->off transitions 1368 * 1369 * @state: Generic network queuing layer state, see netdev_state_t 1370 * @dev_list: The global list of network devices 1371 * @napi_list: List entry, that is used for polling napi devices 1372 * @unreg_list: List entry, that is used, when we are unregistering the 1373 * device, see the function unregister_netdev 1374 * @close_list: List entry, that is used, when we are closing the device 1375 * 1376 * @adj_list: Directly linked devices, like slaves for bonding 1377 * @all_adj_list: All linked devices, *including* neighbours 1378 * @features: Currently active device features 1379 * @hw_features: User-changeable features 1380 * 1381 * @wanted_features: User-requested features 1382 * @vlan_features: Mask of features inheritable by VLAN devices 1383 * 1384 * @hw_enc_features: Mask of features inherited by encapsulating devices 1385 * This field indicates what encapsulation 1386 * offloads the hardware is capable of doing, 1387 * and drivers will need to set them appropriately. 1388 * 1389 * @mpls_features: Mask of features inheritable by MPLS 1390 * 1391 * @ifindex: interface index 1392 * @group: The group, that the device belongs to 1393 * 1394 * @stats: Statistics struct, which was left as a legacy, use 1395 * rtnl_link_stats64 instead 1396 * 1397 * @rx_dropped: Dropped packets by core network, 1398 * do not use this in drivers 1399 * @tx_dropped: Dropped packets by core network, 1400 * do not use this in drivers 1401 * 1402 * @wireless_handlers: List of functions to handle Wireless Extensions, 1403 * instead of ioctl, 1404 * see <net/iw_handler.h> for details. 1405 * @wireless_data: Instance data managed by the core of wireless extensions 1406 * 1407 * @netdev_ops: Includes several pointers to callbacks, 1408 * if one wants to override the ndo_*() functions 1409 * @ethtool_ops: Management operations 1410 * @header_ops: Includes callbacks for creating,parsing,caching,etc 1411 * of Layer 2 headers. 1412 * 1413 * @flags: Interface flags (a la BSD) 1414 * @priv_flags: Like 'flags' but invisible to userspace, 1415 * see if.h for the definitions 1416 * @gflags: Global flags ( kept as legacy ) 1417 * @padded: How much padding added by alloc_netdev() 1418 * @operstate: RFC2863 operstate 1419 * @link_mode: Mapping policy to operstate 1420 * @if_port: Selectable AUI, TP, ... 1421 * @dma: DMA channel 1422 * @mtu: Interface MTU value 1423 * @type: Interface hardware type 1424 * @hard_header_len: Hardware header length, which means that this is the 1425 * minimum size of a packet. 1426 * 1427 * @needed_headroom: Extra headroom the hardware may need, but not in all 1428 * cases can this be guaranteed 1429 * @needed_tailroom: Extra tailroom the hardware may need, but not in all 1430 * cases can this be guaranteed. Some cases also use 1431 * LL_MAX_HEADER instead to allocate the skb 1432 * 1433 * interface address info: 1434 * 1435 * @perm_addr: Permanent hw address 1436 * @addr_assign_type: Hw address assignment type 1437 * @addr_len: Hardware address length 1438 * @neigh_priv_len; Used in neigh_alloc(), 1439 * initialized only in atm/clip.c 1440 * @dev_id: Used to differentiate devices that share 1441 * the same link layer address 1442 * @dev_port: Used to differentiate devices that share 1443 * the same function 1444 * @addr_list_lock: XXX: need comments on this one 1445 * @uc_promisc: Counter, that indicates, that promiscuous mode 1446 * has been enabled due to the need to listen to 1447 * additional unicast addresses in a device that 1448 * does not implement ndo_set_rx_mode() 1449 * @uc: unicast mac addresses 1450 * @mc: multicast mac addresses 1451 * @dev_addrs: list of device hw addresses 1452 * @queues_kset: Group of all Kobjects in the Tx and RX queues 1453 * @promiscuity: Number of times, the NIC is told to work in 1454 * Promiscuous mode, if it becomes 0 the NIC will 1455 * exit from working in Promiscuous mode 1456 * @allmulti: Counter, enables or disables allmulticast mode 1457 * 1458 * @vlan_info: VLAN info 1459 * @dsa_ptr: dsa specific data 1460 * @tipc_ptr: TIPC specific data 1461 * @atalk_ptr: AppleTalk link 1462 * @ip_ptr: IPv4 specific data 1463 * @dn_ptr: DECnet specific data 1464 * @ip6_ptr: IPv6 specific data 1465 * @ax25_ptr: AX.25 specific data 1466 * @ieee80211_ptr: IEEE 802.11 specific data, assign before registering 1467 * 1468 * @last_rx: Time of last Rx 1469 * @dev_addr: Hw address (before bcast, 1470 * because most packets are unicast) 1471 * 1472 * @_rx: Array of RX queues 1473 * @num_rx_queues: Number of RX queues 1474 * allocated at register_netdev() time 1475 * @real_num_rx_queues: Number of RX queues currently active in device 1476 * 1477 * @rx_handler: handler for received packets 1478 * @rx_handler_data: XXX: need comments on this one 1479 * @ingress_queue: XXX: need comments on this one 1480 * @broadcast: hw bcast address 1481 * 1482 * @rx_cpu_rmap: CPU reverse-mapping for RX completion interrupts, 1483 * indexed by RX queue number. Assigned by driver. 1484 * This must only be set if the ndo_rx_flow_steer 1485 * operation is defined 1486 * @index_hlist: Device index hash chain 1487 * 1488 * @_tx: Array of TX queues 1489 * @num_tx_queues: Number of TX queues allocated at alloc_netdev_mq() time 1490 * @real_num_tx_queues: Number of TX queues currently active in device 1491 * @qdisc: Root qdisc from userspace point of view 1492 * @tx_queue_len: Max frames per queue allowed 1493 * @tx_global_lock: XXX: need comments on this one 1494 * 1495 * @xps_maps: XXX: need comments on this one 1496 * 1497 * @offload_fwd_mark: Offload device fwding mark 1498 * 1499 * @trans_start: Time (in jiffies) of last Tx 1500 * @watchdog_timeo: Represents the timeout that is used by 1501 * the watchdog ( see dev_watchdog() ) 1502 * @watchdog_timer: List of timers 1503 * 1504 * @pcpu_refcnt: Number of references to this device 1505 * @todo_list: Delayed register/unregister 1506 * @link_watch_list: XXX: need comments on this one 1507 * 1508 * @reg_state: Register/unregister state machine 1509 * @dismantle: Device is going to be freed 1510 * @rtnl_link_state: This enum represents the phases of creating 1511 * a new link 1512 * 1513 * @destructor: Called from unregister, 1514 * can be used to call free_netdev 1515 * @npinfo: XXX: need comments on this one 1516 * @nd_net: Network namespace this network device is inside 1517 * 1518 * @ml_priv: Mid-layer private 1519 * @lstats: Loopback statistics 1520 * @tstats: Tunnel statistics 1521 * @dstats: Dummy statistics 1522 * @vstats: Virtual ethernet statistics 1523 * 1524 * @garp_port: GARP 1525 * @mrp_port: MRP 1526 * 1527 * @dev: Class/net/name entry 1528 * @sysfs_groups: Space for optional device, statistics and wireless 1529 * sysfs groups 1530 * 1531 * @sysfs_rx_queue_group: Space for optional per-rx queue attributes 1532 * @rtnl_link_ops: Rtnl_link_ops 1533 * 1534 * @gso_max_size: Maximum size of generic segmentation offload 1535 * @gso_max_segs: Maximum number of segments that can be passed to the 1536 * NIC for GSO 1537 * @gso_min_segs: Minimum number of segments that can be passed to the 1538 * NIC for GSO 1539 * 1540 * @dcbnl_ops: Data Center Bridging netlink ops 1541 * @num_tc: Number of traffic classes in the net device 1542 * @tc_to_txq: XXX: need comments on this one 1543 * @prio_tc_map XXX: need comments on this one 1544 * 1545 * @fcoe_ddp_xid: Max exchange id for FCoE LRO by ddp 1546 * 1547 * @priomap: XXX: need comments on this one 1548 * @phydev: Physical device may attach itself 1549 * for hardware timestamping 1550 * 1551 * @qdisc_tx_busylock: XXX: need comments on this one 1552 * 1553 * @proto_down: protocol port state information can be sent to the 1554 * switch driver and used to set the phys state of the 1555 * switch port. 1556 * 1557 * FIXME: cleanup struct net_device such that network protocol info 1558 * moves out. 1559 */ 1560 1561 struct net_device { 1562 char name[IFNAMSIZ]; 1563 struct hlist_node name_hlist; 1564 char *ifalias; 1565 /* 1566 * I/O specific fields 1567 * FIXME: Merge these and struct ifmap into one 1568 */ 1569 unsigned long mem_end; 1570 unsigned long mem_start; 1571 unsigned long base_addr; 1572 int irq; 1573 1574 atomic_t carrier_changes; 1575 1576 /* 1577 * Some hardware also needs these fields (state,dev_list, 1578 * napi_list,unreg_list,close_list) but they are not 1579 * part of the usual set specified in Space.c. 1580 */ 1581 1582 unsigned long state; 1583 1584 struct list_head dev_list; 1585 struct list_head napi_list; 1586 struct list_head unreg_list; 1587 struct list_head close_list; 1588 struct list_head ptype_all; 1589 struct list_head ptype_specific; 1590 1591 struct { 1592 struct list_head upper; 1593 struct list_head lower; 1594 } adj_list; 1595 1596 struct { 1597 struct list_head upper; 1598 struct list_head lower; 1599 } all_adj_list; 1600 1601 netdev_features_t features; 1602 netdev_features_t hw_features; 1603 netdev_features_t wanted_features; 1604 netdev_features_t vlan_features; 1605 netdev_features_t hw_enc_features; 1606 netdev_features_t mpls_features; 1607 1608 int ifindex; 1609 int group; 1610 1611 struct net_device_stats stats; 1612 1613 atomic_long_t rx_dropped; 1614 atomic_long_t tx_dropped; 1615 1616 #ifdef CONFIG_WIRELESS_EXT 1617 const struct iw_handler_def * wireless_handlers; 1618 struct iw_public_data * wireless_data; 1619 #endif 1620 const struct net_device_ops *netdev_ops; 1621 const struct ethtool_ops *ethtool_ops; 1622 #ifdef CONFIG_NET_SWITCHDEV 1623 const struct switchdev_ops *switchdev_ops; 1624 #endif 1625 #ifdef CONFIG_NET_L3_MASTER_DEV 1626 const struct l3mdev_ops *l3mdev_ops; 1627 #endif 1628 1629 const struct header_ops *header_ops; 1630 1631 unsigned int flags; 1632 unsigned int priv_flags; 1633 1634 unsigned short gflags; 1635 unsigned short padded; 1636 1637 unsigned char operstate; 1638 unsigned char link_mode; 1639 1640 unsigned char if_port; 1641 unsigned char dma; 1642 1643 unsigned int mtu; 1644 unsigned short type; 1645 unsigned short hard_header_len; 1646 1647 unsigned short needed_headroom; 1648 unsigned short needed_tailroom; 1649 1650 /* Interface address info. */ 1651 unsigned char perm_addr[MAX_ADDR_LEN]; 1652 unsigned char addr_assign_type; 1653 unsigned char addr_len; 1654 unsigned short neigh_priv_len; 1655 unsigned short dev_id; 1656 unsigned short dev_port; 1657 spinlock_t addr_list_lock; 1658 unsigned char name_assign_type; 1659 bool uc_promisc; 1660 struct netdev_hw_addr_list uc; 1661 struct netdev_hw_addr_list mc; 1662 struct netdev_hw_addr_list dev_addrs; 1663 1664 #ifdef CONFIG_SYSFS 1665 struct kset *queues_kset; 1666 #endif 1667 unsigned int promiscuity; 1668 unsigned int allmulti; 1669 1670 1671 /* Protocol specific pointers */ 1672 1673 #if IS_ENABLED(CONFIG_VLAN_8021Q) 1674 struct vlan_info __rcu *vlan_info; 1675 #endif 1676 #if IS_ENABLED(CONFIG_NET_DSA) 1677 struct dsa_switch_tree *dsa_ptr; 1678 #endif 1679 #if IS_ENABLED(CONFIG_TIPC) 1680 struct tipc_bearer __rcu *tipc_ptr; 1681 #endif 1682 void *atalk_ptr; 1683 struct in_device __rcu *ip_ptr; 1684 struct dn_dev __rcu *dn_ptr; 1685 struct inet6_dev __rcu *ip6_ptr; 1686 void *ax25_ptr; 1687 struct wireless_dev *ieee80211_ptr; 1688 struct wpan_dev *ieee802154_ptr; 1689 #if IS_ENABLED(CONFIG_MPLS_ROUTING) 1690 struct mpls_dev __rcu *mpls_ptr; 1691 #endif 1692 1693 /* 1694 * Cache lines mostly used on receive path (including eth_type_trans()) 1695 */ 1696 unsigned long last_rx; 1697 1698 /* Interface address info used in eth_type_trans() */ 1699 unsigned char *dev_addr; 1700 1701 1702 #ifdef CONFIG_SYSFS 1703 struct netdev_rx_queue *_rx; 1704 1705 unsigned int num_rx_queues; 1706 unsigned int real_num_rx_queues; 1707 1708 #endif 1709 1710 unsigned long gro_flush_timeout; 1711 rx_handler_func_t __rcu *rx_handler; 1712 void __rcu *rx_handler_data; 1713 1714 #ifdef CONFIG_NET_CLS_ACT 1715 struct tcf_proto __rcu *ingress_cl_list; 1716 #endif 1717 struct netdev_queue __rcu *ingress_queue; 1718 #ifdef CONFIG_NETFILTER_INGRESS 1719 struct list_head nf_hooks_ingress; 1720 #endif 1721 1722 unsigned char broadcast[MAX_ADDR_LEN]; 1723 #ifdef CONFIG_RFS_ACCEL 1724 struct cpu_rmap *rx_cpu_rmap; 1725 #endif 1726 struct hlist_node index_hlist; 1727 1728 /* 1729 * Cache lines mostly used on transmit path 1730 */ 1731 struct netdev_queue *_tx ____cacheline_aligned_in_smp; 1732 unsigned int num_tx_queues; 1733 unsigned int real_num_tx_queues; 1734 struct Qdisc *qdisc; 1735 unsigned long tx_queue_len; 1736 spinlock_t tx_global_lock; 1737 int watchdog_timeo; 1738 1739 #ifdef CONFIG_XPS 1740 struct xps_dev_maps __rcu *xps_maps; 1741 #endif 1742 #ifdef CONFIG_NET_CLS_ACT 1743 struct tcf_proto __rcu *egress_cl_list; 1744 #endif 1745 #ifdef CONFIG_NET_SWITCHDEV 1746 u32 offload_fwd_mark; 1747 #endif 1748 1749 /* These may be needed for future network-power-down code. */ 1750 1751 /* 1752 * trans_start here is expensive for high speed devices on SMP, 1753 * please use netdev_queue->trans_start instead. 1754 */ 1755 unsigned long trans_start; 1756 1757 struct timer_list watchdog_timer; 1758 1759 int __percpu *pcpu_refcnt; 1760 struct list_head todo_list; 1761 1762 struct list_head link_watch_list; 1763 1764 enum { NETREG_UNINITIALIZED=0, 1765 NETREG_REGISTERED, /* completed register_netdevice */ 1766 NETREG_UNREGISTERING, /* called unregister_netdevice */ 1767 NETREG_UNREGISTERED, /* completed unregister todo */ 1768 NETREG_RELEASED, /* called free_netdev */ 1769 NETREG_DUMMY, /* dummy device for NAPI poll */ 1770 } reg_state:8; 1771 1772 bool dismantle; 1773 1774 enum { 1775 RTNL_LINK_INITIALIZED, 1776 RTNL_LINK_INITIALIZING, 1777 } rtnl_link_state:16; 1778 1779 void (*destructor)(struct net_device *dev); 1780 1781 #ifdef CONFIG_NETPOLL 1782 struct netpoll_info __rcu *npinfo; 1783 #endif 1784 1785 possible_net_t nd_net; 1786 1787 /* mid-layer private */ 1788 union { 1789 void *ml_priv; 1790 struct pcpu_lstats __percpu *lstats; 1791 struct pcpu_sw_netstats __percpu *tstats; 1792 struct pcpu_dstats __percpu *dstats; 1793 struct pcpu_vstats __percpu *vstats; 1794 }; 1795 1796 struct garp_port __rcu *garp_port; 1797 struct mrp_port __rcu *mrp_port; 1798 1799 struct device dev; 1800 const struct attribute_group *sysfs_groups[4]; 1801 const struct attribute_group *sysfs_rx_queue_group; 1802 1803 const struct rtnl_link_ops *rtnl_link_ops; 1804 1805 /* for setting kernel sock attribute on TCP connection setup */ 1806 #define GSO_MAX_SIZE 65536 1807 unsigned int gso_max_size; 1808 #define GSO_MAX_SEGS 65535 1809 u16 gso_max_segs; 1810 u16 gso_min_segs; 1811 #ifdef CONFIG_DCB 1812 const struct dcbnl_rtnl_ops *dcbnl_ops; 1813 #endif 1814 u8 num_tc; 1815 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 1816 u8 prio_tc_map[TC_BITMASK + 1]; 1817 1818 #if IS_ENABLED(CONFIG_FCOE) 1819 unsigned int fcoe_ddp_xid; 1820 #endif 1821 #if IS_ENABLED(CONFIG_CGROUP_NET_PRIO) 1822 struct netprio_map __rcu *priomap; 1823 #endif 1824 struct phy_device *phydev; 1825 struct lock_class_key *qdisc_tx_busylock; 1826 bool proto_down; 1827 }; 1828 #define to_net_dev(d) container_of(d, struct net_device, dev) 1829 1830 #define NETDEV_ALIGN 32 1831 1832 static inline 1833 int netdev_get_prio_tc_map(const struct net_device *dev, u32 prio) 1834 { 1835 return dev->prio_tc_map[prio & TC_BITMASK]; 1836 } 1837 1838 static inline 1839 int netdev_set_prio_tc_map(struct net_device *dev, u8 prio, u8 tc) 1840 { 1841 if (tc >= dev->num_tc) 1842 return -EINVAL; 1843 1844 dev->prio_tc_map[prio & TC_BITMASK] = tc & TC_BITMASK; 1845 return 0; 1846 } 1847 1848 static inline 1849 void netdev_reset_tc(struct net_device *dev) 1850 { 1851 dev->num_tc = 0; 1852 memset(dev->tc_to_txq, 0, sizeof(dev->tc_to_txq)); 1853 memset(dev->prio_tc_map, 0, sizeof(dev->prio_tc_map)); 1854 } 1855 1856 static inline 1857 int netdev_set_tc_queue(struct net_device *dev, u8 tc, u16 count, u16 offset) 1858 { 1859 if (tc >= dev->num_tc) 1860 return -EINVAL; 1861 1862 dev->tc_to_txq[tc].count = count; 1863 dev->tc_to_txq[tc].offset = offset; 1864 return 0; 1865 } 1866 1867 static inline 1868 int netdev_set_num_tc(struct net_device *dev, u8 num_tc) 1869 { 1870 if (num_tc > TC_MAX_QUEUE) 1871 return -EINVAL; 1872 1873 dev->num_tc = num_tc; 1874 return 0; 1875 } 1876 1877 static inline 1878 int netdev_get_num_tc(struct net_device *dev) 1879 { 1880 return dev->num_tc; 1881 } 1882 1883 static inline 1884 struct netdev_queue *netdev_get_tx_queue(const struct net_device *dev, 1885 unsigned int index) 1886 { 1887 return &dev->_tx[index]; 1888 } 1889 1890 static inline struct netdev_queue *skb_get_tx_queue(const struct net_device *dev, 1891 const struct sk_buff *skb) 1892 { 1893 return netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 1894 } 1895 1896 static inline void netdev_for_each_tx_queue(struct net_device *dev, 1897 void (*f)(struct net_device *, 1898 struct netdev_queue *, 1899 void *), 1900 void *arg) 1901 { 1902 unsigned int i; 1903 1904 for (i = 0; i < dev->num_tx_queues; i++) 1905 f(dev, &dev->_tx[i], arg); 1906 } 1907 1908 struct netdev_queue *netdev_pick_tx(struct net_device *dev, 1909 struct sk_buff *skb, 1910 void *accel_priv); 1911 1912 /* 1913 * Net namespace inlines 1914 */ 1915 static inline 1916 struct net *dev_net(const struct net_device *dev) 1917 { 1918 return read_pnet(&dev->nd_net); 1919 } 1920 1921 static inline 1922 void dev_net_set(struct net_device *dev, struct net *net) 1923 { 1924 write_pnet(&dev->nd_net, net); 1925 } 1926 1927 static inline bool netdev_uses_dsa(struct net_device *dev) 1928 { 1929 #if IS_ENABLED(CONFIG_NET_DSA) 1930 if (dev->dsa_ptr != NULL) 1931 return dsa_uses_tagged_protocol(dev->dsa_ptr); 1932 #endif 1933 return false; 1934 } 1935 1936 /** 1937 * netdev_priv - access network device private data 1938 * @dev: network device 1939 * 1940 * Get network device private data 1941 */ 1942 static inline void *netdev_priv(const struct net_device *dev) 1943 { 1944 return (char *)dev + ALIGN(sizeof(struct net_device), NETDEV_ALIGN); 1945 } 1946 1947 /* Set the sysfs physical device reference for the network logical device 1948 * if set prior to registration will cause a symlink during initialization. 1949 */ 1950 #define SET_NETDEV_DEV(net, pdev) ((net)->dev.parent = (pdev)) 1951 1952 /* Set the sysfs device type for the network logical device to allow 1953 * fine-grained identification of different network device types. For 1954 * example Ethernet, Wirelss LAN, Bluetooth, WiMAX etc. 1955 */ 1956 #define SET_NETDEV_DEVTYPE(net, devtype) ((net)->dev.type = (devtype)) 1957 1958 /* Default NAPI poll() weight 1959 * Device drivers are strongly advised to not use bigger value 1960 */ 1961 #define NAPI_POLL_WEIGHT 64 1962 1963 /** 1964 * netif_napi_add - initialize a napi context 1965 * @dev: network device 1966 * @napi: napi context 1967 * @poll: polling function 1968 * @weight: default weight 1969 * 1970 * netif_napi_add() must be used to initialize a napi context prior to calling 1971 * *any* of the other napi related functions. 1972 */ 1973 void netif_napi_add(struct net_device *dev, struct napi_struct *napi, 1974 int (*poll)(struct napi_struct *, int), int weight); 1975 1976 /** 1977 * netif_tx_napi_add - initialize a napi context 1978 * @dev: network device 1979 * @napi: napi context 1980 * @poll: polling function 1981 * @weight: default weight 1982 * 1983 * This variant of netif_napi_add() should be used from drivers using NAPI 1984 * to exclusively poll a TX queue. 1985 * This will avoid we add it into napi_hash[], thus polluting this hash table. 1986 */ 1987 static inline void netif_tx_napi_add(struct net_device *dev, 1988 struct napi_struct *napi, 1989 int (*poll)(struct napi_struct *, int), 1990 int weight) 1991 { 1992 set_bit(NAPI_STATE_NO_BUSY_POLL, &napi->state); 1993 netif_napi_add(dev, napi, poll, weight); 1994 } 1995 1996 /** 1997 * netif_napi_del - remove a napi context 1998 * @napi: napi context 1999 * 2000 * netif_napi_del() removes a napi context from the network device napi list 2001 */ 2002 void netif_napi_del(struct napi_struct *napi); 2003 2004 struct napi_gro_cb { 2005 /* Virtual address of skb_shinfo(skb)->frags[0].page + offset. */ 2006 void *frag0; 2007 2008 /* Length of frag0. */ 2009 unsigned int frag0_len; 2010 2011 /* This indicates where we are processing relative to skb->data. */ 2012 int data_offset; 2013 2014 /* This is non-zero if the packet cannot be merged with the new skb. */ 2015 u16 flush; 2016 2017 /* Save the IP ID here and check when we get to the transport layer */ 2018 u16 flush_id; 2019 2020 /* Number of segments aggregated. */ 2021 u16 count; 2022 2023 /* Start offset for remote checksum offload */ 2024 u16 gro_remcsum_start; 2025 2026 /* jiffies when first packet was created/queued */ 2027 unsigned long age; 2028 2029 /* Used in ipv6_gro_receive() and foo-over-udp */ 2030 u16 proto; 2031 2032 /* This is non-zero if the packet may be of the same flow. */ 2033 u8 same_flow:1; 2034 2035 /* Used in udp_gro_receive */ 2036 u8 udp_mark:1; 2037 2038 /* GRO checksum is valid */ 2039 u8 csum_valid:1; 2040 2041 /* Number of checksums via CHECKSUM_UNNECESSARY */ 2042 u8 csum_cnt:3; 2043 2044 /* Free the skb? */ 2045 u8 free:2; 2046 #define NAPI_GRO_FREE 1 2047 #define NAPI_GRO_FREE_STOLEN_HEAD 2 2048 2049 /* Used in foo-over-udp, set in udp[46]_gro_receive */ 2050 u8 is_ipv6:1; 2051 2052 /* 7 bit hole */ 2053 2054 /* used to support CHECKSUM_COMPLETE for tunneling protocols */ 2055 __wsum csum; 2056 2057 /* used in skb_gro_receive() slow path */ 2058 struct sk_buff *last; 2059 }; 2060 2061 #define NAPI_GRO_CB(skb) ((struct napi_gro_cb *)(skb)->cb) 2062 2063 struct packet_type { 2064 __be16 type; /* This is really htons(ether_type). */ 2065 struct net_device *dev; /* NULL is wildcarded here */ 2066 int (*func) (struct sk_buff *, 2067 struct net_device *, 2068 struct packet_type *, 2069 struct net_device *); 2070 bool (*id_match)(struct packet_type *ptype, 2071 struct sock *sk); 2072 void *af_packet_priv; 2073 struct list_head list; 2074 }; 2075 2076 struct offload_callbacks { 2077 struct sk_buff *(*gso_segment)(struct sk_buff *skb, 2078 netdev_features_t features); 2079 struct sk_buff **(*gro_receive)(struct sk_buff **head, 2080 struct sk_buff *skb); 2081 int (*gro_complete)(struct sk_buff *skb, int nhoff); 2082 }; 2083 2084 struct packet_offload { 2085 __be16 type; /* This is really htons(ether_type). */ 2086 u16 priority; 2087 struct offload_callbacks callbacks; 2088 struct list_head list; 2089 }; 2090 2091 struct udp_offload; 2092 2093 struct udp_offload_callbacks { 2094 struct sk_buff **(*gro_receive)(struct sk_buff **head, 2095 struct sk_buff *skb, 2096 struct udp_offload *uoff); 2097 int (*gro_complete)(struct sk_buff *skb, 2098 int nhoff, 2099 struct udp_offload *uoff); 2100 }; 2101 2102 struct udp_offload { 2103 __be16 port; 2104 u8 ipproto; 2105 struct udp_offload_callbacks callbacks; 2106 }; 2107 2108 /* often modified stats are per cpu, other are shared (netdev->stats) */ 2109 struct pcpu_sw_netstats { 2110 u64 rx_packets; 2111 u64 rx_bytes; 2112 u64 tx_packets; 2113 u64 tx_bytes; 2114 struct u64_stats_sync syncp; 2115 }; 2116 2117 #define __netdev_alloc_pcpu_stats(type, gfp) \ 2118 ({ \ 2119 typeof(type) __percpu *pcpu_stats = alloc_percpu_gfp(type, gfp);\ 2120 if (pcpu_stats) { \ 2121 int __cpu; \ 2122 for_each_possible_cpu(__cpu) { \ 2123 typeof(type) *stat; \ 2124 stat = per_cpu_ptr(pcpu_stats, __cpu); \ 2125 u64_stats_init(&stat->syncp); \ 2126 } \ 2127 } \ 2128 pcpu_stats; \ 2129 }) 2130 2131 #define netdev_alloc_pcpu_stats(type) \ 2132 __netdev_alloc_pcpu_stats(type, GFP_KERNEL) 2133 2134 enum netdev_lag_tx_type { 2135 NETDEV_LAG_TX_TYPE_UNKNOWN, 2136 NETDEV_LAG_TX_TYPE_RANDOM, 2137 NETDEV_LAG_TX_TYPE_BROADCAST, 2138 NETDEV_LAG_TX_TYPE_ROUNDROBIN, 2139 NETDEV_LAG_TX_TYPE_ACTIVEBACKUP, 2140 NETDEV_LAG_TX_TYPE_HASH, 2141 }; 2142 2143 struct netdev_lag_upper_info { 2144 enum netdev_lag_tx_type tx_type; 2145 }; 2146 2147 struct netdev_lag_lower_state_info { 2148 u8 link_up : 1, 2149 tx_enabled : 1; 2150 }; 2151 2152 #include <linux/notifier.h> 2153 2154 /* netdevice notifier chain. Please remember to update the rtnetlink 2155 * notification exclusion list in rtnetlink_event() when adding new 2156 * types. 2157 */ 2158 #define NETDEV_UP 0x0001 /* For now you can't veto a device up/down */ 2159 #define NETDEV_DOWN 0x0002 2160 #define NETDEV_REBOOT 0x0003 /* Tell a protocol stack a network interface 2161 detected a hardware crash and restarted 2162 - we can use this eg to kick tcp sessions 2163 once done */ 2164 #define NETDEV_CHANGE 0x0004 /* Notify device state change */ 2165 #define NETDEV_REGISTER 0x0005 2166 #define NETDEV_UNREGISTER 0x0006 2167 #define NETDEV_CHANGEMTU 0x0007 /* notify after mtu change happened */ 2168 #define NETDEV_CHANGEADDR 0x0008 2169 #define NETDEV_GOING_DOWN 0x0009 2170 #define NETDEV_CHANGENAME 0x000A 2171 #define NETDEV_FEAT_CHANGE 0x000B 2172 #define NETDEV_BONDING_FAILOVER 0x000C 2173 #define NETDEV_PRE_UP 0x000D 2174 #define NETDEV_PRE_TYPE_CHANGE 0x000E 2175 #define NETDEV_POST_TYPE_CHANGE 0x000F 2176 #define NETDEV_POST_INIT 0x0010 2177 #define NETDEV_UNREGISTER_FINAL 0x0011 2178 #define NETDEV_RELEASE 0x0012 2179 #define NETDEV_NOTIFY_PEERS 0x0013 2180 #define NETDEV_JOIN 0x0014 2181 #define NETDEV_CHANGEUPPER 0x0015 2182 #define NETDEV_RESEND_IGMP 0x0016 2183 #define NETDEV_PRECHANGEMTU 0x0017 /* notify before mtu change happened */ 2184 #define NETDEV_CHANGEINFODATA 0x0018 2185 #define NETDEV_BONDING_INFO 0x0019 2186 #define NETDEV_PRECHANGEUPPER 0x001A 2187 #define NETDEV_CHANGELOWERSTATE 0x001B 2188 2189 int register_netdevice_notifier(struct notifier_block *nb); 2190 int unregister_netdevice_notifier(struct notifier_block *nb); 2191 2192 struct netdev_notifier_info { 2193 struct net_device *dev; 2194 }; 2195 2196 struct netdev_notifier_change_info { 2197 struct netdev_notifier_info info; /* must be first */ 2198 unsigned int flags_changed; 2199 }; 2200 2201 struct netdev_notifier_changeupper_info { 2202 struct netdev_notifier_info info; /* must be first */ 2203 struct net_device *upper_dev; /* new upper dev */ 2204 bool master; /* is upper dev master */ 2205 bool linking; /* is the nofication for link or unlink */ 2206 void *upper_info; /* upper dev info */ 2207 }; 2208 2209 struct netdev_notifier_changelowerstate_info { 2210 struct netdev_notifier_info info; /* must be first */ 2211 void *lower_state_info; /* is lower dev state */ 2212 }; 2213 2214 static inline void netdev_notifier_info_init(struct netdev_notifier_info *info, 2215 struct net_device *dev) 2216 { 2217 info->dev = dev; 2218 } 2219 2220 static inline struct net_device * 2221 netdev_notifier_info_to_dev(const struct netdev_notifier_info *info) 2222 { 2223 return info->dev; 2224 } 2225 2226 int call_netdevice_notifiers(unsigned long val, struct net_device *dev); 2227 2228 2229 extern rwlock_t dev_base_lock; /* Device list lock */ 2230 2231 #define for_each_netdev(net, d) \ 2232 list_for_each_entry(d, &(net)->dev_base_head, dev_list) 2233 #define for_each_netdev_reverse(net, d) \ 2234 list_for_each_entry_reverse(d, &(net)->dev_base_head, dev_list) 2235 #define for_each_netdev_rcu(net, d) \ 2236 list_for_each_entry_rcu(d, &(net)->dev_base_head, dev_list) 2237 #define for_each_netdev_safe(net, d, n) \ 2238 list_for_each_entry_safe(d, n, &(net)->dev_base_head, dev_list) 2239 #define for_each_netdev_continue(net, d) \ 2240 list_for_each_entry_continue(d, &(net)->dev_base_head, dev_list) 2241 #define for_each_netdev_continue_rcu(net, d) \ 2242 list_for_each_entry_continue_rcu(d, &(net)->dev_base_head, dev_list) 2243 #define for_each_netdev_in_bond_rcu(bond, slave) \ 2244 for_each_netdev_rcu(&init_net, slave) \ 2245 if (netdev_master_upper_dev_get_rcu(slave) == (bond)) 2246 #define net_device_entry(lh) list_entry(lh, struct net_device, dev_list) 2247 2248 static inline struct net_device *next_net_device(struct net_device *dev) 2249 { 2250 struct list_head *lh; 2251 struct net *net; 2252 2253 net = dev_net(dev); 2254 lh = dev->dev_list.next; 2255 return lh == &net->dev_base_head ? NULL : net_device_entry(lh); 2256 } 2257 2258 static inline struct net_device *next_net_device_rcu(struct net_device *dev) 2259 { 2260 struct list_head *lh; 2261 struct net *net; 2262 2263 net = dev_net(dev); 2264 lh = rcu_dereference(list_next_rcu(&dev->dev_list)); 2265 return lh == &net->dev_base_head ? NULL : net_device_entry(lh); 2266 } 2267 2268 static inline struct net_device *first_net_device(struct net *net) 2269 { 2270 return list_empty(&net->dev_base_head) ? NULL : 2271 net_device_entry(net->dev_base_head.next); 2272 } 2273 2274 static inline struct net_device *first_net_device_rcu(struct net *net) 2275 { 2276 struct list_head *lh = rcu_dereference(list_next_rcu(&net->dev_base_head)); 2277 2278 return lh == &net->dev_base_head ? NULL : net_device_entry(lh); 2279 } 2280 2281 int netdev_boot_setup_check(struct net_device *dev); 2282 unsigned long netdev_boot_base(const char *prefix, int unit); 2283 struct net_device *dev_getbyhwaddr_rcu(struct net *net, unsigned short type, 2284 const char *hwaddr); 2285 struct net_device *dev_getfirstbyhwtype(struct net *net, unsigned short type); 2286 struct net_device *__dev_getfirstbyhwtype(struct net *net, unsigned short type); 2287 void dev_add_pack(struct packet_type *pt); 2288 void dev_remove_pack(struct packet_type *pt); 2289 void __dev_remove_pack(struct packet_type *pt); 2290 void dev_add_offload(struct packet_offload *po); 2291 void dev_remove_offload(struct packet_offload *po); 2292 2293 int dev_get_iflink(const struct net_device *dev); 2294 int dev_fill_metadata_dst(struct net_device *dev, struct sk_buff *skb); 2295 struct net_device *__dev_get_by_flags(struct net *net, unsigned short flags, 2296 unsigned short mask); 2297 struct net_device *dev_get_by_name(struct net *net, const char *name); 2298 struct net_device *dev_get_by_name_rcu(struct net *net, const char *name); 2299 struct net_device *__dev_get_by_name(struct net *net, const char *name); 2300 int dev_alloc_name(struct net_device *dev, const char *name); 2301 int dev_open(struct net_device *dev); 2302 int dev_close(struct net_device *dev); 2303 int dev_close_many(struct list_head *head, bool unlink); 2304 void dev_disable_lro(struct net_device *dev); 2305 int dev_loopback_xmit(struct net *net, struct sock *sk, struct sk_buff *newskb); 2306 int dev_queue_xmit(struct sk_buff *skb); 2307 int dev_queue_xmit_accel(struct sk_buff *skb, void *accel_priv); 2308 int register_netdevice(struct net_device *dev); 2309 void unregister_netdevice_queue(struct net_device *dev, struct list_head *head); 2310 void unregister_netdevice_many(struct list_head *head); 2311 static inline void unregister_netdevice(struct net_device *dev) 2312 { 2313 unregister_netdevice_queue(dev, NULL); 2314 } 2315 2316 int netdev_refcnt_read(const struct net_device *dev); 2317 void free_netdev(struct net_device *dev); 2318 void netdev_freemem(struct net_device *dev); 2319 void synchronize_net(void); 2320 int init_dummy_netdev(struct net_device *dev); 2321 2322 DECLARE_PER_CPU(int, xmit_recursion); 2323 static inline int dev_recursion_level(void) 2324 { 2325 return this_cpu_read(xmit_recursion); 2326 } 2327 2328 struct net_device *dev_get_by_index(struct net *net, int ifindex); 2329 struct net_device *__dev_get_by_index(struct net *net, int ifindex); 2330 struct net_device *dev_get_by_index_rcu(struct net *net, int ifindex); 2331 int netdev_get_name(struct net *net, char *name, int ifindex); 2332 int dev_restart(struct net_device *dev); 2333 int skb_gro_receive(struct sk_buff **head, struct sk_buff *skb); 2334 2335 static inline unsigned int skb_gro_offset(const struct sk_buff *skb) 2336 { 2337 return NAPI_GRO_CB(skb)->data_offset; 2338 } 2339 2340 static inline unsigned int skb_gro_len(const struct sk_buff *skb) 2341 { 2342 return skb->len - NAPI_GRO_CB(skb)->data_offset; 2343 } 2344 2345 static inline void skb_gro_pull(struct sk_buff *skb, unsigned int len) 2346 { 2347 NAPI_GRO_CB(skb)->data_offset += len; 2348 } 2349 2350 static inline void *skb_gro_header_fast(struct sk_buff *skb, 2351 unsigned int offset) 2352 { 2353 return NAPI_GRO_CB(skb)->frag0 + offset; 2354 } 2355 2356 static inline int skb_gro_header_hard(struct sk_buff *skb, unsigned int hlen) 2357 { 2358 return NAPI_GRO_CB(skb)->frag0_len < hlen; 2359 } 2360 2361 static inline void *skb_gro_header_slow(struct sk_buff *skb, unsigned int hlen, 2362 unsigned int offset) 2363 { 2364 if (!pskb_may_pull(skb, hlen)) 2365 return NULL; 2366 2367 NAPI_GRO_CB(skb)->frag0 = NULL; 2368 NAPI_GRO_CB(skb)->frag0_len = 0; 2369 return skb->data + offset; 2370 } 2371 2372 static inline void *skb_gro_network_header(struct sk_buff *skb) 2373 { 2374 return (NAPI_GRO_CB(skb)->frag0 ?: skb->data) + 2375 skb_network_offset(skb); 2376 } 2377 2378 static inline void skb_gro_postpull_rcsum(struct sk_buff *skb, 2379 const void *start, unsigned int len) 2380 { 2381 if (NAPI_GRO_CB(skb)->csum_valid) 2382 NAPI_GRO_CB(skb)->csum = csum_sub(NAPI_GRO_CB(skb)->csum, 2383 csum_partial(start, len, 0)); 2384 } 2385 2386 /* GRO checksum functions. These are logical equivalents of the normal 2387 * checksum functions (in skbuff.h) except that they operate on the GRO 2388 * offsets and fields in sk_buff. 2389 */ 2390 2391 __sum16 __skb_gro_checksum_complete(struct sk_buff *skb); 2392 2393 static inline bool skb_at_gro_remcsum_start(struct sk_buff *skb) 2394 { 2395 return (NAPI_GRO_CB(skb)->gro_remcsum_start == skb_gro_offset(skb)); 2396 } 2397 2398 static inline bool __skb_gro_checksum_validate_needed(struct sk_buff *skb, 2399 bool zero_okay, 2400 __sum16 check) 2401 { 2402 return ((skb->ip_summed != CHECKSUM_PARTIAL || 2403 skb_checksum_start_offset(skb) < 2404 skb_gro_offset(skb)) && 2405 !skb_at_gro_remcsum_start(skb) && 2406 NAPI_GRO_CB(skb)->csum_cnt == 0 && 2407 (!zero_okay || check)); 2408 } 2409 2410 static inline __sum16 __skb_gro_checksum_validate_complete(struct sk_buff *skb, 2411 __wsum psum) 2412 { 2413 if (NAPI_GRO_CB(skb)->csum_valid && 2414 !csum_fold(csum_add(psum, NAPI_GRO_CB(skb)->csum))) 2415 return 0; 2416 2417 NAPI_GRO_CB(skb)->csum = psum; 2418 2419 return __skb_gro_checksum_complete(skb); 2420 } 2421 2422 static inline void skb_gro_incr_csum_unnecessary(struct sk_buff *skb) 2423 { 2424 if (NAPI_GRO_CB(skb)->csum_cnt > 0) { 2425 /* Consume a checksum from CHECKSUM_UNNECESSARY */ 2426 NAPI_GRO_CB(skb)->csum_cnt--; 2427 } else { 2428 /* Update skb for CHECKSUM_UNNECESSARY and csum_level when we 2429 * verified a new top level checksum or an encapsulated one 2430 * during GRO. This saves work if we fallback to normal path. 2431 */ 2432 __skb_incr_checksum_unnecessary(skb); 2433 } 2434 } 2435 2436 #define __skb_gro_checksum_validate(skb, proto, zero_okay, check, \ 2437 compute_pseudo) \ 2438 ({ \ 2439 __sum16 __ret = 0; \ 2440 if (__skb_gro_checksum_validate_needed(skb, zero_okay, check)) \ 2441 __ret = __skb_gro_checksum_validate_complete(skb, \ 2442 compute_pseudo(skb, proto)); \ 2443 if (__ret) \ 2444 __skb_mark_checksum_bad(skb); \ 2445 else \ 2446 skb_gro_incr_csum_unnecessary(skb); \ 2447 __ret; \ 2448 }) 2449 2450 #define skb_gro_checksum_validate(skb, proto, compute_pseudo) \ 2451 __skb_gro_checksum_validate(skb, proto, false, 0, compute_pseudo) 2452 2453 #define skb_gro_checksum_validate_zero_check(skb, proto, check, \ 2454 compute_pseudo) \ 2455 __skb_gro_checksum_validate(skb, proto, true, check, compute_pseudo) 2456 2457 #define skb_gro_checksum_simple_validate(skb) \ 2458 __skb_gro_checksum_validate(skb, 0, false, 0, null_compute_pseudo) 2459 2460 static inline bool __skb_gro_checksum_convert_check(struct sk_buff *skb) 2461 { 2462 return (NAPI_GRO_CB(skb)->csum_cnt == 0 && 2463 !NAPI_GRO_CB(skb)->csum_valid); 2464 } 2465 2466 static inline void __skb_gro_checksum_convert(struct sk_buff *skb, 2467 __sum16 check, __wsum pseudo) 2468 { 2469 NAPI_GRO_CB(skb)->csum = ~pseudo; 2470 NAPI_GRO_CB(skb)->csum_valid = 1; 2471 } 2472 2473 #define skb_gro_checksum_try_convert(skb, proto, check, compute_pseudo) \ 2474 do { \ 2475 if (__skb_gro_checksum_convert_check(skb)) \ 2476 __skb_gro_checksum_convert(skb, check, \ 2477 compute_pseudo(skb, proto)); \ 2478 } while (0) 2479 2480 struct gro_remcsum { 2481 int offset; 2482 __wsum delta; 2483 }; 2484 2485 static inline void skb_gro_remcsum_init(struct gro_remcsum *grc) 2486 { 2487 grc->offset = 0; 2488 grc->delta = 0; 2489 } 2490 2491 static inline void *skb_gro_remcsum_process(struct sk_buff *skb, void *ptr, 2492 unsigned int off, size_t hdrlen, 2493 int start, int offset, 2494 struct gro_remcsum *grc, 2495 bool nopartial) 2496 { 2497 __wsum delta; 2498 size_t plen = hdrlen + max_t(size_t, offset + sizeof(u16), start); 2499 2500 BUG_ON(!NAPI_GRO_CB(skb)->csum_valid); 2501 2502 if (!nopartial) { 2503 NAPI_GRO_CB(skb)->gro_remcsum_start = off + hdrlen + start; 2504 return ptr; 2505 } 2506 2507 ptr = skb_gro_header_fast(skb, off); 2508 if (skb_gro_header_hard(skb, off + plen)) { 2509 ptr = skb_gro_header_slow(skb, off + plen, off); 2510 if (!ptr) 2511 return NULL; 2512 } 2513 2514 delta = remcsum_adjust(ptr + hdrlen, NAPI_GRO_CB(skb)->csum, 2515 start, offset); 2516 2517 /* Adjust skb->csum since we changed the packet */ 2518 NAPI_GRO_CB(skb)->csum = csum_add(NAPI_GRO_CB(skb)->csum, delta); 2519 2520 grc->offset = off + hdrlen + offset; 2521 grc->delta = delta; 2522 2523 return ptr; 2524 } 2525 2526 static inline void skb_gro_remcsum_cleanup(struct sk_buff *skb, 2527 struct gro_remcsum *grc) 2528 { 2529 void *ptr; 2530 size_t plen = grc->offset + sizeof(u16); 2531 2532 if (!grc->delta) 2533 return; 2534 2535 ptr = skb_gro_header_fast(skb, grc->offset); 2536 if (skb_gro_header_hard(skb, grc->offset + sizeof(u16))) { 2537 ptr = skb_gro_header_slow(skb, plen, grc->offset); 2538 if (!ptr) 2539 return; 2540 } 2541 2542 remcsum_unadjust((__sum16 *)ptr, grc->delta); 2543 } 2544 2545 struct skb_csum_offl_spec { 2546 __u16 ipv4_okay:1, 2547 ipv6_okay:1, 2548 encap_okay:1, 2549 ip_options_okay:1, 2550 ext_hdrs_okay:1, 2551 tcp_okay:1, 2552 udp_okay:1, 2553 sctp_okay:1, 2554 vlan_okay:1, 2555 no_encapped_ipv6:1, 2556 no_not_encapped:1; 2557 }; 2558 2559 bool __skb_csum_offload_chk(struct sk_buff *skb, 2560 const struct skb_csum_offl_spec *spec, 2561 bool *csum_encapped, 2562 bool csum_help); 2563 2564 static inline bool skb_csum_offload_chk(struct sk_buff *skb, 2565 const struct skb_csum_offl_spec *spec, 2566 bool *csum_encapped, 2567 bool csum_help) 2568 { 2569 if (skb->ip_summed != CHECKSUM_PARTIAL) 2570 return false; 2571 2572 return __skb_csum_offload_chk(skb, spec, csum_encapped, csum_help); 2573 } 2574 2575 static inline bool skb_csum_offload_chk_help(struct sk_buff *skb, 2576 const struct skb_csum_offl_spec *spec) 2577 { 2578 bool csum_encapped; 2579 2580 return skb_csum_offload_chk(skb, spec, &csum_encapped, true); 2581 } 2582 2583 static inline bool skb_csum_off_chk_help_cmn(struct sk_buff *skb) 2584 { 2585 static const struct skb_csum_offl_spec csum_offl_spec = { 2586 .ipv4_okay = 1, 2587 .ip_options_okay = 1, 2588 .ipv6_okay = 1, 2589 .vlan_okay = 1, 2590 .tcp_okay = 1, 2591 .udp_okay = 1, 2592 }; 2593 2594 return skb_csum_offload_chk_help(skb, &csum_offl_spec); 2595 } 2596 2597 static inline bool skb_csum_off_chk_help_cmn_v4_only(struct sk_buff *skb) 2598 { 2599 static const struct skb_csum_offl_spec csum_offl_spec = { 2600 .ipv4_okay = 1, 2601 .ip_options_okay = 1, 2602 .tcp_okay = 1, 2603 .udp_okay = 1, 2604 .vlan_okay = 1, 2605 }; 2606 2607 return skb_csum_offload_chk_help(skb, &csum_offl_spec); 2608 } 2609 2610 static inline int dev_hard_header(struct sk_buff *skb, struct net_device *dev, 2611 unsigned short type, 2612 const void *daddr, const void *saddr, 2613 unsigned int len) 2614 { 2615 if (!dev->header_ops || !dev->header_ops->create) 2616 return 0; 2617 2618 return dev->header_ops->create(skb, dev, type, daddr, saddr, len); 2619 } 2620 2621 static inline int dev_parse_header(const struct sk_buff *skb, 2622 unsigned char *haddr) 2623 { 2624 const struct net_device *dev = skb->dev; 2625 2626 if (!dev->header_ops || !dev->header_ops->parse) 2627 return 0; 2628 return dev->header_ops->parse(skb, haddr); 2629 } 2630 2631 typedef int gifconf_func_t(struct net_device * dev, char __user * bufptr, int len); 2632 int register_gifconf(unsigned int family, gifconf_func_t *gifconf); 2633 static inline int unregister_gifconf(unsigned int family) 2634 { 2635 return register_gifconf(family, NULL); 2636 } 2637 2638 #ifdef CONFIG_NET_FLOW_LIMIT 2639 #define FLOW_LIMIT_HISTORY (1 << 7) /* must be ^2 and !overflow buckets */ 2640 struct sd_flow_limit { 2641 u64 count; 2642 unsigned int num_buckets; 2643 unsigned int history_head; 2644 u16 history[FLOW_LIMIT_HISTORY]; 2645 u8 buckets[]; 2646 }; 2647 2648 extern int netdev_flow_limit_table_len; 2649 #endif /* CONFIG_NET_FLOW_LIMIT */ 2650 2651 /* 2652 * Incoming packets are placed on per-cpu queues 2653 */ 2654 struct softnet_data { 2655 struct list_head poll_list; 2656 struct sk_buff_head process_queue; 2657 2658 /* stats */ 2659 unsigned int processed; 2660 unsigned int time_squeeze; 2661 unsigned int cpu_collision; 2662 unsigned int received_rps; 2663 #ifdef CONFIG_RPS 2664 struct softnet_data *rps_ipi_list; 2665 #endif 2666 #ifdef CONFIG_NET_FLOW_LIMIT 2667 struct sd_flow_limit __rcu *flow_limit; 2668 #endif 2669 struct Qdisc *output_queue; 2670 struct Qdisc **output_queue_tailp; 2671 struct sk_buff *completion_queue; 2672 2673 #ifdef CONFIG_RPS 2674 /* Elements below can be accessed between CPUs for RPS */ 2675 struct call_single_data csd ____cacheline_aligned_in_smp; 2676 struct softnet_data *rps_ipi_next; 2677 unsigned int cpu; 2678 unsigned int input_queue_head; 2679 unsigned int input_queue_tail; 2680 #endif 2681 unsigned int dropped; 2682 struct sk_buff_head input_pkt_queue; 2683 struct napi_struct backlog; 2684 2685 }; 2686 2687 static inline void input_queue_head_incr(struct softnet_data *sd) 2688 { 2689 #ifdef CONFIG_RPS 2690 sd->input_queue_head++; 2691 #endif 2692 } 2693 2694 static inline void input_queue_tail_incr_save(struct softnet_data *sd, 2695 unsigned int *qtail) 2696 { 2697 #ifdef CONFIG_RPS 2698 *qtail = ++sd->input_queue_tail; 2699 #endif 2700 } 2701 2702 DECLARE_PER_CPU_ALIGNED(struct softnet_data, softnet_data); 2703 2704 void __netif_schedule(struct Qdisc *q); 2705 void netif_schedule_queue(struct netdev_queue *txq); 2706 2707 static inline void netif_tx_schedule_all(struct net_device *dev) 2708 { 2709 unsigned int i; 2710 2711 for (i = 0; i < dev->num_tx_queues; i++) 2712 netif_schedule_queue(netdev_get_tx_queue(dev, i)); 2713 } 2714 2715 static inline void netif_tx_start_queue(struct netdev_queue *dev_queue) 2716 { 2717 clear_bit(__QUEUE_STATE_DRV_XOFF, &dev_queue->state); 2718 } 2719 2720 /** 2721 * netif_start_queue - allow transmit 2722 * @dev: network device 2723 * 2724 * Allow upper layers to call the device hard_start_xmit routine. 2725 */ 2726 static inline void netif_start_queue(struct net_device *dev) 2727 { 2728 netif_tx_start_queue(netdev_get_tx_queue(dev, 0)); 2729 } 2730 2731 static inline void netif_tx_start_all_queues(struct net_device *dev) 2732 { 2733 unsigned int i; 2734 2735 for (i = 0; i < dev->num_tx_queues; i++) { 2736 struct netdev_queue *txq = netdev_get_tx_queue(dev, i); 2737 netif_tx_start_queue(txq); 2738 } 2739 } 2740 2741 void netif_tx_wake_queue(struct netdev_queue *dev_queue); 2742 2743 /** 2744 * netif_wake_queue - restart transmit 2745 * @dev: network device 2746 * 2747 * Allow upper layers to call the device hard_start_xmit routine. 2748 * Used for flow control when transmit resources are available. 2749 */ 2750 static inline void netif_wake_queue(struct net_device *dev) 2751 { 2752 netif_tx_wake_queue(netdev_get_tx_queue(dev, 0)); 2753 } 2754 2755 static inline void netif_tx_wake_all_queues(struct net_device *dev) 2756 { 2757 unsigned int i; 2758 2759 for (i = 0; i < dev->num_tx_queues; i++) { 2760 struct netdev_queue *txq = netdev_get_tx_queue(dev, i); 2761 netif_tx_wake_queue(txq); 2762 } 2763 } 2764 2765 static inline void netif_tx_stop_queue(struct netdev_queue *dev_queue) 2766 { 2767 set_bit(__QUEUE_STATE_DRV_XOFF, &dev_queue->state); 2768 } 2769 2770 /** 2771 * netif_stop_queue - stop transmitted packets 2772 * @dev: network device 2773 * 2774 * Stop upper layers calling the device hard_start_xmit routine. 2775 * Used for flow control when transmit resources are unavailable. 2776 */ 2777 static inline void netif_stop_queue(struct net_device *dev) 2778 { 2779 netif_tx_stop_queue(netdev_get_tx_queue(dev, 0)); 2780 } 2781 2782 void netif_tx_stop_all_queues(struct net_device *dev); 2783 2784 static inline bool netif_tx_queue_stopped(const struct netdev_queue *dev_queue) 2785 { 2786 return test_bit(__QUEUE_STATE_DRV_XOFF, &dev_queue->state); 2787 } 2788 2789 /** 2790 * netif_queue_stopped - test if transmit queue is flowblocked 2791 * @dev: network device 2792 * 2793 * Test if transmit queue on device is currently unable to send. 2794 */ 2795 static inline bool netif_queue_stopped(const struct net_device *dev) 2796 { 2797 return netif_tx_queue_stopped(netdev_get_tx_queue(dev, 0)); 2798 } 2799 2800 static inline bool netif_xmit_stopped(const struct netdev_queue *dev_queue) 2801 { 2802 return dev_queue->state & QUEUE_STATE_ANY_XOFF; 2803 } 2804 2805 static inline bool 2806 netif_xmit_frozen_or_stopped(const struct netdev_queue *dev_queue) 2807 { 2808 return dev_queue->state & QUEUE_STATE_ANY_XOFF_OR_FROZEN; 2809 } 2810 2811 static inline bool 2812 netif_xmit_frozen_or_drv_stopped(const struct netdev_queue *dev_queue) 2813 { 2814 return dev_queue->state & QUEUE_STATE_DRV_XOFF_OR_FROZEN; 2815 } 2816 2817 /** 2818 * netdev_txq_bql_enqueue_prefetchw - prefetch bql data for write 2819 * @dev_queue: pointer to transmit queue 2820 * 2821 * BQL enabled drivers might use this helper in their ndo_start_xmit(), 2822 * to give appropriate hint to the cpu. 2823 */ 2824 static inline void netdev_txq_bql_enqueue_prefetchw(struct netdev_queue *dev_queue) 2825 { 2826 #ifdef CONFIG_BQL 2827 prefetchw(&dev_queue->dql.num_queued); 2828 #endif 2829 } 2830 2831 /** 2832 * netdev_txq_bql_complete_prefetchw - prefetch bql data for write 2833 * @dev_queue: pointer to transmit queue 2834 * 2835 * BQL enabled drivers might use this helper in their TX completion path, 2836 * to give appropriate hint to the cpu. 2837 */ 2838 static inline void netdev_txq_bql_complete_prefetchw(struct netdev_queue *dev_queue) 2839 { 2840 #ifdef CONFIG_BQL 2841 prefetchw(&dev_queue->dql.limit); 2842 #endif 2843 } 2844 2845 static inline void netdev_tx_sent_queue(struct netdev_queue *dev_queue, 2846 unsigned int bytes) 2847 { 2848 #ifdef CONFIG_BQL 2849 dql_queued(&dev_queue->dql, bytes); 2850 2851 if (likely(dql_avail(&dev_queue->dql) >= 0)) 2852 return; 2853 2854 set_bit(__QUEUE_STATE_STACK_XOFF, &dev_queue->state); 2855 2856 /* 2857 * The XOFF flag must be set before checking the dql_avail below, 2858 * because in netdev_tx_completed_queue we update the dql_completed 2859 * before checking the XOFF flag. 2860 */ 2861 smp_mb(); 2862 2863 /* check again in case another CPU has just made room avail */ 2864 if (unlikely(dql_avail(&dev_queue->dql) >= 0)) 2865 clear_bit(__QUEUE_STATE_STACK_XOFF, &dev_queue->state); 2866 #endif 2867 } 2868 2869 /** 2870 * netdev_sent_queue - report the number of bytes queued to hardware 2871 * @dev: network device 2872 * @bytes: number of bytes queued to the hardware device queue 2873 * 2874 * Report the number of bytes queued for sending/completion to the network 2875 * device hardware queue. @bytes should be a good approximation and should 2876 * exactly match netdev_completed_queue() @bytes 2877 */ 2878 static inline void netdev_sent_queue(struct net_device *dev, unsigned int bytes) 2879 { 2880 netdev_tx_sent_queue(netdev_get_tx_queue(dev, 0), bytes); 2881 } 2882 2883 static inline void netdev_tx_completed_queue(struct netdev_queue *dev_queue, 2884 unsigned int pkts, unsigned int bytes) 2885 { 2886 #ifdef CONFIG_BQL 2887 if (unlikely(!bytes)) 2888 return; 2889 2890 dql_completed(&dev_queue->dql, bytes); 2891 2892 /* 2893 * Without the memory barrier there is a small possiblity that 2894 * netdev_tx_sent_queue will miss the update and cause the queue to 2895 * be stopped forever 2896 */ 2897 smp_mb(); 2898 2899 if (dql_avail(&dev_queue->dql) < 0) 2900 return; 2901 2902 if (test_and_clear_bit(__QUEUE_STATE_STACK_XOFF, &dev_queue->state)) 2903 netif_schedule_queue(dev_queue); 2904 #endif 2905 } 2906 2907 /** 2908 * netdev_completed_queue - report bytes and packets completed by device 2909 * @dev: network device 2910 * @pkts: actual number of packets sent over the medium 2911 * @bytes: actual number of bytes sent over the medium 2912 * 2913 * Report the number of bytes and packets transmitted by the network device 2914 * hardware queue over the physical medium, @bytes must exactly match the 2915 * @bytes amount passed to netdev_sent_queue() 2916 */ 2917 static inline void netdev_completed_queue(struct net_device *dev, 2918 unsigned int pkts, unsigned int bytes) 2919 { 2920 netdev_tx_completed_queue(netdev_get_tx_queue(dev, 0), pkts, bytes); 2921 } 2922 2923 static inline void netdev_tx_reset_queue(struct netdev_queue *q) 2924 { 2925 #ifdef CONFIG_BQL 2926 clear_bit(__QUEUE_STATE_STACK_XOFF, &q->state); 2927 dql_reset(&q->dql); 2928 #endif 2929 } 2930 2931 /** 2932 * netdev_reset_queue - reset the packets and bytes count of a network device 2933 * @dev_queue: network device 2934 * 2935 * Reset the bytes and packet count of a network device and clear the 2936 * software flow control OFF bit for this network device 2937 */ 2938 static inline void netdev_reset_queue(struct net_device *dev_queue) 2939 { 2940 netdev_tx_reset_queue(netdev_get_tx_queue(dev_queue, 0)); 2941 } 2942 2943 /** 2944 * netdev_cap_txqueue - check if selected tx queue exceeds device queues 2945 * @dev: network device 2946 * @queue_index: given tx queue index 2947 * 2948 * Returns 0 if given tx queue index >= number of device tx queues, 2949 * otherwise returns the originally passed tx queue index. 2950 */ 2951 static inline u16 netdev_cap_txqueue(struct net_device *dev, u16 queue_index) 2952 { 2953 if (unlikely(queue_index >= dev->real_num_tx_queues)) { 2954 net_warn_ratelimited("%s selects TX queue %d, but real number of TX queues is %d\n", 2955 dev->name, queue_index, 2956 dev->real_num_tx_queues); 2957 return 0; 2958 } 2959 2960 return queue_index; 2961 } 2962 2963 /** 2964 * netif_running - test if up 2965 * @dev: network device 2966 * 2967 * Test if the device has been brought up. 2968 */ 2969 static inline bool netif_running(const struct net_device *dev) 2970 { 2971 return test_bit(__LINK_STATE_START, &dev->state); 2972 } 2973 2974 /* 2975 * Routines to manage the subqueues on a device. We only need start 2976 * stop, and a check if it's stopped. All other device management is 2977 * done at the overall netdevice level. 2978 * Also test the device if we're multiqueue. 2979 */ 2980 2981 /** 2982 * netif_start_subqueue - allow sending packets on subqueue 2983 * @dev: network device 2984 * @queue_index: sub queue index 2985 * 2986 * Start individual transmit queue of a device with multiple transmit queues. 2987 */ 2988 static inline void netif_start_subqueue(struct net_device *dev, u16 queue_index) 2989 { 2990 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue_index); 2991 2992 netif_tx_start_queue(txq); 2993 } 2994 2995 /** 2996 * netif_stop_subqueue - stop sending packets on subqueue 2997 * @dev: network device 2998 * @queue_index: sub queue index 2999 * 3000 * Stop individual transmit queue of a device with multiple transmit queues. 3001 */ 3002 static inline void netif_stop_subqueue(struct net_device *dev, u16 queue_index) 3003 { 3004 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue_index); 3005 netif_tx_stop_queue(txq); 3006 } 3007 3008 /** 3009 * netif_subqueue_stopped - test status of subqueue 3010 * @dev: network device 3011 * @queue_index: sub queue index 3012 * 3013 * Check individual transmit queue of a device with multiple transmit queues. 3014 */ 3015 static inline bool __netif_subqueue_stopped(const struct net_device *dev, 3016 u16 queue_index) 3017 { 3018 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue_index); 3019 3020 return netif_tx_queue_stopped(txq); 3021 } 3022 3023 static inline bool netif_subqueue_stopped(const struct net_device *dev, 3024 struct sk_buff *skb) 3025 { 3026 return __netif_subqueue_stopped(dev, skb_get_queue_mapping(skb)); 3027 } 3028 3029 void netif_wake_subqueue(struct net_device *dev, u16 queue_index); 3030 3031 #ifdef CONFIG_XPS 3032 int netif_set_xps_queue(struct net_device *dev, const struct cpumask *mask, 3033 u16 index); 3034 #else 3035 static inline int netif_set_xps_queue(struct net_device *dev, 3036 const struct cpumask *mask, 3037 u16 index) 3038 { 3039 return 0; 3040 } 3041 #endif 3042 3043 u16 __skb_tx_hash(const struct net_device *dev, struct sk_buff *skb, 3044 unsigned int num_tx_queues); 3045 3046 /* 3047 * Returns a Tx hash for the given packet when dev->real_num_tx_queues is used 3048 * as a distribution range limit for the returned value. 3049 */ 3050 static inline u16 skb_tx_hash(const struct net_device *dev, 3051 struct sk_buff *skb) 3052 { 3053 return __skb_tx_hash(dev, skb, dev->real_num_tx_queues); 3054 } 3055 3056 /** 3057 * netif_is_multiqueue - test if device has multiple transmit queues 3058 * @dev: network device 3059 * 3060 * Check if device has multiple transmit queues 3061 */ 3062 static inline bool netif_is_multiqueue(const struct net_device *dev) 3063 { 3064 return dev->num_tx_queues > 1; 3065 } 3066 3067 int netif_set_real_num_tx_queues(struct net_device *dev, unsigned int txq); 3068 3069 #ifdef CONFIG_SYSFS 3070 int netif_set_real_num_rx_queues(struct net_device *dev, unsigned int rxq); 3071 #else 3072 static inline int netif_set_real_num_rx_queues(struct net_device *dev, 3073 unsigned int rxq) 3074 { 3075 return 0; 3076 } 3077 #endif 3078 3079 #ifdef CONFIG_SYSFS 3080 static inline unsigned int get_netdev_rx_queue_index( 3081 struct netdev_rx_queue *queue) 3082 { 3083 struct net_device *dev = queue->dev; 3084 int index = queue - dev->_rx; 3085 3086 BUG_ON(index >= dev->num_rx_queues); 3087 return index; 3088 } 3089 #endif 3090 3091 #define DEFAULT_MAX_NUM_RSS_QUEUES (8) 3092 int netif_get_num_default_rss_queues(void); 3093 3094 enum skb_free_reason { 3095 SKB_REASON_CONSUMED, 3096 SKB_REASON_DROPPED, 3097 }; 3098 3099 void __dev_kfree_skb_irq(struct sk_buff *skb, enum skb_free_reason reason); 3100 void __dev_kfree_skb_any(struct sk_buff *skb, enum skb_free_reason reason); 3101 3102 /* 3103 * It is not allowed to call kfree_skb() or consume_skb() from hardware 3104 * interrupt context or with hardware interrupts being disabled. 3105 * (in_irq() || irqs_disabled()) 3106 * 3107 * We provide four helpers that can be used in following contexts : 3108 * 3109 * dev_kfree_skb_irq(skb) when caller drops a packet from irq context, 3110 * replacing kfree_skb(skb) 3111 * 3112 * dev_consume_skb_irq(skb) when caller consumes a packet from irq context. 3113 * Typically used in place of consume_skb(skb) in TX completion path 3114 * 3115 * dev_kfree_skb_any(skb) when caller doesn't know its current irq context, 3116 * replacing kfree_skb(skb) 3117 * 3118 * dev_consume_skb_any(skb) when caller doesn't know its current irq context, 3119 * and consumed a packet. Used in place of consume_skb(skb) 3120 */ 3121 static inline void dev_kfree_skb_irq(struct sk_buff *skb) 3122 { 3123 __dev_kfree_skb_irq(skb, SKB_REASON_DROPPED); 3124 } 3125 3126 static inline void dev_consume_skb_irq(struct sk_buff *skb) 3127 { 3128 __dev_kfree_skb_irq(skb, SKB_REASON_CONSUMED); 3129 } 3130 3131 static inline void dev_kfree_skb_any(struct sk_buff *skb) 3132 { 3133 __dev_kfree_skb_any(skb, SKB_REASON_DROPPED); 3134 } 3135 3136 static inline void dev_consume_skb_any(struct sk_buff *skb) 3137 { 3138 __dev_kfree_skb_any(skb, SKB_REASON_CONSUMED); 3139 } 3140 3141 int netif_rx(struct sk_buff *skb); 3142 int netif_rx_ni(struct sk_buff *skb); 3143 int netif_receive_skb(struct sk_buff *skb); 3144 gro_result_t napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb); 3145 void napi_gro_flush(struct napi_struct *napi, bool flush_old); 3146 struct sk_buff *napi_get_frags(struct napi_struct *napi); 3147 gro_result_t napi_gro_frags(struct napi_struct *napi); 3148 struct packet_offload *gro_find_receive_by_type(__be16 type); 3149 struct packet_offload *gro_find_complete_by_type(__be16 type); 3150 3151 static inline void napi_free_frags(struct napi_struct *napi) 3152 { 3153 kfree_skb(napi->skb); 3154 napi->skb = NULL; 3155 } 3156 3157 int netdev_rx_handler_register(struct net_device *dev, 3158 rx_handler_func_t *rx_handler, 3159 void *rx_handler_data); 3160 void netdev_rx_handler_unregister(struct net_device *dev); 3161 3162 bool dev_valid_name(const char *name); 3163 int dev_ioctl(struct net *net, unsigned int cmd, void __user *); 3164 int dev_ethtool(struct net *net, struct ifreq *); 3165 unsigned int dev_get_flags(const struct net_device *); 3166 int __dev_change_flags(struct net_device *, unsigned int flags); 3167 int dev_change_flags(struct net_device *, unsigned int); 3168 void __dev_notify_flags(struct net_device *, unsigned int old_flags, 3169 unsigned int gchanges); 3170 int dev_change_name(struct net_device *, const char *); 3171 int dev_set_alias(struct net_device *, const char *, size_t); 3172 int dev_change_net_namespace(struct net_device *, struct net *, const char *); 3173 int dev_set_mtu(struct net_device *, int); 3174 void dev_set_group(struct net_device *, int); 3175 int dev_set_mac_address(struct net_device *, struct sockaddr *); 3176 int dev_change_carrier(struct net_device *, bool new_carrier); 3177 int dev_get_phys_port_id(struct net_device *dev, 3178 struct netdev_phys_item_id *ppid); 3179 int dev_get_phys_port_name(struct net_device *dev, 3180 char *name, size_t len); 3181 int dev_change_proto_down(struct net_device *dev, bool proto_down); 3182 struct sk_buff *validate_xmit_skb_list(struct sk_buff *skb, struct net_device *dev); 3183 struct sk_buff *dev_hard_start_xmit(struct sk_buff *skb, struct net_device *dev, 3184 struct netdev_queue *txq, int *ret); 3185 int __dev_forward_skb(struct net_device *dev, struct sk_buff *skb); 3186 int dev_forward_skb(struct net_device *dev, struct sk_buff *skb); 3187 bool is_skb_forwardable(struct net_device *dev, struct sk_buff *skb); 3188 3189 extern int netdev_budget; 3190 3191 /* Called by rtnetlink.c:rtnl_unlock() */ 3192 void netdev_run_todo(void); 3193 3194 /** 3195 * dev_put - release reference to device 3196 * @dev: network device 3197 * 3198 * Release reference to device to allow it to be freed. 3199 */ 3200 static inline void dev_put(struct net_device *dev) 3201 { 3202 this_cpu_dec(*dev->pcpu_refcnt); 3203 } 3204 3205 /** 3206 * dev_hold - get reference to device 3207 * @dev: network device 3208 * 3209 * Hold reference to device to keep it from being freed. 3210 */ 3211 static inline void dev_hold(struct net_device *dev) 3212 { 3213 this_cpu_inc(*dev->pcpu_refcnt); 3214 } 3215 3216 /* Carrier loss detection, dial on demand. The functions netif_carrier_on 3217 * and _off may be called from IRQ context, but it is caller 3218 * who is responsible for serialization of these calls. 3219 * 3220 * The name carrier is inappropriate, these functions should really be 3221 * called netif_lowerlayer_*() because they represent the state of any 3222 * kind of lower layer not just hardware media. 3223 */ 3224 3225 void linkwatch_init_dev(struct net_device *dev); 3226 void linkwatch_fire_event(struct net_device *dev); 3227 void linkwatch_forget_dev(struct net_device *dev); 3228 3229 /** 3230 * netif_carrier_ok - test if carrier present 3231 * @dev: network device 3232 * 3233 * Check if carrier is present on device 3234 */ 3235 static inline bool netif_carrier_ok(const struct net_device *dev) 3236 { 3237 return !test_bit(__LINK_STATE_NOCARRIER, &dev->state); 3238 } 3239 3240 unsigned long dev_trans_start(struct net_device *dev); 3241 3242 void __netdev_watchdog_up(struct net_device *dev); 3243 3244 void netif_carrier_on(struct net_device *dev); 3245 3246 void netif_carrier_off(struct net_device *dev); 3247 3248 /** 3249 * netif_dormant_on - mark device as dormant. 3250 * @dev: network device 3251 * 3252 * Mark device as dormant (as per RFC2863). 3253 * 3254 * The dormant state indicates that the relevant interface is not 3255 * actually in a condition to pass packets (i.e., it is not 'up') but is 3256 * in a "pending" state, waiting for some external event. For "on- 3257 * demand" interfaces, this new state identifies the situation where the 3258 * interface is waiting for events to place it in the up state. 3259 * 3260 */ 3261 static inline void netif_dormant_on(struct net_device *dev) 3262 { 3263 if (!test_and_set_bit(__LINK_STATE_DORMANT, &dev->state)) 3264 linkwatch_fire_event(dev); 3265 } 3266 3267 /** 3268 * netif_dormant_off - set device as not dormant. 3269 * @dev: network device 3270 * 3271 * Device is not in dormant state. 3272 */ 3273 static inline void netif_dormant_off(struct net_device *dev) 3274 { 3275 if (test_and_clear_bit(__LINK_STATE_DORMANT, &dev->state)) 3276 linkwatch_fire_event(dev); 3277 } 3278 3279 /** 3280 * netif_dormant - test if carrier present 3281 * @dev: network device 3282 * 3283 * Check if carrier is present on device 3284 */ 3285 static inline bool netif_dormant(const struct net_device *dev) 3286 { 3287 return test_bit(__LINK_STATE_DORMANT, &dev->state); 3288 } 3289 3290 3291 /** 3292 * netif_oper_up - test if device is operational 3293 * @dev: network device 3294 * 3295 * Check if carrier is operational 3296 */ 3297 static inline bool netif_oper_up(const struct net_device *dev) 3298 { 3299 return (dev->operstate == IF_OPER_UP || 3300 dev->operstate == IF_OPER_UNKNOWN /* backward compat */); 3301 } 3302 3303 /** 3304 * netif_device_present - is device available or removed 3305 * @dev: network device 3306 * 3307 * Check if device has not been removed from system. 3308 */ 3309 static inline bool netif_device_present(struct net_device *dev) 3310 { 3311 return test_bit(__LINK_STATE_PRESENT, &dev->state); 3312 } 3313 3314 void netif_device_detach(struct net_device *dev); 3315 3316 void netif_device_attach(struct net_device *dev); 3317 3318 /* 3319 * Network interface message level settings 3320 */ 3321 3322 enum { 3323 NETIF_MSG_DRV = 0x0001, 3324 NETIF_MSG_PROBE = 0x0002, 3325 NETIF_MSG_LINK = 0x0004, 3326 NETIF_MSG_TIMER = 0x0008, 3327 NETIF_MSG_IFDOWN = 0x0010, 3328 NETIF_MSG_IFUP = 0x0020, 3329 NETIF_MSG_RX_ERR = 0x0040, 3330 NETIF_MSG_TX_ERR = 0x0080, 3331 NETIF_MSG_TX_QUEUED = 0x0100, 3332 NETIF_MSG_INTR = 0x0200, 3333 NETIF_MSG_TX_DONE = 0x0400, 3334 NETIF_MSG_RX_STATUS = 0x0800, 3335 NETIF_MSG_PKTDATA = 0x1000, 3336 NETIF_MSG_HW = 0x2000, 3337 NETIF_MSG_WOL = 0x4000, 3338 }; 3339 3340 #define netif_msg_drv(p) ((p)->msg_enable & NETIF_MSG_DRV) 3341 #define netif_msg_probe(p) ((p)->msg_enable & NETIF_MSG_PROBE) 3342 #define netif_msg_link(p) ((p)->msg_enable & NETIF_MSG_LINK) 3343 #define netif_msg_timer(p) ((p)->msg_enable & NETIF_MSG_TIMER) 3344 #define netif_msg_ifdown(p) ((p)->msg_enable & NETIF_MSG_IFDOWN) 3345 #define netif_msg_ifup(p) ((p)->msg_enable & NETIF_MSG_IFUP) 3346 #define netif_msg_rx_err(p) ((p)->msg_enable & NETIF_MSG_RX_ERR) 3347 #define netif_msg_tx_err(p) ((p)->msg_enable & NETIF_MSG_TX_ERR) 3348 #define netif_msg_tx_queued(p) ((p)->msg_enable & NETIF_MSG_TX_QUEUED) 3349 #define netif_msg_intr(p) ((p)->msg_enable & NETIF_MSG_INTR) 3350 #define netif_msg_tx_done(p) ((p)->msg_enable & NETIF_MSG_TX_DONE) 3351 #define netif_msg_rx_status(p) ((p)->msg_enable & NETIF_MSG_RX_STATUS) 3352 #define netif_msg_pktdata(p) ((p)->msg_enable & NETIF_MSG_PKTDATA) 3353 #define netif_msg_hw(p) ((p)->msg_enable & NETIF_MSG_HW) 3354 #define netif_msg_wol(p) ((p)->msg_enable & NETIF_MSG_WOL) 3355 3356 static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits) 3357 { 3358 /* use default */ 3359 if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) 3360 return default_msg_enable_bits; 3361 if (debug_value == 0) /* no output */ 3362 return 0; 3363 /* set low N bits */ 3364 return (1 << debug_value) - 1; 3365 } 3366 3367 static inline void __netif_tx_lock(struct netdev_queue *txq, int cpu) 3368 { 3369 spin_lock(&txq->_xmit_lock); 3370 txq->xmit_lock_owner = cpu; 3371 } 3372 3373 static inline void __netif_tx_lock_bh(struct netdev_queue *txq) 3374 { 3375 spin_lock_bh(&txq->_xmit_lock); 3376 txq->xmit_lock_owner = smp_processor_id(); 3377 } 3378 3379 static inline bool __netif_tx_trylock(struct netdev_queue *txq) 3380 { 3381 bool ok = spin_trylock(&txq->_xmit_lock); 3382 if (likely(ok)) 3383 txq->xmit_lock_owner = smp_processor_id(); 3384 return ok; 3385 } 3386 3387 static inline void __netif_tx_unlock(struct netdev_queue *txq) 3388 { 3389 txq->xmit_lock_owner = -1; 3390 spin_unlock(&txq->_xmit_lock); 3391 } 3392 3393 static inline void __netif_tx_unlock_bh(struct netdev_queue *txq) 3394 { 3395 txq->xmit_lock_owner = -1; 3396 spin_unlock_bh(&txq->_xmit_lock); 3397 } 3398 3399 static inline void txq_trans_update(struct netdev_queue *txq) 3400 { 3401 if (txq->xmit_lock_owner != -1) 3402 txq->trans_start = jiffies; 3403 } 3404 3405 /** 3406 * netif_tx_lock - grab network device transmit lock 3407 * @dev: network device 3408 * 3409 * Get network device transmit lock 3410 */ 3411 static inline void netif_tx_lock(struct net_device *dev) 3412 { 3413 unsigned int i; 3414 int cpu; 3415 3416 spin_lock(&dev->tx_global_lock); 3417 cpu = smp_processor_id(); 3418 for (i = 0; i < dev->num_tx_queues; i++) { 3419 struct netdev_queue *txq = netdev_get_tx_queue(dev, i); 3420 3421 /* We are the only thread of execution doing a 3422 * freeze, but we have to grab the _xmit_lock in 3423 * order to synchronize with threads which are in 3424 * the ->hard_start_xmit() handler and already 3425 * checked the frozen bit. 3426 */ 3427 __netif_tx_lock(txq, cpu); 3428 set_bit(__QUEUE_STATE_FROZEN, &txq->state); 3429 __netif_tx_unlock(txq); 3430 } 3431 } 3432 3433 static inline void netif_tx_lock_bh(struct net_device *dev) 3434 { 3435 local_bh_disable(); 3436 netif_tx_lock(dev); 3437 } 3438 3439 static inline void netif_tx_unlock(struct net_device *dev) 3440 { 3441 unsigned int i; 3442 3443 for (i = 0; i < dev->num_tx_queues; i++) { 3444 struct netdev_queue *txq = netdev_get_tx_queue(dev, i); 3445 3446 /* No need to grab the _xmit_lock here. If the 3447 * queue is not stopped for another reason, we 3448 * force a schedule. 3449 */ 3450 clear_bit(__QUEUE_STATE_FROZEN, &txq->state); 3451 netif_schedule_queue(txq); 3452 } 3453 spin_unlock(&dev->tx_global_lock); 3454 } 3455 3456 static inline void netif_tx_unlock_bh(struct net_device *dev) 3457 { 3458 netif_tx_unlock(dev); 3459 local_bh_enable(); 3460 } 3461 3462 #define HARD_TX_LOCK(dev, txq, cpu) { \ 3463 if ((dev->features & NETIF_F_LLTX) == 0) { \ 3464 __netif_tx_lock(txq, cpu); \ 3465 } \ 3466 } 3467 3468 #define HARD_TX_TRYLOCK(dev, txq) \ 3469 (((dev->features & NETIF_F_LLTX) == 0) ? \ 3470 __netif_tx_trylock(txq) : \ 3471 true ) 3472 3473 #define HARD_TX_UNLOCK(dev, txq) { \ 3474 if ((dev->features & NETIF_F_LLTX) == 0) { \ 3475 __netif_tx_unlock(txq); \ 3476 } \ 3477 } 3478 3479 static inline void netif_tx_disable(struct net_device *dev) 3480 { 3481 unsigned int i; 3482 int cpu; 3483 3484 local_bh_disable(); 3485 cpu = smp_processor_id(); 3486 for (i = 0; i < dev->num_tx_queues; i++) { 3487 struct netdev_queue *txq = netdev_get_tx_queue(dev, i); 3488 3489 __netif_tx_lock(txq, cpu); 3490 netif_tx_stop_queue(txq); 3491 __netif_tx_unlock(txq); 3492 } 3493 local_bh_enable(); 3494 } 3495 3496 static inline void netif_addr_lock(struct net_device *dev) 3497 { 3498 spin_lock(&dev->addr_list_lock); 3499 } 3500 3501 static inline void netif_addr_lock_nested(struct net_device *dev) 3502 { 3503 int subclass = SINGLE_DEPTH_NESTING; 3504 3505 if (dev->netdev_ops->ndo_get_lock_subclass) 3506 subclass = dev->netdev_ops->ndo_get_lock_subclass(dev); 3507 3508 spin_lock_nested(&dev->addr_list_lock, subclass); 3509 } 3510 3511 static inline void netif_addr_lock_bh(struct net_device *dev) 3512 { 3513 spin_lock_bh(&dev->addr_list_lock); 3514 } 3515 3516 static inline void netif_addr_unlock(struct net_device *dev) 3517 { 3518 spin_unlock(&dev->addr_list_lock); 3519 } 3520 3521 static inline void netif_addr_unlock_bh(struct net_device *dev) 3522 { 3523 spin_unlock_bh(&dev->addr_list_lock); 3524 } 3525 3526 /* 3527 * dev_addrs walker. Should be used only for read access. Call with 3528 * rcu_read_lock held. 3529 */ 3530 #define for_each_dev_addr(dev, ha) \ 3531 list_for_each_entry_rcu(ha, &dev->dev_addrs.list, list) 3532 3533 /* These functions live elsewhere (drivers/net/net_init.c, but related) */ 3534 3535 void ether_setup(struct net_device *dev); 3536 3537 /* Support for loadable net-drivers */ 3538 struct net_device *alloc_netdev_mqs(int sizeof_priv, const char *name, 3539 unsigned char name_assign_type, 3540 void (*setup)(struct net_device *), 3541 unsigned int txqs, unsigned int rxqs); 3542 #define alloc_netdev(sizeof_priv, name, name_assign_type, setup) \ 3543 alloc_netdev_mqs(sizeof_priv, name, name_assign_type, setup, 1, 1) 3544 3545 #define alloc_netdev_mq(sizeof_priv, name, name_assign_type, setup, count) \ 3546 alloc_netdev_mqs(sizeof_priv, name, name_assign_type, setup, count, \ 3547 count) 3548 3549 int register_netdev(struct net_device *dev); 3550 void unregister_netdev(struct net_device *dev); 3551 3552 /* General hardware address lists handling functions */ 3553 int __hw_addr_sync(struct netdev_hw_addr_list *to_list, 3554 struct netdev_hw_addr_list *from_list, int addr_len); 3555 void __hw_addr_unsync(struct netdev_hw_addr_list *to_list, 3556 struct netdev_hw_addr_list *from_list, int addr_len); 3557 int __hw_addr_sync_dev(struct netdev_hw_addr_list *list, 3558 struct net_device *dev, 3559 int (*sync)(struct net_device *, const unsigned char *), 3560 int (*unsync)(struct net_device *, 3561 const unsigned char *)); 3562 void __hw_addr_unsync_dev(struct netdev_hw_addr_list *list, 3563 struct net_device *dev, 3564 int (*unsync)(struct net_device *, 3565 const unsigned char *)); 3566 void __hw_addr_init(struct netdev_hw_addr_list *list); 3567 3568 /* Functions used for device addresses handling */ 3569 int dev_addr_add(struct net_device *dev, const unsigned char *addr, 3570 unsigned char addr_type); 3571 int dev_addr_del(struct net_device *dev, const unsigned char *addr, 3572 unsigned char addr_type); 3573 void dev_addr_flush(struct net_device *dev); 3574 int dev_addr_init(struct net_device *dev); 3575 3576 /* Functions used for unicast addresses handling */ 3577 int dev_uc_add(struct net_device *dev, const unsigned char *addr); 3578 int dev_uc_add_excl(struct net_device *dev, const unsigned char *addr); 3579 int dev_uc_del(struct net_device *dev, const unsigned char *addr); 3580 int dev_uc_sync(struct net_device *to, struct net_device *from); 3581 int dev_uc_sync_multiple(struct net_device *to, struct net_device *from); 3582 void dev_uc_unsync(struct net_device *to, struct net_device *from); 3583 void dev_uc_flush(struct net_device *dev); 3584 void dev_uc_init(struct net_device *dev); 3585 3586 /** 3587 * __dev_uc_sync - Synchonize device's unicast list 3588 * @dev: device to sync 3589 * @sync: function to call if address should be added 3590 * @unsync: function to call if address should be removed 3591 * 3592 * Add newly added addresses to the interface, and release 3593 * addresses that have been deleted. 3594 **/ 3595 static inline int __dev_uc_sync(struct net_device *dev, 3596 int (*sync)(struct net_device *, 3597 const unsigned char *), 3598 int (*unsync)(struct net_device *, 3599 const unsigned char *)) 3600 { 3601 return __hw_addr_sync_dev(&dev->uc, dev, sync, unsync); 3602 } 3603 3604 /** 3605 * __dev_uc_unsync - Remove synchronized addresses from device 3606 * @dev: device to sync 3607 * @unsync: function to call if address should be removed 3608 * 3609 * Remove all addresses that were added to the device by dev_uc_sync(). 3610 **/ 3611 static inline void __dev_uc_unsync(struct net_device *dev, 3612 int (*unsync)(struct net_device *, 3613 const unsigned char *)) 3614 { 3615 __hw_addr_unsync_dev(&dev->uc, dev, unsync); 3616 } 3617 3618 /* Functions used for multicast addresses handling */ 3619 int dev_mc_add(struct net_device *dev, const unsigned char *addr); 3620 int dev_mc_add_global(struct net_device *dev, const unsigned char *addr); 3621 int dev_mc_add_excl(struct net_device *dev, const unsigned char *addr); 3622 int dev_mc_del(struct net_device *dev, const unsigned char *addr); 3623 int dev_mc_del_global(struct net_device *dev, const unsigned char *addr); 3624 int dev_mc_sync(struct net_device *to, struct net_device *from); 3625 int dev_mc_sync_multiple(struct net_device *to, struct net_device *from); 3626 void dev_mc_unsync(struct net_device *to, struct net_device *from); 3627 void dev_mc_flush(struct net_device *dev); 3628 void dev_mc_init(struct net_device *dev); 3629 3630 /** 3631 * __dev_mc_sync - Synchonize device's multicast list 3632 * @dev: device to sync 3633 * @sync: function to call if address should be added 3634 * @unsync: function to call if address should be removed 3635 * 3636 * Add newly added addresses to the interface, and release 3637 * addresses that have been deleted. 3638 **/ 3639 static inline int __dev_mc_sync(struct net_device *dev, 3640 int (*sync)(struct net_device *, 3641 const unsigned char *), 3642 int (*unsync)(struct net_device *, 3643 const unsigned char *)) 3644 { 3645 return __hw_addr_sync_dev(&dev->mc, dev, sync, unsync); 3646 } 3647 3648 /** 3649 * __dev_mc_unsync - Remove synchronized addresses from device 3650 * @dev: device to sync 3651 * @unsync: function to call if address should be removed 3652 * 3653 * Remove all addresses that were added to the device by dev_mc_sync(). 3654 **/ 3655 static inline void __dev_mc_unsync(struct net_device *dev, 3656 int (*unsync)(struct net_device *, 3657 const unsigned char *)) 3658 { 3659 __hw_addr_unsync_dev(&dev->mc, dev, unsync); 3660 } 3661 3662 /* Functions used for secondary unicast and multicast support */ 3663 void dev_set_rx_mode(struct net_device *dev); 3664 void __dev_set_rx_mode(struct net_device *dev); 3665 int dev_set_promiscuity(struct net_device *dev, int inc); 3666 int dev_set_allmulti(struct net_device *dev, int inc); 3667 void netdev_state_change(struct net_device *dev); 3668 void netdev_notify_peers(struct net_device *dev); 3669 void netdev_features_change(struct net_device *dev); 3670 /* Load a device via the kmod */ 3671 void dev_load(struct net *net, const char *name); 3672 struct rtnl_link_stats64 *dev_get_stats(struct net_device *dev, 3673 struct rtnl_link_stats64 *storage); 3674 void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64, 3675 const struct net_device_stats *netdev_stats); 3676 3677 extern int netdev_max_backlog; 3678 extern int netdev_tstamp_prequeue; 3679 extern int weight_p; 3680 extern int bpf_jit_enable; 3681 3682 bool netdev_has_upper_dev(struct net_device *dev, struct net_device *upper_dev); 3683 struct net_device *netdev_upper_get_next_dev_rcu(struct net_device *dev, 3684 struct list_head **iter); 3685 struct net_device *netdev_all_upper_get_next_dev_rcu(struct net_device *dev, 3686 struct list_head **iter); 3687 3688 /* iterate through upper list, must be called under RCU read lock */ 3689 #define netdev_for_each_upper_dev_rcu(dev, updev, iter) \ 3690 for (iter = &(dev)->adj_list.upper, \ 3691 updev = netdev_upper_get_next_dev_rcu(dev, &(iter)); \ 3692 updev; \ 3693 updev = netdev_upper_get_next_dev_rcu(dev, &(iter))) 3694 3695 /* iterate through upper list, must be called under RCU read lock */ 3696 #define netdev_for_each_all_upper_dev_rcu(dev, updev, iter) \ 3697 for (iter = &(dev)->all_adj_list.upper, \ 3698 updev = netdev_all_upper_get_next_dev_rcu(dev, &(iter)); \ 3699 updev; \ 3700 updev = netdev_all_upper_get_next_dev_rcu(dev, &(iter))) 3701 3702 void *netdev_lower_get_next_private(struct net_device *dev, 3703 struct list_head **iter); 3704 void *netdev_lower_get_next_private_rcu(struct net_device *dev, 3705 struct list_head **iter); 3706 3707 #define netdev_for_each_lower_private(dev, priv, iter) \ 3708 for (iter = (dev)->adj_list.lower.next, \ 3709 priv = netdev_lower_get_next_private(dev, &(iter)); \ 3710 priv; \ 3711 priv = netdev_lower_get_next_private(dev, &(iter))) 3712 3713 #define netdev_for_each_lower_private_rcu(dev, priv, iter) \ 3714 for (iter = &(dev)->adj_list.lower, \ 3715 priv = netdev_lower_get_next_private_rcu(dev, &(iter)); \ 3716 priv; \ 3717 priv = netdev_lower_get_next_private_rcu(dev, &(iter))) 3718 3719 void *netdev_lower_get_next(struct net_device *dev, 3720 struct list_head **iter); 3721 #define netdev_for_each_lower_dev(dev, ldev, iter) \ 3722 for (iter = &(dev)->adj_list.lower, \ 3723 ldev = netdev_lower_get_next(dev, &(iter)); \ 3724 ldev; \ 3725 ldev = netdev_lower_get_next(dev, &(iter))) 3726 3727 void *netdev_adjacent_get_private(struct list_head *adj_list); 3728 void *netdev_lower_get_first_private_rcu(struct net_device *dev); 3729 struct net_device *netdev_master_upper_dev_get(struct net_device *dev); 3730 struct net_device *netdev_master_upper_dev_get_rcu(struct net_device *dev); 3731 int netdev_upper_dev_link(struct net_device *dev, struct net_device *upper_dev); 3732 int netdev_master_upper_dev_link(struct net_device *dev, 3733 struct net_device *upper_dev, 3734 void *upper_priv, void *upper_info); 3735 void netdev_upper_dev_unlink(struct net_device *dev, 3736 struct net_device *upper_dev); 3737 void netdev_adjacent_rename_links(struct net_device *dev, char *oldname); 3738 void *netdev_lower_dev_get_private(struct net_device *dev, 3739 struct net_device *lower_dev); 3740 void netdev_lower_state_changed(struct net_device *lower_dev, 3741 void *lower_state_info); 3742 3743 /* RSS keys are 40 or 52 bytes long */ 3744 #define NETDEV_RSS_KEY_LEN 52 3745 extern u8 netdev_rss_key[NETDEV_RSS_KEY_LEN]; 3746 void netdev_rss_key_fill(void *buffer, size_t len); 3747 3748 int dev_get_nest_level(struct net_device *dev, 3749 bool (*type_check)(const struct net_device *dev)); 3750 int skb_checksum_help(struct sk_buff *skb); 3751 struct sk_buff *__skb_gso_segment(struct sk_buff *skb, 3752 netdev_features_t features, bool tx_path); 3753 struct sk_buff *skb_mac_gso_segment(struct sk_buff *skb, 3754 netdev_features_t features); 3755 3756 struct netdev_bonding_info { 3757 ifslave slave; 3758 ifbond master; 3759 }; 3760 3761 struct netdev_notifier_bonding_info { 3762 struct netdev_notifier_info info; /* must be first */ 3763 struct netdev_bonding_info bonding_info; 3764 }; 3765 3766 void netdev_bonding_info_change(struct net_device *dev, 3767 struct netdev_bonding_info *bonding_info); 3768 3769 static inline 3770 struct sk_buff *skb_gso_segment(struct sk_buff *skb, netdev_features_t features) 3771 { 3772 return __skb_gso_segment(skb, features, true); 3773 } 3774 __be16 skb_network_protocol(struct sk_buff *skb, int *depth); 3775 3776 static inline bool can_checksum_protocol(netdev_features_t features, 3777 __be16 protocol) 3778 { 3779 if (protocol == htons(ETH_P_FCOE)) 3780 return !!(features & NETIF_F_FCOE_CRC); 3781 3782 /* Assume this is an IP checksum (not SCTP CRC) */ 3783 3784 if (features & NETIF_F_HW_CSUM) { 3785 /* Can checksum everything */ 3786 return true; 3787 } 3788 3789 switch (protocol) { 3790 case htons(ETH_P_IP): 3791 return !!(features & NETIF_F_IP_CSUM); 3792 case htons(ETH_P_IPV6): 3793 return !!(features & NETIF_F_IPV6_CSUM); 3794 default: 3795 return false; 3796 } 3797 } 3798 3799 /* Map an ethertype into IP protocol if possible */ 3800 static inline int eproto_to_ipproto(int eproto) 3801 { 3802 switch (eproto) { 3803 case htons(ETH_P_IP): 3804 return IPPROTO_IP; 3805 case htons(ETH_P_IPV6): 3806 return IPPROTO_IPV6; 3807 default: 3808 return -1; 3809 } 3810 } 3811 3812 #ifdef CONFIG_BUG 3813 void netdev_rx_csum_fault(struct net_device *dev); 3814 #else 3815 static inline void netdev_rx_csum_fault(struct net_device *dev) 3816 { 3817 } 3818 #endif 3819 /* rx skb timestamps */ 3820 void net_enable_timestamp(void); 3821 void net_disable_timestamp(void); 3822 3823 #ifdef CONFIG_PROC_FS 3824 int __init dev_proc_init(void); 3825 #else 3826 #define dev_proc_init() 0 3827 #endif 3828 3829 static inline netdev_tx_t __netdev_start_xmit(const struct net_device_ops *ops, 3830 struct sk_buff *skb, struct net_device *dev, 3831 bool more) 3832 { 3833 skb->xmit_more = more ? 1 : 0; 3834 return ops->ndo_start_xmit(skb, dev); 3835 } 3836 3837 static inline netdev_tx_t netdev_start_xmit(struct sk_buff *skb, struct net_device *dev, 3838 struct netdev_queue *txq, bool more) 3839 { 3840 const struct net_device_ops *ops = dev->netdev_ops; 3841 int rc; 3842 3843 rc = __netdev_start_xmit(ops, skb, dev, more); 3844 if (rc == NETDEV_TX_OK) 3845 txq_trans_update(txq); 3846 3847 return rc; 3848 } 3849 3850 int netdev_class_create_file_ns(struct class_attribute *class_attr, 3851 const void *ns); 3852 void netdev_class_remove_file_ns(struct class_attribute *class_attr, 3853 const void *ns); 3854 3855 static inline int netdev_class_create_file(struct class_attribute *class_attr) 3856 { 3857 return netdev_class_create_file_ns(class_attr, NULL); 3858 } 3859 3860 static inline void netdev_class_remove_file(struct class_attribute *class_attr) 3861 { 3862 netdev_class_remove_file_ns(class_attr, NULL); 3863 } 3864 3865 extern struct kobj_ns_type_operations net_ns_type_operations; 3866 3867 const char *netdev_drivername(const struct net_device *dev); 3868 3869 void linkwatch_run_queue(void); 3870 3871 static inline netdev_features_t netdev_intersect_features(netdev_features_t f1, 3872 netdev_features_t f2) 3873 { 3874 if ((f1 ^ f2) & NETIF_F_HW_CSUM) { 3875 if (f1 & NETIF_F_HW_CSUM) 3876 f1 |= (NETIF_F_IP_CSUM|NETIF_F_IPV6_CSUM); 3877 else 3878 f2 |= (NETIF_F_IP_CSUM|NETIF_F_IPV6_CSUM); 3879 } 3880 3881 return f1 & f2; 3882 } 3883 3884 static inline netdev_features_t netdev_get_wanted_features( 3885 struct net_device *dev) 3886 { 3887 return (dev->features & ~dev->hw_features) | dev->wanted_features; 3888 } 3889 netdev_features_t netdev_increment_features(netdev_features_t all, 3890 netdev_features_t one, netdev_features_t mask); 3891 3892 /* Allow TSO being used on stacked device : 3893 * Performing the GSO segmentation before last device 3894 * is a performance improvement. 3895 */ 3896 static inline netdev_features_t netdev_add_tso_features(netdev_features_t features, 3897 netdev_features_t mask) 3898 { 3899 return netdev_increment_features(features, NETIF_F_ALL_TSO, mask); 3900 } 3901 3902 int __netdev_update_features(struct net_device *dev); 3903 void netdev_update_features(struct net_device *dev); 3904 void netdev_change_features(struct net_device *dev); 3905 3906 void netif_stacked_transfer_operstate(const struct net_device *rootdev, 3907 struct net_device *dev); 3908 3909 netdev_features_t passthru_features_check(struct sk_buff *skb, 3910 struct net_device *dev, 3911 netdev_features_t features); 3912 netdev_features_t netif_skb_features(struct sk_buff *skb); 3913 3914 static inline bool net_gso_ok(netdev_features_t features, int gso_type) 3915 { 3916 netdev_features_t feature = gso_type << NETIF_F_GSO_SHIFT; 3917 3918 /* check flags correspondence */ 3919 BUILD_BUG_ON(SKB_GSO_TCPV4 != (NETIF_F_TSO >> NETIF_F_GSO_SHIFT)); 3920 BUILD_BUG_ON(SKB_GSO_UDP != (NETIF_F_UFO >> NETIF_F_GSO_SHIFT)); 3921 BUILD_BUG_ON(SKB_GSO_DODGY != (NETIF_F_GSO_ROBUST >> NETIF_F_GSO_SHIFT)); 3922 BUILD_BUG_ON(SKB_GSO_TCP_ECN != (NETIF_F_TSO_ECN >> NETIF_F_GSO_SHIFT)); 3923 BUILD_BUG_ON(SKB_GSO_TCPV6 != (NETIF_F_TSO6 >> NETIF_F_GSO_SHIFT)); 3924 BUILD_BUG_ON(SKB_GSO_FCOE != (NETIF_F_FSO >> NETIF_F_GSO_SHIFT)); 3925 BUILD_BUG_ON(SKB_GSO_GRE != (NETIF_F_GSO_GRE >> NETIF_F_GSO_SHIFT)); 3926 BUILD_BUG_ON(SKB_GSO_GRE_CSUM != (NETIF_F_GSO_GRE_CSUM >> NETIF_F_GSO_SHIFT)); 3927 BUILD_BUG_ON(SKB_GSO_IPIP != (NETIF_F_GSO_IPIP >> NETIF_F_GSO_SHIFT)); 3928 BUILD_BUG_ON(SKB_GSO_SIT != (NETIF_F_GSO_SIT >> NETIF_F_GSO_SHIFT)); 3929 BUILD_BUG_ON(SKB_GSO_UDP_TUNNEL != (NETIF_F_GSO_UDP_TUNNEL >> NETIF_F_GSO_SHIFT)); 3930 BUILD_BUG_ON(SKB_GSO_UDP_TUNNEL_CSUM != (NETIF_F_GSO_UDP_TUNNEL_CSUM >> NETIF_F_GSO_SHIFT)); 3931 BUILD_BUG_ON(SKB_GSO_TUNNEL_REMCSUM != (NETIF_F_GSO_TUNNEL_REMCSUM >> NETIF_F_GSO_SHIFT)); 3932 3933 return (features & feature) == feature; 3934 } 3935 3936 static inline bool skb_gso_ok(struct sk_buff *skb, netdev_features_t features) 3937 { 3938 return net_gso_ok(features, skb_shinfo(skb)->gso_type) && 3939 (!skb_has_frag_list(skb) || (features & NETIF_F_FRAGLIST)); 3940 } 3941 3942 static inline bool netif_needs_gso(struct sk_buff *skb, 3943 netdev_features_t features) 3944 { 3945 return skb_is_gso(skb) && (!skb_gso_ok(skb, features) || 3946 unlikely((skb->ip_summed != CHECKSUM_PARTIAL) && 3947 (skb->ip_summed != CHECKSUM_UNNECESSARY))); 3948 } 3949 3950 static inline void netif_set_gso_max_size(struct net_device *dev, 3951 unsigned int size) 3952 { 3953 dev->gso_max_size = size; 3954 } 3955 3956 static inline void skb_gso_error_unwind(struct sk_buff *skb, __be16 protocol, 3957 int pulled_hlen, u16 mac_offset, 3958 int mac_len) 3959 { 3960 skb->protocol = protocol; 3961 skb->encapsulation = 1; 3962 skb_push(skb, pulled_hlen); 3963 skb_reset_transport_header(skb); 3964 skb->mac_header = mac_offset; 3965 skb->network_header = skb->mac_header + mac_len; 3966 skb->mac_len = mac_len; 3967 } 3968 3969 static inline bool netif_is_macvlan(const struct net_device *dev) 3970 { 3971 return dev->priv_flags & IFF_MACVLAN; 3972 } 3973 3974 static inline bool netif_is_macvlan_port(const struct net_device *dev) 3975 { 3976 return dev->priv_flags & IFF_MACVLAN_PORT; 3977 } 3978 3979 static inline bool netif_is_ipvlan(const struct net_device *dev) 3980 { 3981 return dev->priv_flags & IFF_IPVLAN_SLAVE; 3982 } 3983 3984 static inline bool netif_is_ipvlan_port(const struct net_device *dev) 3985 { 3986 return dev->priv_flags & IFF_IPVLAN_MASTER; 3987 } 3988 3989 static inline bool netif_is_bond_master(const struct net_device *dev) 3990 { 3991 return dev->flags & IFF_MASTER && dev->priv_flags & IFF_BONDING; 3992 } 3993 3994 static inline bool netif_is_bond_slave(const struct net_device *dev) 3995 { 3996 return dev->flags & IFF_SLAVE && dev->priv_flags & IFF_BONDING; 3997 } 3998 3999 static inline bool netif_supports_nofcs(struct net_device *dev) 4000 { 4001 return dev->priv_flags & IFF_SUPP_NOFCS; 4002 } 4003 4004 static inline bool netif_is_l3_master(const struct net_device *dev) 4005 { 4006 return dev->priv_flags & IFF_L3MDEV_MASTER; 4007 } 4008 4009 static inline bool netif_is_l3_slave(const struct net_device *dev) 4010 { 4011 return dev->priv_flags & IFF_L3MDEV_SLAVE; 4012 } 4013 4014 static inline bool netif_is_bridge_master(const struct net_device *dev) 4015 { 4016 return dev->priv_flags & IFF_EBRIDGE; 4017 } 4018 4019 static inline bool netif_is_bridge_port(const struct net_device *dev) 4020 { 4021 return dev->priv_flags & IFF_BRIDGE_PORT; 4022 } 4023 4024 static inline bool netif_is_ovs_master(const struct net_device *dev) 4025 { 4026 return dev->priv_flags & IFF_OPENVSWITCH; 4027 } 4028 4029 static inline bool netif_is_team_master(const struct net_device *dev) 4030 { 4031 return dev->priv_flags & IFF_TEAM; 4032 } 4033 4034 static inline bool netif_is_team_port(const struct net_device *dev) 4035 { 4036 return dev->priv_flags & IFF_TEAM_PORT; 4037 } 4038 4039 static inline bool netif_is_lag_master(const struct net_device *dev) 4040 { 4041 return netif_is_bond_master(dev) || netif_is_team_master(dev); 4042 } 4043 4044 static inline bool netif_is_lag_port(const struct net_device *dev) 4045 { 4046 return netif_is_bond_slave(dev) || netif_is_team_port(dev); 4047 } 4048 4049 /* This device needs to keep skb dst for qdisc enqueue or ndo_start_xmit() */ 4050 static inline void netif_keep_dst(struct net_device *dev) 4051 { 4052 dev->priv_flags &= ~(IFF_XMIT_DST_RELEASE | IFF_XMIT_DST_RELEASE_PERM); 4053 } 4054 4055 extern struct pernet_operations __net_initdata loopback_net_ops; 4056 4057 /* Logging, debugging and troubleshooting/diagnostic helpers. */ 4058 4059 /* netdev_printk helpers, similar to dev_printk */ 4060 4061 static inline const char *netdev_name(const struct net_device *dev) 4062 { 4063 if (!dev->name[0] || strchr(dev->name, '%')) 4064 return "(unnamed net_device)"; 4065 return dev->name; 4066 } 4067 4068 static inline const char *netdev_reg_state(const struct net_device *dev) 4069 { 4070 switch (dev->reg_state) { 4071 case NETREG_UNINITIALIZED: return " (uninitialized)"; 4072 case NETREG_REGISTERED: return ""; 4073 case NETREG_UNREGISTERING: return " (unregistering)"; 4074 case NETREG_UNREGISTERED: return " (unregistered)"; 4075 case NETREG_RELEASED: return " (released)"; 4076 case NETREG_DUMMY: return " (dummy)"; 4077 } 4078 4079 WARN_ONCE(1, "%s: unknown reg_state %d\n", dev->name, dev->reg_state); 4080 return " (unknown)"; 4081 } 4082 4083 __printf(3, 4) 4084 void netdev_printk(const char *level, const struct net_device *dev, 4085 const char *format, ...); 4086 __printf(2, 3) 4087 void netdev_emerg(const struct net_device *dev, const char *format, ...); 4088 __printf(2, 3) 4089 void netdev_alert(const struct net_device *dev, const char *format, ...); 4090 __printf(2, 3) 4091 void netdev_crit(const struct net_device *dev, const char *format, ...); 4092 __printf(2, 3) 4093 void netdev_err(const struct net_device *dev, const char *format, ...); 4094 __printf(2, 3) 4095 void netdev_warn(const struct net_device *dev, const char *format, ...); 4096 __printf(2, 3) 4097 void netdev_notice(const struct net_device *dev, const char *format, ...); 4098 __printf(2, 3) 4099 void netdev_info(const struct net_device *dev, const char *format, ...); 4100 4101 #define MODULE_ALIAS_NETDEV(device) \ 4102 MODULE_ALIAS("netdev-" device) 4103 4104 #if defined(CONFIG_DYNAMIC_DEBUG) 4105 #define netdev_dbg(__dev, format, args...) \ 4106 do { \ 4107 dynamic_netdev_dbg(__dev, format, ##args); \ 4108 } while (0) 4109 #elif defined(DEBUG) 4110 #define netdev_dbg(__dev, format, args...) \ 4111 netdev_printk(KERN_DEBUG, __dev, format, ##args) 4112 #else 4113 #define netdev_dbg(__dev, format, args...) \ 4114 ({ \ 4115 if (0) \ 4116 netdev_printk(KERN_DEBUG, __dev, format, ##args); \ 4117 }) 4118 #endif 4119 4120 #if defined(VERBOSE_DEBUG) 4121 #define netdev_vdbg netdev_dbg 4122 #else 4123 4124 #define netdev_vdbg(dev, format, args...) \ 4125 ({ \ 4126 if (0) \ 4127 netdev_printk(KERN_DEBUG, dev, format, ##args); \ 4128 0; \ 4129 }) 4130 #endif 4131 4132 /* 4133 * netdev_WARN() acts like dev_printk(), but with the key difference 4134 * of using a WARN/WARN_ON to get the message out, including the 4135 * file/line information and a backtrace. 4136 */ 4137 #define netdev_WARN(dev, format, args...) \ 4138 WARN(1, "netdevice: %s%s\n" format, netdev_name(dev), \ 4139 netdev_reg_state(dev), ##args) 4140 4141 /* netif printk helpers, similar to netdev_printk */ 4142 4143 #define netif_printk(priv, type, level, dev, fmt, args...) \ 4144 do { \ 4145 if (netif_msg_##type(priv)) \ 4146 netdev_printk(level, (dev), fmt, ##args); \ 4147 } while (0) 4148 4149 #define netif_level(level, priv, type, dev, fmt, args...) \ 4150 do { \ 4151 if (netif_msg_##type(priv)) \ 4152 netdev_##level(dev, fmt, ##args); \ 4153 } while (0) 4154 4155 #define netif_emerg(priv, type, dev, fmt, args...) \ 4156 netif_level(emerg, priv, type, dev, fmt, ##args) 4157 #define netif_alert(priv, type, dev, fmt, args...) \ 4158 netif_level(alert, priv, type, dev, fmt, ##args) 4159 #define netif_crit(priv, type, dev, fmt, args...) \ 4160 netif_level(crit, priv, type, dev, fmt, ##args) 4161 #define netif_err(priv, type, dev, fmt, args...) \ 4162 netif_level(err, priv, type, dev, fmt, ##args) 4163 #define netif_warn(priv, type, dev, fmt, args...) \ 4164 netif_level(warn, priv, type, dev, fmt, ##args) 4165 #define netif_notice(priv, type, dev, fmt, args...) \ 4166 netif_level(notice, priv, type, dev, fmt, ##args) 4167 #define netif_info(priv, type, dev, fmt, args...) \ 4168 netif_level(info, priv, type, dev, fmt, ##args) 4169 4170 #if defined(CONFIG_DYNAMIC_DEBUG) 4171 #define netif_dbg(priv, type, netdev, format, args...) \ 4172 do { \ 4173 if (netif_msg_##type(priv)) \ 4174 dynamic_netdev_dbg(netdev, format, ##args); \ 4175 } while (0) 4176 #elif defined(DEBUG) 4177 #define netif_dbg(priv, type, dev, format, args...) \ 4178 netif_printk(priv, type, KERN_DEBUG, dev, format, ##args) 4179 #else 4180 #define netif_dbg(priv, type, dev, format, args...) \ 4181 ({ \ 4182 if (0) \ 4183 netif_printk(priv, type, KERN_DEBUG, dev, format, ##args); \ 4184 0; \ 4185 }) 4186 #endif 4187 4188 #if defined(VERBOSE_DEBUG) 4189 #define netif_vdbg netif_dbg 4190 #else 4191 #define netif_vdbg(priv, type, dev, format, args...) \ 4192 ({ \ 4193 if (0) \ 4194 netif_printk(priv, type, KERN_DEBUG, dev, format, ##args); \ 4195 0; \ 4196 }) 4197 #endif 4198 4199 /* 4200 * The list of packet types we will receive (as opposed to discard) 4201 * and the routines to invoke. 4202 * 4203 * Why 16. Because with 16 the only overlap we get on a hash of the 4204 * low nibble of the protocol value is RARP/SNAP/X.25. 4205 * 4206 * NOTE: That is no longer true with the addition of VLAN tags. Not 4207 * sure which should go first, but I bet it won't make much 4208 * difference if we are running VLANs. The good news is that 4209 * this protocol won't be in the list unless compiled in, so 4210 * the average user (w/out VLANs) will not be adversely affected. 4211 * --BLG 4212 * 4213 * 0800 IP 4214 * 8100 802.1Q VLAN 4215 * 0001 802.3 4216 * 0002 AX.25 4217 * 0004 802.2 4218 * 8035 RARP 4219 * 0005 SNAP 4220 * 0805 X.25 4221 * 0806 ARP 4222 * 8137 IPX 4223 * 0009 Localtalk 4224 * 86DD IPv6 4225 */ 4226 #define PTYPE_HASH_SIZE (16) 4227 #define PTYPE_HASH_MASK (PTYPE_HASH_SIZE - 1) 4228 4229 #endif /* _LINUX_NETDEVICE_H */
1 /* 2 * Written by Mark Hemment, 1996 (markhe@nextd.demon.co.uk). 3 * 4 * (C) SGI 2006, Christoph Lameter 5 * Cleaned up and restructured to ease the addition of alternative 6 * implementations of SLAB allocators. 7 * (C) Linux Foundation 2008-2013 8 * Unified interface for all slab allocators 9 */ 10 11 #ifndef _LINUX_SLAB_H 12 #define _LINUX_SLAB_H 13 14 #include <linux/gfp.h> 15 #include <linux/types.h> 16 #include <linux/workqueue.h> 17 18 19 /* 20 * Flags to pass to kmem_cache_create(). 21 * The ones marked DEBUG are only valid if CONFIG_DEBUG_SLAB is set. 22 */ 23 #define SLAB_DEBUG_FREE 0x00000100UL /* DEBUG: Perform (expensive) checks on free */ 24 #define SLAB_RED_ZONE 0x00000400UL /* DEBUG: Red zone objs in a cache */ 25 #define SLAB_POISON 0x00000800UL /* DEBUG: Poison objects */ 26 #define SLAB_HWCACHE_ALIGN 0x00002000UL /* Align objs on cache lines */ 27 #define SLAB_CACHE_DMA 0x00004000UL /* Use GFP_DMA memory */ 28 #define SLAB_STORE_USER 0x00010000UL /* DEBUG: Store the last owner for bug hunting */ 29 #define SLAB_PANIC 0x00040000UL /* Panic if kmem_cache_create() fails */ 30 /* 31 * SLAB_DESTROY_BY_RCU - **WARNING** READ THIS! 32 * 33 * This delays freeing the SLAB page by a grace period, it does _NOT_ 34 * delay object freeing. This means that if you do kmem_cache_free() 35 * that memory location is free to be reused at any time. Thus it may 36 * be possible to see another object there in the same RCU grace period. 37 * 38 * This feature only ensures the memory location backing the object 39 * stays valid, the trick to using this is relying on an independent 40 * object validation pass. Something like: 41 * 42 * rcu_read_lock() 43 * again: 44 * obj = lockless_lookup(key); 45 * if (obj) { 46 * if (!try_get_ref(obj)) // might fail for free objects 47 * goto again; 48 * 49 * if (obj->key != key) { // not the object we expected 50 * put_ref(obj); 51 * goto again; 52 * } 53 * } 54 * rcu_read_unlock(); 55 * 56 * This is useful if we need to approach a kernel structure obliquely, 57 * from its address obtained without the usual locking. We can lock 58 * the structure to stabilize it and check it's still at the given address, 59 * only if we can be sure that the memory has not been meanwhile reused 60 * for some other kind of object (which our subsystem's lock might corrupt). 61 * 62 * rcu_read_lock before reading the address, then rcu_read_unlock after 63 * taking the spinlock within the structure expected at that address. 64 */ 65 #define SLAB_DESTROY_BY_RCU 0x00080000UL /* Defer freeing slabs to RCU */ 66 #define SLAB_MEM_SPREAD 0x00100000UL /* Spread some memory over cpuset */ 67 #define SLAB_TRACE 0x00200000UL /* Trace allocations and frees */ 68 69 /* Flag to prevent checks on free */ 70 #ifdef CONFIG_DEBUG_OBJECTS 71 # define SLAB_DEBUG_OBJECTS 0x00400000UL 72 #else 73 # define SLAB_DEBUG_OBJECTS 0x00000000UL 74 #endif 75 76 #define SLAB_NOLEAKTRACE 0x00800000UL /* Avoid kmemleak tracing */ 77 78 /* Don't track use of uninitialized memory */ 79 #ifdef CONFIG_KMEMCHECK 80 # define SLAB_NOTRACK 0x01000000UL 81 #else 82 # define SLAB_NOTRACK 0x00000000UL 83 #endif 84 #ifdef CONFIG_FAILSLAB 85 # define SLAB_FAILSLAB 0x02000000UL /* Fault injection mark */ 86 #else 87 # define SLAB_FAILSLAB 0x00000000UL 88 #endif 89 #if defined(CONFIG_MEMCG) && !defined(CONFIG_SLOB) 90 # define SLAB_ACCOUNT 0x04000000UL /* Account to memcg */ 91 #else 92 # define SLAB_ACCOUNT 0x00000000UL 93 #endif 94 95 /* The following flags affect the page allocator grouping pages by mobility */ 96 #define SLAB_RECLAIM_ACCOUNT 0x00020000UL /* Objects are reclaimable */ 97 #define SLAB_TEMPORARY SLAB_RECLAIM_ACCOUNT /* Objects are short-lived */ 98 /* 99 * ZERO_SIZE_PTR will be returned for zero sized kmalloc requests. 100 * 101 * Dereferencing ZERO_SIZE_PTR will lead to a distinct access fault. 102 * 103 * ZERO_SIZE_PTR can be passed to kfree though in the same way that NULL can. 104 * Both make kfree a no-op. 105 */ 106 #define ZERO_SIZE_PTR ((void *)16) 107 108 #define ZERO_OR_NULL_PTR(x) ((unsigned long)(x) <= \ 109 (unsigned long)ZERO_SIZE_PTR) 110 111 #include <linux/kmemleak.h> 112 #include <linux/kasan.h> 113 114 struct mem_cgroup; 115 /* 116 * struct kmem_cache related prototypes 117 */ 118 void __init kmem_cache_init(void); 119 bool slab_is_available(void); 120 121 struct kmem_cache *kmem_cache_create(const char *, size_t, size_t, 122 unsigned long, 123 void (*)(void *)); 124 void kmem_cache_destroy(struct kmem_cache *); 125 int kmem_cache_shrink(struct kmem_cache *); 126 127 void memcg_create_kmem_cache(struct mem_cgroup *, struct kmem_cache *); 128 void memcg_deactivate_kmem_caches(struct mem_cgroup *); 129 void memcg_destroy_kmem_caches(struct mem_cgroup *); 130 131 /* 132 * Please use this macro to create slab caches. Simply specify the 133 * name of the structure and maybe some flags that are listed above. 134 * 135 * The alignment of the struct determines object alignment. If you 136 * f.e. add ____cacheline_aligned_in_smp to the struct declaration 137 * then the objects will be properly aligned in SMP configurations. 138 */ 139 #define KMEM_CACHE(__struct, __flags) kmem_cache_create(#__struct,\ 140 sizeof(struct __struct), __alignof__(struct __struct),\ 141 (__flags), NULL) 142 143 /* 144 * Common kmalloc functions provided by all allocators 145 */ 146 void * __must_check __krealloc(const void *, size_t, gfp_t); 147 void * __must_check krealloc(const void *, size_t, gfp_t); 148 void kfree(const void *); 149 void kzfree(const void *); 150 size_t ksize(const void *); 151 152 /* 153 * Some archs want to perform DMA into kmalloc caches and need a guaranteed 154 * alignment larger than the alignment of a 64-bit integer. 155 * Setting ARCH_KMALLOC_MINALIGN in arch headers allows that. 156 */ 157 #if defined(ARCH_DMA_MINALIGN) && ARCH_DMA_MINALIGN > 8 158 #define ARCH_KMALLOC_MINALIGN ARCH_DMA_MINALIGN 159 #define KMALLOC_MIN_SIZE ARCH_DMA_MINALIGN 160 #define KMALLOC_SHIFT_LOW ilog2(ARCH_DMA_MINALIGN) 161 #else 162 #define ARCH_KMALLOC_MINALIGN __alignof__(unsigned long long) 163 #endif 164 165 /* 166 * Setting ARCH_SLAB_MINALIGN in arch headers allows a different alignment. 167 * Intended for arches that get misalignment faults even for 64 bit integer 168 * aligned buffers. 169 */ 170 #ifndef ARCH_SLAB_MINALIGN 171 #define ARCH_SLAB_MINALIGN __alignof__(unsigned long long) 172 #endif 173 174 /* 175 * kmalloc and friends return ARCH_KMALLOC_MINALIGN aligned 176 * pointers. kmem_cache_alloc and friends return ARCH_SLAB_MINALIGN 177 * aligned pointers. 178 */ 179 #define __assume_kmalloc_alignment __assume_aligned(ARCH_KMALLOC_MINALIGN) 180 #define __assume_slab_alignment __assume_aligned(ARCH_SLAB_MINALIGN) 181 #define __assume_page_alignment __assume_aligned(PAGE_SIZE) 182 183 /* 184 * Kmalloc array related definitions 185 */ 186 187 #ifdef CONFIG_SLAB 188 /* 189 * The largest kmalloc size supported by the SLAB allocators is 190 * 32 megabyte (2^25) or the maximum allocatable page order if that is 191 * less than 32 MB. 192 * 193 * WARNING: Its not easy to increase this value since the allocators have 194 * to do various tricks to work around compiler limitations in order to 195 * ensure proper constant folding. 196 */ 197 #define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 25 ? \ 198 (MAX_ORDER + PAGE_SHIFT - 1) : 25) 199 #define KMALLOC_SHIFT_MAX KMALLOC_SHIFT_HIGH 200 #ifndef KMALLOC_SHIFT_LOW 201 #define KMALLOC_SHIFT_LOW 5 202 #endif 203 #endif 204 205 #ifdef CONFIG_SLUB 206 /* 207 * SLUB directly allocates requests fitting in to an order-1 page 208 * (PAGE_SIZE*2). Larger requests are passed to the page allocator. 209 */ 210 #define KMALLOC_SHIFT_HIGH (PAGE_SHIFT + 1) 211 #define KMALLOC_SHIFT_MAX (MAX_ORDER + PAGE_SHIFT) 212 #ifndef KMALLOC_SHIFT_LOW 213 #define KMALLOC_SHIFT_LOW 3 214 #endif 215 #endif 216 217 #ifdef CONFIG_SLOB 218 /* 219 * SLOB passes all requests larger than one page to the page allocator. 220 * No kmalloc array is necessary since objects of different sizes can 221 * be allocated from the same page. 222 */ 223 #define KMALLOC_SHIFT_HIGH PAGE_SHIFT 224 #define KMALLOC_SHIFT_MAX 30 225 #ifndef KMALLOC_SHIFT_LOW 226 #define KMALLOC_SHIFT_LOW 3 227 #endif 228 #endif 229 230 /* Maximum allocatable size */ 231 #define KMALLOC_MAX_SIZE (1UL << KMALLOC_SHIFT_MAX) 232 /* Maximum size for which we actually use a slab cache */ 233 #define KMALLOC_MAX_CACHE_SIZE (1UL << KMALLOC_SHIFT_HIGH) 234 /* Maximum order allocatable via the slab allocagtor */ 235 #define KMALLOC_MAX_ORDER (KMALLOC_SHIFT_MAX - PAGE_SHIFT) 236 237 /* 238 * Kmalloc subsystem. 239 */ 240 #ifndef KMALLOC_MIN_SIZE 241 #define KMALLOC_MIN_SIZE (1 << KMALLOC_SHIFT_LOW) 242 #endif 243 244 /* 245 * This restriction comes from byte sized index implementation. 246 * Page size is normally 2^12 bytes and, in this case, if we want to use 247 * byte sized index which can represent 2^8 entries, the size of the object 248 * should be equal or greater to 2^12 / 2^8 = 2^4 = 16. 249 * If minimum size of kmalloc is less than 16, we use it as minimum object 250 * size and give up to use byte sized index. 251 */ 252 #define SLAB_OBJ_MIN_SIZE (KMALLOC_MIN_SIZE < 16 ? \ 253 (KMALLOC_MIN_SIZE) : 16) 254 255 #ifndef CONFIG_SLOB 256 extern struct kmem_cache *kmalloc_caches[KMALLOC_SHIFT_HIGH + 1]; 257 #ifdef CONFIG_ZONE_DMA 258 extern struct kmem_cache *kmalloc_dma_caches[KMALLOC_SHIFT_HIGH + 1]; 259 #endif 260 261 /* 262 * Figure out which kmalloc slab an allocation of a certain size 263 * belongs to. 264 * 0 = zero alloc 265 * 1 = 65 .. 96 bytes 266 * 2 = 129 .. 192 bytes 267 * n = 2^(n-1)+1 .. 2^n 268 */ 269 static __always_inline int kmalloc_index(size_t size) 270 { 271 if (!size) 272 return 0; 273 274 if (size <= KMALLOC_MIN_SIZE) 275 return KMALLOC_SHIFT_LOW; 276 277 if (KMALLOC_MIN_SIZE <= 32 && size > 64 && size <= 96) 278 return 1; 279 if (KMALLOC_MIN_SIZE <= 64 && size > 128 && size <= 192) 280 return 2; 281 if (size <= 8) return 3; 282 if (size <= 16) return 4; 283 if (size <= 32) return 5; 284 if (size <= 64) return 6; 285 if (size <= 128) return 7; 286 if (size <= 256) return 8; 287 if (size <= 512) return 9; 288 if (size <= 1024) return 10; 289 if (size <= 2 * 1024) return 11; 290 if (size <= 4 * 1024) return 12; 291 if (size <= 8 * 1024) return 13; 292 if (size <= 16 * 1024) return 14; 293 if (size <= 32 * 1024) return 15; 294 if (size <= 64 * 1024) return 16; 295 if (size <= 128 * 1024) return 17; 296 if (size <= 256 * 1024) return 18; 297 if (size <= 512 * 1024) return 19; 298 if (size <= 1024 * 1024) return 20; 299 if (size <= 2 * 1024 * 1024) return 21; 300 if (size <= 4 * 1024 * 1024) return 22; 301 if (size <= 8 * 1024 * 1024) return 23; 302 if (size <= 16 * 1024 * 1024) return 24; 303 if (size <= 32 * 1024 * 1024) return 25; 304 if (size <= 64 * 1024 * 1024) return 26; 305 BUG(); 306 307 /* Will never be reached. Needed because the compiler may complain */ 308 return -1; 309 } 310 #endif /* !CONFIG_SLOB */ 311 312 void *__kmalloc(size_t size, gfp_t flags) __assume_kmalloc_alignment; 313 void *kmem_cache_alloc(struct kmem_cache *, gfp_t flags) __assume_slab_alignment; 314 void kmem_cache_free(struct kmem_cache *, void *); 315 316 /* 317 * Bulk allocation and freeing operations. These are accellerated in an 318 * allocator specific way to avoid taking locks repeatedly or building 319 * metadata structures unnecessarily. 320 * 321 * Note that interrupts must be enabled when calling these functions. 322 */ 323 void kmem_cache_free_bulk(struct kmem_cache *, size_t, void **); 324 int kmem_cache_alloc_bulk(struct kmem_cache *, gfp_t, size_t, void **); 325 326 #ifdef CONFIG_NUMA 327 void *__kmalloc_node(size_t size, gfp_t flags, int node) __assume_kmalloc_alignment; 328 void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node) __assume_slab_alignment; 329 #else 330 static __always_inline void *__kmalloc_node(size_t size, gfp_t flags, int node) 331 { 332 return __kmalloc(size, flags); 333 } 334 335 static __always_inline void *kmem_cache_alloc_node(struct kmem_cache *s, gfp_t flags, int node) 336 { 337 return kmem_cache_alloc(s, flags); 338 } 339 #endif 340 341 #ifdef CONFIG_TRACING 342 extern void *kmem_cache_alloc_trace(struct kmem_cache *, gfp_t, size_t) __assume_slab_alignment; 343 344 #ifdef CONFIG_NUMA 345 extern void *kmem_cache_alloc_node_trace(struct kmem_cache *s, 346 gfp_t gfpflags, 347 int node, size_t size) __assume_slab_alignment; 348 #else 349 static __always_inline void * 350 kmem_cache_alloc_node_trace(struct kmem_cache *s, 351 gfp_t gfpflags, 352 int node, size_t size) 353 { 354 return kmem_cache_alloc_trace(s, gfpflags, size); 355 } 356 #endif /* CONFIG_NUMA */ 357 358 #else /* CONFIG_TRACING */ 359 static __always_inline void *kmem_cache_alloc_trace(struct kmem_cache *s, 360 gfp_t flags, size_t size) 361 { 362 void *ret = kmem_cache_alloc(s, flags); 363 364 kasan_kmalloc(s, ret, size); 365 return ret; 366 } 367 368 static __always_inline void * 369 kmem_cache_alloc_node_trace(struct kmem_cache *s, 370 gfp_t gfpflags, 371 int node, size_t size) 372 { 373 void *ret = kmem_cache_alloc_node(s, gfpflags, node); 374 375 kasan_kmalloc(s, ret, size); 376 return ret; 377 } 378 #endif /* CONFIG_TRACING */ 379 380 extern void *kmalloc_order(size_t size, gfp_t flags, unsigned int order) __assume_page_alignment; 381 382 #ifdef CONFIG_TRACING 383 extern void *kmalloc_order_trace(size_t size, gfp_t flags, unsigned int order) __assume_page_alignment; 384 #else 385 static __always_inline void * 386 kmalloc_order_trace(size_t size, gfp_t flags, unsigned int order) 387 { 388 return kmalloc_order(size, flags, order); 389 } 390 #endif 391 392 static __always_inline void *kmalloc_large(size_t size, gfp_t flags) 393 { 394 unsigned int order = get_order(size); 395 return kmalloc_order_trace(size, flags, order); 396 } 397 398 /** 399 * kmalloc - allocate memory 400 * @size: how many bytes of memory are required. 401 * @flags: the type of memory to allocate. 402 * 403 * kmalloc is the normal method of allocating memory 404 * for objects smaller than page size in the kernel. 405 * 406 * The @flags argument may be one of: 407 * 408 * %GFP_USER - Allocate memory on behalf of user. May sleep. 409 * 410 * %GFP_KERNEL - Allocate normal kernel ram. May sleep. 411 * 412 * %GFP_ATOMIC - Allocation will not sleep. May use emergency pools. 413 * For example, use this inside interrupt handlers. 414 * 415 * %GFP_HIGHUSER - Allocate pages from high memory. 416 * 417 * %GFP_NOIO - Do not do any I/O at all while trying to get memory. 418 * 419 * %GFP_NOFS - Do not make any fs calls while trying to get memory. 420 * 421 * %GFP_NOWAIT - Allocation will not sleep. 422 * 423 * %__GFP_THISNODE - Allocate node-local memory only. 424 * 425 * %GFP_DMA - Allocation suitable for DMA. 426 * Should only be used for kmalloc() caches. Otherwise, use a 427 * slab created with SLAB_DMA. 428 * 429 * Also it is possible to set different flags by OR'ing 430 * in one or more of the following additional @flags: 431 * 432 * %__GFP_COLD - Request cache-cold pages instead of 433 * trying to return cache-warm pages. 434 * 435 * %__GFP_HIGH - This allocation has high priority and may use emergency pools. 436 * 437 * %__GFP_NOFAIL - Indicate that this allocation is in no way allowed to fail 438 * (think twice before using). 439 * 440 * %__GFP_NORETRY - If memory is not immediately available, 441 * then give up at once. 442 * 443 * %__GFP_NOWARN - If allocation fails, don't issue any warnings. 444 * 445 * %__GFP_REPEAT - If allocation fails initially, try once more before failing. 446 * 447 * There are other flags available as well, but these are not intended 448 * for general use, and so are not documented here. For a full list of 449 * potential flags, always refer to linux/gfp.h. 450 */ 451 static __always_inline void *kmalloc(size_t size, gfp_t flags) 452 { 453 if (__builtin_constant_p(size)) { 454 if (size > KMALLOC_MAX_CACHE_SIZE) 455 return kmalloc_large(size, flags); 456 #ifndef CONFIG_SLOB 457 if (!(flags & GFP_DMA)) { 458 int index = kmalloc_index(size); 459 460 if (!index) 461 return ZERO_SIZE_PTR; 462 463 return kmem_cache_alloc_trace(kmalloc_caches[index], 464 flags, size); 465 } 466 #endif 467 } 468 return __kmalloc(size, flags); 469 } 470 471 /* 472 * Determine size used for the nth kmalloc cache. 473 * return size or 0 if a kmalloc cache for that 474 * size does not exist 475 */ 476 static __always_inline int kmalloc_size(int n) 477 { 478 #ifndef CONFIG_SLOB 479 if (n > 2) 480 return 1 << n; 481 482 if (n == 1 && KMALLOC_MIN_SIZE <= 32) 483 return 96; 484 485 if (n == 2 && KMALLOC_MIN_SIZE <= 64) 486 return 192; 487 #endif 488 return 0; 489 } 490 491 static __always_inline void *kmalloc_node(size_t size, gfp_t flags, int node) 492 { 493 #ifndef CONFIG_SLOB 494 if (__builtin_constant_p(size) && 495 size <= KMALLOC_MAX_CACHE_SIZE && !(flags & GFP_DMA)) { 496 int i = kmalloc_index(size); 497 498 if (!i) 499 return ZERO_SIZE_PTR; 500 501 return kmem_cache_alloc_node_trace(kmalloc_caches[i], 502 flags, node, size); 503 } 504 #endif 505 return __kmalloc_node(size, flags, node); 506 } 507 508 struct memcg_cache_array { 509 struct rcu_head rcu; 510 struct kmem_cache *entries[0]; 511 }; 512 513 /* 514 * This is the main placeholder for memcg-related information in kmem caches. 515 * Both the root cache and the child caches will have it. For the root cache, 516 * this will hold a dynamically allocated array large enough to hold 517 * information about the currently limited memcgs in the system. To allow the 518 * array to be accessed without taking any locks, on relocation we free the old 519 * version only after a grace period. 520 * 521 * Child caches will hold extra metadata needed for its operation. Fields are: 522 * 523 * @memcg: pointer to the memcg this cache belongs to 524 * @root_cache: pointer to the global, root cache, this cache was derived from 525 * 526 * Both root and child caches of the same kind are linked into a list chained 527 * through @list. 528 */ 529 struct memcg_cache_params { 530 bool is_root_cache; 531 struct list_head list; 532 union { 533 struct memcg_cache_array __rcu *memcg_caches; 534 struct { 535 struct mem_cgroup *memcg; 536 struct kmem_cache *root_cache; 537 }; 538 }; 539 }; 540 541 int memcg_update_all_caches(int num_memcgs); 542 543 /** 544 * kmalloc_array - allocate memory for an array. 545 * @n: number of elements. 546 * @size: element size. 547 * @flags: the type of memory to allocate (see kmalloc). 548 */ 549 static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags) 550 { 551 if (size != 0 && n > SIZE_MAX / size) 552 return NULL; 553 return __kmalloc(n * size, flags); 554 } 555 556 /** 557 * kcalloc - allocate memory for an array. The memory is set to zero. 558 * @n: number of elements. 559 * @size: element size. 560 * @flags: the type of memory to allocate (see kmalloc). 561 */ 562 static inline void *kcalloc(size_t n, size_t size, gfp_t flags) 563 { 564 return kmalloc_array(n, size, flags | __GFP_ZERO); 565 } 566 567 /* 568 * kmalloc_track_caller is a special version of kmalloc that records the 569 * calling function of the routine calling it for slab leak tracking instead 570 * of just the calling function (confusing, eh?). 571 * It's useful when the call to kmalloc comes from a widely-used standard 572 * allocator where we care about the real place the memory allocation 573 * request comes from. 574 */ 575 extern void *__kmalloc_track_caller(size_t, gfp_t, unsigned long); 576 #define kmalloc_track_caller(size, flags) \ 577 __kmalloc_track_caller(size, flags, _RET_IP_) 578 579 #ifdef CONFIG_NUMA 580 extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, unsigned long); 581 #define kmalloc_node_track_caller(size, flags, node) \ 582 __kmalloc_node_track_caller(size, flags, node, \ 583 _RET_IP_) 584 585 #else /* CONFIG_NUMA */ 586 587 #define kmalloc_node_track_caller(size, flags, node) \ 588 kmalloc_track_caller(size, flags) 589 590 #endif /* CONFIG_NUMA */ 591 592 /* 593 * Shortcuts 594 */ 595 static inline void *kmem_cache_zalloc(struct kmem_cache *k, gfp_t flags) 596 { 597 return kmem_cache_alloc(k, flags | __GFP_ZERO); 598 } 599 600 /** 601 * kzalloc - allocate memory. The memory is set to zero. 602 * @size: how many bytes of memory are required. 603 * @flags: the type of memory to allocate (see kmalloc). 604 */ 605 static inline void *kzalloc(size_t size, gfp_t flags) 606 { 607 return kmalloc(size, flags | __GFP_ZERO); 608 } 609 610 /** 611 * kzalloc_node - allocate zeroed memory from a particular memory node. 612 * @size: how many bytes of memory are required. 613 * @flags: the type of memory to allocate (see kmalloc). 614 * @node: memory node from which to allocate 615 */ 616 static inline void *kzalloc_node(size_t size, gfp_t flags, int node) 617 { 618 return kmalloc_node(size, flags | __GFP_ZERO, node); 619 } 620 621 unsigned int kmem_cache_size(struct kmem_cache *s); 622 void __init kmem_cache_init_late(void); 623 624 #endif /* _LINUX_SLAB_H */
1 #ifndef __LINUX_SPINLOCK_H 2 #define __LINUX_SPINLOCK_H 3 4 /* 5 * include/linux/spinlock.h - generic spinlock/rwlock declarations 6 * 7 * here's the role of the various spinlock/rwlock related include files: 8 * 9 * on SMP builds: 10 * 11 * asm/spinlock_types.h: contains the arch_spinlock_t/arch_rwlock_t and the 12 * initializers 13 * 14 * linux/spinlock_types.h: 15 * defines the generic type and initializers 16 * 17 * asm/spinlock.h: contains the arch_spin_*()/etc. lowlevel 18 * implementations, mostly inline assembly code 19 * 20 * (also included on UP-debug builds:) 21 * 22 * linux/spinlock_api_smp.h: 23 * contains the prototypes for the _spin_*() APIs. 24 * 25 * linux/spinlock.h: builds the final spin_*() APIs. 26 * 27 * on UP builds: 28 * 29 * linux/spinlock_type_up.h: 30 * contains the generic, simplified UP spinlock type. 31 * (which is an empty structure on non-debug builds) 32 * 33 * linux/spinlock_types.h: 34 * defines the generic type and initializers 35 * 36 * linux/spinlock_up.h: 37 * contains the arch_spin_*()/etc. version of UP 38 * builds. (which are NOPs on non-debug, non-preempt 39 * builds) 40 * 41 * (included on UP-non-debug builds:) 42 * 43 * linux/spinlock_api_up.h: 44 * builds the _spin_*() APIs. 45 * 46 * linux/spinlock.h: builds the final spin_*() APIs. 47 */ 48 49 #include <linux/typecheck.h> 50 #include <linux/preempt.h> 51 #include <linux/linkage.h> 52 #include <linux/compiler.h> 53 #include <linux/irqflags.h> 54 #include <linux/thread_info.h> 55 #include <linux/kernel.h> 56 #include <linux/stringify.h> 57 #include <linux/bottom_half.h> 58 #include <asm/barrier.h> 59 60 61 /* 62 * Must define these before including other files, inline functions need them 63 */ 64 #define LOCK_SECTION_NAME ".text..lock."KBUILD_BASENAME 65 66 #define LOCK_SECTION_START(extra) \ 67 ".subsection 1\n\t" \ 68 extra \ 69 ".ifndef " LOCK_SECTION_NAME "\n\t" \ 70 LOCK_SECTION_NAME ":\n\t" \ 71 ".endif\n" 72 73 #define LOCK_SECTION_END \ 74 ".previous\n\t" 75 76 #define __lockfunc __attribute__((section(".spinlock.text"))) 77 78 /* 79 * Pull the arch_spinlock_t and arch_rwlock_t definitions: 80 */ 81 #include <linux/spinlock_types.h> 82 83 /* 84 * Pull the arch_spin*() functions/declarations (UP-nondebug doesn't need them): 85 */ 86 #ifdef CONFIG_SMP 87 # include <asm/spinlock.h> 88 #else 89 # include <linux/spinlock_up.h> 90 #endif 91 92 #ifdef CONFIG_DEBUG_SPINLOCK 93 extern void __raw_spin_lock_init(raw_spinlock_t *lock, const char *name, 94 struct lock_class_key *key); 95 # define raw_spin_lock_init(lock) \ 96 do { \ 97 static struct lock_class_key __key; \ 98 \ 99 __raw_spin_lock_init((lock), #lock, &__key); \ 100 } while (0) 101 102 #else 103 # define raw_spin_lock_init(lock) \ 104 do { *(lock) = __RAW_SPIN_LOCK_UNLOCKED(lock); } while (0) 105 #endif 106 107 #define raw_spin_is_locked(lock) arch_spin_is_locked(&(lock)->raw_lock) 108 109 #ifdef CONFIG_GENERIC_LOCKBREAK 110 #define raw_spin_is_contended(lock) ((lock)->break_lock) 111 #else 112 113 #ifdef arch_spin_is_contended 114 #define raw_spin_is_contended(lock) arch_spin_is_contended(&(lock)->raw_lock) 115 #else 116 #define raw_spin_is_contended(lock) (((void)(lock), 0)) 117 #endif /*arch_spin_is_contended*/ 118 #endif 119 120 /* 121 * Despite its name it doesn't necessarily has to be a full barrier. 122 * It should only guarantee that a STORE before the critical section 123 * can not be reordered with LOADs and STOREs inside this section. 124 * spin_lock() is the one-way barrier, this LOAD can not escape out 125 * of the region. So the default implementation simply ensures that 126 * a STORE can not move into the critical section, smp_wmb() should 127 * serialize it with another STORE done by spin_lock(). 128 */ 129 #ifndef smp_mb__before_spinlock 130 #define smp_mb__before_spinlock() smp_wmb() 131 #endif 132 133 /** 134 * raw_spin_unlock_wait - wait until the spinlock gets unlocked 135 * @lock: the spinlock in question. 136 */ 137 #define raw_spin_unlock_wait(lock) arch_spin_unlock_wait(&(lock)->raw_lock) 138 139 #ifdef CONFIG_DEBUG_SPINLOCK 140 extern void do_raw_spin_lock(raw_spinlock_t *lock) __acquires(lock); 141 #define do_raw_spin_lock_flags(lock, flags) do_raw_spin_lock(lock) 142 extern int do_raw_spin_trylock(raw_spinlock_t *lock); 143 extern void do_raw_spin_unlock(raw_spinlock_t *lock) __releases(lock); 144 #else 145 static inline void do_raw_spin_lock(raw_spinlock_t *lock) __acquires(lock) 146 { 147 __acquire(lock); 148 arch_spin_lock(&lock->raw_lock); 149 } 150 151 static inline void 152 do_raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long *flags) __acquires(lock) 153 { 154 __acquire(lock); 155 arch_spin_lock_flags(&lock->raw_lock, *flags); 156 } 157 158 static inline int do_raw_spin_trylock(raw_spinlock_t *lock) 159 { 160 return arch_spin_trylock(&(lock)->raw_lock); 161 } 162 163 static inline void do_raw_spin_unlock(raw_spinlock_t *lock) __releases(lock) 164 { 165 arch_spin_unlock(&lock->raw_lock); 166 __release(lock); 167 } 168 #endif 169 170 /* 171 * Define the various spin_lock methods. Note we define these 172 * regardless of whether CONFIG_SMP or CONFIG_PREEMPT are set. The 173 * various methods are defined as nops in the case they are not 174 * required. 175 */ 176 #define raw_spin_trylock(lock) __cond_lock(lock, _raw_spin_trylock(lock)) 177 178 #define raw_spin_lock(lock) _raw_spin_lock(lock) 179 180 #ifdef CONFIG_DEBUG_LOCK_ALLOC 181 # define raw_spin_lock_nested(lock, subclass) \ 182 _raw_spin_lock_nested(lock, subclass) 183 # define raw_spin_lock_bh_nested(lock, subclass) \ 184 _raw_spin_lock_bh_nested(lock, subclass) 185 186 # define raw_spin_lock_nest_lock(lock, nest_lock) \ 187 do { \ 188 typecheck(struct lockdep_map *, &(nest_lock)->dep_map);\ 189 _raw_spin_lock_nest_lock(lock, &(nest_lock)->dep_map); \ 190 } while (0) 191 #else 192 /* 193 * Always evaluate the 'subclass' argument to avoid that the compiler 194 * warns about set-but-not-used variables when building with 195 * CONFIG_DEBUG_LOCK_ALLOC=n and with W=1. 196 */ 197 # define raw_spin_lock_nested(lock, subclass) \ 198 _raw_spin_lock(((void)(subclass), (lock))) 199 # define raw_spin_lock_nest_lock(lock, nest_lock) _raw_spin_lock(lock) 200 # define raw_spin_lock_bh_nested(lock, subclass) _raw_spin_lock_bh(lock) 201 #endif 202 203 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_SPINLOCK) 204 205 #define raw_spin_lock_irqsave(lock, flags) \ 206 do { \ 207 typecheck(unsigned long, flags); \ 208 flags = _raw_spin_lock_irqsave(lock); \ 209 } while (0) 210 211 #ifdef CONFIG_DEBUG_LOCK_ALLOC 212 #define raw_spin_lock_irqsave_nested(lock, flags, subclass) \ 213 do { \ 214 typecheck(unsigned long, flags); \ 215 flags = _raw_spin_lock_irqsave_nested(lock, subclass); \ 216 } while (0) 217 #else 218 #define raw_spin_lock_irqsave_nested(lock, flags, subclass) \ 219 do { \ 220 typecheck(unsigned long, flags); \ 221 flags = _raw_spin_lock_irqsave(lock); \ 222 } while (0) 223 #endif 224 225 #else 226 227 #define raw_spin_lock_irqsave(lock, flags) \ 228 do { \ 229 typecheck(unsigned long, flags); \ 230 _raw_spin_lock_irqsave(lock, flags); \ 231 } while (0) 232 233 #define raw_spin_lock_irqsave_nested(lock, flags, subclass) \ 234 raw_spin_lock_irqsave(lock, flags) 235 236 #endif 237 238 #define raw_spin_lock_irq(lock) _raw_spin_lock_irq(lock) 239 #define raw_spin_lock_bh(lock) _raw_spin_lock_bh(lock) 240 #define raw_spin_unlock(lock) _raw_spin_unlock(lock) 241 #define raw_spin_unlock_irq(lock) _raw_spin_unlock_irq(lock) 242 243 #define raw_spin_unlock_irqrestore(lock, flags) \ 244 do { \ 245 typecheck(unsigned long, flags); \ 246 _raw_spin_unlock_irqrestore(lock, flags); \ 247 } while (0) 248 #define raw_spin_unlock_bh(lock) _raw_spin_unlock_bh(lock) 249 250 #define raw_spin_trylock_bh(lock) \ 251 __cond_lock(lock, _raw_spin_trylock_bh(lock)) 252 253 #define raw_spin_trylock_irq(lock) \ 254 ({ \ 255 local_irq_disable(); \ 256 raw_spin_trylock(lock) ? \ 257 1 : ({ local_irq_enable(); 0; }); \ 258 }) 259 260 #define raw_spin_trylock_irqsave(lock, flags) \ 261 ({ \ 262 local_irq_save(flags); \ 263 raw_spin_trylock(lock) ? \ 264 1 : ({ local_irq_restore(flags); 0; }); \ 265 }) 266 267 /** 268 * raw_spin_can_lock - would raw_spin_trylock() succeed? 269 * @lock: the spinlock in question. 270 */ 271 #define raw_spin_can_lock(lock) (!raw_spin_is_locked(lock)) 272 273 /* Include rwlock functions */ 274 #include <linux/rwlock.h> 275 276 /* 277 * Pull the _spin_*()/_read_*()/_write_*() functions/declarations: 278 */ 279 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_SPINLOCK) 280 # include <linux/spinlock_api_smp.h> 281 #else 282 # include <linux/spinlock_api_up.h> 283 #endif 284 285 /* 286 * Map the spin_lock functions to the raw variants for PREEMPT_RT=n 287 */ 288 289 static __always_inline raw_spinlock_t *spinlock_check(spinlock_t *lock) 290 { 291 return &lock->rlock; 292 } 293 294 #define spin_lock_init(_lock) \ 295 do { \ 296 spinlock_check(_lock); \ 297 raw_spin_lock_init(&(_lock)->rlock); \ 298 } while (0) 299 300 static __always_inline void spin_lock(spinlock_t *lock) 301 { 302 raw_spin_lock(&lock->rlock); 303 } 304 305 static __always_inline void spin_lock_bh(spinlock_t *lock) 306 { 307 raw_spin_lock_bh(&lock->rlock); 308 } 309 310 static __always_inline int spin_trylock(spinlock_t *lock) 311 { 312 return raw_spin_trylock(&lock->rlock); 313 } 314 315 #define spin_lock_nested(lock, subclass) \ 316 do { \ 317 raw_spin_lock_nested(spinlock_check(lock), subclass); \ 318 } while (0) 319 320 #define spin_lock_bh_nested(lock, subclass) \ 321 do { \ 322 raw_spin_lock_bh_nested(spinlock_check(lock), subclass);\ 323 } while (0) 324 325 #define spin_lock_nest_lock(lock, nest_lock) \ 326 do { \ 327 raw_spin_lock_nest_lock(spinlock_check(lock), nest_lock); \ 328 } while (0) 329 330 static __always_inline void spin_lock_irq(spinlock_t *lock) 331 { 332 raw_spin_lock_irq(&lock->rlock); 333 } 334 335 #define spin_lock_irqsave(lock, flags) \ 336 do { \ 337 raw_spin_lock_irqsave(spinlock_check(lock), flags); \ 338 } while (0) 339 340 #define spin_lock_irqsave_nested(lock, flags, subclass) \ 341 do { \ 342 raw_spin_lock_irqsave_nested(spinlock_check(lock), flags, subclass); \ 343 } while (0) 344 345 static __always_inline void spin_unlock(spinlock_t *lock) 346 { 347 raw_spin_unlock(&lock->rlock); 348 } 349 350 static __always_inline void spin_unlock_bh(spinlock_t *lock) 351 { 352 raw_spin_unlock_bh(&lock->rlock); 353 } 354 355 static __always_inline void spin_unlock_irq(spinlock_t *lock) 356 { 357 raw_spin_unlock_irq(&lock->rlock); 358 } 359 360 static __always_inline void spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags) 361 { 362 raw_spin_unlock_irqrestore(&lock->rlock, flags); 363 } 364 365 static __always_inline int spin_trylock_bh(spinlock_t *lock) 366 { 367 return raw_spin_trylock_bh(&lock->rlock); 368 } 369 370 static __always_inline int spin_trylock_irq(spinlock_t *lock) 371 { 372 return raw_spin_trylock_irq(&lock->rlock); 373 } 374 375 #define spin_trylock_irqsave(lock, flags) \ 376 ({ \ 377 raw_spin_trylock_irqsave(spinlock_check(lock), flags); \ 378 }) 379 380 static __always_inline void spin_unlock_wait(spinlock_t *lock) 381 { 382 raw_spin_unlock_wait(&lock->rlock); 383 } 384 385 static __always_inline int spin_is_locked(spinlock_t *lock) 386 { 387 return raw_spin_is_locked(&lock->rlock); 388 } 389 390 static __always_inline int spin_is_contended(spinlock_t *lock) 391 { 392 return raw_spin_is_contended(&lock->rlock); 393 } 394 395 static __always_inline int spin_can_lock(spinlock_t *lock) 396 { 397 return raw_spin_can_lock(&lock->rlock); 398 } 399 400 #define assert_spin_locked(lock) assert_raw_spin_locked(&(lock)->rlock) 401 402 /* 403 * Pull the atomic_t declaration: 404 * (asm-mips/atomic.h needs above definitions) 405 */ 406 #include <linux/atomic.h> 407 /** 408 * atomic_dec_and_lock - lock on reaching reference count zero 409 * @atomic: the atomic counter 410 * @lock: the spinlock in question 411 * 412 * Decrements @atomic by 1. If the result is 0, returns true and locks 413 * @lock. Returns false for all other cases. 414 */ 415 extern int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock); 416 #define atomic_dec_and_lock(atomic, lock) \ 417 __cond_lock(lock, _atomic_dec_and_lock(atomic, lock)) 418 419 #endif /* __LINUX_SPINLOCK_H */
1 #ifndef _LINUX_TTY_DRIVER_H 2 #define _LINUX_TTY_DRIVER_H 3 4 /* 5 * This structure defines the interface between the low-level tty 6 * driver and the tty routines. The following routines can be 7 * defined; unless noted otherwise, they are optional, and can be 8 * filled in with a null pointer. 9 * 10 * struct tty_struct * (*lookup)(struct tty_driver *self, int idx) 11 * 12 * Return the tty device corresponding to idx, NULL if there is not 13 * one currently in use and an ERR_PTR value on error. Called under 14 * tty_mutex (for now!) 15 * 16 * Optional method. Default behaviour is to use the ttys array 17 * 18 * int (*install)(struct tty_driver *self, struct tty_struct *tty) 19 * 20 * Install a new tty into the tty driver internal tables. Used in 21 * conjunction with lookup and remove methods. 22 * 23 * Optional method. Default behaviour is to use the ttys array 24 * 25 * void (*remove)(struct tty_driver *self, struct tty_struct *tty) 26 * 27 * Remove a closed tty from the tty driver internal tables. Used in 28 * conjunction with lookup and remove methods. 29 * 30 * Optional method. Default behaviour is to use the ttys array 31 * 32 * int (*open)(struct tty_struct * tty, struct file * filp); 33 * 34 * This routine is called when a particular tty device is opened. 35 * This routine is mandatory; if this routine is not filled in, 36 * the attempted open will fail with ENODEV. 37 * 38 * Required method. Called with tty lock held. 39 * 40 * void (*close)(struct tty_struct * tty, struct file * filp); 41 * 42 * This routine is called when a particular tty device is closed. 43 * Note: called even if the corresponding open() failed. 44 * 45 * Required method. Called with tty lock held. 46 * 47 * void (*shutdown)(struct tty_struct * tty); 48 * 49 * This routine is called under the tty lock when a particular tty device 50 * is closed for the last time. It executes before the tty resources 51 * are freed so may execute while another function holds a tty kref. 52 * 53 * void (*cleanup)(struct tty_struct * tty); 54 * 55 * This routine is called asynchronously when a particular tty device 56 * is closed for the last time freeing up the resources. This is 57 * actually the second part of shutdown for routines that might sleep. 58 * 59 * 60 * int (*write)(struct tty_struct * tty, 61 * const unsigned char *buf, int count); 62 * 63 * This routine is called by the kernel to write a series of 64 * characters to the tty device. The characters may come from 65 * user space or kernel space. This routine will return the 66 * number of characters actually accepted for writing. 67 * 68 * Optional: Required for writable devices. 69 * 70 * int (*put_char)(struct tty_struct *tty, unsigned char ch); 71 * 72 * This routine is called by the kernel to write a single 73 * character to the tty device. If the kernel uses this routine, 74 * it must call the flush_chars() routine (if defined) when it is 75 * done stuffing characters into the driver. If there is no room 76 * in the queue, the character is ignored. 77 * 78 * Optional: Kernel will use the write method if not provided. 79 * 80 * Note: Do not call this function directly, call tty_put_char 81 * 82 * void (*flush_chars)(struct tty_struct *tty); 83 * 84 * This routine is called by the kernel after it has written a 85 * series of characters to the tty device using put_char(). 86 * 87 * Optional: 88 * 89 * Note: Do not call this function directly, call tty_driver_flush_chars 90 * 91 * int (*write_room)(struct tty_struct *tty); 92 * 93 * This routine returns the numbers of characters the tty driver 94 * will accept for queuing to be written. This number is subject 95 * to change as output buffers get emptied, or if the output flow 96 * control is acted. 97 * 98 * Required if write method is provided else not needed. 99 * 100 * Note: Do not call this function directly, call tty_write_room 101 * 102 * int (*ioctl)(struct tty_struct *tty, unsigned int cmd, unsigned long arg); 103 * 104 * This routine allows the tty driver to implement 105 * device-specific ioctls. If the ioctl number passed in cmd 106 * is not recognized by the driver, it should return ENOIOCTLCMD. 107 * 108 * Optional 109 * 110 * long (*compat_ioctl)(struct tty_struct *tty,, 111 * unsigned int cmd, unsigned long arg); 112 * 113 * implement ioctl processing for 32 bit process on 64 bit system 114 * 115 * Optional 116 * 117 * void (*set_termios)(struct tty_struct *tty, struct ktermios * old); 118 * 119 * This routine allows the tty driver to be notified when 120 * device's termios settings have changed. 121 * 122 * Optional: Called under the termios lock 123 * 124 * 125 * void (*set_ldisc)(struct tty_struct *tty); 126 * 127 * This routine allows the tty driver to be notified when the 128 * device's termios settings have changed. 129 * 130 * Optional: Called under BKL (currently) 131 * 132 * void (*throttle)(struct tty_struct * tty); 133 * 134 * This routine notifies the tty driver that input buffers for 135 * the line discipline are close to full, and it should somehow 136 * signal that no more characters should be sent to the tty. 137 * 138 * Optional: Always invoke via tty_throttle(), called under the 139 * termios lock. 140 * 141 * void (*unthrottle)(struct tty_struct * tty); 142 * 143 * This routine notifies the tty drivers that it should signals 144 * that characters can now be sent to the tty without fear of 145 * overrunning the input buffers of the line disciplines. 146 * 147 * Optional: Always invoke via tty_unthrottle(), called under the 148 * termios lock. 149 * 150 * void (*stop)(struct tty_struct *tty); 151 * 152 * This routine notifies the tty driver that it should stop 153 * outputting characters to the tty device. 154 * 155 * Called with ->flow_lock held. Serialized with start() method. 156 * 157 * Optional: 158 * 159 * Note: Call stop_tty not this method. 160 * 161 * void (*start)(struct tty_struct *tty); 162 * 163 * This routine notifies the tty driver that it resume sending 164 * characters to the tty device. 165 * 166 * Called with ->flow_lock held. Serialized with stop() method. 167 * 168 * Optional: 169 * 170 * Note: Call start_tty not this method. 171 * 172 * void (*hangup)(struct tty_struct *tty); 173 * 174 * This routine notifies the tty driver that it should hang up the 175 * tty device. 176 * 177 * Optional: 178 * 179 * Called with tty lock held. 180 * 181 * int (*break_ctl)(struct tty_struct *tty, int state); 182 * 183 * This optional routine requests the tty driver to turn on or 184 * off BREAK status on the RS-232 port. If state is -1, 185 * then the BREAK status should be turned on; if state is 0, then 186 * BREAK should be turned off. 187 * 188 * If this routine is implemented, the high-level tty driver will 189 * handle the following ioctls: TCSBRK, TCSBRKP, TIOCSBRK, 190 * TIOCCBRK. 191 * 192 * If the driver sets TTY_DRIVER_HARDWARE_BREAK then the interface 193 * will also be called with actual times and the hardware is expected 194 * to do the delay work itself. 0 and -1 are still used for on/off. 195 * 196 * Optional: Required for TCSBRK/BRKP/etc handling. 197 * 198 * void (*wait_until_sent)(struct tty_struct *tty, int timeout); 199 * 200 * This routine waits until the device has written out all of the 201 * characters in its transmitter FIFO. 202 * 203 * Optional: If not provided the device is assumed to have no FIFO 204 * 205 * Note: Usually correct to call tty_wait_until_sent 206 * 207 * void (*send_xchar)(struct tty_struct *tty, char ch); 208 * 209 * This routine is used to send a high-priority XON/XOFF 210 * character to the device. 211 * 212 * Optional: If not provided then the write method is called under 213 * the atomic write lock to keep it serialized with the ldisc. 214 * 215 * int (*resize)(struct tty_struct *tty, struct winsize *ws) 216 * 217 * Called when a termios request is issued which changes the 218 * requested terminal geometry. 219 * 220 * Optional: the default action is to update the termios structure 221 * without error. This is usually the correct behaviour. Drivers should 222 * not force errors here if they are not resizable objects (eg a serial 223 * line). See tty_do_resize() if you need to wrap the standard method 224 * in your own logic - the usual case. 225 * 226 * void (*set_termiox)(struct tty_struct *tty, struct termiox *new); 227 * 228 * Called when the device receives a termiox based ioctl. Passes down 229 * the requested data from user space. This method will not be invoked 230 * unless the tty also has a valid tty->termiox pointer. 231 * 232 * Optional: Called under the termios lock 233 * 234 * int (*get_icount)(struct tty_struct *tty, struct serial_icounter *icount); 235 * 236 * Called when the device receives a TIOCGICOUNT ioctl. Passed a kernel 237 * structure to complete. This method is optional and will only be called 238 * if provided (otherwise EINVAL will be returned). 239 */ 240 241 #include <linux/export.h> 242 #include <linux/fs.h> 243 #include <linux/list.h> 244 #include <linux/cdev.h> 245 #include <linux/termios.h> 246 247 struct tty_struct; 248 struct tty_driver; 249 struct serial_icounter_struct; 250 251 struct tty_operations { 252 struct tty_struct * (*lookup)(struct tty_driver *driver, 253 struct inode *inode, int idx); 254 int (*install)(struct tty_driver *driver, struct tty_struct *tty); 255 void (*remove)(struct tty_driver *driver, struct tty_struct *tty); 256 int (*open)(struct tty_struct * tty, struct file * filp); 257 void (*close)(struct tty_struct * tty, struct file * filp); 258 void (*shutdown)(struct tty_struct *tty); 259 void (*cleanup)(struct tty_struct *tty); 260 int (*write)(struct tty_struct * tty, 261 const unsigned char *buf, int count); 262 int (*put_char)(struct tty_struct *tty, unsigned char ch); 263 void (*flush_chars)(struct tty_struct *tty); 264 int (*write_room)(struct tty_struct *tty); 265 int (*chars_in_buffer)(struct tty_struct *tty); 266 int (*ioctl)(struct tty_struct *tty, 267 unsigned int cmd, unsigned long arg); 268 long (*compat_ioctl)(struct tty_struct *tty, 269 unsigned int cmd, unsigned long arg); 270 void (*set_termios)(struct tty_struct *tty, struct ktermios * old); 271 void (*throttle)(struct tty_struct * tty); 272 void (*unthrottle)(struct tty_struct * tty); 273 void (*stop)(struct tty_struct *tty); 274 void (*start)(struct tty_struct *tty); 275 void (*hangup)(struct tty_struct *tty); 276 int (*break_ctl)(struct tty_struct *tty, int state); 277 void (*flush_buffer)(struct tty_struct *tty); 278 void (*set_ldisc)(struct tty_struct *tty); 279 void (*wait_until_sent)(struct tty_struct *tty, int timeout); 280 void (*send_xchar)(struct tty_struct *tty, char ch); 281 int (*tiocmget)(struct tty_struct *tty); 282 int (*tiocmset)(struct tty_struct *tty, 283 unsigned int set, unsigned int clear); 284 int (*resize)(struct tty_struct *tty, struct winsize *ws); 285 int (*set_termiox)(struct tty_struct *tty, struct termiox *tnew); 286 int (*get_icount)(struct tty_struct *tty, 287 struct serial_icounter_struct *icount); 288 #ifdef CONFIG_CONSOLE_POLL 289 int (*poll_init)(struct tty_driver *driver, int line, char *options); 290 int (*poll_get_char)(struct tty_driver *driver, int line); 291 void (*poll_put_char)(struct tty_driver *driver, int line, char ch); 292 #endif 293 const struct file_operations *proc_fops; 294 }; 295 296 struct tty_driver { 297 int magic; /* magic number for this structure */ 298 struct kref kref; /* Reference management */ 299 struct cdev **cdevs; 300 struct module *owner; 301 const char *driver_name; 302 const char *name; 303 int name_base; /* offset of printed name */ 304 int major; /* major device number */ 305 int minor_start; /* start of minor device number */ 306 unsigned int num; /* number of devices allocated */ 307 short type; /* type of tty driver */ 308 short subtype; /* subtype of tty driver */ 309 struct ktermios init_termios; /* Initial termios */ 310 unsigned long flags; /* tty driver flags */ 311 struct proc_dir_entry *proc_entry; /* /proc fs entry */ 312 struct tty_driver *other; /* only used for the PTY driver */ 313 314 /* 315 * Pointer to the tty data structures 316 */ 317 struct tty_struct **ttys; 318 struct tty_port **ports; 319 struct ktermios **termios; 320 void *driver_state; 321 322 /* 323 * Driver methods 324 */ 325 326 const struct tty_operations *ops; 327 struct list_head tty_drivers; 328 }; 329 330 extern struct list_head tty_drivers; 331 332 extern struct tty_driver *__tty_alloc_driver(unsigned int lines, 333 struct module *owner, unsigned long flags); 334 extern void put_tty_driver(struct tty_driver *driver); 335 extern void tty_set_operations(struct tty_driver *driver, 336 const struct tty_operations *op); 337 extern struct tty_driver *tty_find_polling_driver(char *name, int *line); 338 339 extern void tty_driver_kref_put(struct tty_driver *driver); 340 341 /* Use TTY_DRIVER_* flags below */ 342 #define tty_alloc_driver(lines, flags) \ 343 __tty_alloc_driver(lines, THIS_MODULE, flags) 344 345 /* 346 * DEPRECATED Do not use this in new code, use tty_alloc_driver instead. 347 * (And change the return value checks.) 348 */ 349 static inline struct tty_driver *alloc_tty_driver(unsigned int lines) 350 { 351 struct tty_driver *ret = tty_alloc_driver(lines, 0); 352 if (IS_ERR(ret)) 353 return NULL; 354 return ret; 355 } 356 357 static inline struct tty_driver *tty_driver_kref_get(struct tty_driver *d) 358 { 359 kref_get(&d->kref); 360 return d; 361 } 362 363 /* tty driver magic number */ 364 #define TTY_DRIVER_MAGIC 0x5402 365 366 /* 367 * tty driver flags 368 * 369 * TTY_DRIVER_RESET_TERMIOS --- requests the tty layer to reset the 370 * termios setting when the last process has closed the device. 371 * Used for PTY's, in particular. 372 * 373 * TTY_DRIVER_REAL_RAW --- if set, indicates that the driver will 374 * guarantee never not to set any special character handling 375 * flags if ((IGNBRK || (!BRKINT && !PARMRK)) && (IGNPAR || 376 * !INPCK)). That is, if there is no reason for the driver to 377 * send notifications of parity and break characters up to the 378 * line driver, it won't do so. This allows the line driver to 379 * optimize for this case if this flag is set. (Note that there 380 * is also a promise, if the above case is true, not to signal 381 * overruns, either.) 382 * 383 * TTY_DRIVER_DYNAMIC_DEV --- if set, the individual tty devices need 384 * to be registered with a call to tty_register_device() when the 385 * device is found in the system and unregistered with a call to 386 * tty_unregister_device() so the devices will be show up 387 * properly in sysfs. If not set, driver->num entries will be 388 * created by the tty core in sysfs when tty_register_driver() is 389 * called. This is to be used by drivers that have tty devices 390 * that can appear and disappear while the main tty driver is 391 * registered with the tty core. 392 * 393 * TTY_DRIVER_DEVPTS_MEM -- don't use the standard arrays, instead 394 * use dynamic memory keyed through the devpts filesystem. This 395 * is only applicable to the pty driver. 396 * 397 * TTY_DRIVER_HARDWARE_BREAK -- hardware handles break signals. Pass 398 * the requested timeout to the caller instead of using a simple 399 * on/off interface. 400 * 401 * TTY_DRIVER_DYNAMIC_ALLOC -- do not allocate structures which are 402 * needed per line for this driver as it would waste memory. 403 * The driver will take care. 404 * 405 * TTY_DRIVER_UNNUMBERED_NODE -- do not create numbered /dev nodes. In 406 * other words create /dev/ttyprintk and not /dev/ttyprintk0. 407 * Applicable only when a driver for a single tty device is 408 * being allocated. 409 */ 410 #define TTY_DRIVER_INSTALLED 0x0001 411 #define TTY_DRIVER_RESET_TERMIOS 0x0002 412 #define TTY_DRIVER_REAL_RAW 0x0004 413 #define TTY_DRIVER_DYNAMIC_DEV 0x0008 414 #define TTY_DRIVER_DEVPTS_MEM 0x0010 415 #define TTY_DRIVER_HARDWARE_BREAK 0x0020 416 #define TTY_DRIVER_DYNAMIC_ALLOC 0x0040 417 #define TTY_DRIVER_UNNUMBERED_NODE 0x0080 418 419 /* tty driver types */ 420 #define TTY_DRIVER_TYPE_SYSTEM 0x0001 421 #define TTY_DRIVER_TYPE_CONSOLE 0x0002 422 #define TTY_DRIVER_TYPE_SERIAL 0x0003 423 #define TTY_DRIVER_TYPE_PTY 0x0004 424 #define TTY_DRIVER_TYPE_SCC 0x0005 /* scc driver */ 425 #define TTY_DRIVER_TYPE_SYSCONS 0x0006 426 427 /* system subtypes (magic, used by tty_io.c) */ 428 #define SYSTEM_TYPE_TTY 0x0001 429 #define SYSTEM_TYPE_CONSOLE 0x0002 430 #define SYSTEM_TYPE_SYSCONS 0x0003 431 #define SYSTEM_TYPE_SYSPTMX 0x0004 432 433 /* pty subtypes (magic, used by tty_io.c) */ 434 #define PTY_TYPE_MASTER 0x0001 435 #define PTY_TYPE_SLAVE 0x0002 436 437 /* serial subtype definitions */ 438 #define SERIAL_TYPE_NORMAL 1 439 440 #endif /* #ifdef _LINUX_TTY_DRIVER_H */

Here is an explanation of a rule violation arisen while checking your driver against a corresponding kernel.

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Ядро Модуль Правило Верификатор Вердикт Статус Время создания Описание проблемы
linux-4.5-rc1.tar.xz drivers/tty/synclinkmp.ko 134_1a CPAchecker Bug Fixed 2016-09-10 00:23:29 L0218

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Reported: 24 Oct 2015

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